commit e33703443ccf59b6938d8d3202f4297a0b4f5511 Author: sansi Date: Tue Jun 9 16:28:01 2020 +0800 first commit diff --git a/Miz_sys/Miz_sys.hw/Miz_sys.lpr b/Miz_sys/Miz_sys.hw/Miz_sys.lpr new file mode 100644 index 0000000..8c04d07 --- /dev/null +++ b/Miz_sys/Miz_sys.hw/Miz_sys.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.hw/hw_1/hw.xml b/Miz_sys/Miz_sys.hw/hw_1/hw.xml new file mode 100644 index 0000000..b629be7 --- /dev/null +++ b/Miz_sys/Miz_sys.hw/hw_1/hw.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/README.txt b/Miz_sys/Miz_sys.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv b/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv new file mode 100644 index 0000000..82f9334 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv @@ -0,0 +1,1117 @@ +`timescale 1ns/1ps + +//PORTS + + bit CAN0_PHY_TX; + bit CAN0_PHY_RX; + bit CAN1_PHY_TX; + bit CAN1_PHY_RX; + bit [0 : 0] ENET0_GMII_TX_EN; + bit [0 : 0] ENET0_GMII_TX_ER; + bit ENET0_MDIO_MDC; + bit ENET0_MDIO_O; + bit ENET0_MDIO_T; + bit ENET0_PTP_DELAY_REQ_RX; + bit ENET0_PTP_DELAY_REQ_TX; + bit ENET0_PTP_PDELAY_REQ_RX; + bit ENET0_PTP_PDELAY_REQ_TX; + bit ENET0_PTP_PDELAY_RESP_RX; + bit ENET0_PTP_PDELAY_RESP_TX; + bit ENET0_PTP_SYNC_FRAME_RX; + bit ENET0_PTP_SYNC_FRAME_TX; + bit ENET0_SOF_RX; + bit ENET0_SOF_TX; + bit [7 : 0] ENET0_GMII_TXD; + bit ENET0_GMII_COL; + bit ENET0_GMII_CRS; + bit ENET0_GMII_RX_CLK; + bit ENET0_GMII_RX_DV; + bit ENET0_GMII_RX_ER; + bit ENET0_GMII_TX_CLK; + bit ENET0_MDIO_I; + bit ENET0_EXT_INTIN; + bit [7 : 0] ENET0_GMII_RXD; + bit [0 : 0] ENET1_GMII_TX_EN; + bit [0 : 0] ENET1_GMII_TX_ER; + bit ENET1_MDIO_MDC; + bit ENET1_MDIO_O; + bit ENET1_MDIO_T; + bit ENET1_PTP_DELAY_REQ_RX; + bit ENET1_PTP_DELAY_REQ_TX; + bit ENET1_PTP_PDELAY_REQ_RX; + bit ENET1_PTP_PDELAY_REQ_TX; + bit ENET1_PTP_PDELAY_RESP_RX; + bit ENET1_PTP_PDELAY_RESP_TX; + bit ENET1_PTP_SYNC_FRAME_RX; + bit ENET1_PTP_SYNC_FRAME_TX; + bit ENET1_SOF_RX; + bit ENET1_SOF_TX; + bit [7 : 0] ENET1_GMII_TXD; + bit ENET1_GMII_COL; + bit ENET1_GMII_CRS; + bit ENET1_GMII_RX_CLK; + bit ENET1_GMII_RX_DV; + bit ENET1_GMII_RX_ER; + bit ENET1_GMII_TX_CLK; + bit ENET1_MDIO_I; + bit ENET1_EXT_INTIN; + bit [7 : 0] ENET1_GMII_RXD; + bit [63 : 0] GPIO_I; + bit [63 : 0] GPIO_O; + bit [63 : 0] GPIO_T; + bit I2C0_SDA_I; + bit I2C0_SDA_O; + bit I2C0_SDA_T; + bit I2C0_SCL_I; + bit I2C0_SCL_O; + bit I2C0_SCL_T; + bit I2C1_SDA_I; + bit I2C1_SDA_O; + bit I2C1_SDA_T; + bit I2C1_SCL_I; + bit I2C1_SCL_O; + bit I2C1_SCL_T; + bit PJTAG_TCK; + bit PJTAG_TMS; + bit PJTAG_TDI; + bit PJTAG_TDO; + bit SDIO0_CLK; + bit SDIO0_CLK_FB; + bit SDIO0_CMD_O; + bit SDIO0_CMD_I; + bit SDIO0_CMD_T; + bit [3 : 0] SDIO0_DATA_I; + bit [3 : 0] SDIO0_DATA_O; + bit [3 : 0] SDIO0_DATA_T; + bit SDIO0_LED; + bit SDIO0_CDN; + bit SDIO0_WP; + bit SDIO0_BUSPOW; + bit [2 : 0] SDIO0_BUSVOLT; + bit SDIO1_CLK; + bit SDIO1_CLK_FB; + bit SDIO1_CMD_O; + bit SDIO1_CMD_I; + bit SDIO1_CMD_T; + bit [3 : 0] SDIO1_DATA_I; + bit [3 : 0] SDIO1_DATA_O; + bit [3 : 0] SDIO1_DATA_T; + bit SDIO1_LED; + bit SDIO1_CDN; + bit SDIO1_WP; + bit SDIO1_BUSPOW; + bit [2 : 0] SDIO1_BUSVOLT; + bit SPI0_SCLK_I; + bit SPI0_SCLK_O; + bit SPI0_SCLK_T; + bit SPI0_MOSI_I; + bit SPI0_MOSI_O; + bit SPI0_MOSI_T; + bit SPI0_MISO_I; + bit SPI0_MISO_O; + bit SPI0_MISO_T; + bit SPI0_SS_I; + bit SPI0_SS_O; + bit SPI0_SS1_O; + bit SPI0_SS2_O; + bit SPI0_SS_T; + bit SPI1_SCLK_I; + bit SPI1_SCLK_O; + bit SPI1_SCLK_T; + bit SPI1_MOSI_I; + bit SPI1_MOSI_O; + bit SPI1_MOSI_T; + bit SPI1_MISO_I; + bit SPI1_MISO_O; + bit SPI1_MISO_T; + bit SPI1_SS_I; + bit SPI1_SS_O; + bit SPI1_SS1_O; + bit SPI1_SS2_O; + bit SPI1_SS_T; + bit UART0_DTRN; + bit UART0_RTSN; + bit UART0_TX; + bit UART0_CTSN; + bit UART0_DCDN; + bit UART0_DSRN; + bit UART0_RIN; + bit UART0_RX; + bit UART1_DTRN; + bit UART1_RTSN; + bit UART1_TX; + bit UART1_CTSN; + bit UART1_DCDN; + bit UART1_DSRN; + bit UART1_RIN; + bit UART1_RX; + bit TTC0_WAVE0_OUT; + bit TTC0_WAVE1_OUT; + bit TTC0_WAVE2_OUT; + bit TTC0_CLK0_IN; + bit TTC0_CLK1_IN; + bit TTC0_CLK2_IN; + bit TTC1_WAVE0_OUT; + bit TTC1_WAVE1_OUT; + bit TTC1_WAVE2_OUT; + bit TTC1_CLK0_IN; + bit TTC1_CLK1_IN; + bit TTC1_CLK2_IN; + bit WDT_CLK_IN; + bit WDT_RST_OUT; + bit TRACE_CLK; + bit TRACE_CLK_OUT; + bit TRACE_CTL; + bit [1 : 0] TRACE_DATA; + bit [1 : 0] USB0_PORT_INDCTL; + bit USB0_VBUS_PWRSELECT; + bit USB0_VBUS_PWRFAULT; + bit [1 : 0] USB1_PORT_INDCTL; + bit USB1_VBUS_PWRSELECT; + bit USB1_VBUS_PWRFAULT; + bit SRAM_INTIN; + bit M_AXI_GP0_ARVALID; + bit M_AXI_GP0_AWVALID; + bit M_AXI_GP0_BREADY; + bit M_AXI_GP0_RREADY; + bit M_AXI_GP0_WLAST; + bit M_AXI_GP0_WVALID; + bit [11 : 0] M_AXI_GP0_ARID; + bit [11 : 0] M_AXI_GP0_AWID; + bit [11 : 0] M_AXI_GP0_WID; + bit [1 : 0] M_AXI_GP0_ARBURST; + bit [1 : 0] M_AXI_GP0_ARLOCK; + bit [2 : 0] M_AXI_GP0_ARSIZE; + bit [1 : 0] M_AXI_GP0_AWBURST; + bit [1 : 0] M_AXI_GP0_AWLOCK; + bit [2 : 0] M_AXI_GP0_AWSIZE; + bit [2 : 0] M_AXI_GP0_ARPROT; + bit [2 : 0] M_AXI_GP0_AWPROT; + bit [31 : 0] M_AXI_GP0_ARADDR; + bit [31 : 0] M_AXI_GP0_AWADDR; + bit [31 : 0] M_AXI_GP0_WDATA; + bit [3 : 0] M_AXI_GP0_ARCACHE; + bit [3 : 0] M_AXI_GP0_ARLEN; + bit [3 : 0] M_AXI_GP0_ARQOS; + bit [3 : 0] M_AXI_GP0_AWCACHE; + bit [3 : 0] M_AXI_GP0_AWLEN; + bit [3 : 0] M_AXI_GP0_AWQOS; + bit [3 : 0] M_AXI_GP0_WSTRB; + bit M_AXI_GP0_ACLK; + bit M_AXI_GP0_ARREADY; + bit M_AXI_GP0_AWREADY; + bit M_AXI_GP0_BVALID; + bit M_AXI_GP0_RLAST; + bit M_AXI_GP0_RVALID; + bit M_AXI_GP0_WREADY; + bit [11 : 0] M_AXI_GP0_BID; + bit [11 : 0] M_AXI_GP0_RID; + bit [1 : 0] M_AXI_GP0_BRESP; + bit [1 : 0] M_AXI_GP0_RRESP; + bit [31 : 0] M_AXI_GP0_RDATA; + bit M_AXI_GP1_ARVALID; + bit M_AXI_GP1_AWVALID; + bit M_AXI_GP1_BREADY; + bit M_AXI_GP1_RREADY; + bit M_AXI_GP1_WLAST; + bit M_AXI_GP1_WVALID; + bit [11 : 0] M_AXI_GP1_ARID; + bit [11 : 0] M_AXI_GP1_AWID; + bit [11 : 0] M_AXI_GP1_WID; + bit [1 : 0] M_AXI_GP1_ARBURST; + bit [1 : 0] M_AXI_GP1_ARLOCK; + bit [2 : 0] M_AXI_GP1_ARSIZE; + bit [1 : 0] M_AXI_GP1_AWBURST; + bit [1 : 0] M_AXI_GP1_AWLOCK; + bit [2 : 0] M_AXI_GP1_AWSIZE; + bit [2 : 0] M_AXI_GP1_ARPROT; + bit [2 : 0] M_AXI_GP1_AWPROT; + bit [31 : 0] M_AXI_GP1_ARADDR; + bit [31 : 0] M_AXI_GP1_AWADDR; + bit [31 : 0] M_AXI_GP1_WDATA; + bit [3 : 0] M_AXI_GP1_ARCACHE; + bit [3 : 0] M_AXI_GP1_ARLEN; + bit [3 : 0] M_AXI_GP1_ARQOS; + bit [3 : 0] M_AXI_GP1_AWCACHE; + bit [3 : 0] M_AXI_GP1_AWLEN; + bit [3 : 0] M_AXI_GP1_AWQOS; + bit [3 : 0] M_AXI_GP1_WSTRB; + bit M_AXI_GP1_ACLK; + bit M_AXI_GP1_ARREADY; + bit M_AXI_GP1_AWREADY; + bit M_AXI_GP1_BVALID; + bit M_AXI_GP1_RLAST; + bit M_AXI_GP1_RVALID; + bit M_AXI_GP1_WREADY; + bit [11 : 0] M_AXI_GP1_BID; + bit [11 : 0] M_AXI_GP1_RID; + bit [1 : 0] M_AXI_GP1_BRESP; + bit [1 : 0] M_AXI_GP1_RRESP; + bit [31 : 0] M_AXI_GP1_RDATA; + bit S_AXI_GP0_ARREADY; + bit S_AXI_GP0_AWREADY; + bit S_AXI_GP0_BVALID; + bit S_AXI_GP0_RLAST; + bit S_AXI_GP0_RVALID; + bit S_AXI_GP0_WREADY; + bit [1 : 0] S_AXI_GP0_BRESP; + bit [1 : 0] S_AXI_GP0_RRESP; + bit [31 : 0] S_AXI_GP0_RDATA; + bit [5 : 0] S_AXI_GP0_BID; + bit [5 : 0] S_AXI_GP0_RID; + bit S_AXI_GP0_ACLK; + bit S_AXI_GP0_ARVALID; + bit S_AXI_GP0_AWVALID; + bit S_AXI_GP0_BREADY; + bit S_AXI_GP0_RREADY; + bit S_AXI_GP0_WLAST; + bit S_AXI_GP0_WVALID; + bit [1 : 0] S_AXI_GP0_ARBURST; + bit [1 : 0] S_AXI_GP0_ARLOCK; + bit [2 : 0] S_AXI_GP0_ARSIZE; + bit [1 : 0] S_AXI_GP0_AWBURST; + bit [1 : 0] S_AXI_GP0_AWLOCK; + bit [2 : 0] S_AXI_GP0_AWSIZE; + bit [2 : 0] S_AXI_GP0_ARPROT; + bit [2 : 0] S_AXI_GP0_AWPROT; + bit [31 : 0] S_AXI_GP0_ARADDR; + bit [31 : 0] S_AXI_GP0_AWADDR; + bit [31 : 0] S_AXI_GP0_WDATA; + bit [3 : 0] S_AXI_GP0_ARCACHE; + bit [3 : 0] S_AXI_GP0_ARLEN; + bit [3 : 0] S_AXI_GP0_ARQOS; + bit [3 : 0] S_AXI_GP0_AWCACHE; + bit [3 : 0] S_AXI_GP0_AWLEN; + bit [3 : 0] S_AXI_GP0_AWQOS; + bit [3 : 0] S_AXI_GP0_WSTRB; + bit [5 : 0] S_AXI_GP0_ARID; + bit [5 : 0] S_AXI_GP0_AWID; + bit [5 : 0] S_AXI_GP0_WID; + bit S_AXI_GP1_ARREADY; + bit S_AXI_GP1_AWREADY; + bit S_AXI_GP1_BVALID; + bit S_AXI_GP1_RLAST; + bit S_AXI_GP1_RVALID; + bit S_AXI_GP1_WREADY; + bit [1 : 0] S_AXI_GP1_BRESP; + bit [1 : 0] S_AXI_GP1_RRESP; + bit [31 : 0] S_AXI_GP1_RDATA; + bit [5 : 0] S_AXI_GP1_BID; + bit [5 : 0] S_AXI_GP1_RID; + bit S_AXI_GP1_ACLK; + bit S_AXI_GP1_ARVALID; + bit S_AXI_GP1_AWVALID; + bit S_AXI_GP1_BREADY; + bit S_AXI_GP1_RREADY; + bit S_AXI_GP1_WLAST; + bit S_AXI_GP1_WVALID; + bit [1 : 0] S_AXI_GP1_ARBURST; + bit [1 : 0] S_AXI_GP1_ARLOCK; + bit [2 : 0] S_AXI_GP1_ARSIZE; + bit [1 : 0] S_AXI_GP1_AWBURST; + bit [1 : 0] S_AXI_GP1_AWLOCK; + bit [2 : 0] S_AXI_GP1_AWSIZE; + bit [2 : 0] S_AXI_GP1_ARPROT; + bit [2 : 0] S_AXI_GP1_AWPROT; + bit [31 : 0] S_AXI_GP1_ARADDR; + bit [31 : 0] S_AXI_GP1_AWADDR; + bit [31 : 0] S_AXI_GP1_WDATA; + bit [3 : 0] S_AXI_GP1_ARCACHE; + bit [3 : 0] S_AXI_GP1_ARLEN; + bit [3 : 0] S_AXI_GP1_ARQOS; + bit [3 : 0] S_AXI_GP1_AWCACHE; + bit [3 : 0] S_AXI_GP1_AWLEN; + bit [3 : 0] S_AXI_GP1_AWQOS; + bit [3 : 0] S_AXI_GP1_WSTRB; + bit [5 : 0] S_AXI_GP1_ARID; + bit [5 : 0] S_AXI_GP1_AWID; + bit [5 : 0] S_AXI_GP1_WID; + bit S_AXI_ACP_ARREADY; + bit S_AXI_ACP_AWREADY; + bit S_AXI_ACP_BVALID; + bit S_AXI_ACP_RLAST; + bit S_AXI_ACP_RVALID; + bit S_AXI_ACP_WREADY; + bit [1 : 0] S_AXI_ACP_BRESP; + bit [1 : 0] S_AXI_ACP_RRESP; + bit [2 : 0] S_AXI_ACP_BID; + bit [2 : 0] S_AXI_ACP_RID; + bit [63 : 0] S_AXI_ACP_RDATA; + bit S_AXI_ACP_ACLK; + bit S_AXI_ACP_ARVALID; + bit S_AXI_ACP_AWVALID; + bit S_AXI_ACP_BREADY; + bit S_AXI_ACP_RREADY; + bit S_AXI_ACP_WLAST; + bit S_AXI_ACP_WVALID; + bit [2 : 0] S_AXI_ACP_ARID; + bit [2 : 0] S_AXI_ACP_ARPROT; + bit [2 : 0] S_AXI_ACP_AWID; + bit [2 : 0] S_AXI_ACP_AWPROT; + bit [2 : 0] S_AXI_ACP_WID; + bit [31 : 0] S_AXI_ACP_ARADDR; + bit [31 : 0] S_AXI_ACP_AWADDR; + bit [3 : 0] S_AXI_ACP_ARCACHE; + bit [3 : 0] S_AXI_ACP_ARLEN; + bit [3 : 0] S_AXI_ACP_ARQOS; + bit [3 : 0] S_AXI_ACP_AWCACHE; + bit [3 : 0] S_AXI_ACP_AWLEN; + bit [3 : 0] S_AXI_ACP_AWQOS; + bit [1 : 0] S_AXI_ACP_ARBURST; + bit [1 : 0] S_AXI_ACP_ARLOCK; + bit [2 : 0] S_AXI_ACP_ARSIZE; + bit [1 : 0] S_AXI_ACP_AWBURST; + bit [1 : 0] S_AXI_ACP_AWLOCK; + bit [2 : 0] S_AXI_ACP_AWSIZE; + bit [4 : 0] S_AXI_ACP_ARUSER; + bit [4 : 0] S_AXI_ACP_AWUSER; + bit [63 : 0] S_AXI_ACP_WDATA; + bit [7 : 0] S_AXI_ACP_WSTRB; + bit S_AXI_HP0_ARREADY; + bit S_AXI_HP0_AWREADY; + bit S_AXI_HP0_BVALID; + bit S_AXI_HP0_RLAST; + bit S_AXI_HP0_RVALID; + bit S_AXI_HP0_WREADY; + bit [1 : 0] S_AXI_HP0_BRESP; + bit [1 : 0] S_AXI_HP0_RRESP; + bit [5 : 0] S_AXI_HP0_BID; + bit [5 : 0] S_AXI_HP0_RID; + bit [63 : 0] S_AXI_HP0_RDATA; + bit [7 : 0] S_AXI_HP0_RCOUNT; + bit [7 : 0] S_AXI_HP0_WCOUNT; + bit [2 : 0] S_AXI_HP0_RACOUNT; + bit [5 : 0] S_AXI_HP0_WACOUNT; + bit S_AXI_HP0_ACLK; + bit S_AXI_HP0_ARVALID; + bit S_AXI_HP0_AWVALID; + bit S_AXI_HP0_BREADY; + bit S_AXI_HP0_RDISSUECAP1_EN; + bit S_AXI_HP0_RREADY; + bit S_AXI_HP0_WLAST; + bit S_AXI_HP0_WRISSUECAP1_EN; + bit S_AXI_HP0_WVALID; + bit [1 : 0] S_AXI_HP0_ARBURST; + bit [1 : 0] S_AXI_HP0_ARLOCK; + bit [2 : 0] S_AXI_HP0_ARSIZE; + bit [1 : 0] S_AXI_HP0_AWBURST; + bit [1 : 0] S_AXI_HP0_AWLOCK; + bit [2 : 0] S_AXI_HP0_AWSIZE; + bit [2 : 0] S_AXI_HP0_ARPROT; + bit [2 : 0] S_AXI_HP0_AWPROT; + bit [31 : 0] S_AXI_HP0_ARADDR; + bit [31 : 0] S_AXI_HP0_AWADDR; + bit [3 : 0] S_AXI_HP0_ARCACHE; + bit [3 : 0] S_AXI_HP0_ARLEN; + bit [3 : 0] S_AXI_HP0_ARQOS; + bit [3 : 0] S_AXI_HP0_AWCACHE; + bit [3 : 0] S_AXI_HP0_AWLEN; + bit [3 : 0] S_AXI_HP0_AWQOS; + bit [5 : 0] S_AXI_HP0_ARID; + bit [5 : 0] S_AXI_HP0_AWID; + bit [5 : 0] S_AXI_HP0_WID; + bit [63 : 0] S_AXI_HP0_WDATA; + bit [7 : 0] S_AXI_HP0_WSTRB; + bit S_AXI_HP1_ARREADY; + bit S_AXI_HP1_AWREADY; + bit S_AXI_HP1_BVALID; + bit S_AXI_HP1_RLAST; + bit S_AXI_HP1_RVALID; + bit S_AXI_HP1_WREADY; + bit [1 : 0] S_AXI_HP1_BRESP; + bit [1 : 0] S_AXI_HP1_RRESP; + bit [5 : 0] S_AXI_HP1_BID; + bit [5 : 0] S_AXI_HP1_RID; + bit [63 : 0] S_AXI_HP1_RDATA; + bit [7 : 0] S_AXI_HP1_RCOUNT; + bit [7 : 0] S_AXI_HP1_WCOUNT; + bit [2 : 0] S_AXI_HP1_RACOUNT; + bit [5 : 0] S_AXI_HP1_WACOUNT; + bit S_AXI_HP1_ACLK; + bit S_AXI_HP1_ARVALID; + bit S_AXI_HP1_AWVALID; + bit S_AXI_HP1_BREADY; + bit S_AXI_HP1_RDISSUECAP1_EN; + bit S_AXI_HP1_RREADY; + bit S_AXI_HP1_WLAST; + bit S_AXI_HP1_WRISSUECAP1_EN; + bit S_AXI_HP1_WVALID; + bit [1 : 0] S_AXI_HP1_ARBURST; + bit [1 : 0] S_AXI_HP1_ARLOCK; + bit [2 : 0] S_AXI_HP1_ARSIZE; + bit [1 : 0] S_AXI_HP1_AWBURST; + bit [1 : 0] S_AXI_HP1_AWLOCK; + bit [2 : 0] S_AXI_HP1_AWSIZE; + bit [2 : 0] S_AXI_HP1_ARPROT; + bit [2 : 0] S_AXI_HP1_AWPROT; + bit [31 : 0] S_AXI_HP1_ARADDR; + bit [31 : 0] S_AXI_HP1_AWADDR; + bit [3 : 0] S_AXI_HP1_ARCACHE; + bit [3 : 0] S_AXI_HP1_ARLEN; + bit [3 : 0] S_AXI_HP1_ARQOS; + bit [3 : 0] S_AXI_HP1_AWCACHE; + bit [3 : 0] S_AXI_HP1_AWLEN; + bit [3 : 0] S_AXI_HP1_AWQOS; + bit [5 : 0] S_AXI_HP1_ARID; + bit [5 : 0] S_AXI_HP1_AWID; + bit [5 : 0] S_AXI_HP1_WID; + bit [63 : 0] S_AXI_HP1_WDATA; + bit [7 : 0] S_AXI_HP1_WSTRB; + bit S_AXI_HP2_ARREADY; + bit S_AXI_HP2_AWREADY; + bit S_AXI_HP2_BVALID; + bit S_AXI_HP2_RLAST; + bit S_AXI_HP2_RVALID; + bit S_AXI_HP2_WREADY; + bit [1 : 0] S_AXI_HP2_BRESP; + bit [1 : 0] S_AXI_HP2_RRESP; + bit [5 : 0] S_AXI_HP2_BID; + bit [5 : 0] S_AXI_HP2_RID; + bit [63 : 0] S_AXI_HP2_RDATA; + bit [7 : 0] S_AXI_HP2_RCOUNT; + bit [7 : 0] S_AXI_HP2_WCOUNT; + bit [2 : 0] S_AXI_HP2_RACOUNT; + bit [5 : 0] S_AXI_HP2_WACOUNT; + bit S_AXI_HP2_ACLK; + bit S_AXI_HP2_ARVALID; + bit S_AXI_HP2_AWVALID; + bit S_AXI_HP2_BREADY; + bit S_AXI_HP2_RDISSUECAP1_EN; + bit S_AXI_HP2_RREADY; + bit S_AXI_HP2_WLAST; + bit S_AXI_HP2_WRISSUECAP1_EN; + bit S_AXI_HP2_WVALID; + bit [1 : 0] S_AXI_HP2_ARBURST; + bit [1 : 0] S_AXI_HP2_ARLOCK; + bit [2 : 0] S_AXI_HP2_ARSIZE; + bit [1 : 0] S_AXI_HP2_AWBURST; + bit [1 : 0] S_AXI_HP2_AWLOCK; + bit [2 : 0] S_AXI_HP2_AWSIZE; + bit [2 : 0] S_AXI_HP2_ARPROT; + bit [2 : 0] S_AXI_HP2_AWPROT; + bit [31 : 0] S_AXI_HP2_ARADDR; + bit [31 : 0] S_AXI_HP2_AWADDR; + bit [3 : 0] S_AXI_HP2_ARCACHE; + bit [3 : 0] S_AXI_HP2_ARLEN; + bit [3 : 0] S_AXI_HP2_ARQOS; + bit [3 : 0] S_AXI_HP2_AWCACHE; + bit [3 : 0] S_AXI_HP2_AWLEN; + bit [3 : 0] S_AXI_HP2_AWQOS; + bit [5 : 0] S_AXI_HP2_ARID; + bit [5 : 0] S_AXI_HP2_AWID; + bit [5 : 0] S_AXI_HP2_WID; + bit [63 : 0] S_AXI_HP2_WDATA; + bit [7 : 0] S_AXI_HP2_WSTRB; + bit S_AXI_HP3_ARREADY; + bit S_AXI_HP3_AWREADY; + bit S_AXI_HP3_BVALID; + bit S_AXI_HP3_RLAST; + bit S_AXI_HP3_RVALID; + bit S_AXI_HP3_WREADY; + bit [1 : 0] S_AXI_HP3_BRESP; + bit [1 : 0] S_AXI_HP3_RRESP; + bit [5 : 0] S_AXI_HP3_BID; + bit [5 : 0] S_AXI_HP3_RID; + bit [63 : 0] S_AXI_HP3_RDATA; + bit [7 : 0] S_AXI_HP3_RCOUNT; + bit [7 : 0] S_AXI_HP3_WCOUNT; + bit [2 : 0] S_AXI_HP3_RACOUNT; + bit [5 : 0] S_AXI_HP3_WACOUNT; + bit S_AXI_HP3_ACLK; + bit S_AXI_HP3_ARVALID; + bit S_AXI_HP3_AWVALID; + bit S_AXI_HP3_BREADY; + bit S_AXI_HP3_RDISSUECAP1_EN; + bit S_AXI_HP3_RREADY; + bit S_AXI_HP3_WLAST; + bit S_AXI_HP3_WRISSUECAP1_EN; + bit S_AXI_HP3_WVALID; + bit [1 : 0] S_AXI_HP3_ARBURST; + bit [1 : 0] S_AXI_HP3_ARLOCK; + bit [2 : 0] S_AXI_HP3_ARSIZE; + bit [1 : 0] S_AXI_HP3_AWBURST; + bit [1 : 0] S_AXI_HP3_AWLOCK; + bit [2 : 0] S_AXI_HP3_AWSIZE; + bit [2 : 0] S_AXI_HP3_ARPROT; + bit [2 : 0] S_AXI_HP3_AWPROT; + bit [31 : 0] S_AXI_HP3_ARADDR; + bit [31 : 0] S_AXI_HP3_AWADDR; + bit [3 : 0] S_AXI_HP3_ARCACHE; + bit [3 : 0] S_AXI_HP3_ARLEN; + bit [3 : 0] S_AXI_HP3_ARQOS; + bit [3 : 0] S_AXI_HP3_AWCACHE; + bit [3 : 0] S_AXI_HP3_AWLEN; + bit [3 : 0] S_AXI_HP3_AWQOS; + bit [5 : 0] S_AXI_HP3_ARID; + bit [5 : 0] S_AXI_HP3_AWID; + bit [5 : 0] S_AXI_HP3_WID; + bit [63 : 0] S_AXI_HP3_WDATA; + bit [7 : 0] S_AXI_HP3_WSTRB; + bit IRQ_P2F_DMAC_ABORT; + bit IRQ_P2F_DMAC0; + bit IRQ_P2F_DMAC1; + bit IRQ_P2F_DMAC2; + bit IRQ_P2F_DMAC3; + bit IRQ_P2F_DMAC4; + bit IRQ_P2F_DMAC5; + bit IRQ_P2F_DMAC6; + bit IRQ_P2F_DMAC7; + bit IRQ_P2F_SMC; + bit IRQ_P2F_QSPI; + bit IRQ_P2F_CTI; + bit IRQ_P2F_GPIO; + bit IRQ_P2F_USB0; + bit IRQ_P2F_ENET0; + bit IRQ_P2F_ENET_WAKE0; + bit IRQ_P2F_SDIO0; + bit IRQ_P2F_I2C0; + bit IRQ_P2F_SPI0; + bit IRQ_P2F_UART0; + bit IRQ_P2F_CAN0; + bit IRQ_P2F_USB1; + bit IRQ_P2F_ENET1; + bit IRQ_P2F_ENET_WAKE1; + bit IRQ_P2F_SDIO1; + bit IRQ_P2F_I2C1; + bit IRQ_P2F_SPI1; + bit IRQ_P2F_UART1; + bit IRQ_P2F_CAN1; + bit [1 : 0] IRQ_F2P; + bit Core0_nFIQ; + bit Core0_nIRQ; + bit Core1_nFIQ; + bit Core1_nIRQ; + bit [1 : 0] DMA0_DATYPE; + bit DMA0_DAVALID; + bit DMA0_DRREADY; + bit [1 : 0] DMA1_DATYPE; + bit DMA1_DAVALID; + bit DMA1_DRREADY; + bit [1 : 0] DMA2_DATYPE; + bit DMA2_DAVALID; + bit DMA2_DRREADY; + bit [1 : 0] DMA3_DATYPE; + bit DMA3_DAVALID; + bit DMA3_DRREADY; + bit DMA0_ACLK; + bit DMA0_DAREADY; + bit DMA0_DRLAST; + bit DMA0_DRVALID; + bit DMA1_ACLK; + bit DMA1_DAREADY; + bit DMA1_DRLAST; + bit DMA1_DRVALID; + bit DMA2_ACLK; + bit DMA2_DAREADY; + bit DMA2_DRLAST; + bit DMA2_DRVALID; + bit DMA3_ACLK; + bit DMA3_DAREADY; + bit DMA3_DRLAST; + bit DMA3_DRVALID; + bit [1 : 0] DMA0_DRTYPE; + bit [1 : 0] DMA1_DRTYPE; + bit [1 : 0] DMA2_DRTYPE; + bit [1 : 0] DMA3_DRTYPE; + bit FCLK_CLK0; + bit FCLK_CLK1; + bit FCLK_CLK2; + bit FCLK_CLK3; + bit FCLK_CLKTRIG0_N; + bit FCLK_CLKTRIG1_N; + bit FCLK_CLKTRIG2_N; + bit FCLK_CLKTRIG3_N; + bit FCLK_RESET0_N; + bit FCLK_RESET1_N; + bit FCLK_RESET2_N; + bit FCLK_RESET3_N; + bit [31 : 0] FTMD_TRACEIN_DATA; + bit FTMD_TRACEIN_VALID; + bit FTMD_TRACEIN_CLK; + bit [3 : 0] FTMD_TRACEIN_ATID; + bit FTMT_F2P_TRIG_0; + bit FTMT_F2P_TRIGACK_0; + bit FTMT_F2P_TRIG_1; + bit FTMT_F2P_TRIGACK_1; + bit FTMT_F2P_TRIG_2; + bit FTMT_F2P_TRIGACK_2; + bit FTMT_F2P_TRIG_3; + bit FTMT_F2P_TRIGACK_3; + bit [31 : 0] FTMT_F2P_DEBUG; + bit FTMT_P2F_TRIGACK_0; + bit FTMT_P2F_TRIG_0; + bit FTMT_P2F_TRIGACK_1; + bit FTMT_P2F_TRIG_1; + bit FTMT_P2F_TRIGACK_2; + bit FTMT_P2F_TRIG_2; + bit FTMT_P2F_TRIGACK_3; + bit FTMT_P2F_TRIG_3; + bit [31 : 0] FTMT_P2F_DEBUG; + bit FPGA_IDLE_N; + bit EVENT_EVENTO; + bit [1 : 0] EVENT_STANDBYWFE; + bit [1 : 0] EVENT_STANDBYWFI; + bit EVENT_EVENTI; + bit [3 : 0] DDR_ARB; + bit [53 : 0] MIO; + bit DDR_CAS_n; + bit DDR_CKE; + bit DDR_Clk_n; + bit DDR_Clk; + bit DDR_CS_n; + bit DDR_DRSTB; + bit DDR_ODT; + bit DDR_RAS_n; + bit DDR_WEB; + bit [2 : 0] DDR_BankAddr; + bit [14 : 0] DDR_Addr; + bit DDR_VRN; + bit DDR_VRP; + bit [3 : 0] DDR_DM; + bit [31 : 0] DDR_DQ; + bit [3 : 0] DDR_DQS_n; + bit [3 : 0] DDR_DQS; + bit PS_SRSTB; + bit PS_CLK; + bit PS_PORB; + +//MODULE DECLARATION + module system_processing_system7_0_0 ( + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + FCLK_CLK0, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB + ); + +//PARAMETERS + + parameter C_EN_EMIO_PJTAG = 0; + parameter C_EN_EMIO_ENET0 = 0; + parameter C_EN_EMIO_ENET1 = 0; + parameter C_EN_EMIO_TRACE = 0; + parameter C_INCLUDE_TRACE_BUFFER = 0; + parameter C_TRACE_BUFFER_FIFO_SIZE = 128; + parameter USE_TRACE_DATA_EDGE_DETECTOR = 0; + parameter C_TRACE_PIPELINE_WIDTH = 8; + parameter C_TRACE_BUFFER_CLOCK_DELAY = 12; + parameter C_EMIO_GPIO_WIDTH = 64; + parameter C_INCLUDE_ACP_TRANS_CHECK = 0; + parameter C_USE_DEFAULT_ACP_USER_VAL = 0; + parameter C_S_AXI_ACP_ARUSER_VAL = 31; + parameter C_S_AXI_ACP_AWUSER_VAL = 31; + parameter C_M_AXI_GP0_ID_WIDTH = 12; + parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; + parameter C_M_AXI_GP1_ID_WIDTH = 12; + parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; + parameter C_S_AXI_GP0_ID_WIDTH = 6; + parameter C_S_AXI_GP1_ID_WIDTH = 6; + parameter C_S_AXI_ACP_ID_WIDTH = 3; + parameter C_S_AXI_HP0_ID_WIDTH = 6; + parameter C_S_AXI_HP0_DATA_WIDTH = 64; + parameter C_S_AXI_HP1_ID_WIDTH = 6; + parameter C_S_AXI_HP1_DATA_WIDTH = 64; + parameter C_S_AXI_HP2_ID_WIDTH = 6; + parameter C_S_AXI_HP2_DATA_WIDTH = 64; + parameter C_S_AXI_HP3_ID_WIDTH = 6; + parameter C_S_AXI_HP3_DATA_WIDTH = 64; + parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; + parameter C_NUM_F2P_INTR_INPUTS = 2; + parameter C_IRQ_F2P_MODE = "DIRECT"; + parameter C_DQ_WIDTH = 32; + parameter C_DQS_WIDTH = 4; + parameter C_DM_WIDTH = 4; + parameter C_MIO_PRIMITIVE = 54; + parameter C_TRACE_INTERNAL_WIDTH = 2; + parameter C_USE_AXI_NONSECURE = 0; + parameter C_USE_M_AXI_GP0 = 1; + parameter C_USE_M_AXI_GP1 = 0; + parameter C_USE_S_AXI_GP0 = 0; + parameter C_USE_S_AXI_GP1 = 0; + parameter C_USE_S_AXI_HP0 = 0; + parameter C_USE_S_AXI_HP1 = 0; + parameter C_USE_S_AXI_HP2 = 0; + parameter C_USE_S_AXI_HP3 = 0; + parameter C_USE_S_AXI_ACP = 0; + parameter C_PS7_SI_REV = "PRODUCTION"; + parameter C_FCLK_CLK0_BUF = "TRUE"; + parameter C_FCLK_CLK1_BUF = "FALSE"; + parameter C_FCLK_CLK2_BUF = "FALSE"; + parameter C_FCLK_CLK3_BUF = "FALSE"; + parameter C_PACKAGE_NAME = "clg400"; + parameter C_GP0_EN_MODIFIABLE_TXN = "0"; + parameter C_GP1_EN_MODIFIABLE_TXN = "0"; + +//INPUT AND OUTPUT PORTS + + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11 : 0] M_AXI_GP0_ARID; + output [11 : 0] M_AXI_GP0_AWID; + output [11 : 0] M_AXI_GP0_WID; + output [1 : 0] M_AXI_GP0_ARBURST; + output [1 : 0] M_AXI_GP0_ARLOCK; + output [2 : 0] M_AXI_GP0_ARSIZE; + output [1 : 0] M_AXI_GP0_AWBURST; + output [1 : 0] M_AXI_GP0_AWLOCK; + output [2 : 0] M_AXI_GP0_AWSIZE; + output [2 : 0] M_AXI_GP0_ARPROT; + output [2 : 0] M_AXI_GP0_AWPROT; + output [31 : 0] M_AXI_GP0_ARADDR; + output [31 : 0] M_AXI_GP0_AWADDR; + output [31 : 0] M_AXI_GP0_WDATA; + output [3 : 0] M_AXI_GP0_ARCACHE; + output [3 : 0] M_AXI_GP0_ARLEN; + output [3 : 0] M_AXI_GP0_ARQOS; + output [3 : 0] M_AXI_GP0_AWCACHE; + output [3 : 0] M_AXI_GP0_AWLEN; + output [3 : 0] M_AXI_GP0_AWQOS; + output [3 : 0] M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11 : 0] M_AXI_GP0_BID; + input [11 : 0] M_AXI_GP0_RID; + input [1 : 0] M_AXI_GP0_BRESP; + input [1 : 0] M_AXI_GP0_RRESP; + input [31 : 0] M_AXI_GP0_RDATA; + output FCLK_CLK0; + output FCLK_RESET0_N; + inout [53 : 0] MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2 : 0] DDR_BankAddr; + inout [14 : 0] DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [3 : 0] DDR_DM; + inout [31 : 0] DDR_DQ; + inout [3 : 0] DDR_DQS_n; + inout [3 : 0] DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; + +//REG DECLARATIONS + + reg M_AXI_GP0_ARVALID; + reg M_AXI_GP0_AWVALID; + reg M_AXI_GP0_BREADY; + reg M_AXI_GP0_RREADY; + reg M_AXI_GP0_WLAST; + reg M_AXI_GP0_WVALID; + reg [11 : 0] M_AXI_GP0_ARID; + reg [11 : 0] M_AXI_GP0_AWID; + reg [11 : 0] M_AXI_GP0_WID; + reg [1 : 0] M_AXI_GP0_ARBURST; + reg [1 : 0] M_AXI_GP0_ARLOCK; + reg [2 : 0] M_AXI_GP0_ARSIZE; + reg [1 : 0] M_AXI_GP0_AWBURST; + reg [1 : 0] M_AXI_GP0_AWLOCK; + reg [2 : 0] M_AXI_GP0_AWSIZE; + reg [2 : 0] M_AXI_GP0_ARPROT; + reg [2 : 0] M_AXI_GP0_AWPROT; + reg [31 : 0] M_AXI_GP0_ARADDR; + reg [31 : 0] M_AXI_GP0_AWADDR; + reg [31 : 0] M_AXI_GP0_WDATA; + reg [3 : 0] M_AXI_GP0_ARCACHE; + reg [3 : 0] M_AXI_GP0_ARLEN; + reg [3 : 0] M_AXI_GP0_ARQOS; + reg [3 : 0] M_AXI_GP0_AWCACHE; + reg [3 : 0] M_AXI_GP0_AWLEN; + reg [3 : 0] M_AXI_GP0_AWQOS; + reg [3 : 0] M_AXI_GP0_WSTRB; + reg FCLK_CLK0; + reg FCLK_RESET0_N; + string ip_name; + reg disable_port; + +//DPI DECLARATIONS +import "DPI-C" function void ps7_set_ip_context(input string ip_name); +import "DPI-C" function void ps7_set_str_param(input string name,input string val); +import "DPI-C" function void ps7_set_int_param(input string name,input longint val); +import "DPI-C" function void ps7_init_c_model(); +import "DPI-C" function void ps7_init_m_axi_gp0(input int M_AXI_GP0_AWID_size,input int M_AXI_GP0_AWADDR_size,input int M_AXI_GP0_AWLEN_size,input int M_AXI_GP0_AWSIZE_size,input int M_AXI_GP0_AWBURST_size,input int M_AXI_GP0_AWLOCK_size,input int M_AXI_GP0_AWCACHE_size,input int M_AXI_GP0_AWPROT_size,input int M_AXI_GP0_AWQOS_size,input int M_AXI_GP0_AWVALID_size,input int M_AXI_GP0_AWREADY_size,input int M_AXI_GP0_WID_size,input int M_AXI_GP0_WDATA_size,input int M_AXI_GP0_WSTRB_size,input int M_AXI_GP0_WLAST_size,input int M_AXI_GP0_WVALID_size,input int M_AXI_GP0_WREADY_size,input int M_AXI_GP0_BID_size,input int M_AXI_GP0_BRESP_size,input int M_AXI_GP0_BVALID_size,input int M_AXI_GP0_BREADY_size,input int M_AXI_GP0_ARID_size,input int M_AXI_GP0_ARADDR_size,input int M_AXI_GP0_ARLEN_size,input int M_AXI_GP0_ARSIZE_size,input int M_AXI_GP0_ARBURST_size,input int M_AXI_GP0_ARLOCK_size,input int M_AXI_GP0_ARCACHE_size,input int M_AXI_GP0_ARPROT_size,input int M_AXI_GP0_ARQOS_size,input int M_AXI_GP0_ARVALID_size,input int M_AXI_GP0_ARREADY_size,input int M_AXI_GP0_RID_size,input int M_AXI_GP0_RDATA_size,input int M_AXI_GP0_RRESP_size,input int M_AXI_GP0_RLAST_size,input int M_AXI_GP0_RVALID_size,input int M_AXI_GP0_RREADY_size); +import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0(); +import "DPI-C" function void ps7_simulate_single_cycle_M_AXI_GP0_ACLK(); +import "DPI-C" function void ps7_set_inputs_m_axi_gp0_M_AXI_GP0_ACLK( +input bit M_AXI_GP0_AWREADY, +input bit M_AXI_GP0_WREADY, +input bit [11 : 0] M_AXI_GP0_BID, +input bit [1 : 0] M_AXI_GP0_BRESP, +input bit M_AXI_GP0_BVALID, +input bit M_AXI_GP0_ARREADY, +input bit [11 : 0] M_AXI_GP0_RID, +input bit [31 : 0] M_AXI_GP0_RDATA, +input bit [1 : 0] M_AXI_GP0_RRESP, +input bit M_AXI_GP0_RLAST, +input bit M_AXI_GP0_RVALID +); +import "DPI-C" function void ps7_get_outputs_m_axi_gp0_M_AXI_GP0_ACLK( +output bit [11 : 0] M_AXI_GP0_AWID, +output bit [31 : 0] M_AXI_GP0_AWADDR, +output bit [3 : 0] M_AXI_GP0_AWLEN, +output bit [2 : 0] M_AXI_GP0_AWSIZE, +output bit [1 : 0] M_AXI_GP0_AWBURST, +output bit [1 : 0] M_AXI_GP0_AWLOCK, +output bit [3 : 0] M_AXI_GP0_AWCACHE, +output bit [2 : 0] M_AXI_GP0_AWPROT, +output bit [3 : 0] M_AXI_GP0_AWQOS, +output bit M_AXI_GP0_AWVALID, +output bit [11 : 0] M_AXI_GP0_WID, +output bit [31 : 0] M_AXI_GP0_WDATA, +output bit [3 : 0] M_AXI_GP0_WSTRB, +output bit M_AXI_GP0_WLAST, +output bit M_AXI_GP0_WVALID, +output bit M_AXI_GP0_BREADY, +output bit [11 : 0] M_AXI_GP0_ARID, +output bit [31 : 0] M_AXI_GP0_ARADDR, +output bit [3 : 0] M_AXI_GP0_ARLEN, +output bit [2 : 0] M_AXI_GP0_ARSIZE, +output bit [1 : 0] M_AXI_GP0_ARBURST, +output bit [1 : 0] M_AXI_GP0_ARLOCK, +output bit [3 : 0] M_AXI_GP0_ARCACHE, +output bit [2 : 0] M_AXI_GP0_ARPROT, +output bit [3 : 0] M_AXI_GP0_ARQOS, +output bit M_AXI_GP0_ARVALID, +output bit M_AXI_GP0_RREADY +); + + export "DPI-C" function ps7_stop_sim; + function void ps7_stop_sim(); + $display("End of simulation"); + $finish(0); + endfunction + export "DPI-C" function ps7_get_time; + function real ps7_get_time(); + ps7_get_time = $time; + endfunction + + export "DPI-C" function ps7_set_output_pins_FCLK_RESET0_N; + function void ps7_set_output_pins_FCLK_RESET0_N(int value); + FCLK_RESET0_N = value; + endfunction + + export "DPI-C" function ps7_set_output_pins_FCLK_RESET1_N; + function void ps7_set_output_pins_FCLK_RESET1_N(int value); + FCLK_RESET1_N = value; + endfunction + + export "DPI-C" function ps7_set_output_pins_FCLK_RESET2_N; + function void ps7_set_output_pins_FCLK_RESET2_N(int value); + FCLK_RESET2_N = value; + endfunction + + export "DPI-C" function ps7_set_output_pins_FCLK_RESET3_N; + function void ps7_set_output_pins_FCLK_RESET3_N(int value); + FCLK_RESET3_N = value; + endfunction + + +//INITIAL BLOCK + + initial + begin + $sformat(ip_name,"%m"); + ps7_set_ip_context(ip_name); + ps7_set_int_param ( "C_EN_EMIO_PJTAG",C_EN_EMIO_PJTAG ); + ps7_set_int_param ( "C_EN_EMIO_ENET0",C_EN_EMIO_ENET0 ); + ps7_set_int_param ( "C_EN_EMIO_ENET1",C_EN_EMIO_ENET1 ); + ps7_set_int_param ( "C_EN_EMIO_TRACE",C_EN_EMIO_TRACE ); + ps7_set_int_param ( "C_INCLUDE_TRACE_BUFFER",C_INCLUDE_TRACE_BUFFER ); + ps7_set_int_param ( "C_TRACE_BUFFER_FIFO_SIZE",C_TRACE_BUFFER_FIFO_SIZE ); + ps7_set_int_param ( "USE_TRACE_DATA_EDGE_DETECTOR",USE_TRACE_DATA_EDGE_DETECTOR ); + ps7_set_int_param ( "C_TRACE_PIPELINE_WIDTH",C_TRACE_PIPELINE_WIDTH ); + ps7_set_int_param ( "C_TRACE_BUFFER_CLOCK_DELAY",C_TRACE_BUFFER_CLOCK_DELAY ); + ps7_set_int_param ( "C_EMIO_GPIO_WIDTH",C_EMIO_GPIO_WIDTH ); + ps7_set_int_param ( "C_INCLUDE_ACP_TRANS_CHECK",C_INCLUDE_ACP_TRANS_CHECK ); + ps7_set_int_param ( "C_USE_DEFAULT_ACP_USER_VAL",C_USE_DEFAULT_ACP_USER_VAL ); + ps7_set_int_param ( "C_S_AXI_ACP_ARUSER_VAL",C_S_AXI_ACP_ARUSER_VAL ); + ps7_set_int_param ( "C_S_AXI_ACP_AWUSER_VAL",C_S_AXI_ACP_AWUSER_VAL ); + ps7_set_int_param ( "C_M_AXI_GP0_ID_WIDTH",C_M_AXI_GP0_ID_WIDTH ); + ps7_set_int_param ( "C_M_AXI_GP0_ENABLE_STATIC_REMAP",C_M_AXI_GP0_ENABLE_STATIC_REMAP ); + ps7_set_int_param ( "C_M_AXI_GP1_ID_WIDTH",C_M_AXI_GP1_ID_WIDTH ); + ps7_set_int_param ( "C_M_AXI_GP1_ENABLE_STATIC_REMAP",C_M_AXI_GP1_ENABLE_STATIC_REMAP ); + ps7_set_int_param ( "C_S_AXI_GP0_ID_WIDTH",C_S_AXI_GP0_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_GP1_ID_WIDTH",C_S_AXI_GP1_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_ACP_ID_WIDTH",C_S_AXI_ACP_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP0_ID_WIDTH",C_S_AXI_HP0_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP0_DATA_WIDTH",C_S_AXI_HP0_DATA_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP1_ID_WIDTH",C_S_AXI_HP1_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP1_DATA_WIDTH",C_S_AXI_HP1_DATA_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP2_ID_WIDTH",C_S_AXI_HP2_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP2_DATA_WIDTH",C_S_AXI_HP2_DATA_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP3_ID_WIDTH",C_S_AXI_HP3_ID_WIDTH ); + ps7_set_int_param ( "C_S_AXI_HP3_DATA_WIDTH",C_S_AXI_HP3_DATA_WIDTH ); + ps7_set_int_param ( "C_M_AXI_GP0_THREAD_ID_WIDTH",C_M_AXI_GP0_THREAD_ID_WIDTH ); + ps7_set_int_param ( "C_M_AXI_GP1_THREAD_ID_WIDTH",C_M_AXI_GP1_THREAD_ID_WIDTH ); + ps7_set_int_param ( "C_NUM_F2P_INTR_INPUTS",C_NUM_F2P_INTR_INPUTS ); + ps7_set_str_param ( "C_IRQ_F2P_MODE",C_IRQ_F2P_MODE ); + ps7_set_int_param ( "C_DQ_WIDTH",C_DQ_WIDTH ); + ps7_set_int_param ( "C_DQS_WIDTH",C_DQS_WIDTH ); + ps7_set_int_param ( "C_DM_WIDTH",C_DM_WIDTH ); + ps7_set_int_param ( "C_MIO_PRIMITIVE",C_MIO_PRIMITIVE ); + ps7_set_int_param ( "C_TRACE_INTERNAL_WIDTH",C_TRACE_INTERNAL_WIDTH ); + ps7_set_int_param ( "C_USE_AXI_NONSECURE",C_USE_AXI_NONSECURE ); + ps7_set_int_param ( "C_USE_M_AXI_GP0",C_USE_M_AXI_GP0 ); + ps7_set_int_param ( "C_USE_M_AXI_GP1",C_USE_M_AXI_GP1 ); + ps7_set_int_param ( "C_USE_S_AXI_GP0",C_USE_S_AXI_GP0 ); + ps7_set_int_param ( "C_USE_S_AXI_GP1",C_USE_S_AXI_GP1 ); + ps7_set_int_param ( "C_USE_S_AXI_HP0",C_USE_S_AXI_HP0 ); + ps7_set_int_param ( "C_USE_S_AXI_HP1",C_USE_S_AXI_HP1 ); + ps7_set_int_param ( "C_USE_S_AXI_HP2",C_USE_S_AXI_HP2 ); + ps7_set_int_param ( "C_USE_S_AXI_HP3",C_USE_S_AXI_HP3 ); + ps7_set_int_param ( "C_USE_S_AXI_ACP",C_USE_S_AXI_ACP ); + ps7_set_str_param ( "C_PS7_SI_REV",C_PS7_SI_REV ); + ps7_set_str_param ( "C_FCLK_CLK0_BUF",C_FCLK_CLK0_BUF ); + ps7_set_str_param ( "C_FCLK_CLK1_BUF",C_FCLK_CLK1_BUF ); + ps7_set_str_param ( "C_FCLK_CLK2_BUF",C_FCLK_CLK2_BUF ); + ps7_set_str_param ( "C_FCLK_CLK3_BUF",C_FCLK_CLK3_BUF ); + ps7_set_str_param ( "C_PACKAGE_NAME",C_PACKAGE_NAME ); + ps7_set_str_param ( "C_GP0_EN_MODIFIABLE_TXN",C_GP0_EN_MODIFIABLE_TXN ); + ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN ); + + ps7_init_m_axi_gp0($bits(M_AXI_GP0_AWID),$bits(M_AXI_GP0_AWADDR),$bits(M_AXI_GP0_AWLEN),$bits(M_AXI_GP0_AWSIZE),$bits(M_AXI_GP0_AWBURST),$bits(M_AXI_GP0_AWLOCK),$bits(M_AXI_GP0_AWCACHE),$bits(M_AXI_GP0_AWPROT),$bits(M_AXI_GP0_AWQOS),$bits(M_AXI_GP0_AWVALID),$bits(M_AXI_GP0_AWREADY),$bits(M_AXI_GP0_WID),$bits(M_AXI_GP0_WDATA),$bits(M_AXI_GP0_WSTRB),$bits(M_AXI_GP0_WLAST),$bits(M_AXI_GP0_WVALID),$bits(M_AXI_GP0_WREADY),$bits(M_AXI_GP0_BID),$bits(M_AXI_GP0_BRESP),$bits(M_AXI_GP0_BVALID),$bits(M_AXI_GP0_BREADY),$bits(M_AXI_GP0_ARID),$bits(M_AXI_GP0_ARADDR),$bits(M_AXI_GP0_ARLEN),$bits(M_AXI_GP0_ARSIZE),$bits(M_AXI_GP0_ARBURST),$bits(M_AXI_GP0_ARLOCK),$bits(M_AXI_GP0_ARCACHE),$bits(M_AXI_GP0_ARPROT),$bits(M_AXI_GP0_ARQOS),$bits(M_AXI_GP0_ARVALID),$bits(M_AXI_GP0_ARREADY),$bits(M_AXI_GP0_RID),$bits(M_AXI_GP0_RDATA),$bits(M_AXI_GP0_RRESP),$bits(M_AXI_GP0_RLAST),$bits(M_AXI_GP0_RVALID),$bits(M_AXI_GP0_RREADY)); + ps7_init_c_model(); + end + initial + begin + FCLK_CLK0 = 1'b0; + end + + always #(10.0) FCLK_CLK0 <= ~FCLK_CLK0; + + always@(posedge FCLK_CLK0) + begin + ps7_set_ip_context(ip_name); + ps7_simulate_single_cycle_FCLK_CLK0(); + end + + +always@(posedge M_AXI_GP0_ACLK) + begin + + ps7_set_ip_context(ip_name); + + ps7_set_inputs_m_axi_gp0_M_AXI_GP0_ACLK( + M_AXI_GP0_AWREADY, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_BRESP, + M_AXI_GP0_BVALID, + M_AXI_GP0_ARREADY, + M_AXI_GP0_RID, + M_AXI_GP0_RDATA, + M_AXI_GP0_RRESP, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID + ); + + ps7_simulate_single_cycle_M_AXI_GP0_ACLK(); + + ps7_get_outputs_m_axi_gp0_M_AXI_GP0_ACLK( + M_AXI_GP0_AWID, + M_AXI_GP0_AWADDR, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWPROT, + M_AXI_GP0_AWQOS, + M_AXI_GP0_AWVALID, + M_AXI_GP0_WID, + M_AXI_GP0_WDATA, + M_AXI_GP0_WSTRB, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_ARID, + M_AXI_GP0_ARADDR, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_ARQOS, + M_AXI_GP0_ARVALID, + M_AXI_GP0_RREADY + ); + end + +endmodule + diff --git a/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v b/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v new file mode 100644 index 0000000..c917432 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v @@ -0,0 +1,578 @@ + + + +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +module system_processing_system7_0_0 ( +M_AXI_GP0_ARVALID, +M_AXI_GP0_AWVALID, +M_AXI_GP0_BREADY, +M_AXI_GP0_RREADY, +M_AXI_GP0_WLAST, +M_AXI_GP0_WVALID, +M_AXI_GP0_ARID, +M_AXI_GP0_AWID, +M_AXI_GP0_WID, +M_AXI_GP0_ARBURST, +M_AXI_GP0_ARLOCK, +M_AXI_GP0_ARSIZE, +M_AXI_GP0_AWBURST, +M_AXI_GP0_AWLOCK, +M_AXI_GP0_AWSIZE, +M_AXI_GP0_ARPROT, +M_AXI_GP0_AWPROT, +M_AXI_GP0_ARADDR, +M_AXI_GP0_AWADDR, +M_AXI_GP0_WDATA, +M_AXI_GP0_ARCACHE, +M_AXI_GP0_ARLEN, +M_AXI_GP0_ARQOS, +M_AXI_GP0_AWCACHE, +M_AXI_GP0_AWLEN, +M_AXI_GP0_AWQOS, +M_AXI_GP0_WSTRB, +M_AXI_GP0_ACLK, +M_AXI_GP0_ARREADY, +M_AXI_GP0_AWREADY, +M_AXI_GP0_BVALID, +M_AXI_GP0_RLAST, +M_AXI_GP0_RVALID, +M_AXI_GP0_WREADY, +M_AXI_GP0_BID, +M_AXI_GP0_RID, +M_AXI_GP0_BRESP, +M_AXI_GP0_RRESP, +M_AXI_GP0_RDATA, +FCLK_CLK0, +FCLK_RESET0_N, +MIO, +DDR_CAS_n, +DDR_CKE, +DDR_Clk_n, +DDR_Clk, +DDR_CS_n, +DDR_DRSTB, +DDR_ODT, +DDR_RAS_n, +DDR_WEB, +DDR_BankAddr, +DDR_Addr, +DDR_VRN, +DDR_VRP, +DDR_DM, +DDR_DQ, +DDR_DQS_n, +DDR_DQS, +PS_SRSTB, +PS_CLK, +PS_PORB +); +output M_AXI_GP0_ARVALID; +output M_AXI_GP0_AWVALID; +output M_AXI_GP0_BREADY; +output M_AXI_GP0_RREADY; +output M_AXI_GP0_WLAST; +output M_AXI_GP0_WVALID; +output [11 : 0] M_AXI_GP0_ARID; +output [11 : 0] M_AXI_GP0_AWID; +output [11 : 0] M_AXI_GP0_WID; +output [1 : 0] M_AXI_GP0_ARBURST; +output [1 : 0] M_AXI_GP0_ARLOCK; +output [2 : 0] M_AXI_GP0_ARSIZE; +output [1 : 0] M_AXI_GP0_AWBURST; +output [1 : 0] M_AXI_GP0_AWLOCK; +output [2 : 0] M_AXI_GP0_AWSIZE; +output [2 : 0] M_AXI_GP0_ARPROT; +output [2 : 0] M_AXI_GP0_AWPROT; +output [31 : 0] M_AXI_GP0_ARADDR; +output [31 : 0] M_AXI_GP0_AWADDR; +output [31 : 0] M_AXI_GP0_WDATA; +output [3 : 0] M_AXI_GP0_ARCACHE; +output [3 : 0] M_AXI_GP0_ARLEN; +output [3 : 0] M_AXI_GP0_ARQOS; +output [3 : 0] M_AXI_GP0_AWCACHE; +output [3 : 0] M_AXI_GP0_AWLEN; +output [3 : 0] M_AXI_GP0_AWQOS; +output [3 : 0] M_AXI_GP0_WSTRB; +input M_AXI_GP0_ACLK; +input M_AXI_GP0_ARREADY; +input M_AXI_GP0_AWREADY; +input M_AXI_GP0_BVALID; +input M_AXI_GP0_RLAST; +input M_AXI_GP0_RVALID; +input M_AXI_GP0_WREADY; +input [11 : 0] M_AXI_GP0_BID; +input [11 : 0] M_AXI_GP0_RID; +input [1 : 0] M_AXI_GP0_BRESP; +input [1 : 0] M_AXI_GP0_RRESP; +input [31 : 0] M_AXI_GP0_RDATA; +output FCLK_CLK0; +output FCLK_RESET0_N; +input [53 : 0] MIO; +input DDR_CAS_n; +input DDR_CKE; +input DDR_Clk_n; +input DDR_Clk; +input DDR_CS_n; +input DDR_DRSTB; +input DDR_ODT; +input DDR_RAS_n; +input DDR_WEB; +input [2 : 0] DDR_BankAddr; +input [14 : 0] DDR_Addr; +input DDR_VRN; +input DDR_VRP; +input [3 : 0] DDR_DM; +input [31 : 0] DDR_DQ; +input [3 : 0] DDR_DQS_n; +input [3 : 0] DDR_DQS; +input PS_SRSTB; +input PS_CLK; +input PS_PORB; + + processing_system7_vip_v1_0_3 #( + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_ACP(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(0), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_HIGH_OCM_EN(0), + .C_FCLK_CLK0_FREQ(50.0), + .C_FCLK_CLK1_FREQ(10.0), + .C_FCLK_CLK2_FREQ(10.0), + .C_FCLK_CLK3_FREQ(10.0), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP0_THREAD_ID_WIDTH (12), + .C_M_AXI_GP1_THREAD_ID_WIDTH (12) + ) inst ( + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(), + .S_AXI_HP0_AWREADY(), + .S_AXI_HP0_BVALID(), + .S_AXI_HP0_RLAST(), + .S_AXI_HP0_RVALID(), + .S_AXI_HP0_WREADY(), + .S_AXI_HP0_BRESP(), + .S_AXI_HP0_RRESP(), + .S_AXI_HP0_BID(), + .S_AXI_HP0_RID(), + .S_AXI_HP0_RDATA(), + .S_AXI_HP0_ACLK(1'B0), + .S_AXI_HP0_ARVALID(1'B0), + .S_AXI_HP0_AWVALID(1'B0), + .S_AXI_HP0_BREADY(1'B0), + .S_AXI_HP0_RREADY(1'B0), + .S_AXI_HP0_WLAST(1'B0), + .S_AXI_HP0_WVALID(1'B0), + .S_AXI_HP0_ARBURST(2'B0), + .S_AXI_HP0_ARLOCK(2'B0), + .S_AXI_HP0_ARSIZE(3'B0), + .S_AXI_HP0_AWBURST(2'B0), + .S_AXI_HP0_AWLOCK(2'B0), + .S_AXI_HP0_AWSIZE(3'B0), + .S_AXI_HP0_ARPROT(3'B0), + .S_AXI_HP0_AWPROT(3'B0), + .S_AXI_HP0_ARADDR(32'B0), + .S_AXI_HP0_AWADDR(32'B0), + .S_AXI_HP0_ARCACHE(4'B0), + .S_AXI_HP0_ARLEN(4'B0), + .S_AXI_HP0_ARQOS(4'B0), + .S_AXI_HP0_AWCACHE(4'B0), + .S_AXI_HP0_AWLEN(4'B0), + .S_AXI_HP0_AWQOS(4'B0), + .S_AXI_HP0_ARID(6'B0), + .S_AXI_HP0_AWID(6'B0), + .S_AXI_HP0_WID(6'B0), + .S_AXI_HP0_WDATA(64'B0), + .S_AXI_HP0_WSTRB(8'B0), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .FCLK_CLK0(FCLK_CLK0), + + .FCLK_CLK1(), + + .FCLK_CLK2(), + + .FCLK_CLK3(), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(), + .FCLK_RESET2_N(), + .FCLK_RESET3_N(), + .IRQ_F2P(IRQ_F2P), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/bd/system/sim/system.v b/Miz_sys/Miz_sys.ip_user_files/bd/system/sim/system.v new file mode 100644 index 0000000..355463b --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/bd/system/sim/system.v @@ -0,0 +1,115 @@ +//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +//Date : Sat May 25 13:08:00 2019 +//Host : LB-201810041430 running 64-bit major release (build 9200) +//Command : generate_target system.bd +//Design : system +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "system.hwdef" *) +module system + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb; + + wire [14:0]processing_system7_0_DDR_ADDR; + wire [2:0]processing_system7_0_DDR_BA; + wire processing_system7_0_DDR_CAS_N; + wire processing_system7_0_DDR_CKE; + wire processing_system7_0_DDR_CK_N; + wire processing_system7_0_DDR_CK_P; + wire processing_system7_0_DDR_CS_N; + wire [3:0]processing_system7_0_DDR_DM; + wire [31:0]processing_system7_0_DDR_DQ; + wire [3:0]processing_system7_0_DDR_DQS_N; + wire [3:0]processing_system7_0_DDR_DQS_P; + wire processing_system7_0_DDR_ODT; + wire processing_system7_0_DDR_RAS_N; + wire processing_system7_0_DDR_RESET_N; + wire processing_system7_0_DDR_WE_N; + wire processing_system7_0_FCLK_CLK0; + wire processing_system7_0_FIXED_IO_DDR_VRN; + wire processing_system7_0_FIXED_IO_DDR_VRP; + wire [53:0]processing_system7_0_FIXED_IO_MIO; + wire processing_system7_0_FIXED_IO_PS_CLK; + wire processing_system7_0_FIXED_IO_PS_PORB; + wire processing_system7_0_FIXED_IO_PS_SRSTB; + + system_processing_system7_0_0 processing_system7_0 + (.DDR_Addr(DDR_addr[14:0]), + .DDR_BankAddr(DDR_ba[2:0]), + .DDR_CAS_n(DDR_cas_n), + .DDR_CKE(DDR_cke), + .DDR_CS_n(DDR_cs_n), + .DDR_Clk(DDR_ck_p), + .DDR_Clk_n(DDR_ck_n), + .DDR_DM(DDR_dm[3:0]), + .DDR_DQ(DDR_dq[31:0]), + .DDR_DQS(DDR_dqs_p[3:0]), + .DDR_DQS_n(DDR_dqs_n[3:0]), + .DDR_DRSTB(DDR_reset_n), + .DDR_ODT(DDR_odt), + .DDR_RAS_n(DDR_ras_n), + .DDR_VRN(FIXED_IO_ddr_vrn), + .DDR_VRP(FIXED_IO_ddr_vrp), + .DDR_WEB(DDR_we_n), + .FCLK_CLK0(processing_system7_0_FCLK_CLK0), + .MIO(FIXED_IO_mio[53:0]), + .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0), + .M_AXI_GP0_ARREADY(1'b0), + .M_AXI_GP0_AWREADY(1'b0), + .M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_BRESP({1'b0,1'b0}), + .M_AXI_GP0_BVALID(1'b0), + .M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RLAST(1'b0), + .M_AXI_GP0_RRESP({1'b0,1'b0}), + .M_AXI_GP0_RVALID(1'b0), + .M_AXI_GP0_WREADY(1'b0), + .PS_CLK(FIXED_IO_ps_clk), + .PS_PORB(FIXED_IO_ps_porb), + .PS_SRSTB(FIXED_IO_ps_srstb)); +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_apis.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_apis.v new file mode 100644 index 0000000..9a06639 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_apis.v @@ -0,0 +1,825 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_apis.v + * + * Date : 2012-11 + * + * Description : Set of Zynq BFM APIs that are used for writing tests. + * + *****************************************************************************/ + + /* API for setting the STOP_ON_ERROR*/ + task automatic set_stop_on_error; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL); + STOP_ON_ERROR = LEVEL; + M_AXI_GP0.master.set_stop_on_error(LEVEL); + M_AXI_GP1.master.set_stop_on_error(LEVEL); + S_AXI_GP0.slave.set_stop_on_error(LEVEL); + S_AXI_GP1.slave.set_stop_on_error(LEVEL); + S_AXI_HP0.slave.set_stop_on_error(LEVEL); + S_AXI_HP1.slave.set_stop_on_error(LEVEL); + S_AXI_HP2.slave.set_stop_on_error(LEVEL); + S_AXI_HP3.slave.set_stop_on_error(LEVEL); + S_AXI_ACP.slave.set_stop_on_error(LEVEL); + M_AXI_GP0.STOP_ON_ERROR = LEVEL; + M_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_GP0.STOP_ON_ERROR = LEVEL; + S_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP0.STOP_ON_ERROR = LEVEL; + S_AXI_HP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP2.STOP_ON_ERROR = LEVEL; + S_AXI_HP3.STOP_ON_ERROR = LEVEL; + S_AXI_ACP.STOP_ON_ERROR = LEVEL; + + end + endtask + + /* API for setting the verbosity for channel level info*/ + task automatic set_channel_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) + "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL); + "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL); + "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL); + "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL); + "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL); + "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL); + "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL); + "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL); + "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL); + "ALL" : begin + M_AXI_GP0.master.set_channel_level_info(LEVEL); + M_AXI_GP1.master.set_channel_level_info(LEVEL); + S_AXI_GP0.slave.set_channel_level_info(LEVEL); + S_AXI_GP1.slave.set_channel_level_info(LEVEL); + S_AXI_HP0.slave.set_channel_level_info(LEVEL); + S_AXI_HP1.slave.set_channel_level_info(LEVEL); + S_AXI_HP2.slave.set_channel_level_info(LEVEL); + S_AXI_HP3.slave.set_channel_level_info(LEVEL); + S_AXI_ACP.slave.set_channel_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the verbosity for function level info*/ + task automatic set_function_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) + "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL); + "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL); + "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL); + "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL); + "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL); + "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL); + "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL); + "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL); + "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL); + "ALL" : begin + M_AXI_GP0.master.set_function_level_info(LEVEL); + M_AXI_GP1.master.set_function_level_info(LEVEL); + S_AXI_GP0.slave.set_function_level_info(LEVEL); + S_AXI_GP1.slave.set_function_level_info(LEVEL); + S_AXI_HP0.slave.set_function_level_info(LEVEL); + S_AXI_HP1.slave.set_function_level_info(LEVEL); + S_AXI_HP2.slave.set_function_level_info(LEVEL); + S_AXI_HP3.slave.set_function_level_info(LEVEL); + S_AXI_ACP.slave.set_function_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the Message verbosity */ + task automatic set_debug_level_info; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL); + DEBUG_INFO = LEVEL; + M_AXI_GP0.DEBUG_INFO = LEVEL; + M_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_GP0.DEBUG_INFO = LEVEL; + S_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_HP0.DEBUG_INFO = LEVEL; + S_AXI_HP1.DEBUG_INFO = LEVEL; + S_AXI_HP2.DEBUG_INFO = LEVEL; + S_AXI_HP3.DEBUG_INFO = LEVEL; + S_AXI_ACP.DEBUG_INFO = LEVEL; + end + endtask + + /* API for setting ARQos Values */ + task automatic set_arqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_arqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_arqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_arqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_arqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_arqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_arqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_arqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting AWQos Values */ + task automatic set_awqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_awqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_awqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_awqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_awqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_awqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_awqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_awqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for soft reset control */ + task automatic fpga_soft_reset; + input[data_width-1:0] reset_ctrl; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl); + gen_rst.fpga_soft_reset(reset_ctrl); + end + endtask + + /* API for pre-loading memories from (DDR/OCM model) */ + task automatic pre_load_mem_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for pre-loading memories (DDR/OCM) */ + task automatic pre_load_mem; + input [1:0] data_type; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API for backdoor write to memories (DDR/OCM) */ + task automatic write_mem; + input [max_burst_bits-1 :0] data; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.write_mem(data,start_addr,no_of_bytes); + else + ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.write_mem(data,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* read_memory */ + task automatic read_mem; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width :0] no_of_bytes; + output[max_burst_bits-1 :0] data; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.read_mem(data,start_addr,no_of_bytes); + else + ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.read_mem(data,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for backdoor read to memories (DDR/OCM) */ + task automatic peek_mem_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API to read interrupt status */ + task automatic read_interrupt; + output[irq_width-1:0] irq_status; + begin + irq_status = IRQ_F2P; + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status); + end + endtask + + /* API to wait on interrup */ + task automatic wait_interrupt; + input [3:0] irq; + output[irq_width-1:0] irq_status; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq); + + case(irq) + 0 : wait(IRQ_F2P[0] === 1'b1); + 1 : wait(IRQ_F2P[1] === 1'b1); + 2 : wait(IRQ_F2P[2] === 1'b1); + 3 : wait(IRQ_F2P[3] === 1'b1); + 4 : wait(IRQ_F2P[4] === 1'b1); + 5 : wait(IRQ_F2P[5] === 1'b1); + 6 : wait(IRQ_F2P[6] === 1'b1); + 7 : wait(IRQ_F2P[7] === 1'b1); + 8 : wait(IRQ_F2P[8] === 1'b1); + 8 : wait(IRQ_F2P[9] === 1'b1); + 10: wait(IRQ_F2P[10] === 1'b1); + 11: wait(IRQ_F2P[11] === 1'b1); + 12: wait(IRQ_F2P[12] === 1'b1); + 13: wait(IRQ_F2P[13] === 1'b1); + 14: wait(IRQ_F2P[14] === 1'b1); + 15: wait(IRQ_F2P[15] === 1'b1); + default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR); + endcase + if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq); + irq_status = IRQ_F2P; + end + endtask + + /* API to wait for a certain match pattern*/ + task automatic wait_mem_update; + input[addr_width-1:0] address; + input[data_width-1:0] data_in; + output[data_width-1:0] data_out; + reg[data_width-1:0] datao; + begin + if(mem_update_key) begin + mem_update_key = 0; + if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); + if(check_addr_aligned(address)) begin + ddrc.ddr.wait_mem_update(address, datao); + if(datao != data_in)begin + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao); + $stop; + end else + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in); + data_out = datao; + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address); + if(STOP_ON_ERROR) $stop; + end + mem_update_key = 1; + end else + $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end + endtask + + + /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ + task automatic write_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] wr_size; + output [axi_rsp_width-1:0] response; + integer succ; + begin + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + $fclose(succ); + case(start_addr[31:30]) + GP_M0 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + GP_M1 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + default : begin + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API to initiate a READ transaction on one of the AXI-Master ports*/ + task automatic read_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] rd_size; + output [axi_rsp_width-1:0] response; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + case(start_addr[31:30]) + GP_M0 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + GP_M1 : begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end + default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic write_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] wr_size; + input [(max_transfer_bytes*8)-1:0] w_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(wr_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP0.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP1.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + + /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic read_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] rd_size; + output[(max_transfer_bytes*8)-1:0] rd_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(rd_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + +/* Hooks to call to BFM APIs */ + task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; /// string for response + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic read_burst; + input [addr_width-1:0] start_addr; + input [axi_len_width-1:0] len; + input [axi_size_width-1:0] siz; + input [axi_brst_type_width-1:0] burst; + input [axi_lock_width-1:0] lck; + input [axi_cache_width-1:0] cache; + input [axi_prot_width-1:0] prot; + output [(axi_mgp_data_width*axi_burst_len)-1:0] data; + output [(axi_rsp_width*axi_burst_len)-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic wait_reg_update; + input [addr_width-1:0] addr; + input [data_width-1:0] data_i; + input [data_width-1:0] mask_i; + input [int_width-1:0] time_interval; + input [int_width-1:0] time_out; + output [data_width-1:0] data_o; + + reg upd_done0; + reg upd_done1; + begin + if(!check_master_address(addr)) begin + $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr); + if(STOP_ON_ERROR) $stop; + end else if(addr[31:30] === GP_M0) begin + if(reg_update_key_0) begin + reg_update_key_0 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0); + if(DEBUG_INFO && upd_done0) + $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_0 = 1; + end else + $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else if(addr[31:30] === GP_M1) begin + if(reg_update_key_1) begin + reg_update_key_1 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1); + if(DEBUG_INFO && upd_done1) + $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_1 = 1; + end else + $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); + end + endtask + +/* API to read register map */ + task read_register_map; + input [addr_width-1:0] start_addr; + input [max_regs_width:0] no_of_registers; + output[max_burst_bits-1 :0] data; + reg [max_regs_width:0] no_of_regs; + begin + no_of_regs = no_of_registers; + if(no_of_registers > 32) begin + $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr); + no_of_regs = 32; + end + if(check_addr_aligned(start_addr)) begin + if(decode_address(start_addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs ); + regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end + endtask + +/* API to read single register */ + task read_register; + input [addr_width-1:0] addr; + output[data_width-1:0] data; + begin + if(check_addr_aligned(addr)) begin + if(decode_address(addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr ); + regc.regm.get_data(addr >> 2, data); + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + + end + endtask + + /* API to set the AXI-Slave profile*/ + task automatic set_slave_profile; + input[1023:0] name; + input[1:0] latency ; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency); + "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency); + "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency); + "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency); + "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency); + "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency); + "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency); + "ALL" : begin + S_AXI_GP0.set_latency_type(latency); + S_AXI_GP1.set_latency_type(latency); + S_AXI_HP0.set_latency_type(latency); + S_AXI_HP1.set_latency_type(latency); + S_AXI_HP2.set_latency_type(latency); + S_AXI_HP3.set_latency_type(latency); + S_AXI_ACP.set_latency_type(latency); + end + endcase + end + endtask + + +/*------------------------------ LOCAL APIs ------------------------------------------------ */ + + /* local API for address decoding*/ + function automatic [1:0] decode_address; + input [addr_width-1:0] address; + begin + if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) + decode_address = OCM_MEM; /// OCM + else if(address >= ddr_start_addr && address <= ddr_end_addr) + decode_address = DDR_MEM; /// DDR + else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr) + decode_address = OCM_MEM; /// OCM + else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr) + decode_address = REG_MEM; /// Register Map + else + decode_address = INVALID_MEM_TYPE; /// ERROR in Address + end + endfunction + + /* local API for checking address is 32-bit (4-byte) aligned */ + function automatic check_addr_aligned; + input [addr_width-1:0] address; + begin + if((address%4) !=0 ) begin // + check_addr_aligned = 0; ///not_aligned + end else + check_addr_aligned = 1; + end + endfunction + + /* local API to check address for GP Masters */ + function check_master_address; + input [addr_width-1:0] address; + begin + if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) + check_master_address = 1'b1; + else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) + check_master_address = 1'b1; + else + check_master_address = 1'b0; /// ERROR in Address + end + endfunction + + /* Response decode */ + function automatic [511:0] get_resp; + input[axi_rsp_width-1:0] response; + begin + case(response) + 2'b00 : get_resp = "OKAY"; + 2'b01 : get_resp = "EXOKAY"; + 2'b10 : get_resp = "SLVERR"; + 2'b11 : get_resp = "DECERR"; + endcase + end + endfunction diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_acp.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_acp.v new file mode 100644 index 0000000..11edfe4 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_acp.v @@ -0,0 +1,93 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_axi_acp.v + * + * Date : 2012-11 + * + * Description : Connections for ACP port + * + *****************************************************************************/ + +/* AXI Slave ACP */ + processing_system7_bfm_v2_0_5_axi_slave #( C_USE_S_AXI_ACP, // enable + axi_acp_name, // name + axi_acp_data_width, // data width + addr_width, /// address width + axi_acp_id_width, // ID width + C_S_AXI_ACP_BASEADDR, // slave base address + C_S_AXI_ACP_HIGHADDR,// slave size + axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes + axi_slv_excl_support, // Exclusive access support + axi_acp_wr_outstanding, + axi_acp_rd_outstanding) + S_AXI_ACP(.S_RESETN (net_axi_acp_rstn), + .S_ACLK (S_AXI_ACP_ACLK), + // Write Address Channel + .S_AWID (S_AXI_ACP_AWID), + .S_AWADDR (S_AXI_ACP_AWADDR), + .S_AWLEN (S_AXI_ACP_AWLEN), + .S_AWSIZE (S_AXI_ACP_AWSIZE), + .S_AWBURST (S_AXI_ACP_AWBURST), + .S_AWLOCK (S_AXI_ACP_AWLOCK), + .S_AWCACHE (S_AXI_ACP_AWCACHE), + .S_AWPROT (S_AXI_ACP_AWPROT), + .S_AWVALID (S_AXI_ACP_AWVALID), + .S_AWREADY (S_AXI_ACP_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_ACP_WID), + .S_WDATA (S_AXI_ACP_WDATA), + .S_WSTRB (S_AXI_ACP_WSTRB), + .S_WLAST (S_AXI_ACP_WLAST), + .S_WVALID (S_AXI_ACP_WVALID), + .S_WREADY (S_AXI_ACP_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_ACP_BID), + .S_BRESP (S_AXI_ACP_BRESP), + .S_BVALID (S_AXI_ACP_BVALID), + .S_BREADY (S_AXI_ACP_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_ACP_ARID), + .S_ARADDR (S_AXI_ACP_ARADDR), + .S_ARLEN (S_AXI_ACP_ARLEN), + .S_ARSIZE (S_AXI_ACP_ARSIZE), + .S_ARBURST (S_AXI_ACP_ARBURST), + .S_ARLOCK (S_AXI_ACP_ARLOCK), + .S_ARCACHE (S_AXI_ACP_ARCACHE), + .S_ARPROT (S_AXI_ACP_ARPROT), + .S_ARVALID (S_AXI_ACP_ARVALID), + .S_ARREADY (S_AXI_ACP_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_ACP_RID), + .S_RDATA (S_AXI_ACP_RDATA), + .S_RRESP (S_AXI_ACP_RRESP), + .S_RLAST (S_AXI_ACP_RLAST), + .S_RVALID (S_AXI_ACP_RVALID), + .S_RREADY (S_AXI_ACP_RREADY), + // Side band signals + .S_AWQOS (S_AXI_ACP_AWQOS), + .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals + + .SW_CLK (net_sw_clk), +/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/ + .WR_DATA_ACK_DDR (ddr_wr_ack_port0), + .WR_DATA_ACK_OCM (ocm_wr_ack_port0), + .WR_DATA (net_wr_data_acp), + .WR_ADDR (net_wr_addr_acp), + .WR_BYTES (net_wr_bytes_acp), + .WR_DATA_VALID_DDR (ddr_wr_dv_port0), + .WR_DATA_VALID_OCM (ocm_wr_dv_port0), + .WR_QOS (net_wr_qos_acp), + + .RD_REQ_DDR (ddr_rd_req_port0), + .RD_REQ_OCM (ocm_rd_req_port0), + .RD_REQ_REG (reg_rd_req_port0), + .RD_ADDR (net_rd_addr_acp), + .RD_DATA_DDR (ddr_rd_data_port0), + .RD_DATA_OCM (ocm_rd_data_port0), + .RD_DATA_REG (reg_rd_data_port0), + .RD_BYTES (net_rd_bytes_acp), + .RD_DATA_VALID_DDR (ddr_rd_dv_port0), + .RD_DATA_VALID_OCM (ocm_rd_dv_port0), + .RD_DATA_VALID_REG (reg_rd_dv_port0), + .RD_QOS (net_rd_qos_acp) + +); diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_gp.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_gp.v new file mode 100644 index 0000000..4955f2c --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_gp.v @@ -0,0 +1,309 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_axi_gp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI GP ports + * + *****************************************************************************/ + + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + +/* AXI -Master GP0 */ + processing_system7_bfm_v2_0_5_axi_master #(C_USE_M_AXI_GP0, // enable + axi_mgp0_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn), + .M_ACLK (M_AXI_GP0_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP0_AWID_FULL), + .M_AWADDR (M_AXI_GP0_AWADDR), + .M_AWLEN (M_AXI_GP0_AWLEN), + .M_AWSIZE (M_AXI_GP0_AWSIZE), + .M_AWBURST (M_AXI_GP0_AWBURST), + .M_AWLOCK (M_AXI_GP0_AWLOCK), + .M_AWCACHE (M_AXI_GP0_AWCACHE), + .M_AWPROT (M_AXI_GP0_AWPROT), + .M_AWVALID (M_AXI_GP0_AWVALID), + .M_AWREADY (M_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP0_WID_FULL), + .M_WDATA (M_AXI_GP0_WDATA), + .M_WSTRB (M_AXI_GP0_WSTRB), + .M_WLAST (M_AXI_GP0_WLAST), + .M_WVALID (M_AXI_GP0_WVALID), + .M_WREADY (M_AXI_GP0_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP0_BID_FULL), + .M_BRESP (M_AXI_GP0_BRESP), + .M_BVALID (M_AXI_GP0_BVALID), + .M_BREADY (M_AXI_GP0_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP0_ARID_FULL), + .M_ARADDR (M_AXI_GP0_ARADDR), + .M_ARLEN (M_AXI_GP0_ARLEN), + .M_ARSIZE (M_AXI_GP0_ARSIZE), + .M_ARBURST (M_AXI_GP0_ARBURST), + .M_ARLOCK (M_AXI_GP0_ARLOCK), + .M_ARCACHE (M_AXI_GP0_ARCACHE), + .M_ARPROT (M_AXI_GP0_ARPROT), + .M_ARVALID (M_AXI_GP0_ARVALID), + .M_ARREADY (M_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP0_RID_FULL), + .M_RDATA (M_AXI_GP0_RDATA), + .M_RRESP (M_AXI_GP0_RRESP), + .M_RLAST (M_AXI_GP0_RLAST), + .M_RVALID (M_AXI_GP0_RVALID), + .M_RREADY (M_AXI_GP0_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP0_AWQOS), + .M_ARQOS (M_AXI_GP0_ARQOS) + ); + + /* AXI Master GP1 */ + processing_system7_bfm_v2_0_5_axi_master #(C_USE_M_AXI_GP1, // enable + axi_mgp1_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn), + .M_ACLK (M_AXI_GP1_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP1_AWID_FULL), + .M_AWADDR (M_AXI_GP1_AWADDR), + .M_AWLEN (M_AXI_GP1_AWLEN), + .M_AWSIZE (M_AXI_GP1_AWSIZE), + .M_AWBURST (M_AXI_GP1_AWBURST), + .M_AWLOCK (M_AXI_GP1_AWLOCK), + .M_AWCACHE (M_AXI_GP1_AWCACHE), + .M_AWPROT (M_AXI_GP1_AWPROT), + .M_AWVALID (M_AXI_GP1_AWVALID), + .M_AWREADY (M_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP1_WID_FULL), + .M_WDATA (M_AXI_GP1_WDATA), + .M_WSTRB (M_AXI_GP1_WSTRB), + .M_WLAST (M_AXI_GP1_WLAST), + .M_WVALID (M_AXI_GP1_WVALID), + .M_WREADY (M_AXI_GP1_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP1_BID_FULL), + .M_BRESP (M_AXI_GP1_BRESP), + .M_BVALID (M_AXI_GP1_BVALID), + .M_BREADY (M_AXI_GP1_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP1_ARID_FULL), + .M_ARADDR (M_AXI_GP1_ARADDR), + .M_ARLEN (M_AXI_GP1_ARLEN), + .M_ARSIZE (M_AXI_GP1_ARSIZE), + .M_ARBURST (M_AXI_GP1_ARBURST), + .M_ARLOCK (M_AXI_GP1_ARLOCK), + .M_ARCACHE (M_AXI_GP1_ARCACHE), + .M_ARPROT (M_AXI_GP1_ARPROT), + .M_ARVALID (M_AXI_GP1_ARVALID), + .M_ARREADY (M_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP1_RID_FULL), + .M_RDATA (M_AXI_GP1_RDATA), + .M_RRESP (M_AXI_GP1_RRESP), + .M_RLAST (M_AXI_GP1_RLAST), + .M_RVALID (M_AXI_GP1_RVALID), + .M_RREADY (M_AXI_GP1_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP1_AWQOS), + .M_ARQOS (M_AXI_GP1_ARQOS) + ); + +/* AXI Slave GP0 */ + processing_system7_bfm_v2_0_5_axi_slave #(C_USE_S_AXI_GP0, /// enable + axi_sgp0_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP0_BASEADDR,//// base address + C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access not supported + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn), + .S_ACLK (S_AXI_GP0_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP0_AWID), + .S_AWADDR (S_AXI_GP0_AWADDR), + .S_AWLEN (S_AXI_GP0_AWLEN), + .S_AWSIZE (S_AXI_GP0_AWSIZE), + .S_AWBURST (S_AXI_GP0_AWBURST), + .S_AWLOCK (S_AXI_GP0_AWLOCK), + .S_AWCACHE (S_AXI_GP0_AWCACHE), + .S_AWPROT (S_AXI_GP0_AWPROT), + .S_AWVALID (S_AXI_GP0_AWVALID), + .S_AWREADY (S_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP0_WID), + .S_WDATA (S_AXI_GP0_WDATA), + .S_WSTRB (S_AXI_GP0_WSTRB), + .S_WLAST (S_AXI_GP0_WLAST), + .S_WVALID (S_AXI_GP0_WVALID), + .S_WREADY (S_AXI_GP0_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP0_BID), + .S_BRESP (S_AXI_GP0_BRESP), + .S_BVALID (S_AXI_GP0_BVALID), + .S_BREADY (S_AXI_GP0_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP0_ARID), + .S_ARADDR (S_AXI_GP0_ARADDR), + .S_ARLEN (S_AXI_GP0_ARLEN), + .S_ARSIZE (S_AXI_GP0_ARSIZE), + .S_ARBURST (S_AXI_GP0_ARBURST), + .S_ARLOCK (S_AXI_GP0_ARLOCK), + .S_ARCACHE (S_AXI_GP0_ARCACHE), + .S_ARPROT (S_AXI_GP0_ARPROT), + .S_ARVALID (S_AXI_GP0_ARVALID), + .S_ARREADY (S_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP0_RID), + .S_RDATA (S_AXI_GP0_RDATA), + .S_RRESP (S_AXI_GP0_RRESP), + .S_RLAST (S_AXI_GP0_RLAST), + .S_RVALID (S_AXI_GP0_RVALID), + .S_RREADY (S_AXI_GP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP0_AWQOS), + .S_ARQOS (S_AXI_GP0_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0), + .WR_DATA (net_wr_data_gp0), + .WR_ADDR (net_wr_addr_gp0), + .WR_BYTES (net_wr_bytes_gp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0), + .WR_QOS (net_wr_qos_gp0), + .RD_REQ_DDR (net_rd_req_ddr_gp0), + .RD_REQ_OCM (net_rd_req_ocm_gp0), + .RD_REQ_REG (net_rd_req_reg_gp0), + .RD_ADDR (net_rd_addr_gp0), + .RD_DATA_DDR (net_rd_data_ddr_gp0), + .RD_DATA_OCM (net_rd_data_ocm_gp0), + .RD_DATA_REG (net_rd_data_reg_gp0), + .RD_BYTES (net_rd_bytes_gp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp0), + .RD_QOS (net_rd_qos_gp0) + +); + +/* AXI Slave GP1 */ + processing_system7_bfm_v2_0_5_axi_slave #(C_USE_S_AXI_GP1, /// enable + axi_sgp1_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP1_BASEADDR,//// base address + C_S_AXI_GP1_HIGHADDR,/// HIGh_addr + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn), + .S_ACLK (S_AXI_GP1_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP1_AWID), + .S_AWADDR (S_AXI_GP1_AWADDR), + .S_AWLEN (S_AXI_GP1_AWLEN), + .S_AWSIZE (S_AXI_GP1_AWSIZE), + .S_AWBURST (S_AXI_GP1_AWBURST), + .S_AWLOCK (S_AXI_GP1_AWLOCK), + .S_AWCACHE (S_AXI_GP1_AWCACHE), + .S_AWPROT (S_AXI_GP1_AWPROT), + .S_AWVALID (S_AXI_GP1_AWVALID), + .S_AWREADY (S_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP1_WID), + .S_WDATA (S_AXI_GP1_WDATA), + .S_WSTRB (S_AXI_GP1_WSTRB), + .S_WLAST (S_AXI_GP1_WLAST), + .S_WVALID (S_AXI_GP1_WVALID), + .S_WREADY (S_AXI_GP1_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP1_BID), + .S_BRESP (S_AXI_GP1_BRESP), + .S_BVALID (S_AXI_GP1_BVALID), + .S_BREADY (S_AXI_GP1_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP1_ARID), + .S_ARADDR (S_AXI_GP1_ARADDR), + .S_ARLEN (S_AXI_GP1_ARLEN), + .S_ARSIZE (S_AXI_GP1_ARSIZE), + .S_ARBURST (S_AXI_GP1_ARBURST), + .S_ARLOCK (S_AXI_GP1_ARLOCK), + .S_ARCACHE (S_AXI_GP1_ARCACHE), + .S_ARPROT (S_AXI_GP1_ARPROT), + .S_ARVALID (S_AXI_GP1_ARVALID), + .S_ARREADY (S_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP1_RID), + .S_RDATA (S_AXI_GP1_RDATA), + .S_RRESP (S_AXI_GP1_RRESP), + .S_RLAST (S_AXI_GP1_RLAST), + .S_RVALID (S_AXI_GP1_RVALID), + .S_RREADY (S_AXI_GP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP1_AWQOS), + .S_ARQOS (S_AXI_GP1_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1), + .WR_DATA (net_wr_data_gp1), + .WR_ADDR (net_wr_addr_gp1), + .WR_BYTES (net_wr_bytes_gp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1), + .WR_QOS (net_wr_qos_gp1), + .RD_REQ_OCM (net_rd_req_ocm_gp1), + .RD_REQ_DDR (net_rd_req_ddr_gp1), + .RD_REQ_REG (net_rd_req_reg_gp1), + .RD_ADDR (net_rd_addr_gp1), + .RD_DATA_DDR (net_rd_data_ddr_gp1), + .RD_DATA_OCM (net_rd_data_ocm_gp1), + .RD_DATA_REG (net_rd_data_reg_gp1), + .RD_BYTES (net_rd_bytes_gp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp1), + .RD_QOS (net_rd_qos_gp1) + +); diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_hp.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_hp.v new file mode 100644 index 0000000..eb4fda9 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_axi_hp.v @@ -0,0 +1,346 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_axi_hp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI HP ports + * + *****************************************************************************/ + +/* AXI Slave HP0 */ + processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP0, // enable + axi_hp0_name, // name + C_S_AXI_HP0_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP0_BASEADDR, // slave base address + C_S_AXI_HP0_HIGHADDR, // slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn), + .S_ACLK (S_AXI_HP0_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP0_AWID), + .S_AWADDR (S_AXI_HP0_AWADDR), + .S_AWLEN (S_AXI_HP0_AWLEN), + .S_AWSIZE (S_AXI_HP0_AWSIZE), + .S_AWBURST (S_AXI_HP0_AWBURST), + .S_AWLOCK (S_AXI_HP0_AWLOCK), + .S_AWCACHE (S_AXI_HP0_AWCACHE), + .S_AWPROT (S_AXI_HP0_AWPROT), + .S_AWVALID (S_AXI_HP0_AWVALID), + .S_AWREADY (S_AXI_HP0_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP0_WID), + .S_WDATA (S_AXI_HP0_WDATA), + .S_WSTRB (S_AXI_HP0_WSTRB), + .S_WLAST (S_AXI_HP0_WLAST), + .S_WVALID (S_AXI_HP0_WVALID), + .S_WREADY (S_AXI_HP0_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP0_BID), + .S_BRESP (S_AXI_HP0_BRESP), + .S_BVALID (S_AXI_HP0_BVALID), + .S_BREADY (S_AXI_HP0_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP0_ARID), + .S_ARADDR (S_AXI_HP0_ARADDR), + .S_ARLEN (S_AXI_HP0_ARLEN), + .S_ARSIZE (S_AXI_HP0_ARSIZE), + .S_ARBURST (S_AXI_HP0_ARBURST), + .S_ARLOCK (S_AXI_HP0_ARLOCK), + .S_ARCACHE (S_AXI_HP0_ARCACHE), + .S_ARPROT (S_AXI_HP0_ARPROT), + .S_ARVALID (S_AXI_HP0_ARVALID), + .S_ARREADY (S_AXI_HP0_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP0_RID), + .S_RDATA (S_AXI_HP0_RDATA), + .S_RRESP (S_AXI_HP0_RRESP), + .S_RLAST (S_AXI_HP0_RLAST), + .S_RVALID (S_AXI_HP0_RVALID), + .S_RREADY (S_AXI_HP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP0_AWQOS), + .S_ARQOS (S_AXI_HP0_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP0_RCOUNT), + .S_WCOUNT (S_AXI_HP0_WCOUNT), + .S_RACOUNT (S_AXI_HP0_RACOUNT), + .S_WACOUNT (S_AXI_HP0_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0), + .WR_DATA (net_wr_data_hp0), + .WR_ADDR (net_wr_addr_hp0), + .WR_BYTES (net_wr_bytes_hp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0), + .WR_QOS (net_wr_qos_hp0), + .RD_REQ_DDR (net_rd_req_ddr_hp0), + .RD_REQ_OCM (net_rd_req_ocm_hp0), + .RD_ADDR (net_rd_addr_hp0), + .RD_DATA_DDR (net_rd_data_ddr_hp0), + .RD_DATA_OCM (net_rd_data_ocm_hp0), + .RD_BYTES (net_rd_bytes_hp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0), + .RD_QOS (net_rd_qos_hp0) + ); + +/* AXI Slave HP1 */ + processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP1, // enable + axi_hp1_name, // name + C_S_AXI_HP1_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP1_BASEADDR, // slave base address + C_S_AXI_HP1_HIGHADDR, // Slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn), + .S_ACLK (S_AXI_HP1_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP1_AWID), + .S_AWADDR (S_AXI_HP1_AWADDR), + .S_AWLEN (S_AXI_HP1_AWLEN), + .S_AWSIZE (S_AXI_HP1_AWSIZE), + .S_AWBURST (S_AXI_HP1_AWBURST), + .S_AWLOCK (S_AXI_HP1_AWLOCK), + .S_AWCACHE (S_AXI_HP1_AWCACHE), + .S_AWPROT (S_AXI_HP1_AWPROT), + .S_AWVALID (S_AXI_HP1_AWVALID), + .S_AWREADY (S_AXI_HP1_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP1_WID), + .S_WDATA (S_AXI_HP1_WDATA), + .S_WSTRB (S_AXI_HP1_WSTRB), + .S_WLAST (S_AXI_HP1_WLAST), + .S_WVALID (S_AXI_HP1_WVALID), + .S_WREADY (S_AXI_HP1_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP1_BID), + .S_BRESP (S_AXI_HP1_BRESP), + .S_BVALID (S_AXI_HP1_BVALID), + .S_BREADY (S_AXI_HP1_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP1_ARID), + .S_ARADDR (S_AXI_HP1_ARADDR), + .S_ARLEN (S_AXI_HP1_ARLEN), + .S_ARSIZE (S_AXI_HP1_ARSIZE), + .S_ARBURST (S_AXI_HP1_ARBURST), + .S_ARLOCK (S_AXI_HP1_ARLOCK), + .S_ARCACHE (S_AXI_HP1_ARCACHE), + .S_ARPROT (S_AXI_HP1_ARPROT), + .S_ARVALID (S_AXI_HP1_ARVALID), + .S_ARREADY (S_AXI_HP1_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP1_RID), + .S_RDATA (S_AXI_HP1_RDATA), + .S_RRESP (S_AXI_HP1_RRESP), + .S_RLAST (S_AXI_HP1_RLAST), + .S_RVALID (S_AXI_HP1_RVALID), + .S_RREADY (S_AXI_HP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP1_AWQOS), + .S_ARQOS (S_AXI_HP1_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP1_RCOUNT), + .S_WCOUNT (S_AXI_HP1_WCOUNT), + .S_RACOUNT (S_AXI_HP1_RACOUNT), + .S_WACOUNT (S_AXI_HP1_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1), + .WR_DATA (net_wr_data_hp1), + .WR_ADDR (net_wr_addr_hp1), + .WR_BYTES (net_wr_bytes_hp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), + .WR_QOS (net_wr_qos_hp1), + .RD_REQ_DDR (net_rd_req_ddr_hp1), + .RD_REQ_OCM (net_rd_req_ocm_hp1), + .RD_ADDR (net_rd_addr_hp1), + .RD_DATA_DDR (net_rd_data_ddr_hp1), + .RD_DATA_OCM (net_rd_data_ocm_hp1), + .RD_BYTES (net_rd_bytes_hp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1), + .RD_QOS (net_rd_qos_hp1) + + ); + +/* AXI Slave HP2 */ + processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP2, // enable + axi_hp2_name, // name + C_S_AXI_HP2_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP2_BASEADDR, // slave base address + C_S_AXI_HP2_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn), + .S_ACLK (S_AXI_HP2_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP2_AWID), + .S_AWADDR (S_AXI_HP2_AWADDR), + .S_AWLEN (S_AXI_HP2_AWLEN), + .S_AWSIZE (S_AXI_HP2_AWSIZE), + .S_AWBURST (S_AXI_HP2_AWBURST), + .S_AWLOCK (S_AXI_HP2_AWLOCK), + .S_AWCACHE (S_AXI_HP2_AWCACHE), + .S_AWPROT (S_AXI_HP2_AWPROT), + .S_AWVALID (S_AXI_HP2_AWVALID), + .S_AWREADY (S_AXI_HP2_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP2_WID), + .S_WDATA (S_AXI_HP2_WDATA), + .S_WSTRB (S_AXI_HP2_WSTRB), + .S_WLAST (S_AXI_HP2_WLAST), + .S_WVALID (S_AXI_HP2_WVALID), + .S_WREADY (S_AXI_HP2_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP2_BID), + .S_BRESP (S_AXI_HP2_BRESP), + .S_BVALID (S_AXI_HP2_BVALID), + .S_BREADY (S_AXI_HP2_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP2_ARID), + .S_ARADDR (S_AXI_HP2_ARADDR), + .S_ARLEN (S_AXI_HP2_ARLEN), + .S_ARSIZE (S_AXI_HP2_ARSIZE), + .S_ARBURST (S_AXI_HP2_ARBURST), + .S_ARLOCK (S_AXI_HP2_ARLOCK), + .S_ARCACHE (S_AXI_HP2_ARCACHE), + .S_ARPROT (S_AXI_HP2_ARPROT), + .S_ARVALID (S_AXI_HP2_ARVALID), + .S_ARREADY (S_AXI_HP2_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP2_RID), + .S_RDATA (S_AXI_HP2_RDATA), + .S_RRESP (S_AXI_HP2_RRESP), + .S_RLAST (S_AXI_HP2_RLAST), + .S_RVALID (S_AXI_HP2_RVALID), + .S_RREADY (S_AXI_HP2_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP2_AWQOS), + .S_ARQOS (S_AXI_HP2_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP2_RCOUNT), + .S_WCOUNT (S_AXI_HP2_WCOUNT), + .S_RACOUNT (S_AXI_HP2_RACOUNT), + .S_WACOUNT (S_AXI_HP2_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2), + .WR_DATA (net_wr_data_hp2), + .WR_ADDR (net_wr_addr_hp2), + .WR_BYTES (net_wr_bytes_hp2), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2), + .WR_QOS (net_wr_qos_hp2), + .RD_REQ_DDR (net_rd_req_ddr_hp2), + .RD_REQ_OCM (net_rd_req_ocm_hp2), + .RD_ADDR (net_rd_addr_hp2), + .RD_DATA_DDR (net_rd_data_ddr_hp2), + .RD_DATA_OCM (net_rd_data_ocm_hp2), + .RD_BYTES (net_rd_bytes_hp2), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2), + .RD_QOS (net_rd_qos_hp2) + + ); + +/* AXI Slave HP3 */ + processing_system7_bfm_v2_0_5_afi_slave #( C_USE_S_AXI_HP3, // enable + axi_hp3_name, // name + C_S_AXI_HP3_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP3_BASEADDR, // slave base address + C_S_AXI_HP3_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn), + .S_ACLK (S_AXI_HP3_ACLK), + // Write ADDRESS CHANNEL + .S_AWID (S_AXI_HP3_AWID), + .S_AWADDR (S_AXI_HP3_AWADDR), + .S_AWLEN (S_AXI_HP3_AWLEN), + .S_AWSIZE (S_AXI_HP3_AWSIZE), + .S_AWBURST (S_AXI_HP3_AWBURST), + .S_AWLOCK (S_AXI_HP3_AWLOCK), + .S_AWCACHE (S_AXI_HP3_AWCACHE), + .S_AWPROT (S_AXI_HP3_AWPROT), + .S_AWVALID (S_AXI_HP3_AWVALID), + .S_AWREADY (S_AXI_HP3_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP3_WID), + .S_WDATA (S_AXI_HP3_WDATA), + .S_WSTRB (S_AXI_HP3_WSTRB), + .S_WLAST (S_AXI_HP3_WLAST), + .S_WVALID (S_AXI_HP3_WVALID), + .S_WREADY (S_AXI_HP3_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP3_BID), + .S_BRESP (S_AXI_HP3_BRESP), + .S_BVALID (S_AXI_HP3_BVALID), + .S_BREADY (S_AXI_HP3_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP3_ARID), + .S_ARADDR (S_AXI_HP3_ARADDR), + .S_ARLEN (S_AXI_HP3_ARLEN), + .S_ARSIZE (S_AXI_HP3_ARSIZE), + .S_ARBURST (S_AXI_HP3_ARBURST), + .S_ARLOCK (S_AXI_HP3_ARLOCK), + .S_ARCACHE (S_AXI_HP3_ARCACHE), + .S_ARPROT (S_AXI_HP3_ARPROT), + .S_ARVALID (S_AXI_HP3_ARVALID), + .S_ARREADY (S_AXI_HP3_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP3_RID), + .S_RDATA (S_AXI_HP3_RDATA), + .S_RRESP (S_AXI_HP3_RRESP), + .S_RLAST (S_AXI_HP3_RLAST), + .S_RVALID (S_AXI_HP3_RVALID), + .S_RREADY (S_AXI_HP3_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP3_AWQOS), + .S_ARQOS (S_AXI_HP3_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP3_RCOUNT), + .S_WCOUNT (S_AXI_HP3_WCOUNT), + .S_RACOUNT (S_AXI_HP3_RACOUNT), + .S_WACOUNT (S_AXI_HP3_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3), + .WR_DATA (net_wr_data_hp3), + .WR_ADDR (net_wr_addr_hp3), + .WR_BYTES (net_wr_bytes_hp3), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3), + .WR_QOS (net_wr_qos_hp3), + .RD_REQ_DDR (net_rd_req_ddr_hp3), + .RD_REQ_OCM (net_rd_req_ocm_hp3), + .RD_ADDR (net_rd_addr_hp3), + .RD_DATA_DDR (net_rd_data_ddr_hp3), + .RD_DATA_OCM (net_rd_data_ocm_hp3), + .RD_BYTES (net_rd_bytes_hp3), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3), + .RD_QOS (net_rd_qos_hp3) + ); diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_local_params.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_local_params.v new file mode 100644 index 0000000..9e51987 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_local_params.v @@ -0,0 +1,239 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_local_params.v + * + * Date : 2012-11 + * + * Description : Parameters used in Zynq BFM + * + *****************************************************************************/ + +/* local */ +parameter m_axi_gp0_baseaddr = 32'h4000_0000; +parameter m_axi_gp1_baseaddr = 32'h8000_0000; +parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF; +parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF; + +parameter addr_width = 32; // maximum address width +parameter data_width = 32; // maximum data width. +parameter max_chars = 128; // max characters for file name +parameter mem_width = data_width/8; /// memory width in bytes +parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted +parameter int_width = 32; //integre width + +/* for internal read/write APIs used for data transfers */ +parameter max_burst_len = 16; /// maximum brst length on axi +parameter max_data_width = 64; // maximum data width for internal AXI bursts +parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts +parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer +parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts + +parameter max_registers = 32; +parameter max_regs_width = clogb2(max_registers); + +parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; + +/* Interrupt bits supported */ +parameter irq_width = 16; + +/* GP Master0 & Master1 address decode */ +parameter GP_M0 = 2'b01; +parameter GP_M1 = 2'b10; + +parameter ALL_RANDOM= 2'b00; +parameter ALL_ZEROS = 2'b01; +parameter ALL_ONES = 2'b10; + +parameter ddr_start_addr = 32'h0008_0000; +parameter ddr_end_addr = 32'h3FFF_FFFF; + +parameter ocm_start_addr = 32'h0000_0000; +parameter ocm_end_addr = 32'h0003_FFFF; +parameter high_ocm_start_addr = 32'hFFFC_0000; +parameter high_ocm_end_addr = 32'hFFFF_FFFF; +parameter ocm_low_addr = 32'hFFFF_0000; + +parameter reg_start_addr = 32'hE000_0000; +parameter reg_end_addr = 32'hF8F0_2F80; + + +/* for Master port APIs and AXI protocol related signal widths*/ +parameter axi_burst_len = 16; +parameter axi_len_width = clogb2(axi_burst_len); +parameter axi_size_width = 3; +parameter axi_brst_type_width = 2; +parameter axi_lock_width = 2; +parameter axi_cache_width = 4; +parameter axi_prot_width = 3; +parameter axi_rsp_width = 2; +parameter axi_mgp_data_width = 32; +parameter axi_mgp_id_width = 12; +parameter axi_mgp_outstanding = 8; +parameter axi_mgp_wr_id = 12'hC00; +parameter axi_mgp_rd_id = 12'hC0C; +parameter axi_mgp0_name = "M_AXI_GP0"; +parameter axi_mgp1_name = "M_AXI_GP1"; +parameter axi_qos_width = 4; +parameter max_transfer_bytes = 128; // For Master APIs. +parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs. + + +/* for GP slave ports*/ +parameter axi_sgp_data_width = 32; +parameter axi_sgp_id_width = 6; +parameter axi_sgp_rd_outstanding = 8; +parameter axi_sgp_wr_outstanding = 8; +parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding; +parameter axi_sgp0_name = "S_AXI_GP0"; +parameter axi_sgp1_name = "S_AXI_GP1"; + +/* for ACP slave ports*/ +parameter axi_acp_data_width = 64; +parameter axi_acp_id_width = 3; +parameter axi_acp_rd_outstanding = 7; +parameter axi_acp_wr_outstanding = 3; +parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding; +parameter axi_acp_name = "S_AXI_ACP"; + +/* for HP slave ports*/ +parameter axi_hp_id_width = 6; +parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT .. +parameter axi_hp0_name = "S_AXI_HP0"; +parameter axi_hp1_name = "S_AXI_HP1"; +parameter axi_hp2_name = "S_AXI_HP2"; +parameter axi_hp3_name = "S_AXI_HP3"; + + +parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported +parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported + +/* AXI transfer types */ +parameter AXI_FIXED = 2'b00; +parameter AXI_INCR = 2'b01; +parameter AXI_WRAP = 2'b10; + +/* Exclusive Access */ +parameter AXI_NRML = 2'b00; +parameter AXI_EXCL = 2'b01; +parameter AXI_LOCK = 2'b10; + +/* AXI Response types */ +parameter AXI_OK = 2'b00; +parameter AXI_EXCL_OK = 2'b01; +parameter AXI_SLV_ERR = 2'b10; +parameter AXI_DEC_ERR = 2'b11; + +function automatic integer clogb2; + input [31:0] value; + begin + value = value - 1; + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin + value = value >> 1; + end + end +endfunction + +/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */ + /* WR FIFO data */ + parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + parameter wr_data_msb = wr_data_lsb + max_burst_bits-1; + parameter wr_qos_lsb = wr_data_msb + 1; + parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + + /* WR AFI FIFO data */ + /* ID - 1071:1066 + Resp - 1065:1064 + data - 1063:40 + address - 39:8 + valid_bytes - 7:0 + */ + parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1); + parameter wr_afi_bytes_lsb = 0; + parameter wr_afi_bytes_msb = max_burst_bytes_width; + parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; + parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; + parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; + parameter wr_afi_data_msb = wr_afi_data_lsb + max_burst_bits-1; + parameter wr_afi_rsp_lsb = wr_afi_data_msb + 1; + parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; + parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; + parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; + parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; + parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; + parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; + parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; + + + parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes + parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes) + parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location + +/* for interconnect fifo models */ + parameter intr_max_outstanding = 8; + parameter intr_cnt_width = clogb2(intr_max_outstanding)+1; + parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1); + parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ; + + //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + parameter rd_afi_bytes_lsb = 0; + parameter rd_afi_bytes_msb = max_burst_bytes_width; + parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1; + parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1; + parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1; + parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1; + parameter rd_afi_ln_lsb = rd_afi_id_msb + 1; + parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1; + parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1; + parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1; + parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1; + parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1; + parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1; + parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1; + parameter rd_afi_data_lsb = rd_afi_addr_msb + 1; + parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1; + + +/* Latency types */ + parameter BEST_CASE = 0; + parameter AVG_CASE = 1; + parameter WORST_CASE = 2; + parameter RANDOM_CASE = 3; + +/* Latency Parameters ACP */ + parameter acp_wr_min = 21; + parameter acp_wr_avg = 16; + parameter acp_wr_max = 27; + parameter acp_rd_min = 34; + parameter acp_rd_avg = 125; + parameter acp_rd_max = 130; + +/* Latency Parameters GP */ + parameter gp_wr_min = 21; + parameter gp_wr_avg = 16; + parameter gp_wr_max = 46; + parameter gp_rd_min = 38; + parameter gp_rd_avg = 125; + parameter gp_rd_max = 130; + +/* Latency Parameters HP */ + parameter afi_wr_min = 37; + parameter afi_wr_avg = 41; + parameter afi_wr_max = 42; + parameter afi_rd_min = 41; + parameter afi_rd_avg = 221; + parameter afi_rd_max = 229; + +/* ID VALID and INVALID */ + parameter secure_access_enabled = 0; + parameter id_invalid = 0; + parameter id_valid = 1; + +/* Display */ + parameter DISP_INFO = "*ZYNQ_BFM_INFO"; + parameter DISP_WARN = "*ZYNQ_BFM_WARNING"; + parameter DISP_ERR = "*ZYNQ_BFM_ERROR"; + parameter DISP_INT_INFO = "ZYNQ_BFM_INT_INFO"; diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_init.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_init.v new file mode 100644 index 0000000..03fc94d --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_init.v @@ -0,0 +1,2924 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_reg_init.v + * + * Date : 2012-11 + * + * Description : Initialize register default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL); +set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS); +set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG); +set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL); +set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS); +set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG); + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL); +set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS); +set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG); +set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL); +set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS); +set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG); + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL); +set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS); +set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG); +set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL); +set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS); +set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG); + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL); +set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS); +set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG); +set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL); +set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS); +set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG); + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can0__SRR, val_can0__SRR); +set_reset_data( can0__MSR, val_can0__MSR); +set_reset_data( can0__BRPR, val_can0__BRPR); +set_reset_data( can0__BTR, val_can0__BTR); +set_reset_data( can0__ECR, val_can0__ECR); +set_reset_data( can0__ESR, val_can0__ESR); +set_reset_data( can0__SR, val_can0__SR); +set_reset_data( can0__ISR, val_can0__ISR); +set_reset_data( can0__IER, val_can0__IER); +set_reset_data( can0__ICR, val_can0__ICR); +set_reset_data( can0__TCR, val_can0__TCR); +set_reset_data( can0__WIR, val_can0__WIR); +set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID); +set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC); +set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1); +set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2); +set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID); +set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC); +set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1); +set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2); +set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID); +set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC); +set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1); +set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2); +set_reset_data( can0__AFR, val_can0__AFR); +set_reset_data( can0__AFMR1, val_can0__AFMR1); +set_reset_data( can0__AFIR1, val_can0__AFIR1); +set_reset_data( can0__AFMR2, val_can0__AFMR2); +set_reset_data( can0__AFIR2, val_can0__AFIR2); +set_reset_data( can0__AFMR3, val_can0__AFMR3); +set_reset_data( can0__AFIR3, val_can0__AFIR3); +set_reset_data( can0__AFMR4, val_can0__AFMR4); +set_reset_data( can0__AFIR4, val_can0__AFIR4); + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can1__SRR, val_can1__SRR); +set_reset_data( can1__MSR, val_can1__MSR); +set_reset_data( can1__BRPR, val_can1__BRPR); +set_reset_data( can1__BTR, val_can1__BTR); +set_reset_data( can1__ECR, val_can1__ECR); +set_reset_data( can1__ESR, val_can1__ESR); +set_reset_data( can1__SR, val_can1__SR); +set_reset_data( can1__ISR, val_can1__ISR); +set_reset_data( can1__IER, val_can1__IER); +set_reset_data( can1__ICR, val_can1__ICR); +set_reset_data( can1__TCR, val_can1__TCR); +set_reset_data( can1__WIR, val_can1__WIR); +set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID); +set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC); +set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1); +set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2); +set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID); +set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC); +set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1); +set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2); +set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID); +set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC); +set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1); +set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2); +set_reset_data( can1__AFR, val_can1__AFR); +set_reset_data( can1__AFMR1, val_can1__AFMR1); +set_reset_data( can1__AFIR1, val_can1__AFIR1); +set_reset_data( can1__AFMR2, val_can1__AFMR2); +set_reset_data( can1__AFIR2, val_can1__AFIR2); +set_reset_data( can1__AFMR3, val_can1__AFMR3); +set_reset_data( can1__AFIR3, val_can1__AFIR3); +set_reset_data( can1__AFMR4, val_can1__AFMR4); +set_reset_data( can1__AFIR4, val_can1__AFIR4); + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl); +set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg); +set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg); +set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg); +set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg); +set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0); +set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1); +set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2); +set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3); +set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4); +set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param); +set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg); +set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg); +set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr); +set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ); +set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank); +set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col); +set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row); +set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg); +set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg); +set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt); +set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg); +set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib); +set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold); +set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1); +set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2); +set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3); +set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4); +set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5); +set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6); +set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01); +set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ); +set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg); +set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg); +set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c); +set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d); +set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing); +set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2); +set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing); +set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET); +set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET); +set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable); +set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0); +set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1); +set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2); +set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3); +set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0); +set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1); +set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2); +set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3); +set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0); +set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1); +set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2); +set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3); +set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0); +set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1); +set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2); +set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3); +set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0); +set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1); +set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2); +set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3); +set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0); +set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1); +set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2); +set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3); +set_reset_data( ddrc__reg_64, val_ddrc__reg_64); +set_reset_data( ddrc__reg_65, val_ddrc__reg_65); +set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0); +set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1); +set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2); +set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3); +set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710); +set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711); +set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712); +set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713); +set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0); +set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1); +set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2); +set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3); +set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts); +set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts); +set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2); +set_reset_data( ddrc__axi_id, val_ddrc__axi_id); +set_reset_data( ddrc__page_mask, val_ddrc__page_mask); +set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0); +set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1); +set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2); +set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3); +set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0); +set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1); +set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2); +set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3); +set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0); +set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1); +set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2); +set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3); +set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0); +set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1); +set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2); +set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3); +set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20); +set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21); +set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22); +set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23); +set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30); +set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31); +set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32); +set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33); +set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg); +set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0); +set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1); +set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2); +set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3); +set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read); +set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0); +set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1); +set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2); +set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3); +set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm); +set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm); +set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm); + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL); +set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS); +set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL); +set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL); +set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS); +set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL); +set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL); +set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH); +set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT); +set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER); +set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT); +set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD); +set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT); +set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK); +set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER); +set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER); +set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC); +set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK); +set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER); +set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER); +set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC); +set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK); +set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER); +set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER); +set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC); +set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK); +set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER); +set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER); +set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC); +set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK); +set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER); +set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER); +set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC); +set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK); +set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER); +set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER); +set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC); +set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK); +set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER); +set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER); +set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC); +set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK); +set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER); +set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER); +set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC); +set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL); +set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT); +set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK); +set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN); +set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK); +set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA); +set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS); +set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1); +set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0); +set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL); +set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET); +set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR); +set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS); +set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS); +set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS); +set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID); +set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE); +set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4); +set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5); +set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6); +set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7); +set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0); +set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1); +set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2); +set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3); +set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0); +set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1); +set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2); +set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL); +set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK); +set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET); +set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE); +set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0); +set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1); +set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2); +set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3); +set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4); +set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5); +set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6); +set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7); +set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0); +set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1); +set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2); +set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3); +set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4); +set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5); +set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6); +set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7); +set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS); +set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE); +set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL); +set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK); +set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK); +set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT); +set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT); +set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK); +set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN); +set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN); +set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL); +set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR); +set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR); +set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR); +set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR); +set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR); +set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID); +set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR); +set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4); +set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5); +set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6); +set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7); +set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0); +set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1); +set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2); +set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3); +set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0); +set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1); +set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2); +set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL); +set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK); +set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET); +set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE); +set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0); +set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1); +set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2); +set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3); +set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4); +set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5); +set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6); +set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7); +set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0); +set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1); +set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2); +set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3); +set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4); +set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5); +set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6); +set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7); +set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS); +set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE); +set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL); +set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK); +set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK); +set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT); +set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT); +set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK); +set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN); +set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN); +set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL); +set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR); +set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR); +set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR); +set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR); +set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR); +set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID); +set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR); +set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4); +set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5); +set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6); +set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7); +set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0); +set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1); +set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2); +set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3); +set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0); +set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1); +set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2); +set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3); + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET); +set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR); +set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET); +set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR); +set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR); +set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC); +set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR); +set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET); +set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR); +set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET); +set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR); +set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR); +set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC); +set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR); +set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR); +set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR); +set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER); +set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR); +set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR); +set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR); +set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1); +set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1); +set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2); +set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3); +set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4); +set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5); +set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6); +set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7); +set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8); +set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1); +set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2); +set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3); +set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4); +set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5); +set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6); +set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7); +set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1); +set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2); +set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR); +set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR); +set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR); +set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER); +set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR); +set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR); +set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR); +set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT); +set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN); +set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER); +set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0); +set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2); +set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID); +set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0); +set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL); +set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR); +set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR); +set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR); +set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR); +set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR); +set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID); +set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR); +set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4); +set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5); +set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6); +set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7); +set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0); +set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1); +set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2); +set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3); +set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0); +set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1); +set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2); +set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3); + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR); +set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR); +set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER); +set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR); +set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR); +set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR); +set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1); +set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1); +set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2); +set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3); +set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4); +set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5); +set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6); +set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7); +set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8); +set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1); +set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2); +set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3); +set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4); +set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5); +set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6); +set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7); +set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1); +set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2); +set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR); +set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR); +set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR); +set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER); +set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR); +set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR); +set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR); +set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT); +set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN); +set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER); +set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0); +set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2); +set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID); +set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0); +set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL); +set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR); +set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR); +set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR); +set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR); +set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR); +set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID); +set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR); +set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4); +set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5); +set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6); +set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7); +set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0); +set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1); +set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2); +set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3); +set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0); +set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1); +set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2); +set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3); + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL); +set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK); +set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET); +set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR); +set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE); +set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0); +set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1); +set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2); +set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3); +set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4); +set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5); +set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6); +set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7); +set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0); +set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1); +set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2); +set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3); +set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4); +set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5); +set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6); +set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7); +set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS); +set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS); +set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS); +set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE); +set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL); +set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK); +set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK); +set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT); +set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT); +set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK); +set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK); +set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN); +set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN); +set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL); +set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR); +set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR); +set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR); +set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR); +set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR); +set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID); +set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR); +set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4); +set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5); +set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6); +set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7); +set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0); +set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1); +set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2); +set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3); +set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0); +set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1); +set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2); +set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3); + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL); +set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK); +set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET); +set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR); +set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE); +set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0); +set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1); +set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2); +set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3); +set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4); +set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5); +set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6); +set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7); +set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE); +set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL); +set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK); +set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT); +set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN); +set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN); +set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL); +set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR); +set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR); +set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR); +set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR); +set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR); +set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID); +set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR); +set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4); +set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5); +set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6); +set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7); +set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0); +set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1); +set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2); +set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3); +set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0); +set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1); +set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2); +set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3); + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL); +set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK); +set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET); +set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR); +set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE); +set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0); +set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1); +set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2); +set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3); +set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4); +set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5); +set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6); +set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7); +set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0); +set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1); +set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2); +set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3); +set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4); +set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5); +set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6); +set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7); +set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS); +set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS); +set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS); +set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE); +set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL); +set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK); +set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK); +set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT); +set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT); +set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK); +set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK); +set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN); +set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN); +set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL); +set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR); +set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR); +set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR); +set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR); +set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR); +set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID); +set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR); +set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4); +set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5); +set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6); +set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7); +set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0); +set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1); +set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2); +set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3); +set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0); +set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1); +set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2); +set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3); + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00); +set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01); +set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02); +set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03); +set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04); +set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05); +set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06); +set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07); +set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08); +set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09); +set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10); +set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11); +set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12); +set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13); +set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14); +set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15); +set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4); +set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5); +set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6); +set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7); +set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0); +set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1); +set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2); +set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3); +set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0); +set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1); +set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2); +set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3); + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_etb__RDP, val_debug_etb__RDP); +set_reset_data( debug_etb__STS, val_debug_etb__STS); +set_reset_data( debug_etb__RRD, val_debug_etb__RRD); +set_reset_data( debug_etb__RRP, val_debug_etb__RRP); +set_reset_data( debug_etb__RWP, val_debug_etb__RWP); +set_reset_data( debug_etb__TRG, val_debug_etb__TRG); +set_reset_data( debug_etb__CTL, val_debug_etb__CTL); +set_reset_data( debug_etb__RWD, val_debug_etb__RWD); +set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR); +set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR); +set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0); +set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK); +set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN); +set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0); +set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2); +set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1); +set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0); +set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR); +set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR); +set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR); +set_reset_data( debug_etb__LAR, val_debug_etb__LAR); +set_reset_data( debug_etb__LSR, val_debug_etb__LSR); +set_reset_data( debug_etb__ASR, val_debug_etb__ASR); +set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID); +set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR); +set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4); +set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5); +set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6); +set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7); +set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0); +set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1); +set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2); +set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3); +set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0); +set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1); +set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2); +set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3); + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL); +set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS); +set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL); +set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0); +set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1); +set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2); +set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3); +set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0); +set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1); +set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2); +set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3); +set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE); +set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD); +set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT); +set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID); +set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK); +set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER); +set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS); +set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT); +set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0); +set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2); +set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1); +set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0); +set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR); +set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET); +set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR); +set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS); +set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS); +set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS); +set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID); +set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE); +set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4); +set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5); +set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6); +set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7); +set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0); +set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1); +set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2); +set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3); +set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0); +set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1); +set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2); +set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3); + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_funnel__Control, val_debug_funnel__Control); +set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl); +set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0); +set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2); +set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1); +set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0); +set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR); +set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR); +set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR); +set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR); +set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR); +set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR); +set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID); +set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR); +set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4); +set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5); +set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6); +set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7); +set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0); +set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1); +set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2); +set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3); +set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0); +set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1); +set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2); +set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3); + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00); +set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01); +set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02); +set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03); +set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04); +set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05); +set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06); +set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07); +set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08); +set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09); +set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10); +set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11); +set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12); +set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13); +set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14); +set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15); +set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16); +set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17); +set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18); +set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19); +set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20); +set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21); +set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22); +set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23); +set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24); +set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25); +set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26); +set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27); +set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28); +set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29); +set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30); +set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31); +set_reset_data( debug_itm__TER, val_debug_itm__TER); +set_reset_data( debug_itm__TTR, val_debug_itm__TTR); +set_reset_data( debug_itm__CR, val_debug_itm__CR); +set_reset_data( debug_itm__SCR, val_debug_itm__SCR); +set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK); +set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT); +set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0); +set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2); +set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1); +set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0); +set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR); +set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR); +set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR); +set_reset_data( debug_itm__LAR, val_debug_itm__LAR); +set_reset_data( debug_itm__LSR, val_debug_itm__LSR); +set_reset_data( debug_itm__ASR, val_debug_itm__ASR); +set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID); +set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR); +set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4); +set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5); +set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6); +set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7); +set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0); +set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1); +set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2); +set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3); +set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0); +set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1); +set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2); +set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3); + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize); +set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize); +set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode); +set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount); +set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult); +set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest); +set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest); +set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount); +set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR); +set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR); +set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount); +set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn); +set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut); +set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK); +set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN); +set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0); +set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2); +set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1); +set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0); +set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR); +set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR); +set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR); +set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR); +set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR); +set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR); +set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID); +set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR); +set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4); +set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5); +set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6); +set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7); +set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0); +set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1); +set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2); +set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3); +set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0); +set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1); +set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2); +set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3); + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( devcfg__CTRL, val_devcfg__CTRL); +set_reset_data( devcfg__LOCK, val_devcfg__LOCK); +set_reset_data( devcfg__CFG, val_devcfg__CFG); +set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS); +set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK); +set_reset_data( devcfg__STATUS, val_devcfg__STATUS); +set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR); +set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR); +set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN); +set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN); +set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW); +set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR); +set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID); +set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK); +set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL); +set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG); +set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS); +set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK); +set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS); +set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO); +set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO); +set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL); + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR); +set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC); +set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN); +set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS); +set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS); +set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR); +set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD); +set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC); +set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD); +set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0); +set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1); +set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2); +set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3); +set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4); +set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5); +set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6); +set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7); +set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0); +set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0); +set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1); +set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1); +set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2); +set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2); +set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3); +set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3); +set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4); +set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4); +set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5); +set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5); +set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6); +set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6); +set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7); +set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7); +set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0); +set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0); +set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0); +set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0); +set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0); +set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1); +set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1); +set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1); +set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1); +set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1); +set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2); +set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2); +set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2); +set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2); +set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2); +set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3); +set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3); +set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3); +set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3); +set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3); +set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4); +set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4); +set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4); +set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4); +set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4); +set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5); +set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5); +set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5); +set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5); +set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5); +set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6); +set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6); +set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6); +set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6); +set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6); +set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7); +set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7); +set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7); +set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7); +set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7); +set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS); +set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD); +set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0); +set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1); +set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0); +set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1); +set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2); +set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3); +set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4); +set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD); +set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD); +set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0); +set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1); +set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2); +set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3); +set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0); +set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1); +set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2); +set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3); + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR); +set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC); +set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN); +set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS); +set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS); +set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR); +set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD); +set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC); +set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD); +set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0); +set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1); +set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2); +set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3); +set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4); +set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5); +set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6); +set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7); +set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0); +set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0); +set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1); +set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1); +set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2); +set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2); +set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3); +set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3); +set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4); +set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4); +set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5); +set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5); +set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6); +set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6); +set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7); +set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7); +set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0); +set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0); +set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0); +set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0); +set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0); +set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1); +set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1); +set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1); +set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1); +set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1); +set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2); +set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2); +set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2); +set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2); +set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2); +set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3); +set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3); +set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3); +set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3); +set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3); +set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4); +set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4); +set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4); +set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4); +set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4); +set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5); +set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5); +set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5); +set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5); +set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5); +set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6); +set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6); +set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6); +set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6); +set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6); +set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7); +set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7); +set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7); +set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7); +set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7); +set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS); +set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD); +set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0); +set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1); +set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0); +set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1); +set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2); +set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3); +set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4); +set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD); +set_reset_data( dmac0_s__WD, val_dmac0_s__WD); +set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0); +set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1); +set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2); +set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3); +set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0); +set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1); +set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2); +set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3); + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK); +set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK); +set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA); +set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG); +set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS); +set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL); +set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW); +set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW); + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl); +set_reset_data( gem0__net_cfg, val_gem0__net_cfg); +set_reset_data( gem0__net_status, val_gem0__net_status); +set_reset_data( gem0__user_io, val_gem0__user_io); +set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg); +set_reset_data( gem0__tx_status, val_gem0__tx_status); +set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar); +set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar); +set_reset_data( gem0__rx_status, val_gem0__rx_status); +set_reset_data( gem0__intr_status, val_gem0__intr_status); +set_reset_data( gem0__intr_en, val_gem0__intr_en); +set_reset_data( gem0__intr_dis, val_gem0__intr_dis); +set_reset_data( gem0__intr_mask, val_gem0__intr_mask); +set_reset_data( gem0__phy_maint, val_gem0__phy_maint); +set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq); +set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq); +set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd); +set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd); +set_reset_data( gem0__hash_bot, val_gem0__hash_bot); +set_reset_data( gem0__hash_top, val_gem0__hash_top); +set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot); +set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top); +set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot); +set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top); +set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot); +set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top); +set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot); +set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top); +set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1); +set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2); +set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3); +set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4); +set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan); +set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch); +set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan); +set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause); +set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot); +set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top); +set_reset_data( gem0__module_id, val_gem0__module_id); +set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot); +set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top); +set_reset_data( gem0__frames_tx, val_gem0__frames_tx); +set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx); +set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx); +set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx); +set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx); +set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx); +set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx); +set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx); +set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx); +set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx); +set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx); +set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs); +set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames); +set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames); +set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns); +set_reset_data( gem0__late_collisns, val_gem0__late_collisns); +set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames); +set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs); +set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot); +set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top); +set_reset_data( gem0__frames_rx, val_gem0__frames_rx); +set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx); +set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx); +set_reset_data( gem0__pause_rx, val_gem0__pause_rx); +set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx); +set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx); +set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx); +set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx); +set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx); +set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx); +set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx); +set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx); +set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx); +set_reset_data( gem0__jab_rx, val_gem0__jab_rx); +set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors); +set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors); +set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors); +set_reset_data( gem0__align_errors, val_gem0__align_errors); +set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors); +set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors); +set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors); +set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors); +set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors); +set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s); +set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns); +set_reset_data( gem0__timer_s, val_gem0__timer_s); +set_reset_data( gem0__timer_ns, val_gem0__timer_ns); +set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust); +set_reset_data( gem0__timer_incr, val_gem0__timer_incr); +set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s); +set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns); +set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s); +set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns); +set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s); +set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns); +set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s); +set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns); +set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl); +set_reset_data( gem0__pcs_status, val_gem0__pcs_status); +set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id); +set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id); +set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad); +set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability); +set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp); +set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg); +set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg); +set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status); +set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1); +set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2); +set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3); +set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4); +set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5); +set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6); +set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7); +set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1); +set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2); +set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3); +set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4); +set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5); +set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6); +set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7); +set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1); +set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2); +set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3); +set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4); +set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5); +set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6); +set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7); +set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1); +set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2); +set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3); +set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4); +set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5); +set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6); +set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7); +set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1); +set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2); +set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3); +set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4); +set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5); +set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6); +set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7); +set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0); +set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1); +set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2); +set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3); +set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4); +set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5); +set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6); +set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7); +set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8); +set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9); +set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10); +set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11); +set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12); +set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13); +set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14); +set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15); +set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0); +set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1); +set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2); +set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3); +set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4); +set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5); +set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6); +set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7); +set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8); +set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9); +set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10); +set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11); +set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12); +set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13); +set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14); +set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15); +set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1); +set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2); +set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3); +set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4); +set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5); +set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6); +set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7); +set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1); +set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2); +set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3); +set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4); +set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5); +set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6); +set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7); +set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1); +set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2); +set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3); +set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4); +set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5); +set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6); +set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7); + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl); +set_reset_data( gem1__net_cfg, val_gem1__net_cfg); +set_reset_data( gem1__net_status, val_gem1__net_status); +set_reset_data( gem1__user_io, val_gem1__user_io); +set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg); +set_reset_data( gem1__tx_status, val_gem1__tx_status); +set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar); +set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar); +set_reset_data( gem1__rx_status, val_gem1__rx_status); +set_reset_data( gem1__intr_status, val_gem1__intr_status); +set_reset_data( gem1__intr_en, val_gem1__intr_en); +set_reset_data( gem1__intr_dis, val_gem1__intr_dis); +set_reset_data( gem1__intr_mask, val_gem1__intr_mask); +set_reset_data( gem1__phy_maint, val_gem1__phy_maint); +set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq); +set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq); +set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd); +set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd); +set_reset_data( gem1__hash_bot, val_gem1__hash_bot); +set_reset_data( gem1__hash_top, val_gem1__hash_top); +set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot); +set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top); +set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot); +set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top); +set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot); +set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top); +set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot); +set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top); +set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1); +set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2); +set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3); +set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4); +set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan); +set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch); +set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan); +set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause); +set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot); +set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top); +set_reset_data( gem1__module_id, val_gem1__module_id); +set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot); +set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top); +set_reset_data( gem1__frames_tx, val_gem1__frames_tx); +set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx); +set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx); +set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx); +set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx); +set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx); +set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx); +set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx); +set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx); +set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx); +set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx); +set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs); +set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames); +set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames); +set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns); +set_reset_data( gem1__late_collisns, val_gem1__late_collisns); +set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames); +set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs); +set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot); +set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top); +set_reset_data( gem1__frames_rx, val_gem1__frames_rx); +set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx); +set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx); +set_reset_data( gem1__pause_rx, val_gem1__pause_rx); +set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx); +set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx); +set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx); +set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx); +set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx); +set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx); +set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx); +set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx); +set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx); +set_reset_data( gem1__jab_rx, val_gem1__jab_rx); +set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors); +set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors); +set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors); +set_reset_data( gem1__align_errors, val_gem1__align_errors); +set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors); +set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors); +set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors); +set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors); +set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors); +set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s); +set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns); +set_reset_data( gem1__timer_s, val_gem1__timer_s); +set_reset_data( gem1__timer_ns, val_gem1__timer_ns); +set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust); +set_reset_data( gem1__timer_incr, val_gem1__timer_incr); +set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s); +set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns); +set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s); +set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns); +set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s); +set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns); +set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s); +set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns); +set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl); +set_reset_data( gem1__pcs_status, val_gem1__pcs_status); +set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id); +set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id); +set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad); +set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability); +set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp); +set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg); +set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg); +set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status); +set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1); +set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2); +set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3); +set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4); +set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5); +set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6); +set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7); +set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1); +set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2); +set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3); +set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4); +set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5); +set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6); +set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7); +set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1); +set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2); +set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3); +set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4); +set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5); +set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6); +set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7); +set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1); +set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2); +set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3); +set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4); +set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5); +set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6); +set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7); +set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1); +set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2); +set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3); +set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4); +set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5); +set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6); +set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7); +set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0); +set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1); +set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2); +set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3); +set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4); +set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5); +set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6); +set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7); +set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8); +set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9); +set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10); +set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11); +set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12); +set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13); +set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14); +set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15); +set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0); +set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1); +set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2); +set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3); +set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4); +set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5); +set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6); +set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7); +set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8); +set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9); +set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10); +set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11); +set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12); +set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13); +set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14); +set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15); +set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1); +set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2); +set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3); +set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4); +set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5); +set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6); +set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7); +set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1); +set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2); +set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3); +set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4); +set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5); +set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6); +set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7); +set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1); +set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2); +set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3); +set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4); +set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5); +set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6); +set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7); + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW); +set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW); +set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW); +set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW); +set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW); +set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW); +set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW); +set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW); +set_reset_data( gpio__DATA_0, val_gpio__DATA_0); +set_reset_data( gpio__DATA_1, val_gpio__DATA_1); +set_reset_data( gpio__DATA_2, val_gpio__DATA_2); +set_reset_data( gpio__DATA_3, val_gpio__DATA_3); +set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO); +set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO); +set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO); +set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO); +set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0); +set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0); +set_reset_data( gpio__OEN_0, val_gpio__OEN_0); +set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0); +set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0); +set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0); +set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0); +set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0); +set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0); +set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0); +set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1); +set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1); +set_reset_data( gpio__OEN_1, val_gpio__OEN_1); +set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1); +set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1); +set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1); +set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1); +set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1); +set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1); +set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1); +set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2); +set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2); +set_reset_data( gpio__OEN_2, val_gpio__OEN_2); +set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2); +set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2); +set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2); +set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2); +set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2); +set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2); +set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2); +set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3); +set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3); +set_reset_data( gpio__OEN_3, val_gpio__OEN_3); +set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3); +set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3); +set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3); +set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3); +set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3); +set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3); +set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3); + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap); +set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0); +set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1); +set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi); +set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou); +set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves); +set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc); +set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4); +set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5); +set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6); +set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7); +set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0); +set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1); +set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2); +set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3); +set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0); +set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1); +set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2); +set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0); +set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0); +set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1); +set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1); +set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0); +set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0); +set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1); +set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1); +set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0); +set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0); +set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1); +set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1); +set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou); + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl); +set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot); +set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot); +set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p); +set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b); +set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r); +set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p); +set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b); +set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r); + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl); +set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot); +set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot); +set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p); +set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b); +set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r); +set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p); +set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b); +set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r); + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl); +set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot); +set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot); +set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p); +set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b); +set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r); +set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p); +set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b); +set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r); + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap); +set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0); +set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1); +set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb); + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0); +set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0); +set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0); +set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0); +set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0); +set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0); +set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0); +set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0); +set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0); +set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0); +set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0); + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0); +set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0); +set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0); +set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0); +set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0); +set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0); +set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0); +set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0); +set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0); +set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0); +set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0); + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id); +set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type); +set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control); +set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control); +set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control); +set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control); +set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl); +set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg); +set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg); +set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1); +set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0); +set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask); +set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status); +set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status); +set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear); +set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync); +set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa); +set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way); +set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa); +set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index); +set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way); +set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa); +set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index); +set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way); +set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0); +set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0); +set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1); +set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1); +set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2); +set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2); +set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3); +set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3); +set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4); +set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4); +set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5); +set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5); +set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6); +set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6); +set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7); +set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7); +set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en); +set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way); +set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start); +set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end); +set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl); +set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl); +set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl); + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER); +set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER); +set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register); +set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State); +set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register); +set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register); +set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC); +set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register); +set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR); +set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR); +set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR); +set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR); +set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR); +set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR); +set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR); +set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR); +set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR); +set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0); +set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1); +set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register); +set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0); +set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1); +set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register); +set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register); +set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register); +set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register); +set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register); +set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register); +set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register); +set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register); +set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register); +set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR); +set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR); +set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR); +set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0); +set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1); +set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2); +set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0); +set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1); +set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2); +set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0); +set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1); +set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2); +set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0); +set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1); +set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2); +set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0); +set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1); +set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2); +set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0); +set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1); +set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2); +set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0); +set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1); +set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2); +set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3); +set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4); +set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5); +set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6); +set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7); +set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8); +set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9); +set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10); +set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11); +set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12); +set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13); +set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14); +set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15); +set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16); +set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17); +set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18); +set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19); +set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20); +set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21); +set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22); +set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23); +set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0); +set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1); +set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2); +set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3); +set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4); +set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5); +set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6); +set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7); +set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8); +set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9); +set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10); +set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11); +set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12); +set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13); +set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14); +set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15); +set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16); +set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17); +set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18); +set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19); +set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20); +set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21); +set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22); +set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23); +set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0); +set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1); +set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2); +set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3); +set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4); +set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5); +set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status); +set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0); +set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1); +set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR); +set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4); +set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5); +set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6); +set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7); +set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0); +set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1); +set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2); +set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3); +set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0); +set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1); +set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2); +set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3); + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL); +set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS); +set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS); +set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL); + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +/// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( qspi__Config_reg, val_qspi__Config_reg); +set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG); +set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG); +set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG); +set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG); +set_reset_data( qspi__En_REG, val_qspi__En_REG); +set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG); +set_reset_data( qspi__TXD0, val_qspi__TXD0); +set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG); +set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG); +set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG); +set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG); +set_reset_data( qspi__GPIO, val_qspi__GPIO); +set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ); +set_reset_data( qspi__TXD1, val_qspi__TXD1); +set_reset_data( qspi__TXD2, val_qspi__TXD2); +set_reset_data( qspi__TXD3, val_qspi__TXD3); +set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG); +set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS); +set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID); + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register); +set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count); +set_reset_data( sd0__Argument, val_sd0__Argument); +set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command); +set_reset_data( sd0__Response0, val_sd0__Response0); +set_reset_data( sd0__Response1, val_sd0__Response1); +set_reset_data( sd0__Response2, val_sd0__Response2); +set_reset_data( sd0__Response3, val_sd0__Response3); +set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port); +set_reset_data( sd0__Present_State, val_sd0__Present_State); +set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status); +set_reset_data( sd0__Capabilities, val_sd0__Capabilities); +set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities); +set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status); +set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address); +set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control); +set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection); +set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support); +set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register); +set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count); +set_reset_data( sd1__Argument, val_sd1__Argument); +set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command); +set_reset_data( sd1__Response0, val_sd1__Response0); +set_reset_data( sd1__Response1, val_sd1__Response1); +set_reset_data( sd1__Response2, val_sd1__Response2); +set_reset_data( sd1__Response3, val_sd1__Response3); +set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port); +set_reset_data( sd1__Present_State, val_sd1__Present_State); +set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status); +set_reset_data( sd1__Capabilities, val_sd1__Capabilities); +set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities); +set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status); +set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address); +set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control); +set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection); +set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support); +set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( slcr__SCL, val_slcr__SCL); +set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK); +set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK); +set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA); +set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL); +set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL); +set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL); +set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS); +set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG); +set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG); +set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG); +set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL); +set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL); +set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL); +set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL); +set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL); +set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL); +set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL); +set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL); +set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL); +set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL); +set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL); +set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL); +set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL); +set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL); +set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL); +set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL); +set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL); +set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL); +set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL); +set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL); +set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL); +set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL); +set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL); +set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT); +set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA); +set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL); +set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL); +set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT); +set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA); +set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL); +set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL); +set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT); +set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA); +set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL); +set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL); +set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT); +set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA); +set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL); +set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM); +set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST); +set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR); +set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE); +set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG); +set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT); +set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT); +set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL); +set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL); +set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL); +set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL); +set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL); +set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL); +set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL); +set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL); +set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL); +set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL); +set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL); +set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL); +set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL); +set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL); +set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL); +set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL); +set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL); +set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL); +set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL); +set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON); +set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR); +set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS); +set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE); +set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL); +set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL); +set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0); +set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1); +set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM); +set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM); +set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS); +set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS); +set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS); +set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM); +set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO); +set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB); +set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M); +set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI); +set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL); +set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE); +set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT); +set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START); +set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START); +set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA); +set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL); +set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS); +set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00); +set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01); +set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02); +set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03); +set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04); +set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05); +set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06); +set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07); +set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08); +set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09); +set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10); +set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11); +set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12); +set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13); +set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14); +set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15); +set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16); +set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17); +set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18); +set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19); +set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20); +set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21); +set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22); +set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23); +set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24); +set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25); +set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26); +set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27); +set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28); +set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29); +set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30); +set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31); +set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32); +set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33); +set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34); +set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35); +set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36); +set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37); +set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38); +set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39); +set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40); +set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41); +set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42); +set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43); +set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44); +set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45); +set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46); +set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47); +set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48); +set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49); +set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50); +set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51); +set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52); +set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53); +set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL); +set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK); +set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0); +set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1); +set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL); +set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL); +set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN); +set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG); +set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0); +set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1); +set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2); +set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0); +set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1); +set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2); +set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM); +set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM); +set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01); +set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01); +set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0); +set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1); +set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0); +set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1); +set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI); +set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM); +set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0); +set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1); +set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2); +set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0); +set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1); +set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2); +set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0); +set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1); +set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2); +set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0); +set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1); +set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2); +set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM); +set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0); +set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1); +set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM); +set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM); +set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL); +set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18); +set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25); +set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33); +set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL); +set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL); +set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL); +set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0); +set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1); +set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0); +set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1); +set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0); +set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1); +set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK); +set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL); +set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL); +set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS); + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( smcc__memc_status, val_smcc__memc_status); +set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg); +set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set); +set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr); +set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd); +set_reset_data( smcc__set_cycles, val_smcc__set_cycles); +set_reset_data( smcc__set_opmode, val_smcc__set_opmode); +set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0); +set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1); +set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0); +set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0); +set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1); +set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1); +set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0); +set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0); +set_reset_data( smcc__user_status, val_smcc__user_status); +set_reset_data( smcc__user_config, val_smcc__user_config); +set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0); +set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0); +set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0); +set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0); +set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0); +set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0); +set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0); +set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0); +set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0); +set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0); +set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1); +set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1); +set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1); +set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1); +set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1); +set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1); +set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1); +set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1); +set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1); +set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1); +set_reset_data( smcc__integration_test, val_smcc__integration_test); +set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0); +set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1); +set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2); +set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3); +set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0); +set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1); +set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2); +set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3); + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0); +set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0); +set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0); +set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0); +set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0); +set_reset_data( spi0__En_reg0, val_spi0__En_reg0); +set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0); +set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0); +set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0); +set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0); +set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0); +set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0); +set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0); + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0); +set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0); +set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0); +set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0); +set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0); +set_reset_data( spi1__En_reg0, val_spi1__En_reg0); +set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0); +set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0); +set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0); +set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0); +set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0); +set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0); +set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0); + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( swdt__MODE, val_swdt__MODE); +set_reset_data( swdt__CONTROL, val_swdt__CONTROL); +set_reset_data( swdt__RESTART, val_swdt__RESTART); +set_reset_data( swdt__STATUS, val_swdt__STATUS); + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1); +set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2); +set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3); +set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1); +set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2); +set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3); +set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1); +set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2); +set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3); +set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1); +set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2); +set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3); +set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1); +set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2); +set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3); +set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1); +set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2); +set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3); +set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1); +set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2); +set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3); +set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1); +set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2); +set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3); +set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1); +set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2); +set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3); +set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1); +set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2); +set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3); +set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1); +set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2); +set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3); + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1); +set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2); +set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3); +set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1); +set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2); +set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3); +set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1); +set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2); +set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3); +set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1); +set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2); +set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3); +set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1); +set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2); +set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3); +set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1); +set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2); +set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3); +set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1); +set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2); +set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3); +set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1); +set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2); +set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3); +set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1); +set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2); +set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3); +set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1); +set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2); +set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3); +set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1); +set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2); +set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3); + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0); +set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0); +set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0); +set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0); +set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0); +set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0); +set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0); +set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0); +set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0); +set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0); +set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0); +set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0); +set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0); +set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0); +set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0); +set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0); +set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0); +set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0); +set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0); +set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0); +set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0); +set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0); +set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0); +set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0); +set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0); +set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0); +set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0); +set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0); +set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0); +set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0); +set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0); +set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0); +set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0); +set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0); +set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb0__ID, val_usb0__ID); +set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL); +set_reset_data( usb0__HWHOST, val_usb0__HWHOST); +set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE); +set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF); +set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF); +set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD); +set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL); +set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD); +set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL); +set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG); +set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION); +set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS); +set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS); +set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION); +set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS); +set_reset_data( usb0__USBCMD, val_usb0__USBCMD); +set_reset_data( usb0__USBSTS, val_usb0__USBSTS); +set_reset_data( usb0__USBINTR, val_usb0__USBINTR); +set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX); +set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL); +set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE); +set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING); +set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING); +set_reset_data( usb0__IC_USB, val_usb0__IC_USB); +set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT); +set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK); +set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN); +set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG); +set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1); +set_reset_data( usb0__OTGSC, val_usb0__OTGSC); +set_reset_data( usb0__USBMODE, val_usb0__USBMODE); +set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT); +set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME); +set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH); +set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT); +set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE); +set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0); +set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1); +set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2); +set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3); +set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4); +set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5); +set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6); +set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7); +set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8); +set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9); +set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10); +set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11); +set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12); + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb1__ID, val_usb1__ID); +set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL); +set_reset_data( usb1__HWHOST, val_usb1__HWHOST); +set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE); +set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF); +set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF); +set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD); +set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL); +set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD); +set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL); +set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG); +set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION); +set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS); +set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS); +set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION); +set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS); +set_reset_data( usb1__USBCMD, val_usb1__USBCMD); +set_reset_data( usb1__USBSTS, val_usb1__USBSTS); +set_reset_data( usb1__USBINTR, val_usb1__USBINTR); +set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX); +set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL); +set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE); +set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING); +set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING); +set_reset_data( usb1__IC_USB, val_usb1__IC_USB); +set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT); +set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK); +set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN); +set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG); +set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1); +set_reset_data( usb1__OTGSC, val_usb1__OTGSC); +set_reset_data( usb1__USBMODE, val_usb1__USBMODE); +set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT); +set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME); +set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH); +set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT); +set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE); +set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0); +set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1); +set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2); +set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3); +set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4); +set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5); +set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6); +set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7); +set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8); +set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9); +set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10); +set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11); +set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12); diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_params.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_params.v new file mode 100644 index 0000000..9d2acdb --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_reg_params.v @@ -0,0 +1,10519 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_reg_params.v + * + * Date : 2012-11 + * + * Description : Parameters for Register Address and Default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000; +parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004; +parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_RDQOS = 32'hF8008008; +parameter val_afi0__AFI_RDQOS = 32'h00000000; +parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C; +parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDEBUG = 32'hF8008010; +parameter val_afi0__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014; +parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018; +parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_WRQOS = 32'hF800801C; +parameter val_afi0__AFI_WRQOS = 32'h00000000; +parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020; +parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDEBUG = 32'hF8008024; +parameter val_afi0__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000; +parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004; +parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_RDQOS = 32'hF8009008; +parameter val_afi1__AFI_RDQOS = 32'h00000000; +parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C; +parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDEBUG = 32'hF8009010; +parameter val_afi1__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014; +parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018; +parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_WRQOS = 32'hF800901C; +parameter val_afi1__AFI_WRQOS = 32'h00000000; +parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020; +parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDEBUG = 32'hF8009024; +parameter val_afi1__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000; +parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004; +parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_RDQOS = 32'hF800A008; +parameter val_afi2__AFI_RDQOS = 32'h00000000; +parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C; +parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDEBUG = 32'hF800A010; +parameter val_afi2__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014; +parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018; +parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_WRQOS = 32'hF800A01C; +parameter val_afi2__AFI_WRQOS = 32'h00000000; +parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020; +parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDEBUG = 32'hF800A024; +parameter val_afi2__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000; +parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004; +parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_RDQOS = 32'hF800B008; +parameter val_afi3__AFI_RDQOS = 32'h00000000; +parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C; +parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDEBUG = 32'hF800B010; +parameter val_afi3__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014; +parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018; +parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_WRQOS = 32'hF800B01C; +parameter val_afi3__AFI_WRQOS = 32'h00000000; +parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020; +parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDEBUG = 32'hF800B024; +parameter val_afi3__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can0__SRR = 32'hE0008000; +parameter val_can0__SRR = 32'h00000000; +parameter mask_can0__SRR = 32'hFFFFFFFF; + +parameter can0__MSR = 32'hE0008004; +parameter val_can0__MSR = 32'h00000000; +parameter mask_can0__MSR = 32'hFFFFFFFF; + +parameter can0__BRPR = 32'hE0008008; +parameter val_can0__BRPR = 32'h00000000; +parameter mask_can0__BRPR = 32'hFFFFFFFF; + +parameter can0__BTR = 32'hE000800C; +parameter val_can0__BTR = 32'h00000000; +parameter mask_can0__BTR = 32'hFFFFFFFF; + +parameter can0__ECR = 32'hE0008010; +parameter val_can0__ECR = 32'h00000000; +parameter mask_can0__ECR = 32'hFFFFFFFF; + +parameter can0__ESR = 32'hE0008014; +parameter val_can0__ESR = 32'h00000000; +parameter mask_can0__ESR = 32'hFFFFFFFF; + +parameter can0__SR = 32'hE0008018; +parameter val_can0__SR = 32'h00000001; +parameter mask_can0__SR = 32'hFFFFFFFF; + +parameter can0__ISR = 32'hE000801C; +parameter val_can0__ISR = 32'h00006000; +parameter mask_can0__ISR = 32'hFFFFFFFF; + +parameter can0__IER = 32'hE0008020; +parameter val_can0__IER = 32'h00000000; +parameter mask_can0__IER = 32'hFFFFFFFF; + +parameter can0__ICR = 32'hE0008024; +parameter val_can0__ICR = 32'h00000000; +parameter mask_can0__ICR = 32'hFFFFFFFF; + +parameter can0__TCR = 32'hE0008028; +parameter val_can0__TCR = 32'h00000000; +parameter mask_can0__TCR = 32'hFFFFFFFF; + +parameter can0__WIR = 32'hE000802C; +parameter val_can0__WIR = 32'h00003F3F; +parameter mask_can0__WIR = 32'hFFFFFFFF; + +parameter can0__TXFIFO_ID = 32'hE0008030; +parameter val_can0__TXFIFO_ID = 32'h00000000; +parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DLC = 32'hE0008034; +parameter val_can0__TXFIFO_DLC = 32'h00000000; +parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA1 = 32'hE0008038; +parameter val_can0__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA2 = 32'hE000803C; +parameter val_can0__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can0__TXHPB_ID = 32'hE0008040; +parameter val_can0__TXHPB_ID = 32'h00000000; +parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF; + +parameter can0__TXHPB_DLC = 32'hE0008044; +parameter val_can0__TXHPB_DLC = 32'h00000000; +parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA1 = 32'hE0008048; +parameter val_can0__TXHPB_DATA1 = 32'h00000000; +parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA2 = 32'hE000804C; +parameter val_can0__TXHPB_DATA2 = 32'h00000000; +parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can0__RXFIFO_ID = 32'hE0008050; +parameter val_can0__RXFIFO_ID = 32'h00000000; +parameter mask_can0__RXFIFO_ID = 32'h00000000; + +parameter can0__RXFIFO_DLC = 32'hE0008054; +parameter val_can0__RXFIFO_DLC = 32'h00000000; +parameter mask_can0__RXFIFO_DLC = 32'h00000000; + +parameter can0__RXFIFO_DATA1 = 32'hE0008058; +parameter val_can0__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA1 = 32'h00000000; + +parameter can0__RXFIFO_DATA2 = 32'hE000805C; +parameter val_can0__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA2 = 32'h00000000; + +parameter can0__AFR = 32'hE0008060; +parameter val_can0__AFR = 32'h00000000; +parameter mask_can0__AFR = 32'hFFFFFFFF; + +parameter can0__AFMR1 = 32'hE0008064; +parameter val_can0__AFMR1 = 32'h00000000; +parameter mask_can0__AFMR1 = 32'h00000000; + +parameter can0__AFIR1 = 32'hE0008068; +parameter val_can0__AFIR1 = 32'h00000000; +parameter mask_can0__AFIR1 = 32'h00000000; + +parameter can0__AFMR2 = 32'hE000806C; +parameter val_can0__AFMR2 = 32'h00000000; +parameter mask_can0__AFMR2 = 32'h00000000; + +parameter can0__AFIR2 = 32'hE0008070; +parameter val_can0__AFIR2 = 32'h00000000; +parameter mask_can0__AFIR2 = 32'h00000000; + +parameter can0__AFMR3 = 32'hE0008074; +parameter val_can0__AFMR3 = 32'h00000000; +parameter mask_can0__AFMR3 = 32'h00000000; + +parameter can0__AFIR3 = 32'hE0008078; +parameter val_can0__AFIR3 = 32'h00000000; +parameter mask_can0__AFIR3 = 32'h00000000; + +parameter can0__AFMR4 = 32'hE000807C; +parameter val_can0__AFMR4 = 32'h00000000; +parameter mask_can0__AFMR4 = 32'h00000000; + +parameter can0__AFIR4 = 32'hE0008080; +parameter val_can0__AFIR4 = 32'h00000000; +parameter mask_can0__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can1__SRR = 32'hE0009000; +parameter val_can1__SRR = 32'h00000000; +parameter mask_can1__SRR = 32'hFFFFFFFF; + +parameter can1__MSR = 32'hE0009004; +parameter val_can1__MSR = 32'h00000000; +parameter mask_can1__MSR = 32'hFFFFFFFF; + +parameter can1__BRPR = 32'hE0009008; +parameter val_can1__BRPR = 32'h00000000; +parameter mask_can1__BRPR = 32'hFFFFFFFF; + +parameter can1__BTR = 32'hE000900C; +parameter val_can1__BTR = 32'h00000000; +parameter mask_can1__BTR = 32'hFFFFFFFF; + +parameter can1__ECR = 32'hE0009010; +parameter val_can1__ECR = 32'h00000000; +parameter mask_can1__ECR = 32'hFFFFFFFF; + +parameter can1__ESR = 32'hE0009014; +parameter val_can1__ESR = 32'h00000000; +parameter mask_can1__ESR = 32'hFFFFFFFF; + +parameter can1__SR = 32'hE0009018; +parameter val_can1__SR = 32'h00000001; +parameter mask_can1__SR = 32'hFFFFFFFF; + +parameter can1__ISR = 32'hE000901C; +parameter val_can1__ISR = 32'h00006000; +parameter mask_can1__ISR = 32'hFFFFFFFF; + +parameter can1__IER = 32'hE0009020; +parameter val_can1__IER = 32'h00000000; +parameter mask_can1__IER = 32'hFFFFFFFF; + +parameter can1__ICR = 32'hE0009024; +parameter val_can1__ICR = 32'h00000000; +parameter mask_can1__ICR = 32'hFFFFFFFF; + +parameter can1__TCR = 32'hE0009028; +parameter val_can1__TCR = 32'h00000000; +parameter mask_can1__TCR = 32'hFFFFFFFF; + +parameter can1__WIR = 32'hE000902C; +parameter val_can1__WIR = 32'h00003F3F; +parameter mask_can1__WIR = 32'hFFFFFFFF; + +parameter can1__TXFIFO_ID = 32'hE0009030; +parameter val_can1__TXFIFO_ID = 32'h00000000; +parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DLC = 32'hE0009034; +parameter val_can1__TXFIFO_DLC = 32'h00000000; +parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA1 = 32'hE0009038; +parameter val_can1__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA2 = 32'hE000903C; +parameter val_can1__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can1__TXHPB_ID = 32'hE0009040; +parameter val_can1__TXHPB_ID = 32'h00000000; +parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF; + +parameter can1__TXHPB_DLC = 32'hE0009044; +parameter val_can1__TXHPB_DLC = 32'h00000000; +parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA1 = 32'hE0009048; +parameter val_can1__TXHPB_DATA1 = 32'h00000000; +parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA2 = 32'hE000904C; +parameter val_can1__TXHPB_DATA2 = 32'h00000000; +parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can1__RXFIFO_ID = 32'hE0009050; +parameter val_can1__RXFIFO_ID = 32'h00000000; +parameter mask_can1__RXFIFO_ID = 32'h00000000; + +parameter can1__RXFIFO_DLC = 32'hE0009054; +parameter val_can1__RXFIFO_DLC = 32'h00000000; +parameter mask_can1__RXFIFO_DLC = 32'h00000000; + +parameter can1__RXFIFO_DATA1 = 32'hE0009058; +parameter val_can1__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA1 = 32'h00000000; + +parameter can1__RXFIFO_DATA2 = 32'hE000905C; +parameter val_can1__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA2 = 32'h00000000; + +parameter can1__AFR = 32'hE0009060; +parameter val_can1__AFR = 32'h00000000; +parameter mask_can1__AFR = 32'hFFFFFFFF; + +parameter can1__AFMR1 = 32'hE0009064; +parameter val_can1__AFMR1 = 32'h00000000; +parameter mask_can1__AFMR1 = 32'h00000000; + +parameter can1__AFIR1 = 32'hE0009068; +parameter val_can1__AFIR1 = 32'h00000000; +parameter mask_can1__AFIR1 = 32'h00000000; + +parameter can1__AFMR2 = 32'hE000906C; +parameter val_can1__AFMR2 = 32'h00000000; +parameter mask_can1__AFMR2 = 32'h00000000; + +parameter can1__AFIR2 = 32'hE0009070; +parameter val_can1__AFIR2 = 32'h00000000; +parameter mask_can1__AFIR2 = 32'h00000000; + +parameter can1__AFMR3 = 32'hE0009074; +parameter val_can1__AFMR3 = 32'h00000000; +parameter mask_can1__AFMR3 = 32'h00000000; + +parameter can1__AFIR3 = 32'hE0009078; +parameter val_can1__AFIR3 = 32'h00000000; +parameter mask_can1__AFIR3 = 32'h00000000; + +parameter can1__AFMR4 = 32'hE000907C; +parameter val_can1__AFMR4 = 32'h00000000; +parameter mask_can1__AFMR4 = 32'h00000000; + +parameter can1__AFIR4 = 32'hE0009080; +parameter val_can1__AFIR4 = 32'h00000000; +parameter mask_can1__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ddrc__ddrc_ctrl = 32'hF8006000; +parameter val_ddrc__ddrc_ctrl = 32'h00000200; +parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF; + +parameter ddrc__Two_rank_cfg = 32'hF8006004; +parameter val_ddrc__Two_rank_cfg = 32'h000C1076; +parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF; + +parameter ddrc__HPR_reg = 32'hF8006008; +parameter val_ddrc__HPR_reg = 32'h03C0780F; +parameter mask_ddrc__HPR_reg = 32'h03FFFFFF; + +parameter ddrc__LPR_reg = 32'hF800600C; +parameter val_ddrc__LPR_reg = 32'h03C0780F; +parameter mask_ddrc__LPR_reg = 32'h03FFFFFF; + +parameter ddrc__WR_reg = 32'hF8006010; +parameter val_ddrc__WR_reg = 32'h0007F80F; +parameter mask_ddrc__WR_reg = 32'h03FFFFFF; + +parameter ddrc__DRAM_param_reg0 = 32'hF8006014; +parameter val_ddrc__DRAM_param_reg0 = 32'h00041016; +parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF; + +parameter ddrc__DRAM_param_reg1 = 32'hF8006018; +parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9; +parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF; + +parameter ddrc__DRAM_param_reg2 = 32'hF800601C; +parameter val_ddrc__DRAM_param_reg2 = 32'h83015904; +parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg3 = 32'hF8006020; +parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0; +parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg4 = 32'hF8006024; +parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C; +parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF; + +parameter ddrc__DRAM_init_param = 32'hF8006028; +parameter val_ddrc__DRAM_init_param = 32'h00002007; +parameter mask_ddrc__DRAM_init_param = 32'h00003FFF; + +parameter ddrc__DRAM_EMR_reg = 32'hF800602C; +parameter val_ddrc__DRAM_EMR_reg = 32'h00000008; +parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030; +parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940; +parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034; +parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034; +parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF; + +parameter ddrc__DRAM_disable_DQ = 32'hF8006038; +parameter val_ddrc__DRAM_disable_DQ = 32'h00000000; +parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF; + +parameter ddrc__DRAM_addr_map_bank = 32'hF800603C; +parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77; +parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF; + +parameter ddrc__DRAM_addr_map_col = 32'hF8006040; +parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000; +parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF; + +parameter ddrc__DRAM_addr_map_row = 32'hF8006044; +parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555; +parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF; + +parameter ddrc__DRAM_ODT_reg = 32'hF8006048; +parameter val_ddrc__DRAM_ODT_reg = 32'h00000249; +parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF; + +parameter ddrc__phy_dbg_reg = 32'hF800604C; +parameter val_ddrc__phy_dbg_reg = 32'h00000000; +parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF; + +parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050; +parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200; +parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF; + +parameter ddrc__mode_sts_reg = 32'hF8006054; +parameter val_ddrc__mode_sts_reg = 32'h00000000; +parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF; + +parameter ddrc__DLL_calib = 32'hF8006058; +parameter val_ddrc__DLL_calib = 32'h00000101; +parameter mask_ddrc__DLL_calib = 32'h0001FFFF; + +parameter ddrc__ODT_delay_hold = 32'hF800605C; +parameter val_ddrc__ODT_delay_hold = 32'h00000023; +parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF; + +parameter ddrc__ctrl_reg1 = 32'hF8006060; +parameter val_ddrc__ctrl_reg1 = 32'h0000003E; +parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF; + +parameter ddrc__ctrl_reg2 = 32'hF8006064; +parameter val_ddrc__ctrl_reg2 = 32'h00020000; +parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF; + +parameter ddrc__ctrl_reg3 = 32'hF8006068; +parameter val_ddrc__ctrl_reg3 = 32'h00284027; +parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF; + +parameter ddrc__ctrl_reg4 = 32'hF800606C; +parameter val_ddrc__ctrl_reg4 = 32'h00001610; +parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF; + +parameter ddrc__ctrl_reg5 = 32'hF8006078; +parameter val_ddrc__ctrl_reg5 = 32'h00455111; +parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF; + +parameter ddrc__ctrl_reg6 = 32'hF800607C; +parameter val_ddrc__ctrl_reg6 = 32'h00032222; +parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF; + +parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0; +parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000; +parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF; + +parameter ddrc__CHE_T_ZQ = 32'hF80060A4; +parameter val_ddrc__CHE_T_ZQ = 32'h10300802; +parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF; + +parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8; +parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A; +parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF; + +parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC; +parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000; +parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF; + +parameter ddrc__reg_2c = 32'hF80060B0; +parameter val_ddrc__reg_2c = 32'h00000000; +parameter mask_ddrc__reg_2c = 32'h1FFFFFFF; + +parameter ddrc__reg_2d = 32'hF80060B4; +parameter val_ddrc__reg_2d = 32'h00000200; +parameter mask_ddrc__reg_2d = 32'h000007FF; + +parameter ddrc__dfi_timing = 32'hF80060B8; +parameter val_ddrc__dfi_timing = 32'h00200067; +parameter mask_ddrc__dfi_timing = 32'h01FFFFFF; + +parameter ddrc__refresh_timer_2 = 32'hF80060BC; +parameter val_ddrc__refresh_timer_2 = 32'h00000000; +parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF; + +parameter ddrc__nc_timing = 32'hF80060C0; +parameter val_ddrc__nc_timing = 32'h00000000; +parameter mask_ddrc__nc_timing = 32'h003FFFFF; + +parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4; +parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003; + +parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8; +parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC; +parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0; +parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4; +parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8; +parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC; +parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001; + +parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0; +parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0; +parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF; + +parameter ddrc__ECC_scrub = 32'hF80060F4; +parameter val_ddrc__ECC_scrub = 32'h00000008; +parameter mask_ddrc__ECC_scrub = 32'h0000000F; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__phy_rcvr_enable = 32'hF8006114; +parameter val_ddrc__phy_rcvr_enable = 32'h00000000; +parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF; + +parameter ddrc__PHY_Config0 = 32'hF8006118; +parameter val_ddrc__PHY_Config0 = 32'h40000001; +parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config1 = 32'hF800611C; +parameter val_ddrc__PHY_Config1 = 32'h40000001; +parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config2 = 32'hF8006120; +parameter val_ddrc__PHY_Config2 = 32'h40000001; +parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config3 = 32'hF8006124; +parameter val_ddrc__PHY_Config3 = 32'h40000001; +parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF; + +parameter ddrc__phy_init_ratio0 = 32'hF800612C; +parameter val_ddrc__phy_init_ratio0 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio1 = 32'hF8006130; +parameter val_ddrc__phy_init_ratio1 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio2 = 32'hF8006134; +parameter val_ddrc__phy_init_ratio2 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio3 = 32'hF8006138; +parameter val_ddrc__phy_init_ratio3 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140; +parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144; +parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148; +parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C; +parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154; +parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158; +parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C; +parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160; +parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_we_cfg0 = 32'hF8006168; +parameter val_ddrc__phy_we_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg1 = 32'hF800616C; +parameter val_ddrc__phy_we_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg2 = 32'hF8006170; +parameter val_ddrc__phy_we_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg3 = 32'hF8006174; +parameter val_ddrc__phy_we_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF; + +parameter ddrc__wr_data_slv0 = 32'hF800617C; +parameter val_ddrc__wr_data_slv0 = 32'h00000080; +parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv1 = 32'hF8006180; +parameter val_ddrc__wr_data_slv1 = 32'h00000080; +parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv2 = 32'hF8006184; +parameter val_ddrc__wr_data_slv2 = 32'h00000080; +parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv3 = 32'hF8006188; +parameter val_ddrc__wr_data_slv3 = 32'h00000080; +parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF; + +parameter ddrc__reg_64 = 32'hF8006190; +parameter val_ddrc__reg_64 = 32'h10020000; +parameter mask_ddrc__reg_64 = 32'hFFFFFFFF; + +parameter ddrc__reg_65 = 32'hF8006194; +parameter val_ddrc__reg_65 = 32'h00000000; +parameter mask_ddrc__reg_65 = 32'h000FFFFF; + +parameter ddrc__reg69_6a0 = 32'hF80061A4; +parameter val_ddrc__reg69_6a0 = 32'h000F0000; +parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF; + +parameter ddrc__reg69_6a1 = 32'hF80061A8; +parameter val_ddrc__reg69_6a1 = 32'h000F0000; +parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d2 = 32'hF80061B0; +parameter val_ddrc__reg6c_6d2 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d3 = 32'hF80061B4; +parameter val_ddrc__reg6c_6d3 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF; + +parameter ddrc__reg6e_710 = 32'hF80061B8; +parameter val_ddrc__reg6e_710 = 32'h00000000; +parameter mask_ddrc__reg6e_710 = 32'h00000000; + +parameter ddrc__reg6e_711 = 32'hF80061BC; +parameter val_ddrc__reg6e_711 = 32'h00000000; +parameter mask_ddrc__reg6e_711 = 32'h00000000; + +parameter ddrc__reg6e_712 = 32'hF80061C0; +parameter val_ddrc__reg6e_712 = 32'h00000000; +parameter mask_ddrc__reg6e_712 = 32'h00000000; + +parameter ddrc__reg6e_713 = 32'hF80061C4; +parameter val_ddrc__reg6e_713 = 32'h00000000; +parameter mask_ddrc__reg6e_713 = 32'h00000000; + +parameter ddrc__phy_dll_sts0 = 32'hF80061CC; +parameter val_ddrc__phy_dll_sts0 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts1 = 32'hF80061D0; +parameter val_ddrc__phy_dll_sts1 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts2 = 32'hF80061D4; +parameter val_ddrc__phy_dll_sts2 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts3 = 32'hF80061D8; +parameter val_ddrc__phy_dll_sts3 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF; + +parameter ddrc__dll_lock_sts = 32'hF80061E0; +parameter val_ddrc__dll_lock_sts = 32'h00000000; +parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF; + +parameter ddrc__phy_ctrl_sts = 32'hF80061E4; +parameter val_ddrc__phy_ctrl_sts = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000; + +parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8; +parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF; + +parameter ddrc__axi_id = 32'hF8006200; +parameter val_ddrc__axi_id = 32'h00153042; +parameter mask_ddrc__axi_id = 32'h03FFFFFF; + +parameter ddrc__page_mask = 32'hF8006204; +parameter val_ddrc__page_mask = 32'h00000000; +parameter mask_ddrc__page_mask = 32'hFFFFFFFF; + +parameter ddrc__axi_priority_wr_port0 = 32'hF8006208; +parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port1 = 32'hF800620C; +parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port2 = 32'hF8006210; +parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port3 = 32'hF8006214; +parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port0 = 32'hF8006218; +parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port1 = 32'hF800621C; +parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port2 = 32'hF8006220; +parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port3 = 32'hF8006224; +parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg0 = 32'hF8006248; +parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg1 = 32'hF800624C; +parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg2 = 32'hF8006250; +parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg3 = 32'hF8006254; +parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF; + +parameter ddrc__perf_mon0 = 32'hF8006260; +parameter val_ddrc__perf_mon0 = 32'h00000000; +parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon1 = 32'hF8006264; +parameter val_ddrc__perf_mon1 = 32'h00000000; +parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon2 = 32'hF8006268; +parameter val_ddrc__perf_mon2 = 32'h00000000; +parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon3 = 32'hF800626C; +parameter val_ddrc__perf_mon3 = 32'h00000000; +parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon20 = 32'hF8006270; +parameter val_ddrc__perf_mon20 = 32'h00000000; +parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon21 = 32'hF8006274; +parameter val_ddrc__perf_mon21 = 32'h00000000; +parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon22 = 32'hF8006278; +parameter val_ddrc__perf_mon22 = 32'h00000000; +parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon23 = 32'hF800627C; +parameter val_ddrc__perf_mon23 = 32'h00000000; +parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon30 = 32'hF8006280; +parameter val_ddrc__perf_mon30 = 32'h00000000; +parameter mask_ddrc__perf_mon30 = 32'h0000FFFF; + +parameter ddrc__perf_mon31 = 32'hF8006284; +parameter val_ddrc__perf_mon31 = 32'h00000000; +parameter mask_ddrc__perf_mon31 = 32'h0000FFFF; + +parameter ddrc__perf_mon32 = 32'hF8006288; +parameter val_ddrc__perf_mon32 = 32'h00000000; +parameter mask_ddrc__perf_mon32 = 32'h0000FFFF; + +parameter ddrc__perf_mon33 = 32'hF800628C; +parameter val_ddrc__perf_mon33 = 32'h00000000; +parameter mask_ddrc__perf_mon33 = 32'h0000FFFF; + +parameter ddrc__trusted_mem_cfg = 32'hF8006290; +parameter val_ddrc__trusted_mem_cfg = 32'h00000000; +parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF; + +parameter ddrc__excl_access_cfg0 = 32'hF8006294; +parameter val_ddrc__excl_access_cfg0 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg1 = 32'hF8006298; +parameter val_ddrc__excl_access_cfg1 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg2 = 32'hF800629C; +parameter val_ddrc__excl_access_cfg2 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg3 = 32'hF80062A0; +parameter val_ddrc__excl_access_cfg3 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF; + +parameter ddrc__mode_reg_read = 32'hF80062A4; +parameter val_ddrc__mode_reg_read = 32'h00000000; +parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl0 = 32'hF80062A8; +parameter val_ddrc__lpddr_ctrl0 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF; + +parameter ddrc__lpddr_ctrl1 = 32'hF80062AC; +parameter val_ddrc__lpddr_ctrl1 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl2 = 32'hF80062B0; +parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015; +parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF; + +parameter ddrc__lpddr_ctrl3 = 32'hF80062B4; +parameter val_ddrc__lpddr_ctrl3 = 32'h00000601; +parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF; + +parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8; +parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF; + +parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC; +parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888; +parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF; + +parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0; +parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF; + + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_axim__GLOBAL_CTRL = 32'hF880C000; +parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002; +parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003; + +parameter debug_axim__GLOBAL_STATUS = 32'hF880C004; +parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000; +parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3; + +parameter debug_axim__FILTER_CTRL = 32'hF880C010; +parameter val_debug_axim__FILTER_CTRL = 32'h00000000; +parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F; + +parameter debug_axim__TRIGGER_CTRL = 32'hF880C020; +parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000; +parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF; + +parameter debug_axim__TRIGGER_STATUS = 32'hF880C024; +parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000; +parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003; + +parameter debug_axim__PACKET_CTRL = 32'hF880C030; +parameter val_debug_axim__PACKET_CTRL = 32'h00070000; +parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF; + +parameter debug_axim__TOUT_CTRL = 32'hF880C040; +parameter val_debug_axim__TOUT_CTRL = 32'h00000000; +parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F; + +parameter debug_axim__TOUT_THRESH = 32'hF880C044; +parameter val_debug_axim__TOUT_THRESH = 32'h00008000; +parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_CURRENT = 32'hF880C050; +parameter val_debug_axim__FIFO_CURRENT = 32'h80000000; +parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_HYSTER = 32'hF880C054; +parameter val_debug_axim__FIFO_HYSTER = 32'h00000100; +parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF; + +parameter debug_axim__SYNC_CURRENT = 32'hF880C060; +parameter val_debug_axim__SYNC_CURRENT = 32'h00000000; +parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF; + +parameter debug_axim__SYNC_RELOAD = 32'hF880C064; +parameter val_debug_axim__SYNC_RELOAD = 32'h00000800; +parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF; + +parameter debug_axim__TSTMP_CURRENT = 32'hF880C070; +parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000; +parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000; + +parameter debug_axim__ADDR0_MASK = 32'hF880C200; +parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_LOWER = 32'hF880C204; +parameter val_debug_axim__ADDR0_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_UPPER = 32'hF880C208; +parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_MISC = 32'hF880C20C; +parameter val_debug_axim__ADDR0_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR1_MASK = 32'hF880C210; +parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_LOWER = 32'hF880C214; +parameter val_debug_axim__ADDR1_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_UPPER = 32'hF880C218; +parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_MISC = 32'hF880C21C; +parameter val_debug_axim__ADDR1_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR2_MASK = 32'hF880C220; +parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_LOWER = 32'hF880C224; +parameter val_debug_axim__ADDR2_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_UPPER = 32'hF880C228; +parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_MISC = 32'hF880C22C; +parameter val_debug_axim__ADDR2_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR3_MASK = 32'hF880C230; +parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_LOWER = 32'hF880C234; +parameter val_debug_axim__ADDR3_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_UPPER = 32'hF880C238; +parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_MISC = 32'hF880C23C; +parameter val_debug_axim__ADDR3_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF; + +parameter debug_axim__ID0_MASK = 32'hF880C300; +parameter val_debug_axim__ID0_MASK = 32'h000003FF; +parameter mask_debug_axim__ID0_MASK = 32'h000003FF; + +parameter debug_axim__ID0_LOWER = 32'hF880C304; +parameter val_debug_axim__ID0_LOWER = 32'h00000000; +parameter mask_debug_axim__ID0_LOWER = 32'h000003FF; + +parameter debug_axim__ID0_UPPER = 32'hF880C308; +parameter val_debug_axim__ID0_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID0_UPPER = 32'h000003FF; + +parameter debug_axim__ID0_MISC = 32'hF880C30C; +parameter val_debug_axim__ID0_MISC = 32'h00000000; +parameter mask_debug_axim__ID0_MISC = 32'h00003FFF; + +parameter debug_axim__ID1_MASK = 32'hF880C310; +parameter val_debug_axim__ID1_MASK = 32'h000003FF; +parameter mask_debug_axim__ID1_MASK = 32'h000003FF; + +parameter debug_axim__ID1_LOWER = 32'hF880C314; +parameter val_debug_axim__ID1_LOWER = 32'h00000000; +parameter mask_debug_axim__ID1_LOWER = 32'h000003FF; + +parameter debug_axim__ID1_UPPER = 32'hF880C318; +parameter val_debug_axim__ID1_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID1_UPPER = 32'h000003FF; + +parameter debug_axim__ID1_MISC = 32'hF880C31C; +parameter val_debug_axim__ID1_MISC = 32'h00000000; +parameter mask_debug_axim__ID1_MISC = 32'h00003FFF; + +parameter debug_axim__ID2_MASK = 32'hF880C320; +parameter val_debug_axim__ID2_MASK = 32'h000003FF; +parameter mask_debug_axim__ID2_MASK = 32'h000003FF; + +parameter debug_axim__ID2_LOWER = 32'hF880C324; +parameter val_debug_axim__ID2_LOWER = 32'h00000000; +parameter mask_debug_axim__ID2_LOWER = 32'h000003FF; + +parameter debug_axim__ID2_UPPER = 32'hF880C328; +parameter val_debug_axim__ID2_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID2_UPPER = 32'h000003FF; + +parameter debug_axim__ID2_MISC = 32'hF880C32C; +parameter val_debug_axim__ID2_MISC = 32'h00000000; +parameter mask_debug_axim__ID2_MISC = 32'h00003FFF; + +parameter debug_axim__ID3_MASK = 32'hF880C330; +parameter val_debug_axim__ID3_MASK = 32'h000003FF; +parameter mask_debug_axim__ID3_MASK = 32'h000003FF; + +parameter debug_axim__ID3_LOWER = 32'hF880C334; +parameter val_debug_axim__ID3_LOWER = 32'h00000000; +parameter mask_debug_axim__ID3_LOWER = 32'h000003FF; + +parameter debug_axim__ID3_UPPER = 32'hF880C338; +parameter val_debug_axim__ID3_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID3_UPPER = 32'h000003FF; + +parameter debug_axim__ID3_MISC = 32'hF880C33C; +parameter val_debug_axim__ID3_MISC = 32'h00000000; +parameter mask_debug_axim__ID3_MISC = 32'h00003FFF; + +parameter debug_axim__AXI_SEL = 32'hF880C800; +parameter val_debug_axim__AXI_SEL = 32'h00000000; +parameter mask_debug_axim__AXI_SEL = 32'h00000007; + +parameter debug_axim__IT_TRIGOUT = 32'hF880CED0; +parameter val_debug_axim__IT_TRIGOUT = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001; + +parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4; +parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000; + +parameter debug_axim__IT_TRIGIN = 32'hF880CED8; +parameter val_debug_axim__IT_TRIGIN = 32'h00000000; +parameter mask_debug_axim__IT_TRIGIN = 32'h00000000; + +parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC; +parameter val_debug_axim__IT_TRIGINACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001; + +parameter debug_axim__IT_ATBDATA = 32'hF880CEEC; +parameter val_debug_axim__IT_ATBDATA = 32'h00000000; +parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F; + +parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0; +parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000; +parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000; + +parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4; +parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F; + +parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8; +parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF; + +parameter debug_axim__IT_CTRL = 32'hF880CF00; +parameter val_debug_axim__IT_CTRL = 32'h00000000; +parameter mask_debug_axim__IT_CTRL = 32'h00000001; + +parameter debug_axim__CLAIM_SET = 32'hF880CFA0; +parameter val_debug_axim__CLAIM_SET = 32'h00000001; +parameter mask_debug_axim__CLAIM_SET = 32'h0000000F; + +parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4; +parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000; +parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F; + +parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0; +parameter val_debug_axim__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_axim__LOCK_STATUS = 32'hF880CFB4; +parameter val_debug_axim__LOCK_STATUS = 32'h00000003; +parameter mask_debug_axim__LOCK_STATUS = 32'h00000007; + +parameter debug_axim__AUTH_STATUS = 32'hF880CFB8; +parameter val_debug_axim__AUTH_STATUS = 32'h00000000; +parameter mask_debug_axim__AUTH_STATUS = 32'h00000033; + +parameter debug_axim__DEV_ID = 32'hF880CFC8; +parameter val_debug_axim__DEV_ID = 32'h00000000; +parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF; + +parameter debug_axim__DEV_TYPE = 32'hF880CFCC; +parameter val_debug_axim__DEV_TYPE = 32'h00000043; +parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID4 = 32'hF880CFD0; +parameter val_debug_axim__PERIPHID4 = 32'h00000003; +parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID5 = 32'hF880CFD4; +parameter val_debug_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID6 = 32'hF880CFD8; +parameter val_debug_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID7 = 32'hF880CFDC; +parameter val_debug_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID0 = 32'hF880CFE0; +parameter val_debug_axim__PERIPHID0 = 32'h000000B2; +parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID1 = 32'hF880CFE4; +parameter val_debug_axim__PERIPHID1 = 32'h00000093; +parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID2 = 32'hF880CFE8; +parameter val_debug_axim__PERIPHID2 = 32'h00000008; +parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID3 = 32'hF880CFEC; +parameter val_debug_axim__PERIPHID3 = 32'h00000002; +parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID0 = 32'hF880CFF0; +parameter val_debug_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID1 = 32'hF880CFF4; +parameter val_debug_axim__COMPID1 = 32'h00000090; +parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID2 = 32'hF880CFF8; +parameter val_debug_axim__COMPID2 = 32'h00000005; +parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID3 = 32'hF880CFFC; +parameter val_debug_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000; +parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010; +parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014; +parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018; +parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C; +parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020; +parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024; +parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028; +parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C; +parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030; +parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034; +parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038; +parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C; +parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0; +parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4; +parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8; +parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC; +parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0; +parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4; +parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8; +parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC; +parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130; +parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134; +parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138; +parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C; +parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti0__CTIGATE = 32'hF8898140; +parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti0__ASICCTL = 32'hF8898144; +parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC; +parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0; +parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4; +parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8; +parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC; +parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0; +parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4; +parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8; +parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00; +parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti0__CTSR = 32'hF8898FA0; +parameter val_debug_cpu_cti0__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F; + +parameter debug_cpu_cti0__CTCR = 32'hF8898FA4; +parameter val_debug_cpu_cti0__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F; + +parameter debug_cpu_cti0__LAR = 32'hF8898FB0; +parameter val_debug_cpu_cti0__LAR = 32'h00000000; +parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti0__LSR = 32'hF8898FB4; +parameter val_debug_cpu_cti0__LSR = 32'h00000003; +parameter mask_debug_cpu_cti0__LSR = 32'h00000007; + +parameter debug_cpu_cti0__ASR = 32'hF8898FB8; +parameter val_debug_cpu_cti0__ASR = 32'h00000005; +parameter mask_debug_cpu_cti0__ASR = 32'h00000005; + +parameter debug_cpu_cti0__DEVID = 32'hF8898FC8; +parameter val_debug_cpu_cti0__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti0__DTIR = 32'hF8898FCC; +parameter val_debug_cpu_cti0__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0; +parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4; +parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8; +parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC; +parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0; +parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4; +parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8; +parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC; +parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0; +parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4; +parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8; +parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC; +parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000; +parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010; +parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014; +parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018; +parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C; +parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020; +parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024; +parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028; +parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C; +parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030; +parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034; +parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038; +parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C; +parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0; +parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4; +parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8; +parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC; +parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0; +parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4; +parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8; +parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC; +parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130; +parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134; +parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138; +parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C; +parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti1__CTIGATE = 32'hF8899140; +parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti1__ASICCTL = 32'hF8899144; +parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC; +parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0; +parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4; +parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8; +parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC; +parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0; +parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4; +parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8; +parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00; +parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti1__CTSR = 32'hF8899FA0; +parameter val_debug_cpu_cti1__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F; + +parameter debug_cpu_cti1__CTCR = 32'hF8899FA4; +parameter val_debug_cpu_cti1__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F; + +parameter debug_cpu_cti1__LAR = 32'hF8899FB0; +parameter val_debug_cpu_cti1__LAR = 32'h00000000; +parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti1__LSR = 32'hF8899FB4; +parameter val_debug_cpu_cti1__LSR = 32'h00000003; +parameter mask_debug_cpu_cti1__LSR = 32'h00000007; + +parameter debug_cpu_cti1__ASR = 32'hF8899FB8; +parameter val_debug_cpu_cti1__ASR = 32'h00000005; +parameter mask_debug_cpu_cti1__ASR = 32'h00000005; + +parameter debug_cpu_cti1__DEVID = 32'hF8899FC8; +parameter val_debug_cpu_cti1__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti1__DTIR = 32'hF8899FCC; +parameter val_debug_cpu_cti1__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0; +parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4; +parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8; +parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC; +parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0; +parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4; +parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8; +parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC; +parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0; +parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4; +parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8; +parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC; +parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000; +parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004; +parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008; +parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C; +parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010; +parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014; +parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C; +parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400; +parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404; +parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408; +parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C; +parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410; +parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414; +parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00; +parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20; +parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40; +parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60; +parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80; +parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0; +parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu0__PMCR = 32'hF8891E04; +parameter val_debug_cpu_pmu0__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08; +parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000; +parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004; +parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008; +parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C; +parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010; +parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014; +parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C; +parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400; +parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404; +parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408; +parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C; +parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410; +parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414; +parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00; +parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20; +parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40; +parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60; +parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80; +parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0; +parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu1__PMCR = 32'hF8893E04; +parameter val_debug_cpu_pmu1__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08; +parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm0__ETMCR = 32'hF889C000; +parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004; +parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008; +parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSR = 32'hF889C010; +parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014; +parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018; +parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024; +parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040; +parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044; +parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048; +parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C; +parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050; +parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054; +parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058; +parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C; +parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080; +parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084; +parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088; +parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C; +parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090; +parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094; +parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098; +parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C; +parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150; +parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154; +parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170; +parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174; +parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180; +parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184; +parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188; +parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C; +parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190; +parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194; +parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C; +parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0; +parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC; +parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0; +parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4; +parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8; +parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC; +parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC; +parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200; +parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm0__OSLSR = 32'hF889C304; +parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314; +parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC; +parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0; +parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8; +parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC; +parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0; +parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4; +parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8; +parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00; +parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0; +parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4; +parameter val_debug_cpu_ptm0__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm0__LAR = 32'hF889CFB0; +parameter val_debug_cpu_ptm0__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__LSR = 32'hF889CFB4; +parameter val_debug_cpu_ptm0__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm0__LSR = 32'h00000007; + +parameter debug_cpu_ptm0__ASR = 32'hF889CFB8; +parameter val_debug_cpu_ptm0__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3; + +parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8; +parameter val_debug_cpu_ptm0__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC; +parameter val_debug_cpu_ptm0__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0; +parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4; +parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8; +parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC; +parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0; +parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4; +parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8; +parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC; +parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0; +parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4; +parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8; +parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC; +parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm1__ETMCR = 32'hF889D000; +parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004; +parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008; +parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSR = 32'hF889D010; +parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014; +parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018; +parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024; +parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040; +parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044; +parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048; +parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C; +parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050; +parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054; +parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058; +parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C; +parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080; +parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084; +parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088; +parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C; +parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090; +parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094; +parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098; +parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C; +parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150; +parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154; +parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170; +parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174; +parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180; +parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184; +parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188; +parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C; +parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190; +parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194; +parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C; +parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0; +parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC; +parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0; +parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4; +parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8; +parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC; +parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC; +parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200; +parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm1__OSLSR = 32'hF889D304; +parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314; +parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC; +parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0; +parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8; +parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC; +parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0; +parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4; +parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8; +parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00; +parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0; +parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4; +parameter val_debug_cpu_ptm1__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm1__LAR = 32'hF889DFB0; +parameter val_debug_cpu_ptm1__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__LSR = 32'hF889DFB4; +parameter val_debug_cpu_ptm1__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm1__LSR = 32'h00000007; + +parameter debug_cpu_ptm1__ASR = 32'hF889DFB8; +parameter val_debug_cpu_ptm1__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3; + +parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8; +parameter val_debug_cpu_ptm1__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC; +parameter val_debug_cpu_ptm1__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0; +parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4; +parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8; +parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC; +parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0; +parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4; +parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8; +parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC; +parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0; +parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4; +parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8; +parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC; +parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_axim__CTICONTROL = 32'hF880A000; +parameter val_debug_cti_axim__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001; + +parameter debug_cti_axim__CTIINTACK = 32'hF880A010; +parameter val_debug_cti_axim__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF; + +parameter debug_cti_axim__CTIAPPSET = 32'hF880A014; +parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018; +parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C; +parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN0 = 32'hF880A020; +parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN1 = 32'hF880A024; +parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN2 = 32'hF880A028; +parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C; +parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN4 = 32'hF880A030; +parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN5 = 32'hF880A034; +parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN6 = 32'hF880A038; +parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C; +parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0; +parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4; +parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8; +parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC; +parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0; +parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4; +parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8; +parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC; +parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130; +parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134; +parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138; +parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C; +parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_axim__CTIGATE = 32'hF880A140; +parameter val_debug_cti_axim__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F; + +parameter debug_cti_axim__ASICCTL = 32'hF880A144; +parameter val_debug_cti_axim__ASICCTL = 32'h00000000; +parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF; + +parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC; +parameter val_debug_cti_axim__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0; +parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4; +parameter val_debug_cti_axim__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8; +parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC; +parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0; +parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHIN = 32'hF880AEF4; +parameter val_debug_cti_axim__ITCHIN = 32'h00000000; +parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8; +parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_axim__ITCTRL = 32'hF880AF00; +parameter val_debug_cti_axim__ITCTRL = 32'h00000000; +parameter mask_debug_cti_axim__ITCTRL = 32'h00000001; + +parameter debug_cti_axim__CTSR = 32'hF880AFA0; +parameter val_debug_cti_axim__CTSR = 32'h0000000F; +parameter mask_debug_cti_axim__CTSR = 32'h0000000F; + +parameter debug_cti_axim__CTCR = 32'hF880AFA4; +parameter val_debug_cti_axim__CTCR = 32'h00000000; +parameter mask_debug_cti_axim__CTCR = 32'h0000000F; + +parameter debug_cti_axim__LAR = 32'hF880AFB0; +parameter val_debug_cti_axim__LAR = 32'h00000000; +parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF; + +parameter debug_cti_axim__LSR = 32'hF880AFB4; +parameter val_debug_cti_axim__LSR = 32'h00000003; +parameter mask_debug_cti_axim__LSR = 32'h00000007; + +parameter debug_cti_axim__ASR = 32'hF880AFB8; +parameter val_debug_cti_axim__ASR = 32'h00000005; +parameter mask_debug_cti_axim__ASR = 32'h00000005; + +parameter debug_cti_axim__DEVID = 32'hF880AFC8; +parameter val_debug_cti_axim__DEVID = 32'h00040800; +parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF; + +parameter debug_cti_axim__DTIR = 32'hF880AFCC; +parameter val_debug_cti_axim__DTIR = 32'h00000014; +parameter mask_debug_cti_axim__DTIR = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0; +parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4; +parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8; +parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC; +parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0; +parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4; +parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8; +parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC; +parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_axim__COMPID0 = 32'hF880AFF0; +parameter val_debug_cti_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF; + +parameter debug_cti_axim__COMPID1 = 32'hF880AFF4; +parameter val_debug_cti_axim__COMPID1 = 32'h00000090; +parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF; + +parameter debug_cti_axim__COMPID2 = 32'hF880AFF8; +parameter val_debug_cti_axim__COMPID2 = 32'h00000005; +parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF; + +parameter debug_cti_axim__COMPID3 = 32'hF880AFFC; +parameter val_debug_cti_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000; +parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010; +parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014; +parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018; +parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C; +parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020; +parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024; +parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028; +parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C; +parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030; +parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034; +parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038; +parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C; +parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130; +parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134; +parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138; +parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C; +parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140; +parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144; +parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC; +parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0; +parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4; +parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8; +parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC; +parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0; +parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4; +parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8; +parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00; +parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0; +parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4; +parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0; +parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4; +parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003; +parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007; + +parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8; +parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005; + +parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8; +parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800; +parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF; + +parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC; +parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014; +parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0; +parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4; +parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8; +parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC; +parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0; +parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4; +parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8; +parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC; +parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0; +parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4; +parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8; +parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC; +parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_ftm__CTICONTROL = 32'hF8809000; +parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001; + +parameter debug_cti_ftm__CTIINTACK = 32'hF8809010; +parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF; + +parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014; +parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018; +parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C; +parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020; +parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024; +parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028; +parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C; +parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030; +parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034; +parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038; +parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C; +parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0; +parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4; +parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8; +parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC; +parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0; +parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4; +parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8; +parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC; +parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130; +parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134; +parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138; +parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C; +parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_ftm__CTIGATE = 32'hF8809140; +parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F; + +parameter debug_cti_ftm__ASICCTL = 32'hF8809144; +parameter val_debug_cti_ftm__ASICCTL = 32'h00000000; +parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF; + +parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC; +parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0; +parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4; +parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8; +parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC; +parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0; +parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4; +parameter val_debug_cti_ftm__ITCHIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8; +parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_ftm__ITCTRL = 32'hF8809F00; +parameter val_debug_cti_ftm__ITCTRL = 32'h00000000; +parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001; + +parameter debug_cti_ftm__CTSR = 32'hF8809FA0; +parameter val_debug_cti_ftm__CTSR = 32'h0000000F; +parameter mask_debug_cti_ftm__CTSR = 32'h0000000F; + +parameter debug_cti_ftm__CTCR = 32'hF8809FA4; +parameter val_debug_cti_ftm__CTCR = 32'h00000000; +parameter mask_debug_cti_ftm__CTCR = 32'h0000000F; + +parameter debug_cti_ftm__LAR = 32'hF8809FB0; +parameter val_debug_cti_ftm__LAR = 32'h00000000; +parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF; + +parameter debug_cti_ftm__LSR = 32'hF8809FB4; +parameter val_debug_cti_ftm__LSR = 32'h00000003; +parameter mask_debug_cti_ftm__LSR = 32'h00000007; + +parameter debug_cti_ftm__ASR = 32'hF8809FB8; +parameter val_debug_cti_ftm__ASR = 32'h00000005; +parameter mask_debug_cti_ftm__ASR = 32'h00000005; + +parameter debug_cti_ftm__DEVID = 32'hF8809FC8; +parameter val_debug_cti_ftm__DEVID = 32'h00040800; +parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF; + +parameter debug_cti_ftm__DTIR = 32'hF8809FCC; +parameter val_debug_cti_ftm__DTIR = 32'h00000014; +parameter mask_debug_cti_ftm__DTIR = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0; +parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4; +parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8; +parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC; +parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0; +parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4; +parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8; +parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC; +parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0; +parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4; +parameter val_debug_cti_ftm__COMPID1 = 32'h00000090; +parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8; +parameter val_debug_cti_ftm__COMPID2 = 32'h00000005; +parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC; +parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000; +parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003; +parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004; +parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003; +parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008; +parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003; +parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C; +parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003; +parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010; +parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003; +parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014; +parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003; +parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018; +parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003; +parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C; +parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003; +parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020; +parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003; +parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024; +parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003; +parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028; +parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C; +parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030; +parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034; +parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038; +parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C; +parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF; + +parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0; +parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003; +parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4; +parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8; +parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC; +parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0; +parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2; +parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4; +parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093; +parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8; +parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008; +parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC; +parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF; + +parameter debug_dap_rom__COMPID0 = 32'hF8800FF0; +parameter val_debug_dap_rom__COMPID0 = 32'h0000000D; +parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF; + +parameter debug_dap_rom__COMPID1 = 32'hF8800FF4; +parameter val_debug_dap_rom__COMPID1 = 32'h00000010; +parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF; + +parameter debug_dap_rom__COMPID2 = 32'hF8800FF8; +parameter val_debug_dap_rom__COMPID2 = 32'h00000005; +parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF; + +parameter debug_dap_rom__COMPID3 = 32'hF8800FFC; +parameter val_debug_dap_rom__COMPID3 = 32'h000000B1; +parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_etb__RDP = 32'hF8801004; +parameter val_debug_etb__RDP = 32'h00000400; +parameter mask_debug_etb__RDP = 32'hFFFFFFFF; + +parameter debug_etb__STS = 32'hF880100C; +parameter val_debug_etb__STS = 32'h00000000; +parameter mask_debug_etb__STS = 32'h0000000F; + +parameter debug_etb__RRD = 32'hF8801010; +parameter val_debug_etb__RRD = 32'h00000000; +parameter mask_debug_etb__RRD = 32'hFFFFFFFF; + +parameter debug_etb__RRP = 32'hF8801014; +parameter val_debug_etb__RRP = 32'h00000000; +parameter mask_debug_etb__RRP = 32'h000003FF; + +parameter debug_etb__RWP = 32'hF8801018; +parameter val_debug_etb__RWP = 32'h00000000; +parameter mask_debug_etb__RWP = 32'h000003FF; + +parameter debug_etb__TRG = 32'hF880101C; +parameter val_debug_etb__TRG = 32'h00000000; +parameter mask_debug_etb__TRG = 32'h000003FF; + +parameter debug_etb__CTL = 32'hF8801020; +parameter val_debug_etb__CTL = 32'h00000000; +parameter mask_debug_etb__CTL = 32'h00000001; + +parameter debug_etb__RWD = 32'hF8801024; +parameter val_debug_etb__RWD = 32'h00000000; +parameter mask_debug_etb__RWD = 32'hFFFFFFFF; + +parameter debug_etb__FFSR = 32'hF8801300; +parameter val_debug_etb__FFSR = 32'h00000000; +parameter mask_debug_etb__FFSR = 32'h00000003; + +parameter debug_etb__FFCR = 32'hF8801304; +parameter val_debug_etb__FFCR = 32'h00000200; +parameter mask_debug_etb__FFCR = 32'h00003FFF; + +parameter debug_etb__ITMISCOP0 = 32'hF8801EE0; +parameter val_debug_etb__ITMISCOP0 = 32'h00000000; +parameter mask_debug_etb__ITMISCOP0 = 32'h00000003; + +parameter debug_etb__ITTRFLINACK = 32'hF8801EE4; +parameter val_debug_etb__ITTRFLINACK = 32'h00000000; +parameter mask_debug_etb__ITTRFLINACK = 32'h00000003; + +parameter debug_etb__ITTRFLIN = 32'hF8801EE8; +parameter val_debug_etb__ITTRFLIN = 32'h00000000; +parameter mask_debug_etb__ITTRFLIN = 32'h00000003; + +parameter debug_etb__ITATBDATA0 = 32'hF8801EEC; +parameter val_debug_etb__ITATBDATA0 = 32'h00000000; +parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F; + +parameter debug_etb__ITATBCTR2 = 32'hF8801EF0; +parameter val_debug_etb__ITATBCTR2 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR2 = 32'h00000003; + +parameter debug_etb__ITATBCTR1 = 32'hF8801EF4; +parameter val_debug_etb__ITATBCTR1 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F; + +parameter debug_etb__ITATBCTR0 = 32'hF8801EF8; +parameter val_debug_etb__ITATBCTR0 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF; + +parameter debug_etb__IMCR = 32'hF8801F00; +parameter val_debug_etb__IMCR = 32'h00000000; +parameter mask_debug_etb__IMCR = 32'h00000001; + +parameter debug_etb__CTSR = 32'hF8801FA0; +parameter val_debug_etb__CTSR = 32'h0000000F; +parameter mask_debug_etb__CTSR = 32'h0000000F; + +parameter debug_etb__CTCR = 32'hF8801FA4; +parameter val_debug_etb__CTCR = 32'h00000000; +parameter mask_debug_etb__CTCR = 32'h0000000F; + +parameter debug_etb__LAR = 32'hF8801FB0; +parameter val_debug_etb__LAR = 32'h00000000; +parameter mask_debug_etb__LAR = 32'hFFFFFFFF; + +parameter debug_etb__LSR = 32'hF8801FB4; +parameter val_debug_etb__LSR = 32'h00000003; +parameter mask_debug_etb__LSR = 32'h00000007; + +parameter debug_etb__ASR = 32'hF8801FB8; +parameter val_debug_etb__ASR = 32'h00000000; +parameter mask_debug_etb__ASR = 32'h000000FF; + +parameter debug_etb__DEVID = 32'hF8801FC8; +parameter val_debug_etb__DEVID = 32'h00000000; +parameter mask_debug_etb__DEVID = 32'h0000003F; + +parameter debug_etb__DTIR = 32'hF8801FCC; +parameter val_debug_etb__DTIR = 32'h00000021; +parameter mask_debug_etb__DTIR = 32'h000000FF; + +parameter debug_etb__PERIPHID4 = 32'hF8801FD0; +parameter val_debug_etb__PERIPHID4 = 32'h00000004; +parameter mask_debug_etb__PERIPHID4 = 32'h000000FF; + +parameter debug_etb__PERIPHID5 = 32'hF8801FD4; +parameter val_debug_etb__PERIPHID5 = 32'h00000000; +parameter mask_debug_etb__PERIPHID5 = 32'h000000FF; + +parameter debug_etb__PERIPHID6 = 32'hF8801FD8; +parameter val_debug_etb__PERIPHID6 = 32'h00000000; +parameter mask_debug_etb__PERIPHID6 = 32'h000000FF; + +parameter debug_etb__PERIPHID7 = 32'hF8801FDC; +parameter val_debug_etb__PERIPHID7 = 32'h00000000; +parameter mask_debug_etb__PERIPHID7 = 32'h000000FF; + +parameter debug_etb__PERIPHID0 = 32'hF8801FE0; +parameter val_debug_etb__PERIPHID0 = 32'h00000007; +parameter mask_debug_etb__PERIPHID0 = 32'h000000FF; + +parameter debug_etb__PERIPHID1 = 32'hF8801FE4; +parameter val_debug_etb__PERIPHID1 = 32'h000000B9; +parameter mask_debug_etb__PERIPHID1 = 32'h000000FF; + +parameter debug_etb__PERIPHID2 = 32'hF8801FE8; +parameter val_debug_etb__PERIPHID2 = 32'h0000002B; +parameter mask_debug_etb__PERIPHID2 = 32'h000000FF; + +parameter debug_etb__PERIPHID3 = 32'hF8801FEC; +parameter val_debug_etb__PERIPHID3 = 32'h00000000; +parameter mask_debug_etb__PERIPHID3 = 32'h000000FF; + +parameter debug_etb__COMPID0 = 32'hF8801FF0; +parameter val_debug_etb__COMPID0 = 32'h0000000D; +parameter mask_debug_etb__COMPID0 = 32'h000000FF; + +parameter debug_etb__COMPID1 = 32'hF8801FF4; +parameter val_debug_etb__COMPID1 = 32'h00000090; +parameter mask_debug_etb__COMPID1 = 32'h000000FF; + +parameter debug_etb__COMPID2 = 32'hF8801FF8; +parameter val_debug_etb__COMPID2 = 32'h00000005; +parameter mask_debug_etb__COMPID2 = 32'h000000FF; + +parameter debug_etb__COMPID3 = 32'hF8801FFC; +parameter val_debug_etb__COMPID3 = 32'h000000B1; +parameter mask_debug_etb__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_ftm__FTMGLBCTRL = 32'hF880B000; +parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000; +parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001; + +parameter debug_ftm__FTMSTATUS = 32'hF880B004; +parameter val_debug_ftm__FTMSTATUS = 32'h00000082; +parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMCONTROL = 32'hF880B008; +parameter val_debug_ftm__FTMCONTROL = 32'h00000000; +parameter mask_debug_ftm__FTMCONTROL = 32'h00000007; + +parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C; +parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010; +parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014; +parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018; +parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C; +parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020; +parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024; +parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028; +parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF; + +parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C; +parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000; +parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F; + +parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030; +parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF; + +parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034; +parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF; + +parameter debug_ftm__FTMATID = 32'hF880B400; +parameter val_debug_ftm__FTMATID = 32'h00000000; +parameter mask_debug_ftm__FTMATID = 32'h0000007F; + +parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0; +parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F; + +parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4; +parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F; + +parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8; +parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000; +parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001; + +parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC; +parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001; +parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF; + +parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC; +parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F; + +parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0; +parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001; +parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003; + +parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4; +parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F; + +parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8; +parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF; + +parameter debug_ftm__FTMITCR = 32'hF880BF00; +parameter val_debug_ftm__FTMITCR = 32'h00000000; +parameter mask_debug_ftm__FTMITCR = 32'h00000001; + +parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0; +parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF; + +parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4; +parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF; + +parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0; +parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4; +parameter val_debug_ftm__LOCK_STATUS = 32'h00000003; +parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007; + +parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8; +parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088; +parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMDEVID = 32'hF880BFC8; +parameter val_debug_ftm__FTMDEVID = 32'h00000000; +parameter mask_debug_ftm__FTMDEVID = 32'h00000001; + +parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC; +parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033; +parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0; +parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4; +parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8; +parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC; +parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0; +parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001; +parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4; +parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090; +parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8; +parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C; +parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC; +parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0; +parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D; +parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4; +parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090; +parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8; +parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005; +parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC; +parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1; +parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_funnel__Control = 32'hF8804000; +parameter val_debug_funnel__Control = 32'h00000300; +parameter mask_debug_funnel__Control = 32'h00000FFF; + +parameter debug_funnel__PriControl = 32'hF8804004; +parameter val_debug_funnel__PriControl = 32'h00FAC688; +parameter mask_debug_funnel__PriControl = 32'h00FFFFFF; + +parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC; +parameter val_debug_funnel__ITATBDATA0 = 32'h00000000; +parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F; + +parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0; +parameter val_debug_funnel__ITATBCTR2 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003; + +parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4; +parameter val_debug_funnel__ITATBCTR1 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F; + +parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8; +parameter val_debug_funnel__ITATBCTR0 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF; + +parameter debug_funnel__IMCR = 32'hF8804F00; +parameter val_debug_funnel__IMCR = 32'h00000000; +parameter mask_debug_funnel__IMCR = 32'h00000001; + +parameter debug_funnel__CTSR = 32'hF8804FA0; +parameter val_debug_funnel__CTSR = 32'h0000000F; +parameter mask_debug_funnel__CTSR = 32'h0000000F; + +parameter debug_funnel__CTCR = 32'hF8804FA4; +parameter val_debug_funnel__CTCR = 32'h00000000; +parameter mask_debug_funnel__CTCR = 32'h0000000F; + +parameter debug_funnel__LAR = 32'hF8804FB0; +parameter val_debug_funnel__LAR = 32'h00000000; +parameter mask_debug_funnel__LAR = 32'hFFFFFFFF; + +parameter debug_funnel__LSR = 32'hF8804FB4; +parameter val_debug_funnel__LSR = 32'h00000003; +parameter mask_debug_funnel__LSR = 32'h00000007; + +parameter debug_funnel__ASR = 32'hF8804FB8; +parameter val_debug_funnel__ASR = 32'h00000000; +parameter mask_debug_funnel__ASR = 32'h000000FF; + +parameter debug_funnel__DEVID = 32'hF8804FC8; +parameter val_debug_funnel__DEVID = 32'h00000028; +parameter mask_debug_funnel__DEVID = 32'h000000FF; + +parameter debug_funnel__DTIR = 32'hF8804FCC; +parameter val_debug_funnel__DTIR = 32'h00000012; +parameter mask_debug_funnel__DTIR = 32'h000000FF; + +parameter debug_funnel__PERIPHID4 = 32'hF8804FD0; +parameter val_debug_funnel__PERIPHID4 = 32'h00000004; +parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF; + +parameter debug_funnel__PERIPHID5 = 32'hF8804FD4; +parameter val_debug_funnel__PERIPHID5 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF; + +parameter debug_funnel__PERIPHID6 = 32'hF8804FD8; +parameter val_debug_funnel__PERIPHID6 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF; + +parameter debug_funnel__PERIPHID7 = 32'hF8804FDC; +parameter val_debug_funnel__PERIPHID7 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF; + +parameter debug_funnel__PERIPHID0 = 32'hF8804FE0; +parameter val_debug_funnel__PERIPHID0 = 32'h00000008; +parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF; + +parameter debug_funnel__PERIPHID1 = 32'hF8804FE4; +parameter val_debug_funnel__PERIPHID1 = 32'h000000B9; +parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF; + +parameter debug_funnel__PERIPHID2 = 32'hF8804FE8; +parameter val_debug_funnel__PERIPHID2 = 32'h0000001B; +parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF; + +parameter debug_funnel__PERIPHID3 = 32'hF8804FEC; +parameter val_debug_funnel__PERIPHID3 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF; + +parameter debug_funnel__COMPID0 = 32'hF8804FF0; +parameter val_debug_funnel__COMPID0 = 32'h0000000D; +parameter mask_debug_funnel__COMPID0 = 32'h000000FF; + +parameter debug_funnel__COMPID1 = 32'hF8804FF4; +parameter val_debug_funnel__COMPID1 = 32'h00000090; +parameter mask_debug_funnel__COMPID1 = 32'h000000FF; + +parameter debug_funnel__COMPID2 = 32'hF8804FF8; +parameter val_debug_funnel__COMPID2 = 32'h00000005; +parameter mask_debug_funnel__COMPID2 = 32'h000000FF; + +parameter debug_funnel__COMPID3 = 32'hF8804FFC; +parameter val_debug_funnel__COMPID3 = 32'h000000B1; +parameter mask_debug_funnel__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_itm__StimPort00 = 32'hF8805000; +parameter val_debug_itm__StimPort00 = 32'h00000000; +parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort01 = 32'hF8805004; +parameter val_debug_itm__StimPort01 = 32'h00000000; +parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort02 = 32'hF8805008; +parameter val_debug_itm__StimPort02 = 32'h00000000; +parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort03 = 32'hF880500C; +parameter val_debug_itm__StimPort03 = 32'h00000000; +parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort04 = 32'hF8805010; +parameter val_debug_itm__StimPort04 = 32'h00000000; +parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort05 = 32'hF8805014; +parameter val_debug_itm__StimPort05 = 32'h00000000; +parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort06 = 32'hF8805018; +parameter val_debug_itm__StimPort06 = 32'h00000000; +parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort07 = 32'hF880501C; +parameter val_debug_itm__StimPort07 = 32'h00000000; +parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort08 = 32'hF8805020; +parameter val_debug_itm__StimPort08 = 32'h00000000; +parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort09 = 32'hF8805024; +parameter val_debug_itm__StimPort09 = 32'h00000000; +parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort10 = 32'hF8805028; +parameter val_debug_itm__StimPort10 = 32'h00000000; +parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort11 = 32'hF880502C; +parameter val_debug_itm__StimPort11 = 32'h00000000; +parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort12 = 32'hF8805030; +parameter val_debug_itm__StimPort12 = 32'h00000000; +parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort13 = 32'hF8805034; +parameter val_debug_itm__StimPort13 = 32'h00000000; +parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort14 = 32'hF8805038; +parameter val_debug_itm__StimPort14 = 32'h00000000; +parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort15 = 32'hF880503C; +parameter val_debug_itm__StimPort15 = 32'h00000000; +parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort16 = 32'hF8805040; +parameter val_debug_itm__StimPort16 = 32'h00000000; +parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort17 = 32'hF8805044; +parameter val_debug_itm__StimPort17 = 32'h00000000; +parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort18 = 32'hF8805048; +parameter val_debug_itm__StimPort18 = 32'h00000000; +parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort19 = 32'hF880504C; +parameter val_debug_itm__StimPort19 = 32'h00000000; +parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort20 = 32'hF8805050; +parameter val_debug_itm__StimPort20 = 32'h00000000; +parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort21 = 32'hF8805054; +parameter val_debug_itm__StimPort21 = 32'h00000000; +parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort22 = 32'hF8805058; +parameter val_debug_itm__StimPort22 = 32'h00000000; +parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort23 = 32'hF880505C; +parameter val_debug_itm__StimPort23 = 32'h00000000; +parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort24 = 32'hF8805060; +parameter val_debug_itm__StimPort24 = 32'h00000000; +parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort25 = 32'hF8805064; +parameter val_debug_itm__StimPort25 = 32'h00000000; +parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort26 = 32'hF8805068; +parameter val_debug_itm__StimPort26 = 32'h00000000; +parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort27 = 32'hF880506C; +parameter val_debug_itm__StimPort27 = 32'h00000000; +parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort28 = 32'hF8805070; +parameter val_debug_itm__StimPort28 = 32'h00000000; +parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort29 = 32'hF8805074; +parameter val_debug_itm__StimPort29 = 32'h00000000; +parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort30 = 32'hF8805078; +parameter val_debug_itm__StimPort30 = 32'h00000000; +parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort31 = 32'hF880507C; +parameter val_debug_itm__StimPort31 = 32'h00000000; +parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF; + +parameter debug_itm__TER = 32'hF8805E00; +parameter val_debug_itm__TER = 32'h00000000; +parameter mask_debug_itm__TER = 32'hFFFFFFFF; + +parameter debug_itm__TTR = 32'hF8805E20; +parameter val_debug_itm__TTR = 32'h00000000; +parameter mask_debug_itm__TTR = 32'hFFFFFFFF; + +parameter debug_itm__CR = 32'hF8805E80; +parameter val_debug_itm__CR = 32'h00000004; +parameter mask_debug_itm__CR = 32'h00FFFFFF; + +parameter debug_itm__SCR = 32'hF8805E90; +parameter val_debug_itm__SCR = 32'h00000400; +parameter mask_debug_itm__SCR = 32'h00000FFF; + +parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4; +parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001; + +parameter debug_itm__ITTRIGOUT = 32'hF8805EE8; +parameter val_debug_itm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUT = 32'h00000001; + +parameter debug_itm__ITATBDATA0 = 32'hF8805EEC; +parameter val_debug_itm__ITATBDATA0 = 32'h00000000; +parameter mask_debug_itm__ITATBDATA0 = 32'h00000003; + +parameter debug_itm__ITATBCTR2 = 32'hF8805EF0; +parameter val_debug_itm__ITATBCTR2 = 32'h00000001; +parameter mask_debug_itm__ITATBCTR2 = 32'h00000001; + +parameter debug_itm__ITATABCTR1 = 32'hF8805EF4; +parameter val_debug_itm__ITATABCTR1 = 32'h00000000; +parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F; + +parameter debug_itm__ITATBCTR0 = 32'hF8805EF8; +parameter val_debug_itm__ITATBCTR0 = 32'h00000000; +parameter mask_debug_itm__ITATBCTR0 = 32'h00000003; + +parameter debug_itm__IMCR = 32'hF8805F00; +parameter val_debug_itm__IMCR = 32'h00000000; +parameter mask_debug_itm__IMCR = 32'h00000001; + +parameter debug_itm__CTSR = 32'hF8805FA0; +parameter val_debug_itm__CTSR = 32'h000000FF; +parameter mask_debug_itm__CTSR = 32'h000000FF; + +parameter debug_itm__CTCR = 32'hF8805FA4; +parameter val_debug_itm__CTCR = 32'h00000000; +parameter mask_debug_itm__CTCR = 32'h000000FF; + +parameter debug_itm__LAR = 32'hF8805FB0; +parameter val_debug_itm__LAR = 32'h00000000; +parameter mask_debug_itm__LAR = 32'hFFFFFFFF; + +parameter debug_itm__LSR = 32'hF8805FB4; +parameter val_debug_itm__LSR = 32'h00000003; +parameter mask_debug_itm__LSR = 32'h00000007; + +parameter debug_itm__ASR = 32'hF8805FB8; +parameter val_debug_itm__ASR = 32'h00000088; +parameter mask_debug_itm__ASR = 32'h000000FF; + +parameter debug_itm__DEVID = 32'hF8805FC8; +parameter val_debug_itm__DEVID = 32'h00000020; +parameter mask_debug_itm__DEVID = 32'h00001FFF; + +parameter debug_itm__DTIR = 32'hF8805FCC; +parameter val_debug_itm__DTIR = 32'h00000043; +parameter mask_debug_itm__DTIR = 32'h000000FF; + +parameter debug_itm__PERIPHID4 = 32'hF8805FD0; +parameter val_debug_itm__PERIPHID4 = 32'h00000004; +parameter mask_debug_itm__PERIPHID4 = 32'h000000FF; + +parameter debug_itm__PERIPHID5 = 32'hF8805FD4; +parameter val_debug_itm__PERIPHID5 = 32'h00000000; +parameter mask_debug_itm__PERIPHID5 = 32'h000000FF; + +parameter debug_itm__PERIPHID6 = 32'hF8805FD8; +parameter val_debug_itm__PERIPHID6 = 32'h00000000; +parameter mask_debug_itm__PERIPHID6 = 32'h000000FF; + +parameter debug_itm__PERIPHID7 = 32'hF8805FDC; +parameter val_debug_itm__PERIPHID7 = 32'h00000000; +parameter mask_debug_itm__PERIPHID7 = 32'h000000FF; + +parameter debug_itm__PERIPHID0 = 32'hF8805FE0; +parameter val_debug_itm__PERIPHID0 = 32'h00000013; +parameter mask_debug_itm__PERIPHID0 = 32'h000000FF; + +parameter debug_itm__PERIPHID1 = 32'hF8805FE4; +parameter val_debug_itm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_itm__PERIPHID1 = 32'h000000FF; + +parameter debug_itm__PERIPHID2 = 32'hF8805FE8; +parameter val_debug_itm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_itm__PERIPHID2 = 32'h000000FF; + +parameter debug_itm__PERIPHID3 = 32'hF8805FEC; +parameter val_debug_itm__PERIPHID3 = 32'h00000000; +parameter mask_debug_itm__PERIPHID3 = 32'h000000FF; + +parameter debug_itm__COMPID0 = 32'hF8805FF0; +parameter val_debug_itm__COMPID0 = 32'h0000000D; +parameter mask_debug_itm__COMPID0 = 32'h000000FF; + +parameter debug_itm__COMPID1 = 32'hF8805FF4; +parameter val_debug_itm__COMPID1 = 32'h00000090; +parameter mask_debug_itm__COMPID1 = 32'h000000FF; + +parameter debug_itm__COMPID2 = 32'hF8805FF8; +parameter val_debug_itm__COMPID2 = 32'h00000005; +parameter mask_debug_itm__COMPID2 = 32'h000000FF; + +parameter debug_itm__COMPID3 = 32'hF8805FFC; +parameter val_debug_itm__COMPID3 = 32'h000000B1; +parameter mask_debug_itm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_tpiu__SuppSize = 32'hF8803000; +parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF; +parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF; + +parameter debug_tpiu__CurrentSize = 32'hF8803004; +parameter val_debug_tpiu__CurrentSize = 32'h00000001; +parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF; + +parameter debug_tpiu__SuppTrigMode = 32'hF8803100; +parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F; +parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF; + +parameter debug_tpiu__TrigCount = 32'hF8803104; +parameter val_debug_tpiu__TrigCount = 32'h00000000; +parameter mask_debug_tpiu__TrigCount = 32'h000000FF; + +parameter debug_tpiu__TrigMult = 32'hF8803108; +parameter val_debug_tpiu__TrigMult = 32'h00000000; +parameter mask_debug_tpiu__TrigMult = 32'h0000001F; + +parameter debug_tpiu__SuppTest = 32'hF8803200; +parameter val_debug_tpiu__SuppTest = 32'h0003000F; +parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF; + +parameter debug_tpiu__CurrentTest = 32'hF8803204; +parameter val_debug_tpiu__CurrentTest = 32'h00000000; +parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF; + +parameter debug_tpiu__TestRepeatCount = 32'hF8803208; +parameter val_debug_tpiu__TestRepeatCount = 32'h00000000; +parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF; + +parameter debug_tpiu__FFSR = 32'hF8803300; +parameter val_debug_tpiu__FFSR = 32'h00000006; +parameter mask_debug_tpiu__FFSR = 32'h00000007; + +parameter debug_tpiu__FFCR = 32'hF8803304; +parameter val_debug_tpiu__FFCR = 32'h00000000; +parameter mask_debug_tpiu__FFCR = 32'h00003FFF; + +parameter debug_tpiu__FormatSyncCount = 32'hF8803308; +parameter val_debug_tpiu__FormatSyncCount = 32'h00000040; +parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF; + +parameter debug_tpiu__EXTCTLIn = 32'hF8803400; +parameter val_debug_tpiu__EXTCTLIn = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF; + +parameter debug_tpiu__EXTCTLOut = 32'hF8803404; +parameter val_debug_tpiu__EXTCTLOut = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF; + +parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4; +parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003; + +parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8; +parameter val_debug_tpiu__ITTRFLIN = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000; + +parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC; +parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0; +parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003; + +parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4; +parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8; +parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000; + +parameter debug_tpiu__IMCR = 32'hF8803F00; +parameter val_debug_tpiu__IMCR = 32'h00000000; +parameter mask_debug_tpiu__IMCR = 32'h00000001; + +parameter debug_tpiu__CTSR = 32'hF8803FA0; +parameter val_debug_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_tpiu__CTSR = 32'h0000000F; + +parameter debug_tpiu__CTCR = 32'hF8803FA4; +parameter val_debug_tpiu__CTCR = 32'h00000000; +parameter mask_debug_tpiu__CTCR = 32'h0000000F; + +parameter debug_tpiu__LAR = 32'hF8803FB0; +parameter val_debug_tpiu__LAR = 32'h00000000; +parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_tpiu__LSR = 32'hF8803FB4; +parameter val_debug_tpiu__LSR = 32'h00000003; +parameter mask_debug_tpiu__LSR = 32'h00000007; + +parameter debug_tpiu__ASR = 32'hF8803FB8; +parameter val_debug_tpiu__ASR = 32'h00000000; +parameter mask_debug_tpiu__ASR = 32'h000000FF; + +parameter debug_tpiu__DEVID = 32'hF8803FC8; +parameter val_debug_tpiu__DEVID = 32'h000000A0; +parameter mask_debug_tpiu__DEVID = 32'h00000FFF; + +parameter debug_tpiu__DTIR = 32'hF8803FCC; +parameter val_debug_tpiu__DTIR = 32'h00000011; +parameter mask_debug_tpiu__DTIR = 32'h000000FF; + +parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0; +parameter val_debug_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4; +parameter val_debug_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8; +parameter val_debug_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC; +parameter val_debug_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0; +parameter val_debug_tpiu__PERIPHID0 = 32'h00000012; +parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4; +parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8; +parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B; +parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC; +parameter val_debug_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_tpiu__COMPID0 = 32'hF8803FF0; +parameter val_debug_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_tpiu__COMPID1 = 32'hF8803FF4; +parameter val_debug_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_tpiu__COMPID2 = 32'hF8803FF8; +parameter val_debug_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_tpiu__COMPID3 = 32'hF8803FFC; +parameter val_debug_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter devcfg__CTRL = 32'hF8007000; +parameter val_devcfg__CTRL = 32'h0C000000; +parameter mask_devcfg__CTRL = 32'hFFFFFFFF; + +parameter devcfg__LOCK = 32'hF8007004; +parameter val_devcfg__LOCK = 32'h00000000; +parameter mask_devcfg__LOCK = 32'hFFFFFFFF; + +parameter devcfg__CFG = 32'hF8007008; +parameter val_devcfg__CFG = 32'h0000050B; +parameter mask_devcfg__CFG = 32'hFFFFFFFF; + +parameter devcfg__INT_STS = 32'hF800700C; +parameter val_devcfg__INT_STS = 32'h00000000; +parameter mask_devcfg__INT_STS = 32'hFFFFFFFF; + +parameter devcfg__INT_MASK = 32'hF8007010; +parameter val_devcfg__INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__STATUS = 32'hF8007014; +parameter val_devcfg__STATUS = 32'h40000820; +parameter mask_devcfg__STATUS = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_ADDR = 32'hF8007018; +parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_DST_ADDR = 32'hF800701C; +parameter val_devcfg__DMA_DST_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_LEN = 32'hF8007020; +parameter val_devcfg__DMA_SRC_LEN = 32'h00000000; +parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF; + +parameter devcfg__DMA_DEST_LEN = 32'hF8007024; +parameter val_devcfg__DMA_DEST_LEN = 32'h00000000; +parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF; + +parameter devcfg__ROM_SHADOW = 32'hF8007028; +parameter val_devcfg__ROM_SHADOW = 32'h00000000; +parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF; + +parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C; +parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000; +parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF; + +parameter devcfg__SW_ID = 32'hF8007030; +parameter val_devcfg__SW_ID = 32'h00000000; +parameter mask_devcfg__SW_ID = 32'hFFFFFFFF; + +parameter devcfg__UNLOCK = 32'hF8007034; +parameter val_devcfg__UNLOCK = 32'h00000000; +parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF; + +parameter devcfg__MCTRL = 32'hF8007080; +parameter val_devcfg__MCTRL = 32'h00800000; +parameter mask_devcfg__MCTRL = 32'h0FFFFFFF; + +parameter devcfg__XADCIF_CFG = 32'hF8007100; +parameter val_devcfg__XADCIF_CFG = 32'h00001114; +parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_STS = 32'hF8007104; +parameter val_devcfg__XADCIF_INT_STS = 32'h00000200; +parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_MASK = 32'hF8007108; +parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MSTS = 32'hF800710C; +parameter val_devcfg__XADCIF_MSTS = 32'h00000500; +parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110; +parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_RDFIFO = 32'hF8007114; +parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MCTL = 32'hF8007118; +parameter val_devcfg__XADCIF_MCTL = 32'h00000010; +parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_ns__DSR = 32'hF8004000; +parameter val_dmac0_ns__DSR = 32'h00000000; +parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF; + +parameter dmac0_ns__DPC = 32'hF8004004; +parameter val_dmac0_ns__DPC = 32'h00000000; +parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF; + +parameter dmac0_ns__INTEN = 32'hF8004020; +parameter val_dmac0_ns__INTEN = 32'h00000000; +parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF; + +parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024; +parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTMIS = 32'hF8004028; +parameter val_dmac0_ns__INTMIS = 32'h00000000; +parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTCLR = 32'hF800402C; +parameter val_dmac0_ns__INTCLR = 32'h00000000; +parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRD = 32'hF8004030; +parameter val_dmac0_ns__FSRD = 32'h00000000; +parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRC = 32'hF8004034; +parameter val_dmac0_ns__FSRC = 32'h00000000; +parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF; + +parameter dmac0_ns__FTRD = 32'hF8004038; +parameter val_dmac0_ns__FTRD = 32'h00000000; +parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR0 = 32'hF8004040; +parameter val_dmac0_ns__FTR0 = 32'h00000000; +parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR1 = 32'hF8004044; +parameter val_dmac0_ns__FTR1 = 32'h00000000; +parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR2 = 32'hF8004048; +parameter val_dmac0_ns__FTR2 = 32'h00000000; +parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR3 = 32'hF800404C; +parameter val_dmac0_ns__FTR3 = 32'h00000000; +parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR4 = 32'hF8004050; +parameter val_dmac0_ns__FTR4 = 32'h00000000; +parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR5 = 32'hF8004054; +parameter val_dmac0_ns__FTR5 = 32'h00000000; +parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR6 = 32'hF8004058; +parameter val_dmac0_ns__FTR6 = 32'h00000000; +parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR7 = 32'hF800405C; +parameter val_dmac0_ns__FTR7 = 32'h00000000; +parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR0 = 32'hF8004100; +parameter val_dmac0_ns__CSR0 = 32'h00000000; +parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC0 = 32'hF8004104; +parameter val_dmac0_ns__CPC0 = 32'h00000000; +parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR1 = 32'hF8004108; +parameter val_dmac0_ns__CSR1 = 32'h00000000; +parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC1 = 32'hF800410C; +parameter val_dmac0_ns__CPC1 = 32'h00000000; +parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR2 = 32'hF8004110; +parameter val_dmac0_ns__CSR2 = 32'h00000000; +parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC2 = 32'hF8004114; +parameter val_dmac0_ns__CPC2 = 32'h00000000; +parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR3 = 32'hF8004118; +parameter val_dmac0_ns__CSR3 = 32'h00000000; +parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC3 = 32'hF800411C; +parameter val_dmac0_ns__CPC3 = 32'h00000000; +parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR4 = 32'hF8004120; +parameter val_dmac0_ns__CSR4 = 32'h00000000; +parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC4 = 32'hF8004124; +parameter val_dmac0_ns__CPC4 = 32'h00000000; +parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR5 = 32'hF8004128; +parameter val_dmac0_ns__CSR5 = 32'h00000000; +parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC5 = 32'hF800412C; +parameter val_dmac0_ns__CPC5 = 32'h00000000; +parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR6 = 32'hF8004130; +parameter val_dmac0_ns__CSR6 = 32'h00000000; +parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC6 = 32'hF8004134; +parameter val_dmac0_ns__CPC6 = 32'h00000000; +parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR7 = 32'hF8004138; +parameter val_dmac0_ns__CSR7 = 32'h00000000; +parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC7 = 32'hF800413C; +parameter val_dmac0_ns__CPC7 = 32'h00000000; +parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR0 = 32'hF8004400; +parameter val_dmac0_ns__SAR0 = 32'h00000000; +parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR0 = 32'hF8004404; +parameter val_dmac0_ns__DAR0 = 32'h00000000; +parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR0 = 32'hF8004408; +parameter val_dmac0_ns__CCR0 = 32'h00000000; +parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_0 = 32'hF800440C; +parameter val_dmac0_ns__LC0_0 = 32'h00000000; +parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_0 = 32'hF8004410; +parameter val_dmac0_ns__LC1_0 = 32'h00000000; +parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR1 = 32'hF8004420; +parameter val_dmac0_ns__SAR1 = 32'h00000000; +parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR1 = 32'hF8004424; +parameter val_dmac0_ns__DAR1 = 32'h00000000; +parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR1 = 32'hF8004428; +parameter val_dmac0_ns__CCR1 = 32'h00000000; +parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_1 = 32'hF800442C; +parameter val_dmac0_ns__LC0_1 = 32'h00000000; +parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_1 = 32'hF8004430; +parameter val_dmac0_ns__LC1_1 = 32'h00000000; +parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR2 = 32'hF8004440; +parameter val_dmac0_ns__SAR2 = 32'h00000000; +parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR2 = 32'hF8004444; +parameter val_dmac0_ns__DAR2 = 32'h00000000; +parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR2 = 32'hF8004448; +parameter val_dmac0_ns__CCR2 = 32'h00000000; +parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_2 = 32'hF800444C; +parameter val_dmac0_ns__LC0_2 = 32'h00000000; +parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_2 = 32'hF8004450; +parameter val_dmac0_ns__LC1_2 = 32'h00000000; +parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR3 = 32'hF8004460; +parameter val_dmac0_ns__SAR3 = 32'h00000000; +parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR3 = 32'hF8004464; +parameter val_dmac0_ns__DAR3 = 32'h00000000; +parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR3 = 32'hF8004468; +parameter val_dmac0_ns__CCR3 = 32'h00000000; +parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_3 = 32'hF800446C; +parameter val_dmac0_ns__LC0_3 = 32'h00000000; +parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_3 = 32'hF8004470; +parameter val_dmac0_ns__LC1_3 = 32'h00000000; +parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR4 = 32'hF8004480; +parameter val_dmac0_ns__SAR4 = 32'h00000000; +parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR4 = 32'hF8004484; +parameter val_dmac0_ns__DAR4 = 32'h00000000; +parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR4 = 32'hF8004488; +parameter val_dmac0_ns__CCR4 = 32'h00000000; +parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_4 = 32'hF800448C; +parameter val_dmac0_ns__LC0_4 = 32'h00000000; +parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_4 = 32'hF8004490; +parameter val_dmac0_ns__LC1_4 = 32'h00000000; +parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR5 = 32'hF80044A0; +parameter val_dmac0_ns__SAR5 = 32'h00000000; +parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR5 = 32'hF80044A4; +parameter val_dmac0_ns__DAR5 = 32'h00000000; +parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR5 = 32'hF80044A8; +parameter val_dmac0_ns__CCR5 = 32'h00000000; +parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_5 = 32'hF80044AC; +parameter val_dmac0_ns__LC0_5 = 32'h00000000; +parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_5 = 32'hF80044B0; +parameter val_dmac0_ns__LC1_5 = 32'h00000000; +parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR6 = 32'hF80044C0; +parameter val_dmac0_ns__SAR6 = 32'h00000000; +parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR6 = 32'hF80044C4; +parameter val_dmac0_ns__DAR6 = 32'h00000000; +parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR6 = 32'hF80044C8; +parameter val_dmac0_ns__CCR6 = 32'h00000000; +parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_6 = 32'hF80044CC; +parameter val_dmac0_ns__LC0_6 = 32'h00000000; +parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_6 = 32'hF80044D0; +parameter val_dmac0_ns__LC1_6 = 32'h00000000; +parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR7 = 32'hF80044E0; +parameter val_dmac0_ns__SAR7 = 32'h00000000; +parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR7 = 32'hF80044E4; +parameter val_dmac0_ns__DAR7 = 32'h00000000; +parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR7 = 32'hF80044E8; +parameter val_dmac0_ns__CCR7 = 32'h00000000; +parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_7 = 32'hF80044EC; +parameter val_dmac0_ns__LC0_7 = 32'h00000000; +parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_7 = 32'hF80044F0; +parameter val_dmac0_ns__LC1_7 = 32'h00000000; +parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGSTATUS = 32'hF8004D00; +parameter val_dmac0_ns__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGCMD = 32'hF8004D04; +parameter val_dmac0_ns__DBGCMD = 32'h00000000; +parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST0 = 32'hF8004D08; +parameter val_dmac0_ns__DBGINST0 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST1 = 32'hF8004D0C; +parameter val_dmac0_ns__DBGINST1 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR0 = 32'hF8004E00; +parameter val_dmac0_ns__CR0 = 32'h00000000; +parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR1 = 32'hF8004E04; +parameter val_dmac0_ns__CR1 = 32'h00000000; +parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR2 = 32'hF8004E08; +parameter val_dmac0_ns__CR2 = 32'h00000000; +parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR3 = 32'hF8004E0C; +parameter val_dmac0_ns__CR3 = 32'h00000000; +parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR4 = 32'hF8004E10; +parameter val_dmac0_ns__CR4 = 32'h00000000; +parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CRD = 32'hF8004E14; +parameter val_dmac0_ns__CRD = 32'h00000000; +parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF; + +parameter dmac0_ns__WD = 32'hF8004E80; +parameter val_dmac0_ns__WD = 32'h00000000; +parameter mask_dmac0_ns__WD = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_0 = 32'hF8004FE0; +parameter val_dmac0_ns__periph_id_0 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_1 = 32'hF8004FE4; +parameter val_dmac0_ns__periph_id_1 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_2 = 32'hF8004FE8; +parameter val_dmac0_ns__periph_id_2 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_3 = 32'hF8004FEC; +parameter val_dmac0_ns__periph_id_3 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0; +parameter val_dmac0_ns__pcell_id_0 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4; +parameter val_dmac0_ns__pcell_id_1 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8; +parameter val_dmac0_ns__pcell_id_2 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC; +parameter val_dmac0_ns__pcell_id_3 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_s__DSR = 32'hF8003000; +parameter val_dmac0_s__DSR = 32'h00000000; +parameter mask_dmac0_s__DSR = 32'hFFFFFFFF; + +parameter dmac0_s__DPC = 32'hF8003004; +parameter val_dmac0_s__DPC = 32'h00000000; +parameter mask_dmac0_s__DPC = 32'hFFFFFFFF; + +parameter dmac0_s__INTEN = 32'hF8003020; +parameter val_dmac0_s__INTEN = 32'h00000000; +parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF; + +parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024; +parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTMIS = 32'hF8003028; +parameter val_dmac0_s__INTMIS = 32'h00000000; +parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTCLR = 32'hF800302C; +parameter val_dmac0_s__INTCLR = 32'h00000000; +parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_s__FSRD = 32'hF8003030; +parameter val_dmac0_s__FSRD = 32'h00000000; +parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF; + +parameter dmac0_s__FSRC = 32'hF8003034; +parameter val_dmac0_s__FSRC = 32'h00000000; +parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF; + +parameter dmac0_s__FTRD = 32'hF8003038; +parameter val_dmac0_s__FTRD = 32'h00000000; +parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF; + +parameter dmac0_s__FTR0 = 32'hF8003040; +parameter val_dmac0_s__FTR0 = 32'h00000000; +parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR1 = 32'hF8003044; +parameter val_dmac0_s__FTR1 = 32'h00000000; +parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR2 = 32'hF8003048; +parameter val_dmac0_s__FTR2 = 32'h00000000; +parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR3 = 32'hF800304C; +parameter val_dmac0_s__FTR3 = 32'h00000000; +parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR4 = 32'hF8003050; +parameter val_dmac0_s__FTR4 = 32'h00000000; +parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR5 = 32'hF8003054; +parameter val_dmac0_s__FTR5 = 32'h00000000; +parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR6 = 32'hF8003058; +parameter val_dmac0_s__FTR6 = 32'h00000000; +parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR7 = 32'hF800305C; +parameter val_dmac0_s__FTR7 = 32'h00000000; +parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR0 = 32'hF8003100; +parameter val_dmac0_s__CSR0 = 32'h00000000; +parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC0 = 32'hF8003104; +parameter val_dmac0_s__CPC0 = 32'h00000000; +parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR1 = 32'hF8003108; +parameter val_dmac0_s__CSR1 = 32'h00000000; +parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC1 = 32'hF800310C; +parameter val_dmac0_s__CPC1 = 32'h00000000; +parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR2 = 32'hF8003110; +parameter val_dmac0_s__CSR2 = 32'h00000000; +parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC2 = 32'hF8003114; +parameter val_dmac0_s__CPC2 = 32'h00000000; +parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR3 = 32'hF8003118; +parameter val_dmac0_s__CSR3 = 32'h00000000; +parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC3 = 32'hF800311C; +parameter val_dmac0_s__CPC3 = 32'h00000000; +parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR4 = 32'hF8003120; +parameter val_dmac0_s__CSR4 = 32'h00000000; +parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC4 = 32'hF8003124; +parameter val_dmac0_s__CPC4 = 32'h00000000; +parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR5 = 32'hF8003128; +parameter val_dmac0_s__CSR5 = 32'h00000000; +parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC5 = 32'hF800312C; +parameter val_dmac0_s__CPC5 = 32'h00000000; +parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR6 = 32'hF8003130; +parameter val_dmac0_s__CSR6 = 32'h00000000; +parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC6 = 32'hF8003134; +parameter val_dmac0_s__CPC6 = 32'h00000000; +parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR7 = 32'hF8003138; +parameter val_dmac0_s__CSR7 = 32'h00000000; +parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC7 = 32'hF800313C; +parameter val_dmac0_s__CPC7 = 32'h00000000; +parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR0 = 32'hF8003400; +parameter val_dmac0_s__SAR0 = 32'h00000000; +parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR0 = 32'hF8003404; +parameter val_dmac0_s__DAR0 = 32'h00000000; +parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR0 = 32'hF8003408; +parameter val_dmac0_s__CCR0 = 32'h00800200; +parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_0 = 32'hF800340C; +parameter val_dmac0_s__LC0_0 = 32'h00000000; +parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_0 = 32'hF8003410; +parameter val_dmac0_s__LC1_0 = 32'h00000000; +parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR1 = 32'hF8003420; +parameter val_dmac0_s__SAR1 = 32'h00000000; +parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR1 = 32'hF8003424; +parameter val_dmac0_s__DAR1 = 32'h00000000; +parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR1 = 32'hF8003428; +parameter val_dmac0_s__CCR1 = 32'h00800200; +parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_1 = 32'hF800342C; +parameter val_dmac0_s__LC0_1 = 32'h00000000; +parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_1 = 32'hF8003430; +parameter val_dmac0_s__LC1_1 = 32'h00000000; +parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR2 = 32'hF8003440; +parameter val_dmac0_s__SAR2 = 32'h00000000; +parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR2 = 32'hF8003444; +parameter val_dmac0_s__DAR2 = 32'h00000000; +parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR2 = 32'hF8003448; +parameter val_dmac0_s__CCR2 = 32'h00800200; +parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_2 = 32'hF800344C; +parameter val_dmac0_s__LC0_2 = 32'h00000000; +parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_2 = 32'hF8003450; +parameter val_dmac0_s__LC1_2 = 32'h00000000; +parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR3 = 32'hF8003460; +parameter val_dmac0_s__SAR3 = 32'h00000000; +parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR3 = 32'hF8003464; +parameter val_dmac0_s__DAR3 = 32'h00000000; +parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR3 = 32'hF8003468; +parameter val_dmac0_s__CCR3 = 32'h00800200; +parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_3 = 32'hF800346C; +parameter val_dmac0_s__LC0_3 = 32'h00000000; +parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_3 = 32'hF8003470; +parameter val_dmac0_s__LC1_3 = 32'h00000000; +parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR4 = 32'hF8003480; +parameter val_dmac0_s__SAR4 = 32'h00000000; +parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR4 = 32'hF8003484; +parameter val_dmac0_s__DAR4 = 32'h00000000; +parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR4 = 32'hF8003488; +parameter val_dmac0_s__CCR4 = 32'h00800200; +parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_4 = 32'hF800348C; +parameter val_dmac0_s__LC0_4 = 32'h00000000; +parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_4 = 32'hF8003490; +parameter val_dmac0_s__LC1_4 = 32'h00000000; +parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR5 = 32'hF80034A0; +parameter val_dmac0_s__SAR5 = 32'h00000000; +parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR5 = 32'hF80034A4; +parameter val_dmac0_s__DAR5 = 32'h00000000; +parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR5 = 32'hF80034A8; +parameter val_dmac0_s__CCR5 = 32'h00800200; +parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_5 = 32'hF80034AC; +parameter val_dmac0_s__LC0_5 = 32'h00000000; +parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_5 = 32'hF80034B0; +parameter val_dmac0_s__LC1_5 = 32'h00000000; +parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR6 = 32'hF80034C0; +parameter val_dmac0_s__SAR6 = 32'h00000000; +parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR6 = 32'hF80034C4; +parameter val_dmac0_s__DAR6 = 32'h00000000; +parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR6 = 32'hF80034C8; +parameter val_dmac0_s__CCR6 = 32'h00800200; +parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_6 = 32'hF80034CC; +parameter val_dmac0_s__LC0_6 = 32'h00000000; +parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_6 = 32'hF80034D0; +parameter val_dmac0_s__LC1_6 = 32'h00000000; +parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR7 = 32'hF80034E0; +parameter val_dmac0_s__SAR7 = 32'h00000000; +parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR7 = 32'hF80034E4; +parameter val_dmac0_s__DAR7 = 32'h00000000; +parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR7 = 32'hF80034E8; +parameter val_dmac0_s__CCR7 = 32'h00800200; +parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_7 = 32'hF80034EC; +parameter val_dmac0_s__LC0_7 = 32'h00000000; +parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_7 = 32'hF80034F0; +parameter val_dmac0_s__LC1_7 = 32'h00000000; +parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGSTATUS = 32'hF8003D00; +parameter val_dmac0_s__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_s__DBGCMD = 32'hF8003D04; +parameter val_dmac0_s__DBGCMD = 32'h00000000; +parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST0 = 32'hF8003D08; +parameter val_dmac0_s__DBGINST0 = 32'h00000000; +parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST1 = 32'hF8003D0C; +parameter val_dmac0_s__DBGINST1 = 32'h00000000; +parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR0 = 32'hF8003E00; +parameter val_dmac0_s__CR0 = 32'h001E3071; +parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CR1 = 32'hF8003E04; +parameter val_dmac0_s__CR1 = 32'h00000074; +parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR2 = 32'hF8003E08; +parameter val_dmac0_s__CR2 = 32'h00000000; +parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CR3 = 32'hF8003E0C; +parameter val_dmac0_s__CR3 = 32'h00000000; +parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CR4 = 32'hF8003E10; +parameter val_dmac0_s__CR4 = 32'h00000000; +parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CRD = 32'hF8003E14; +parameter val_dmac0_s__CRD = 32'h07FF7F73; +parameter mask_dmac0_s__CRD = 32'hFFFFFFFF; + +parameter dmac0_s__WD = 32'hF8003E80; +parameter val_dmac0_s__WD = 32'h00000000; +parameter mask_dmac0_s__WD = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_0 = 32'hF8003FE0; +parameter val_dmac0_s__periph_id_0 = 32'h00000030; +parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_1 = 32'hF8003FE4; +parameter val_dmac0_s__periph_id_1 = 32'h00000013; +parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_2 = 32'hF8003FE8; +parameter val_dmac0_s__periph_id_2 = 32'h00000024; +parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_3 = 32'hF8003FEC; +parameter val_dmac0_s__periph_id_3 = 32'h00000000; +parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_0 = 32'hF8003FF0; +parameter val_dmac0_s__pcell_id_0 = 32'h0000000D; +parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_1 = 32'hF8003FF4; +parameter val_dmac0_s__pcell_id_1 = 32'h000000F0; +parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_2 = 32'hF8003FF8; +parameter val_dmac0_s__pcell_id_2 = 32'h00000005; +parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_3 = 32'hF8003FFC; +parameter val_dmac0_s__pcell_id_3 = 32'h000000B1; +parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter efuse_ctrl__WR_LOCK = 32'hF800D000; +parameter val_efuse_ctrl__WR_LOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004; +parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008; +parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001; +parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF; + +parameter efuse_ctrl__CFG = 32'hF800D00C; +parameter val_efuse_ctrl__CFG = 32'h00010F00; +parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF; + +parameter efuse_ctrl__STATUS = 32'hF800D010; +parameter val_efuse_ctrl__STATUS = 32'h00100000; +parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF; + +parameter efuse_ctrl__CONTROL = 32'hF800D014; +parameter val_efuse_ctrl__CONTROL = 32'h00000003; +parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF; + +parameter efuse_ctrl__PGM_STBW = 32'hF800D018; +parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0; +parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF; + +parameter efuse_ctrl__RD_STBW = 32'hF800D01C; +parameter val_efuse_ctrl__RD_STBW = 32'h0000000B; +parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem0__net_ctrl = 32'hE000B000; +parameter val_gem0__net_ctrl = 32'h00000000; +parameter mask_gem0__net_ctrl = 32'hFFFFFFFF; + +parameter gem0__net_cfg = 32'hE000B004; +parameter val_gem0__net_cfg = 32'h00080000; +parameter mask_gem0__net_cfg = 32'hFFFFFFFF; + +parameter gem0__net_status = 32'hE000B008; +parameter val_gem0__net_status = 32'h00000004; +parameter mask_gem0__net_status = 32'hFFFFFFFD; + +parameter gem0__user_io = 32'hE000B00C; +parameter val_gem0__user_io = 32'h00000000; +parameter mask_gem0__user_io = 32'h0000FFFF; + +parameter gem0__dma_cfg = 32'hE000B010; +parameter val_gem0__dma_cfg = 32'h00020784; +parameter mask_gem0__dma_cfg = 32'hFFFFFFFF; + +parameter gem0__tx_status = 32'hE000B014; +parameter val_gem0__tx_status = 32'h00000000; +parameter mask_gem0__tx_status = 32'hFFFFFFFF; + +parameter gem0__rx_qbar = 32'hE000B018; +parameter val_gem0__rx_qbar = 32'h00000000; +parameter mask_gem0__rx_qbar = 32'hFFFFFFFF; + +parameter gem0__tx_qbar = 32'hE000B01C; +parameter val_gem0__tx_qbar = 32'h00000000; +parameter mask_gem0__tx_qbar = 32'hFFFFFFFF; + +parameter gem0__rx_status = 32'hE000B020; +parameter val_gem0__rx_status = 32'h00000000; +parameter mask_gem0__rx_status = 32'hFFFFFFFF; + +parameter gem0__intr_status = 32'hE000B024; +parameter val_gem0__intr_status = 32'h00000000; +parameter mask_gem0__intr_status = 32'hFFFFFFFF; + +parameter gem0__intr_en = 32'hE000B028; +parameter val_gem0__intr_en = 32'h00000000; +parameter mask_gem0__intr_en = 32'h00000000; + +parameter gem0__intr_dis = 32'hE000B02C; +parameter val_gem0__intr_dis = 32'h00000000; +parameter mask_gem0__intr_dis = 32'h00000000; + +parameter gem0__intr_mask = 32'hE000B030; +parameter val_gem0__intr_mask = 32'h0001FFFF; +parameter mask_gem0__intr_mask = 32'hFC01FFFF; + +parameter gem0__phy_maint = 32'hE000B034; +parameter val_gem0__phy_maint = 32'h00000000; +parameter mask_gem0__phy_maint = 32'hFFFFFFFF; + +parameter gem0__rx_pauseq = 32'hE000B038; +parameter val_gem0__rx_pauseq = 32'h00000000; +parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_pauseq = 32'hE000B03C; +parameter val_gem0__tx_pauseq = 32'h0000FFFF; +parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_partial_st_fwd = 32'hE000B040; +parameter val_gem0__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__rx_partial_st_fwd = 32'hE000B044; +parameter val_gem0__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__hash_bot = 32'hE000B080; +parameter val_gem0__hash_bot = 32'h00000000; +parameter mask_gem0__hash_bot = 32'hFFFFFFFF; + +parameter gem0__hash_top = 32'hE000B084; +parameter val_gem0__hash_top = 32'h00000000; +parameter mask_gem0__hash_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_bot = 32'hE000B088; +parameter val_gem0__spec_addr1_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_top = 32'hE000B08C; +parameter val_gem0__spec_addr1_top = 32'h00000000; +parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_bot = 32'hE000B090; +parameter val_gem0__spec_addr2_bot = 32'h00000000; +parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_top = 32'hE000B094; +parameter val_gem0__spec_addr2_top = 32'h00000000; +parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_bot = 32'hE000B098; +parameter val_gem0__spec_addr3_bot = 32'h00000000; +parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_top = 32'hE000B09C; +parameter val_gem0__spec_addr3_top = 32'h00000000; +parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_bot = 32'hE000B0A0; +parameter val_gem0__spec_addr4_bot = 32'h00000000; +parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_top = 32'hE000B0A4; +parameter val_gem0__spec_addr4_top = 32'h00000000; +parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem0__type_id_match1 = 32'hE000B0A8; +parameter val_gem0__type_id_match1 = 32'h00000000; +parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF; + +parameter gem0__type_id_match2 = 32'hE000B0AC; +parameter val_gem0__type_id_match2 = 32'h00000000; +parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF; + +parameter gem0__type_id_match3 = 32'hE000B0B0; +parameter val_gem0__type_id_match3 = 32'h00000000; +parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF; + +parameter gem0__type_id_match4 = 32'hE000B0B4; +parameter val_gem0__type_id_match4 = 32'h00000000; +parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF; + +parameter gem0__wake_on_lan = 32'hE000B0B8; +parameter val_gem0__wake_on_lan = 32'h00000000; +parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF; + +parameter gem0__ipg_stretch = 32'hE000B0BC; +parameter val_gem0__ipg_stretch = 32'h00000000; +parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF; + +parameter gem0__stacked_vlan = 32'hE000B0C0; +parameter val_gem0__stacked_vlan = 32'h00000000; +parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF; + +parameter gem0__tx_pfc_pause = 32'hE000B0C4; +parameter val_gem0__tx_pfc_pause = 32'h00000000; +parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8; +parameter val_gem0__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_top = 32'hE000B0CC; +parameter val_gem0__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem0__module_id = 32'hE000B0FC; +parameter val_gem0__module_id = 32'h00020118; +parameter mask_gem0__module_id = 32'hFFFFFFFF; + +parameter gem0__octets_tx_bot = 32'hE000B100; +parameter val_gem0__octets_tx_bot = 32'h00000000; +parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_tx_top = 32'hE000B104; +parameter val_gem0__octets_tx_top = 32'h00000000; +parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF; + +parameter gem0__frames_tx = 32'hE000B108; +parameter val_gem0__frames_tx = 32'h00000000; +parameter mask_gem0__frames_tx = 32'hFFFFFFFF; + +parameter gem0__broadcast_frames_tx = 32'hE000B10C; +parameter val_gem0__broadcast_frames_tx = 32'h00000000; +parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_tx = 32'hE000B110; +parameter val_gem0__multi_frames_tx = 32'h00000000; +parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem0__pause_frames_tx = 32'hE000B114; +parameter val_gem0__pause_frames_tx = 32'h00000000; +parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_tx = 32'hE000B118; +parameter val_gem0__frames_64b_tx = 32'h00000000; +parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_tx = 32'hE000B11C; +parameter val_gem0__frames_65to127b_tx = 32'h00000000; +parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_tx = 32'hE000B120; +parameter val_gem0__frames_128to255b_tx = 32'h00000000; +parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_tx = 32'hE000B124; +parameter val_gem0__frames_256to511b_tx = 32'h00000000; +parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_tx = 32'hE000B128; +parameter val_gem0__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_tx = 32'hE000B12C; +parameter val_gem0__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_tx = 32'hE000B130; +parameter val_gem0__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem0__tx_under_runs = 32'hE000B134; +parameter val_gem0__tx_under_runs = 32'h00000000; +parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF; + +parameter gem0__single_collisn_frames = 32'hE000B138; +parameter val_gem0__single_collisn_frames = 32'h00000000; +parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__multi_collisn_frames = 32'hE000B13C; +parameter val_gem0__multi_collisn_frames = 32'h00000000; +parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__excessive_collisns = 32'hE000B140; +parameter val_gem0__excessive_collisns = 32'h00000000; +parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF; + +parameter gem0__late_collisns = 32'hE000B144; +parameter val_gem0__late_collisns = 32'h00000000; +parameter mask_gem0__late_collisns = 32'hFFFFFFFF; + +parameter gem0__deferred_tx_frames = 32'hE000B148; +parameter val_gem0__deferred_tx_frames = 32'h00000000; +parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem0__carrier_sense_errs = 32'hE000B14C; +parameter val_gem0__carrier_sense_errs = 32'h00000000; +parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem0__octets_rx_bot = 32'hE000B150; +parameter val_gem0__octets_rx_bot = 32'h00000000; +parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_rx_top = 32'hE000B154; +parameter val_gem0__octets_rx_top = 32'h00000000; +parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF; + +parameter gem0__frames_rx = 32'hE000B158; +parameter val_gem0__frames_rx = 32'h00000000; +parameter mask_gem0__frames_rx = 32'hFFFFFFFF; + +parameter gem0__bdcast_fames_rx = 32'hE000B15C; +parameter val_gem0__bdcast_fames_rx = 32'h00000000; +parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_rx = 32'hE000B160; +parameter val_gem0__multi_frames_rx = 32'h00000000; +parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem0__pause_rx = 32'hE000B164; +parameter val_gem0__pause_rx = 32'h00000000; +parameter mask_gem0__pause_rx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_rx = 32'hE000B168; +parameter val_gem0__frames_64b_rx = 32'h00000000; +parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_rx = 32'hE000B16C; +parameter val_gem0__frames_65to127b_rx = 32'h00000000; +parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_rx = 32'hE000B170; +parameter val_gem0__frames_128to255b_rx = 32'h00000000; +parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_rx = 32'hE000B174; +parameter val_gem0__frames_256to511b_rx = 32'h00000000; +parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_rx = 32'hE000B178; +parameter val_gem0__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_rx = 32'hE000B17C; +parameter val_gem0__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_rx = 32'hE000B180; +parameter val_gem0__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem0__undersz_rx = 32'hE000B184; +parameter val_gem0__undersz_rx = 32'h00000000; +parameter mask_gem0__undersz_rx = 32'hFFFFFFFF; + +parameter gem0__oversz_rx = 32'hE000B188; +parameter val_gem0__oversz_rx = 32'h00000000; +parameter mask_gem0__oversz_rx = 32'hFFFFFFFF; + +parameter gem0__jab_rx = 32'hE000B18C; +parameter val_gem0__jab_rx = 32'h00000000; +parameter mask_gem0__jab_rx = 32'hFFFFFFFF; + +parameter gem0__fcs_errors = 32'hE000B190; +parameter val_gem0__fcs_errors = 32'h00000000; +parameter mask_gem0__fcs_errors = 32'hFFFFFFFF; + +parameter gem0__length_field_errors = 32'hE000B194; +parameter val_gem0__length_field_errors = 32'h00000000; +parameter mask_gem0__length_field_errors = 32'hFFFFFFFF; + +parameter gem0__rx_symbol_errors = 32'hE000B198; +parameter val_gem0__rx_symbol_errors = 32'h00000000; +parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem0__align_errors = 32'hE000B19C; +parameter val_gem0__align_errors = 32'h00000000; +parameter mask_gem0__align_errors = 32'hFFFFFFFF; + +parameter gem0__rx_resource_errors = 32'hE000B1A0; +parameter val_gem0__rx_resource_errors = 32'h00000000; +parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem0__rx_overrun_errors = 32'hE000B1A4; +parameter val_gem0__rx_overrun_errors = 32'h00000000; +parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8; +parameter val_gem0__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem0__tcp_csum_errors = 32'hE000B1AC; +parameter val_gem0__tcp_csum_errors = 32'h00000000; +parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__udp_csum_errors = 32'hE000B1B0; +parameter val_gem0__udp_csum_errors = 32'h00000000; +parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_s = 32'hE000B1C8; +parameter val_gem0__timer_strobe_s = 32'h00000000; +parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_ns = 32'hE000B1CC; +parameter val_gem0__timer_strobe_ns = 32'h00000000; +parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem0__timer_s = 32'hE000B1D0; +parameter val_gem0__timer_s = 32'h00000000; +parameter mask_gem0__timer_s = 32'hFFFFFFFF; + +parameter gem0__timer_ns = 32'hE000B1D4; +parameter val_gem0__timer_ns = 32'h00000000; +parameter mask_gem0__timer_ns = 32'hFFFFFFFF; + +parameter gem0__timer_adjust = 32'hE000B1D8; +parameter val_gem0__timer_adjust = 32'h00000000; +parameter mask_gem0__timer_adjust = 32'hFFFFFFFF; + +parameter gem0__timer_incr = 32'hE000B1DC; +parameter val_gem0__timer_incr = 32'h00000000; +parameter mask_gem0__timer_incr = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_s = 32'hE000B1E0; +parameter val_gem0__ptp_tx_s = 32'h00000000; +parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_ns = 32'hE000B1E4; +parameter val_gem0__ptp_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_s = 32'hE000B1E8; +parameter val_gem0__ptp_rx_s = 32'h00000000; +parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_ns = 32'hE000B1EC; +parameter val_gem0__ptp_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_s = 32'hE000B1F0; +parameter val_gem0__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4; +parameter val_gem0__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_s = 32'hE000B1F8; +parameter val_gem0__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC; +parameter val_gem0__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem0__pcs_ctrl = 32'hE000B200; +parameter val_gem0__pcs_ctrl = 32'h00000000; +parameter mask_gem0__pcs_ctrl = 32'h00000000; + +parameter gem0__pcs_status = 32'hE000B204; +parameter val_gem0__pcs_status = 32'h00000000; +parameter mask_gem0__pcs_status = 32'h00000000; + +parameter gem0__pcs_upper_phy_id = 32'hE000B208; +parameter val_gem0__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem0__pcs_upper_phy_id = 32'h00000000; + +parameter gem0__pcs_lower_phy_id = 32'hE000B20C; +parameter val_gem0__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem0__pcs_lower_phy_id = 32'h00000000; + +parameter gem0__pcs_autoneg_ad = 32'hE000B210; +parameter val_gem0__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ad = 32'h00000000; + +parameter gem0__pcs_autoneg_ability = 32'hE000B214; +parameter val_gem0__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ability = 32'h00000000; + +parameter gem0__pcs_autonec_exp = 32'hE000B218; +parameter val_gem0__pcs_autonec_exp = 32'h00000000; +parameter mask_gem0__pcs_autonec_exp = 32'h00000000; + +parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C; +parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220; +parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem0__pcs_extended_status = 32'hE000B23C; +parameter val_gem0__pcs_extended_status = 32'h00000000; +parameter mask_gem0__pcs_extended_status = 32'h00000000; + +parameter gem0__design_cfg1 = 32'hE000B280; +parameter val_gem0__design_cfg1 = 32'h02000000; +parameter mask_gem0__design_cfg1 = 32'h0E000000; + +parameter gem0__design_cfg2 = 32'hE000B284; +parameter val_gem0__design_cfg2 = 32'h2A813FFF; +parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF; + +parameter gem0__design_cfg3 = 32'hE000B288; +parameter val_gem0__design_cfg3 = 32'h00000000; +parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF; + +parameter gem0__design_cfg4 = 32'hE000B28C; +parameter val_gem0__design_cfg4 = 32'h00000000; +parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF; + +parameter gem0__design_cfg5 = 32'hE000B290; +parameter val_gem0__design_cfg5 = 32'h002F2045; +parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF; + +parameter gem0__design_cfg6 = 32'hE000B294; +parameter val_gem0__design_cfg6 = 32'h00000000; +parameter mask_gem0__design_cfg6 = 32'h00000000; + +parameter gem0__design_cfg7 = 32'hE000B298; +parameter val_gem0__design_cfg7 = 32'h00000000; +parameter mask_gem0__design_cfg7 = 32'h00000000; + +parameter gem0__isr_pq1 = 32'hE000B400; +parameter val_gem0__isr_pq1 = 32'h00000000; +parameter mask_gem0__isr_pq1 = 32'h00000000; + +parameter gem0__isr_pq2 = 32'hE000B404; +parameter val_gem0__isr_pq2 = 32'h00000000; +parameter mask_gem0__isr_pq2 = 32'h00000000; + +parameter gem0__isr_pq3 = 32'hE000B408; +parameter val_gem0__isr_pq3 = 32'h00000000; +parameter mask_gem0__isr_pq3 = 32'h00000000; + +parameter gem0__isr_pq4 = 32'hE000B40C; +parameter val_gem0__isr_pq4 = 32'h00000000; +parameter mask_gem0__isr_pq4 = 32'h00000000; + +parameter gem0__isr_pq5 = 32'hE000B410; +parameter val_gem0__isr_pq5 = 32'h00000000; +parameter mask_gem0__isr_pq5 = 32'h00000000; + +parameter gem0__isr_pq6 = 32'hE000B414; +parameter val_gem0__isr_pq6 = 32'h00000000; +parameter mask_gem0__isr_pq6 = 32'h00000000; + +parameter gem0__isr_pq7 = 32'hE000B418; +parameter val_gem0__isr_pq7 = 32'h00000000; +parameter mask_gem0__isr_pq7 = 32'h00000000; + +parameter gem0__tx_qbar_q1 = 32'hE000B440; +parameter val_gem0__tx_qbar_q1 = 32'h00000000; +parameter mask_gem0__tx_qbar_q1 = 32'h00000000; + +parameter gem0__tx_qbar_q2 = 32'hE000B444; +parameter val_gem0__tx_qbar_q2 = 32'h00000000; +parameter mask_gem0__tx_qbar_q2 = 32'h00000000; + +parameter gem0__tx_qbar_q3 = 32'hE000B448; +parameter val_gem0__tx_qbar_q3 = 32'h00000000; +parameter mask_gem0__tx_qbar_q3 = 32'h00000000; + +parameter gem0__tx_qbar_q4 = 32'hE000B44C; +parameter val_gem0__tx_qbar_q4 = 32'h00000000; +parameter mask_gem0__tx_qbar_q4 = 32'h00000000; + +parameter gem0__tx_qbar_q5 = 32'hE000B450; +parameter val_gem0__tx_qbar_q5 = 32'h00000000; +parameter mask_gem0__tx_qbar_q5 = 32'h00000000; + +parameter gem0__tx_qbar_q6 = 32'hE000B454; +parameter val_gem0__tx_qbar_q6 = 32'h00000000; +parameter mask_gem0__tx_qbar_q6 = 32'h00000000; + +parameter gem0__tx_qbar_q7 = 32'hE000B458; +parameter val_gem0__tx_qbar_q7 = 32'h00000000; +parameter mask_gem0__tx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_qbar_q1 = 32'hE000B480; +parameter val_gem0__rx_qbar_q1 = 32'h00000000; +parameter mask_gem0__rx_qbar_q1 = 32'h00000000; + +parameter gem0__rx_qbar_q2 = 32'hE000B484; +parameter val_gem0__rx_qbar_q2 = 32'h00000000; +parameter mask_gem0__rx_qbar_q2 = 32'h00000000; + +parameter gem0__rx_qbar_q3 = 32'hE000B488; +parameter val_gem0__rx_qbar_q3 = 32'h00000000; +parameter mask_gem0__rx_qbar_q3 = 32'h00000000; + +parameter gem0__rx_qbar_q4 = 32'hE000B48C; +parameter val_gem0__rx_qbar_q4 = 32'h00000000; +parameter mask_gem0__rx_qbar_q4 = 32'h00000000; + +parameter gem0__rx_qbar_q5 = 32'hE000B490; +parameter val_gem0__rx_qbar_q5 = 32'h00000000; +parameter mask_gem0__rx_qbar_q5 = 32'h00000000; + +parameter gem0__rx_qbar_q6 = 32'hE000B494; +parameter val_gem0__rx_qbar_q6 = 32'h00000000; +parameter mask_gem0__rx_qbar_q6 = 32'h00000000; + +parameter gem0__rx_qbar_q7 = 32'hE000B498; +parameter val_gem0__rx_qbar_q7 = 32'h00000000; +parameter mask_gem0__rx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_bufsz_q1 = 32'hE000B4A0; +parameter val_gem0__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q1 = 32'h00000000; + +parameter gem0__rx_bufsz_q2 = 32'hE000B4A4; +parameter val_gem0__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q2 = 32'h00000000; + +parameter gem0__rx_bufsz_q3 = 32'hE000B4A8; +parameter val_gem0__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q3 = 32'h00000000; + +parameter gem0__rx_bufsz_q4 = 32'hE000B4AC; +parameter val_gem0__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q4 = 32'h00000000; + +parameter gem0__rx_bufsz_q5 = 32'hE000B4B0; +parameter val_gem0__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q5 = 32'h00000000; + +parameter gem0__rx_bufsz_q6 = 32'hE000B4B4; +parameter val_gem0__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q6 = 32'h00000000; + +parameter gem0__rx_bufsz_q7 = 32'hE000B4B8; +parameter val_gem0__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q7 = 32'h00000000; + +parameter gem0__screen_t1_r0 = 32'hE000B500; +parameter val_gem0__screen_t1_r0 = 32'h00000000; +parameter mask_gem0__screen_t1_r0 = 32'h00000000; + +parameter gem0__screen_t1_r1 = 32'hE000B504; +parameter val_gem0__screen_t1_r1 = 32'h00000000; +parameter mask_gem0__screen_t1_r1 = 32'h00000000; + +parameter gem0__screen_t1_r2 = 32'hE000B508; +parameter val_gem0__screen_t1_r2 = 32'h00000000; +parameter mask_gem0__screen_t1_r2 = 32'h00000000; + +parameter gem0__screen_t1_r3 = 32'hE000B50C; +parameter val_gem0__screen_t1_r3 = 32'h00000000; +parameter mask_gem0__screen_t1_r3 = 32'h00000000; + +parameter gem0__screen_t1_r4 = 32'hE000B510; +parameter val_gem0__screen_t1_r4 = 32'h00000000; +parameter mask_gem0__screen_t1_r4 = 32'h00000000; + +parameter gem0__screen_t1_r5 = 32'hE000B514; +parameter val_gem0__screen_t1_r5 = 32'h00000000; +parameter mask_gem0__screen_t1_r5 = 32'h00000000; + +parameter gem0__screen_t1_r6 = 32'hE000B518; +parameter val_gem0__screen_t1_r6 = 32'h00000000; +parameter mask_gem0__screen_t1_r6 = 32'h00000000; + +parameter gem0__screen_t1_r7 = 32'hE000B51C; +parameter val_gem0__screen_t1_r7 = 32'h00000000; +parameter mask_gem0__screen_t1_r7 = 32'h00000000; + +parameter gem0__screen_t1_r8 = 32'hE000B520; +parameter val_gem0__screen_t1_r8 = 32'h00000000; +parameter mask_gem0__screen_t1_r8 = 32'h00000000; + +parameter gem0__screen_t1_r9 = 32'hE000B524; +parameter val_gem0__screen_t1_r9 = 32'h00000000; +parameter mask_gem0__screen_t1_r9 = 32'h00000000; + +parameter gem0__screen_t1_r10 = 32'hE000B528; +parameter val_gem0__screen_t1_r10 = 32'h00000000; +parameter mask_gem0__screen_t1_r10 = 32'h00000000; + +parameter gem0__screen_t1_r11 = 32'hE000B52C; +parameter val_gem0__screen_t1_r11 = 32'h00000000; +parameter mask_gem0__screen_t1_r11 = 32'h00000000; + +parameter gem0__screen_t1_r12 = 32'hE000B530; +parameter val_gem0__screen_t1_r12 = 32'h00000000; +parameter mask_gem0__screen_t1_r12 = 32'h00000000; + +parameter gem0__screen_t1_r13 = 32'hE000B534; +parameter val_gem0__screen_t1_r13 = 32'h00000000; +parameter mask_gem0__screen_t1_r13 = 32'h00000000; + +parameter gem0__screen_t1_r14 = 32'hE000B538; +parameter val_gem0__screen_t1_r14 = 32'h00000000; +parameter mask_gem0__screen_t1_r14 = 32'h00000000; + +parameter gem0__screen_t1_r15 = 32'hE000B53C; +parameter val_gem0__screen_t1_r15 = 32'h00000000; +parameter mask_gem0__screen_t1_r15 = 32'h00000000; + +parameter gem0__screen_t2_r0 = 32'hE000B540; +parameter val_gem0__screen_t2_r0 = 32'h00000000; +parameter mask_gem0__screen_t2_r0 = 32'h00000000; + +parameter gem0__screen_t2_r1 = 32'hE000B544; +parameter val_gem0__screen_t2_r1 = 32'h00000000; +parameter mask_gem0__screen_t2_r1 = 32'h00000000; + +parameter gem0__screen_t2_r2 = 32'hE000B548; +parameter val_gem0__screen_t2_r2 = 32'h00000000; +parameter mask_gem0__screen_t2_r2 = 32'h00000000; + +parameter gem0__screen_t2_r3 = 32'hE000B54C; +parameter val_gem0__screen_t2_r3 = 32'h00000000; +parameter mask_gem0__screen_t2_r3 = 32'h00000000; + +parameter gem0__screen_t2_r4 = 32'hE000B550; +parameter val_gem0__screen_t2_r4 = 32'h00000000; +parameter mask_gem0__screen_t2_r4 = 32'h00000000; + +parameter gem0__screen_t2_r5 = 32'hE000B554; +parameter val_gem0__screen_t2_r5 = 32'h00000000; +parameter mask_gem0__screen_t2_r5 = 32'h00000000; + +parameter gem0__screen_t2_r6 = 32'hE000B558; +parameter val_gem0__screen_t2_r6 = 32'h00000000; +parameter mask_gem0__screen_t2_r6 = 32'h00000000; + +parameter gem0__screen_t2_r7 = 32'hE000B55C; +parameter val_gem0__screen_t2_r7 = 32'h00000000; +parameter mask_gem0__screen_t2_r7 = 32'h00000000; + +parameter gem0__screen_t2_r8 = 32'hE000B560; +parameter val_gem0__screen_t2_r8 = 32'h00000000; +parameter mask_gem0__screen_t2_r8 = 32'h00000000; + +parameter gem0__screen_t2_r9 = 32'hE000B564; +parameter val_gem0__screen_t2_r9 = 32'h00000000; +parameter mask_gem0__screen_t2_r9 = 32'h00000000; + +parameter gem0__screen_t2_r10 = 32'hE000B568; +parameter val_gem0__screen_t2_r10 = 32'h00000000; +parameter mask_gem0__screen_t2_r10 = 32'h00000000; + +parameter gem0__screen_t2_r11 = 32'hE000B56C; +parameter val_gem0__screen_t2_r11 = 32'h00000000; +parameter mask_gem0__screen_t2_r11 = 32'h00000000; + +parameter gem0__screen_t2_r12 = 32'hE000B570; +parameter val_gem0__screen_t2_r12 = 32'h00000000; +parameter mask_gem0__screen_t2_r12 = 32'h00000000; + +parameter gem0__screen_t2_r13 = 32'hE000B574; +parameter val_gem0__screen_t2_r13 = 32'h00000000; +parameter mask_gem0__screen_t2_r13 = 32'h00000000; + +parameter gem0__screen_t2_r14 = 32'hE000B578; +parameter val_gem0__screen_t2_r14 = 32'h00000000; +parameter mask_gem0__screen_t2_r14 = 32'h00000000; + +parameter gem0__screen_t2_r15 = 32'hE000B57C; +parameter val_gem0__screen_t2_r15 = 32'h00000000; +parameter mask_gem0__screen_t2_r15 = 32'h00000000; + +parameter gem0__intr_en_pq1 = 32'hE000B600; +parameter val_gem0__intr_en_pq1 = 32'h00000000; +parameter mask_gem0__intr_en_pq1 = 32'h00000000; + +parameter gem0__intr_en_pq2 = 32'hE000B604; +parameter val_gem0__intr_en_pq2 = 32'h00000000; +parameter mask_gem0__intr_en_pq2 = 32'h00000000; + +parameter gem0__intr_en_pq3 = 32'hE000B608; +parameter val_gem0__intr_en_pq3 = 32'h00000000; +parameter mask_gem0__intr_en_pq3 = 32'h00000000; + +parameter gem0__intr_en_pq4 = 32'hE000B60C; +parameter val_gem0__intr_en_pq4 = 32'h00000000; +parameter mask_gem0__intr_en_pq4 = 32'h00000000; + +parameter gem0__intr_en_pq5 = 32'hE000B610; +parameter val_gem0__intr_en_pq5 = 32'h00000000; +parameter mask_gem0__intr_en_pq5 = 32'h00000000; + +parameter gem0__intr_en_pq6 = 32'hE000B614; +parameter val_gem0__intr_en_pq6 = 32'h00000000; +parameter mask_gem0__intr_en_pq6 = 32'h00000000; + +parameter gem0__intr_en_pq7 = 32'hE000B618; +parameter val_gem0__intr_en_pq7 = 32'h00000000; +parameter mask_gem0__intr_en_pq7 = 32'h00000000; + +parameter gem0__intr_dis_pq1 = 32'hE000B620; +parameter val_gem0__intr_dis_pq1 = 32'h00000000; +parameter mask_gem0__intr_dis_pq1 = 32'h00000000; + +parameter gem0__intr_dis_pq2 = 32'hE000B624; +parameter val_gem0__intr_dis_pq2 = 32'h00000000; +parameter mask_gem0__intr_dis_pq2 = 32'h00000000; + +parameter gem0__intr_dis_pq3 = 32'hE000B628; +parameter val_gem0__intr_dis_pq3 = 32'h00000000; +parameter mask_gem0__intr_dis_pq3 = 32'h00000000; + +parameter gem0__intr_dis_pq4 = 32'hE000B62C; +parameter val_gem0__intr_dis_pq4 = 32'h00000000; +parameter mask_gem0__intr_dis_pq4 = 32'h00000000; + +parameter gem0__intr_dis_pq5 = 32'hE000B630; +parameter val_gem0__intr_dis_pq5 = 32'h00000000; +parameter mask_gem0__intr_dis_pq5 = 32'h00000000; + +parameter gem0__intr_dis_pq6 = 32'hE000B634; +parameter val_gem0__intr_dis_pq6 = 32'h00000000; +parameter mask_gem0__intr_dis_pq6 = 32'h00000000; + +parameter gem0__intr_dis_pq7 = 32'hE000B638; +parameter val_gem0__intr_dis_pq7 = 32'h00000000; +parameter mask_gem0__intr_dis_pq7 = 32'h00000000; + +parameter gem0__intr_mask_pq1 = 32'hE000B640; +parameter val_gem0__intr_mask_pq1 = 32'h00000000; +parameter mask_gem0__intr_mask_pq1 = 32'h00000000; + +parameter gem0__intr_mask_pq2 = 32'hE000B644; +parameter val_gem0__intr_mask_pq2 = 32'h00000000; +parameter mask_gem0__intr_mask_pq2 = 32'h00000000; + +parameter gem0__intr_mask_pq3 = 32'hE000B648; +parameter val_gem0__intr_mask_pq3 = 32'h00000000; +parameter mask_gem0__intr_mask_pq3 = 32'h00000000; + +parameter gem0__intr_mask_pq4 = 32'hE000B64C; +parameter val_gem0__intr_mask_pq4 = 32'h00000000; +parameter mask_gem0__intr_mask_pq4 = 32'h00000000; + +parameter gem0__intr_mask_pq5 = 32'hE000B650; +parameter val_gem0__intr_mask_pq5 = 32'h00000000; +parameter mask_gem0__intr_mask_pq5 = 32'h00000000; + +parameter gem0__intr_mask_pq6 = 32'hE000B654; +parameter val_gem0__intr_mask_pq6 = 32'h00000000; +parameter mask_gem0__intr_mask_pq6 = 32'h00000000; + +parameter gem0__intr_mask_pq7 = 32'hE000B658; +parameter val_gem0__intr_mask_pq7 = 32'h00000000; +parameter mask_gem0__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem1__net_ctrl = 32'hE000C000; +parameter val_gem1__net_ctrl = 32'h00000000; +parameter mask_gem1__net_ctrl = 32'hFFFFFFFF; + +parameter gem1__net_cfg = 32'hE000C004; +parameter val_gem1__net_cfg = 32'h00080000; +parameter mask_gem1__net_cfg = 32'hFFFFFFFF; + +parameter gem1__net_status = 32'hE000C008; +parameter val_gem1__net_status = 32'h00000004; +parameter mask_gem1__net_status = 32'hFFFFFFFD; + +parameter gem1__user_io = 32'hE000C00C; +parameter val_gem1__user_io = 32'h00000000; +parameter mask_gem1__user_io = 32'h0000FFFF; + +parameter gem1__dma_cfg = 32'hE000C010; +parameter val_gem1__dma_cfg = 32'h00020784; +parameter mask_gem1__dma_cfg = 32'hFFFFFFFF; + +parameter gem1__tx_status = 32'hE000C014; +parameter val_gem1__tx_status = 32'h00000000; +parameter mask_gem1__tx_status = 32'hFFFFFFFF; + +parameter gem1__rx_qbar = 32'hE000C018; +parameter val_gem1__rx_qbar = 32'h00000000; +parameter mask_gem1__rx_qbar = 32'hFFFFFFFF; + +parameter gem1__tx_qbar = 32'hE000C01C; +parameter val_gem1__tx_qbar = 32'h00000000; +parameter mask_gem1__tx_qbar = 32'hFFFFFFFF; + +parameter gem1__rx_status = 32'hE000C020; +parameter val_gem1__rx_status = 32'h00000000; +parameter mask_gem1__rx_status = 32'hFFFFFFFF; + +parameter gem1__intr_status = 32'hE000C024; +parameter val_gem1__intr_status = 32'h00000000; +parameter mask_gem1__intr_status = 32'hFFFFFFFF; + +parameter gem1__intr_en = 32'hE000C028; +parameter val_gem1__intr_en = 32'h00000000; +parameter mask_gem1__intr_en = 32'h00000000; + +parameter gem1__intr_dis = 32'hE000C02C; +parameter val_gem1__intr_dis = 32'h00000000; +parameter mask_gem1__intr_dis = 32'h00000000; + +parameter gem1__intr_mask = 32'hE000C030; +parameter val_gem1__intr_mask = 32'h0001FFFF; +parameter mask_gem1__intr_mask = 32'hFC01FFFF; + +parameter gem1__phy_maint = 32'hE000C034; +parameter val_gem1__phy_maint = 32'h00000000; +parameter mask_gem1__phy_maint = 32'hFFFFFFFF; + +parameter gem1__rx_pauseq = 32'hE000C038; +parameter val_gem1__rx_pauseq = 32'h00000000; +parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_pauseq = 32'hE000C03C; +parameter val_gem1__tx_pauseq = 32'h0000FFFF; +parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_partial_st_fwd = 32'hE000C040; +parameter val_gem1__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__rx_partial_st_fwd = 32'hE000C044; +parameter val_gem1__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__hash_bot = 32'hE000C080; +parameter val_gem1__hash_bot = 32'h00000000; +parameter mask_gem1__hash_bot = 32'hFFFFFFFF; + +parameter gem1__hash_top = 32'hE000C084; +parameter val_gem1__hash_top = 32'h00000000; +parameter mask_gem1__hash_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_bot = 32'hE000C088; +parameter val_gem1__spec_addr1_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_top = 32'hE000C08C; +parameter val_gem1__spec_addr1_top = 32'h00000000; +parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_bot = 32'hE000C090; +parameter val_gem1__spec_addr2_bot = 32'h00000000; +parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_top = 32'hE000C094; +parameter val_gem1__spec_addr2_top = 32'h00000000; +parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_bot = 32'hE000C098; +parameter val_gem1__spec_addr3_bot = 32'h00000000; +parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_top = 32'hE000C09C; +parameter val_gem1__spec_addr3_top = 32'h00000000; +parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_bot = 32'hE000C0A0; +parameter val_gem1__spec_addr4_bot = 32'h00000000; +parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_top = 32'hE000C0A4; +parameter val_gem1__spec_addr4_top = 32'h00000000; +parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem1__type_id_match1 = 32'hE000C0A8; +parameter val_gem1__type_id_match1 = 32'h00000000; +parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF; + +parameter gem1__type_id_match2 = 32'hE000C0AC; +parameter val_gem1__type_id_match2 = 32'h00000000; +parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF; + +parameter gem1__type_id_match3 = 32'hE000C0B0; +parameter val_gem1__type_id_match3 = 32'h00000000; +parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF; + +parameter gem1__type_id_match4 = 32'hE000C0B4; +parameter val_gem1__type_id_match4 = 32'h00000000; +parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF; + +parameter gem1__wake_on_lan = 32'hE000C0B8; +parameter val_gem1__wake_on_lan = 32'h00000000; +parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF; + +parameter gem1__ipg_stretch = 32'hE000C0BC; +parameter val_gem1__ipg_stretch = 32'h00000000; +parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF; + +parameter gem1__stacked_vlan = 32'hE000C0C0; +parameter val_gem1__stacked_vlan = 32'h00000000; +parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF; + +parameter gem1__tx_pfc_pause = 32'hE000C0C4; +parameter val_gem1__tx_pfc_pause = 32'h00000000; +parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8; +parameter val_gem1__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_top = 32'hE000C0CC; +parameter val_gem1__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem1__module_id = 32'hE000C0FC; +parameter val_gem1__module_id = 32'h00020118; +parameter mask_gem1__module_id = 32'hFFFFFFFF; + +parameter gem1__octets_tx_bot = 32'hE000C100; +parameter val_gem1__octets_tx_bot = 32'h00000000; +parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_tx_top = 32'hE000C104; +parameter val_gem1__octets_tx_top = 32'h00000000; +parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF; + +parameter gem1__frames_tx = 32'hE000C108; +parameter val_gem1__frames_tx = 32'h00000000; +parameter mask_gem1__frames_tx = 32'hFFFFFFFF; + +parameter gem1__broadcast_frames_tx = 32'hE000C10C; +parameter val_gem1__broadcast_frames_tx = 32'h00000000; +parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_tx = 32'hE000C110; +parameter val_gem1__multi_frames_tx = 32'h00000000; +parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem1__pause_frames_tx = 32'hE000C114; +parameter val_gem1__pause_frames_tx = 32'h00000000; +parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_tx = 32'hE000C118; +parameter val_gem1__frames_64b_tx = 32'h00000000; +parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_tx = 32'hE000C11C; +parameter val_gem1__frames_65to127b_tx = 32'h00000000; +parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_tx = 32'hE000C120; +parameter val_gem1__frames_128to255b_tx = 32'h00000000; +parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_tx = 32'hE000C124; +parameter val_gem1__frames_256to511b_tx = 32'h00000000; +parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_tx = 32'hE000C128; +parameter val_gem1__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_tx = 32'hE000C12C; +parameter val_gem1__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_tx = 32'hE000C130; +parameter val_gem1__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem1__tx_under_runs = 32'hE000C134; +parameter val_gem1__tx_under_runs = 32'h00000000; +parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF; + +parameter gem1__single_collisn_frames = 32'hE000C138; +parameter val_gem1__single_collisn_frames = 32'h00000000; +parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__multi_collisn_frames = 32'hE000C13C; +parameter val_gem1__multi_collisn_frames = 32'h00000000; +parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__excessive_collisns = 32'hE000C140; +parameter val_gem1__excessive_collisns = 32'h00000000; +parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF; + +parameter gem1__late_collisns = 32'hE000C144; +parameter val_gem1__late_collisns = 32'h00000000; +parameter mask_gem1__late_collisns = 32'hFFFFFFFF; + +parameter gem1__deferred_tx_frames = 32'hE000C148; +parameter val_gem1__deferred_tx_frames = 32'h00000000; +parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem1__carrier_sense_errs = 32'hE000C14C; +parameter val_gem1__carrier_sense_errs = 32'h00000000; +parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem1__octets_rx_bot = 32'hE000C150; +parameter val_gem1__octets_rx_bot = 32'h00000000; +parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_rx_top = 32'hE000C154; +parameter val_gem1__octets_rx_top = 32'h00000000; +parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF; + +parameter gem1__frames_rx = 32'hE000C158; +parameter val_gem1__frames_rx = 32'h00000000; +parameter mask_gem1__frames_rx = 32'hFFFFFFFF; + +parameter gem1__bdcast_fames_rx = 32'hE000C15C; +parameter val_gem1__bdcast_fames_rx = 32'h00000000; +parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_rx = 32'hE000C160; +parameter val_gem1__multi_frames_rx = 32'h00000000; +parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem1__pause_rx = 32'hE000C164; +parameter val_gem1__pause_rx = 32'h00000000; +parameter mask_gem1__pause_rx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_rx = 32'hE000C168; +parameter val_gem1__frames_64b_rx = 32'h00000000; +parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_rx = 32'hE000C16C; +parameter val_gem1__frames_65to127b_rx = 32'h00000000; +parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_rx = 32'hE000C170; +parameter val_gem1__frames_128to255b_rx = 32'h00000000; +parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_rx = 32'hE000C174; +parameter val_gem1__frames_256to511b_rx = 32'h00000000; +parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_rx = 32'hE000C178; +parameter val_gem1__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_rx = 32'hE000C17C; +parameter val_gem1__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_rx = 32'hE000C180; +parameter val_gem1__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem1__undersz_rx = 32'hE000C184; +parameter val_gem1__undersz_rx = 32'h00000000; +parameter mask_gem1__undersz_rx = 32'hFFFFFFFF; + +parameter gem1__oversz_rx = 32'hE000C188; +parameter val_gem1__oversz_rx = 32'h00000000; +parameter mask_gem1__oversz_rx = 32'hFFFFFFFF; + +parameter gem1__jab_rx = 32'hE000C18C; +parameter val_gem1__jab_rx = 32'h00000000; +parameter mask_gem1__jab_rx = 32'hFFFFFFFF; + +parameter gem1__fcs_errors = 32'hE000C190; +parameter val_gem1__fcs_errors = 32'h00000000; +parameter mask_gem1__fcs_errors = 32'hFFFFFFFF; + +parameter gem1__length_field_errors = 32'hE000C194; +parameter val_gem1__length_field_errors = 32'h00000000; +parameter mask_gem1__length_field_errors = 32'hFFFFFFFF; + +parameter gem1__rx_symbol_errors = 32'hE000C198; +parameter val_gem1__rx_symbol_errors = 32'h00000000; +parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem1__align_errors = 32'hE000C19C; +parameter val_gem1__align_errors = 32'h00000000; +parameter mask_gem1__align_errors = 32'hFFFFFFFF; + +parameter gem1__rx_resource_errors = 32'hE000C1A0; +parameter val_gem1__rx_resource_errors = 32'h00000000; +parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem1__rx_overrun_errors = 32'hE000C1A4; +parameter val_gem1__rx_overrun_errors = 32'h00000000; +parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8; +parameter val_gem1__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem1__tcp_csum_errors = 32'hE000C1AC; +parameter val_gem1__tcp_csum_errors = 32'h00000000; +parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__udp_csum_errors = 32'hE000C1B0; +parameter val_gem1__udp_csum_errors = 32'h00000000; +parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_s = 32'hE000C1C8; +parameter val_gem1__timer_strobe_s = 32'h00000000; +parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_ns = 32'hE000C1CC; +parameter val_gem1__timer_strobe_ns = 32'h00000000; +parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem1__timer_s = 32'hE000C1D0; +parameter val_gem1__timer_s = 32'h00000000; +parameter mask_gem1__timer_s = 32'hFFFFFFFF; + +parameter gem1__timer_ns = 32'hE000C1D4; +parameter val_gem1__timer_ns = 32'h00000000; +parameter mask_gem1__timer_ns = 32'hFFFFFFFF; + +parameter gem1__timer_adjust = 32'hE000C1D8; +parameter val_gem1__timer_adjust = 32'h00000000; +parameter mask_gem1__timer_adjust = 32'hFFFFFFFF; + +parameter gem1__timer_incr = 32'hE000C1DC; +parameter val_gem1__timer_incr = 32'h00000000; +parameter mask_gem1__timer_incr = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_s = 32'hE000C1E0; +parameter val_gem1__ptp_tx_s = 32'h00000000; +parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_ns = 32'hE000C1E4; +parameter val_gem1__ptp_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_s = 32'hE000C1E8; +parameter val_gem1__ptp_rx_s = 32'h00000000; +parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_ns = 32'hE000C1EC; +parameter val_gem1__ptp_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_s = 32'hE000C1F0; +parameter val_gem1__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4; +parameter val_gem1__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_s = 32'hE000C1F8; +parameter val_gem1__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC; +parameter val_gem1__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem1__pcs_ctrl = 32'hE000C200; +parameter val_gem1__pcs_ctrl = 32'h00000000; +parameter mask_gem1__pcs_ctrl = 32'h00000000; + +parameter gem1__pcs_status = 32'hE000C204; +parameter val_gem1__pcs_status = 32'h00000000; +parameter mask_gem1__pcs_status = 32'h00000000; + +parameter gem1__pcs_upper_phy_id = 32'hE000C208; +parameter val_gem1__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem1__pcs_upper_phy_id = 32'h00000000; + +parameter gem1__pcs_lower_phy_id = 32'hE000C20C; +parameter val_gem1__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem1__pcs_lower_phy_id = 32'h00000000; + +parameter gem1__pcs_autoneg_ad = 32'hE000C210; +parameter val_gem1__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ad = 32'h00000000; + +parameter gem1__pcs_autoneg_ability = 32'hE000C214; +parameter val_gem1__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ability = 32'h00000000; + +parameter gem1__pcs_autonec_exp = 32'hE000C218; +parameter val_gem1__pcs_autonec_exp = 32'h00000000; +parameter mask_gem1__pcs_autonec_exp = 32'h00000000; + +parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C; +parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220; +parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem1__pcs_extended_status = 32'hE000C23C; +parameter val_gem1__pcs_extended_status = 32'h00000000; +parameter mask_gem1__pcs_extended_status = 32'h00000000; + +parameter gem1__design_cfg1 = 32'hE000C280; +parameter val_gem1__design_cfg1 = 32'h02000000; +parameter mask_gem1__design_cfg1 = 32'h0E000000; + +parameter gem1__design_cfg2 = 32'hE000C284; +parameter val_gem1__design_cfg2 = 32'h2A813FFF; +parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF; + +parameter gem1__design_cfg3 = 32'hE000C288; +parameter val_gem1__design_cfg3 = 32'h00000000; +parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF; + +parameter gem1__design_cfg4 = 32'hE000C28C; +parameter val_gem1__design_cfg4 = 32'h00000000; +parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF; + +parameter gem1__design_cfg5 = 32'hE000C290; +parameter val_gem1__design_cfg5 = 32'h002F2045; +parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF; + +parameter gem1__design_cfg6 = 32'hE000C294; +parameter val_gem1__design_cfg6 = 32'h00000000; +parameter mask_gem1__design_cfg6 = 32'h00000000; + +parameter gem1__design_cfg7 = 32'hE000C298; +parameter val_gem1__design_cfg7 = 32'h00000000; +parameter mask_gem1__design_cfg7 = 32'h00000000; + +parameter gem1__isr_pq1 = 32'hE000C400; +parameter val_gem1__isr_pq1 = 32'h00000000; +parameter mask_gem1__isr_pq1 = 32'h00000000; + +parameter gem1__isr_pq2 = 32'hE000C404; +parameter val_gem1__isr_pq2 = 32'h00000000; +parameter mask_gem1__isr_pq2 = 32'h00000000; + +parameter gem1__isr_pq3 = 32'hE000C408; +parameter val_gem1__isr_pq3 = 32'h00000000; +parameter mask_gem1__isr_pq3 = 32'h00000000; + +parameter gem1__isr_pq4 = 32'hE000C40C; +parameter val_gem1__isr_pq4 = 32'h00000000; +parameter mask_gem1__isr_pq4 = 32'h00000000; + +parameter gem1__isr_pq5 = 32'hE000C410; +parameter val_gem1__isr_pq5 = 32'h00000000; +parameter mask_gem1__isr_pq5 = 32'h00000000; + +parameter gem1__isr_pq6 = 32'hE000C414; +parameter val_gem1__isr_pq6 = 32'h00000000; +parameter mask_gem1__isr_pq6 = 32'h00000000; + +parameter gem1__isr_pq7 = 32'hE000C418; +parameter val_gem1__isr_pq7 = 32'h00000000; +parameter mask_gem1__isr_pq7 = 32'h00000000; + +parameter gem1__tx_qbar_q1 = 32'hE000C440; +parameter val_gem1__tx_qbar_q1 = 32'h00000000; +parameter mask_gem1__tx_qbar_q1 = 32'h00000000; + +parameter gem1__tx_qbar_q2 = 32'hE000C444; +parameter val_gem1__tx_qbar_q2 = 32'h00000000; +parameter mask_gem1__tx_qbar_q2 = 32'h00000000; + +parameter gem1__tx_qbar_q3 = 32'hE000C448; +parameter val_gem1__tx_qbar_q3 = 32'h00000000; +parameter mask_gem1__tx_qbar_q3 = 32'h00000000; + +parameter gem1__tx_qbar_q4 = 32'hE000C44C; +parameter val_gem1__tx_qbar_q4 = 32'h00000000; +parameter mask_gem1__tx_qbar_q4 = 32'h00000000; + +parameter gem1__tx_qbar_q5 = 32'hE000C450; +parameter val_gem1__tx_qbar_q5 = 32'h00000000; +parameter mask_gem1__tx_qbar_q5 = 32'h00000000; + +parameter gem1__tx_qbar_q6 = 32'hE000C454; +parameter val_gem1__tx_qbar_q6 = 32'h00000000; +parameter mask_gem1__tx_qbar_q6 = 32'h00000000; + +parameter gem1__tx_qbar_q7 = 32'hE000C458; +parameter val_gem1__tx_qbar_q7 = 32'h00000000; +parameter mask_gem1__tx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_qbar_q1 = 32'hE000C480; +parameter val_gem1__rx_qbar_q1 = 32'h00000000; +parameter mask_gem1__rx_qbar_q1 = 32'h00000000; + +parameter gem1__rx_qbar_q2 = 32'hE000C484; +parameter val_gem1__rx_qbar_q2 = 32'h00000000; +parameter mask_gem1__rx_qbar_q2 = 32'h00000000; + +parameter gem1__rx_qbar_q3 = 32'hE000C488; +parameter val_gem1__rx_qbar_q3 = 32'h00000000; +parameter mask_gem1__rx_qbar_q3 = 32'h00000000; + +parameter gem1__rx_qbar_q4 = 32'hE000C48C; +parameter val_gem1__rx_qbar_q4 = 32'h00000000; +parameter mask_gem1__rx_qbar_q4 = 32'h00000000; + +parameter gem1__rx_qbar_q5 = 32'hE000C490; +parameter val_gem1__rx_qbar_q5 = 32'h00000000; +parameter mask_gem1__rx_qbar_q5 = 32'h00000000; + +parameter gem1__rx_qbar_q6 = 32'hE000C494; +parameter val_gem1__rx_qbar_q6 = 32'h00000000; +parameter mask_gem1__rx_qbar_q6 = 32'h00000000; + +parameter gem1__rx_qbar_q7 = 32'hE000C498; +parameter val_gem1__rx_qbar_q7 = 32'h00000000; +parameter mask_gem1__rx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_bufsz_q1 = 32'hE000C4A0; +parameter val_gem1__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q1 = 32'h00000000; + +parameter gem1__rx_bufsz_q2 = 32'hE000C4A4; +parameter val_gem1__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q2 = 32'h00000000; + +parameter gem1__rx_bufsz_q3 = 32'hE000C4A8; +parameter val_gem1__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q3 = 32'h00000000; + +parameter gem1__rx_bufsz_q4 = 32'hE000C4AC; +parameter val_gem1__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q4 = 32'h00000000; + +parameter gem1__rx_bufsz_q5 = 32'hE000C4B0; +parameter val_gem1__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q5 = 32'h00000000; + +parameter gem1__rx_bufsz_q6 = 32'hE000C4B4; +parameter val_gem1__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q6 = 32'h00000000; + +parameter gem1__rx_bufsz_q7 = 32'hE000C4B8; +parameter val_gem1__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q7 = 32'h00000000; + +parameter gem1__screen_t1_r0 = 32'hE000C500; +parameter val_gem1__screen_t1_r0 = 32'h00000000; +parameter mask_gem1__screen_t1_r0 = 32'h00000000; + +parameter gem1__screen_t1_r1 = 32'hE000C504; +parameter val_gem1__screen_t1_r1 = 32'h00000000; +parameter mask_gem1__screen_t1_r1 = 32'h00000000; + +parameter gem1__screen_t1_r2 = 32'hE000C508; +parameter val_gem1__screen_t1_r2 = 32'h00000000; +parameter mask_gem1__screen_t1_r2 = 32'h00000000; + +parameter gem1__screen_t1_r3 = 32'hE000C50C; +parameter val_gem1__screen_t1_r3 = 32'h00000000; +parameter mask_gem1__screen_t1_r3 = 32'h00000000; + +parameter gem1__screen_t1_r4 = 32'hE000C510; +parameter val_gem1__screen_t1_r4 = 32'h00000000; +parameter mask_gem1__screen_t1_r4 = 32'h00000000; + +parameter gem1__screen_t1_r5 = 32'hE000C514; +parameter val_gem1__screen_t1_r5 = 32'h00000000; +parameter mask_gem1__screen_t1_r5 = 32'h00000000; + +parameter gem1__screen_t1_r6 = 32'hE000C518; +parameter val_gem1__screen_t1_r6 = 32'h00000000; +parameter mask_gem1__screen_t1_r6 = 32'h00000000; + +parameter gem1__screen_t1_r7 = 32'hE000C51C; +parameter val_gem1__screen_t1_r7 = 32'h00000000; +parameter mask_gem1__screen_t1_r7 = 32'h00000000; + +parameter gem1__screen_t1_r8 = 32'hE000C520; +parameter val_gem1__screen_t1_r8 = 32'h00000000; +parameter mask_gem1__screen_t1_r8 = 32'h00000000; + +parameter gem1__screen_t1_r9 = 32'hE000C524; +parameter val_gem1__screen_t1_r9 = 32'h00000000; +parameter mask_gem1__screen_t1_r9 = 32'h00000000; + +parameter gem1__screen_t1_r10 = 32'hE000C528; +parameter val_gem1__screen_t1_r10 = 32'h00000000; +parameter mask_gem1__screen_t1_r10 = 32'h00000000; + +parameter gem1__screen_t1_r11 = 32'hE000C52C; +parameter val_gem1__screen_t1_r11 = 32'h00000000; +parameter mask_gem1__screen_t1_r11 = 32'h00000000; + +parameter gem1__screen_t1_r12 = 32'hE000C530; +parameter val_gem1__screen_t1_r12 = 32'h00000000; +parameter mask_gem1__screen_t1_r12 = 32'h00000000; + +parameter gem1__screen_t1_r13 = 32'hE000C534; +parameter val_gem1__screen_t1_r13 = 32'h00000000; +parameter mask_gem1__screen_t1_r13 = 32'h00000000; + +parameter gem1__screen_t1_r14 = 32'hE000C538; +parameter val_gem1__screen_t1_r14 = 32'h00000000; +parameter mask_gem1__screen_t1_r14 = 32'h00000000; + +parameter gem1__screen_t1_r15 = 32'hE000C53C; +parameter val_gem1__screen_t1_r15 = 32'h00000000; +parameter mask_gem1__screen_t1_r15 = 32'h00000000; + +parameter gem1__screen_t2_r0 = 32'hE000C540; +parameter val_gem1__screen_t2_r0 = 32'h00000000; +parameter mask_gem1__screen_t2_r0 = 32'h00000000; + +parameter gem1__screen_t2_r1 = 32'hE000C544; +parameter val_gem1__screen_t2_r1 = 32'h00000000; +parameter mask_gem1__screen_t2_r1 = 32'h00000000; + +parameter gem1__screen_t2_r2 = 32'hE000C548; +parameter val_gem1__screen_t2_r2 = 32'h00000000; +parameter mask_gem1__screen_t2_r2 = 32'h00000000; + +parameter gem1__screen_t2_r3 = 32'hE000C54C; +parameter val_gem1__screen_t2_r3 = 32'h00000000; +parameter mask_gem1__screen_t2_r3 = 32'h00000000; + +parameter gem1__screen_t2_r4 = 32'hE000C550; +parameter val_gem1__screen_t2_r4 = 32'h00000000; +parameter mask_gem1__screen_t2_r4 = 32'h00000000; + +parameter gem1__screen_t2_r5 = 32'hE000C554; +parameter val_gem1__screen_t2_r5 = 32'h00000000; +parameter mask_gem1__screen_t2_r5 = 32'h00000000; + +parameter gem1__screen_t2_r6 = 32'hE000C558; +parameter val_gem1__screen_t2_r6 = 32'h00000000; +parameter mask_gem1__screen_t2_r6 = 32'h00000000; + +parameter gem1__screen_t2_r7 = 32'hE000C55C; +parameter val_gem1__screen_t2_r7 = 32'h00000000; +parameter mask_gem1__screen_t2_r7 = 32'h00000000; + +parameter gem1__screen_t2_r8 = 32'hE000C560; +parameter val_gem1__screen_t2_r8 = 32'h00000000; +parameter mask_gem1__screen_t2_r8 = 32'h00000000; + +parameter gem1__screen_t2_r9 = 32'hE000C564; +parameter val_gem1__screen_t2_r9 = 32'h00000000; +parameter mask_gem1__screen_t2_r9 = 32'h00000000; + +parameter gem1__screen_t2_r10 = 32'hE000C568; +parameter val_gem1__screen_t2_r10 = 32'h00000000; +parameter mask_gem1__screen_t2_r10 = 32'h00000000; + +parameter gem1__screen_t2_r11 = 32'hE000C56C; +parameter val_gem1__screen_t2_r11 = 32'h00000000; +parameter mask_gem1__screen_t2_r11 = 32'h00000000; + +parameter gem1__screen_t2_r12 = 32'hE000C570; +parameter val_gem1__screen_t2_r12 = 32'h00000000; +parameter mask_gem1__screen_t2_r12 = 32'h00000000; + +parameter gem1__screen_t2_r13 = 32'hE000C574; +parameter val_gem1__screen_t2_r13 = 32'h00000000; +parameter mask_gem1__screen_t2_r13 = 32'h00000000; + +parameter gem1__screen_t2_r14 = 32'hE000C578; +parameter val_gem1__screen_t2_r14 = 32'h00000000; +parameter mask_gem1__screen_t2_r14 = 32'h00000000; + +parameter gem1__screen_t2_r15 = 32'hE000C57C; +parameter val_gem1__screen_t2_r15 = 32'h00000000; +parameter mask_gem1__screen_t2_r15 = 32'h00000000; + +parameter gem1__intr_en_pq1 = 32'hE000C600; +parameter val_gem1__intr_en_pq1 = 32'h00000000; +parameter mask_gem1__intr_en_pq1 = 32'h00000000; + +parameter gem1__intr_en_pq2 = 32'hE000C604; +parameter val_gem1__intr_en_pq2 = 32'h00000000; +parameter mask_gem1__intr_en_pq2 = 32'h00000000; + +parameter gem1__intr_en_pq3 = 32'hE000C608; +parameter val_gem1__intr_en_pq3 = 32'h00000000; +parameter mask_gem1__intr_en_pq3 = 32'h00000000; + +parameter gem1__intr_en_pq4 = 32'hE000C60C; +parameter val_gem1__intr_en_pq4 = 32'h00000000; +parameter mask_gem1__intr_en_pq4 = 32'h00000000; + +parameter gem1__intr_en_pq5 = 32'hE000C610; +parameter val_gem1__intr_en_pq5 = 32'h00000000; +parameter mask_gem1__intr_en_pq5 = 32'h00000000; + +parameter gem1__intr_en_pq6 = 32'hE000C614; +parameter val_gem1__intr_en_pq6 = 32'h00000000; +parameter mask_gem1__intr_en_pq6 = 32'h00000000; + +parameter gem1__intr_en_pq7 = 32'hE000C618; +parameter val_gem1__intr_en_pq7 = 32'h00000000; +parameter mask_gem1__intr_en_pq7 = 32'h00000000; + +parameter gem1__intr_dis_pq1 = 32'hE000C620; +parameter val_gem1__intr_dis_pq1 = 32'h00000000; +parameter mask_gem1__intr_dis_pq1 = 32'h00000000; + +parameter gem1__intr_dis_pq2 = 32'hE000C624; +parameter val_gem1__intr_dis_pq2 = 32'h00000000; +parameter mask_gem1__intr_dis_pq2 = 32'h00000000; + +parameter gem1__intr_dis_pq3 = 32'hE000C628; +parameter val_gem1__intr_dis_pq3 = 32'h00000000; +parameter mask_gem1__intr_dis_pq3 = 32'h00000000; + +parameter gem1__intr_dis_pq4 = 32'hE000C62C; +parameter val_gem1__intr_dis_pq4 = 32'h00000000; +parameter mask_gem1__intr_dis_pq4 = 32'h00000000; + +parameter gem1__intr_dis_pq5 = 32'hE000C630; +parameter val_gem1__intr_dis_pq5 = 32'h00000000; +parameter mask_gem1__intr_dis_pq5 = 32'h00000000; + +parameter gem1__intr_dis_pq6 = 32'hE000C634; +parameter val_gem1__intr_dis_pq6 = 32'h00000000; +parameter mask_gem1__intr_dis_pq6 = 32'h00000000; + +parameter gem1__intr_dis_pq7 = 32'hE000C638; +parameter val_gem1__intr_dis_pq7 = 32'h00000000; +parameter mask_gem1__intr_dis_pq7 = 32'h00000000; + +parameter gem1__intr_mask_pq1 = 32'hE000C640; +parameter val_gem1__intr_mask_pq1 = 32'h00000000; +parameter mask_gem1__intr_mask_pq1 = 32'h00000000; + +parameter gem1__intr_mask_pq2 = 32'hE000C644; +parameter val_gem1__intr_mask_pq2 = 32'h00000000; +parameter mask_gem1__intr_mask_pq2 = 32'h00000000; + +parameter gem1__intr_mask_pq3 = 32'hE000C648; +parameter val_gem1__intr_mask_pq3 = 32'h00000000; +parameter mask_gem1__intr_mask_pq3 = 32'h00000000; + +parameter gem1__intr_mask_pq4 = 32'hE000C64C; +parameter val_gem1__intr_mask_pq4 = 32'h00000000; +parameter mask_gem1__intr_mask_pq4 = 32'h00000000; + +parameter gem1__intr_mask_pq5 = 32'hE000C650; +parameter val_gem1__intr_mask_pq5 = 32'h00000000; +parameter mask_gem1__intr_mask_pq5 = 32'h00000000; + +parameter gem1__intr_mask_pq6 = 32'hE000C654; +parameter val_gem1__intr_mask_pq6 = 32'h00000000; +parameter mask_gem1__intr_mask_pq6 = 32'h00000000; + +parameter gem1__intr_mask_pq7 = 32'hE000C658; +parameter val_gem1__intr_mask_pq7 = 32'h00000000; +parameter mask_gem1__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpio__MASK_DATA_0_LSW = 32'hE000A000; +parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_0_MSW = 32'hE000A004; +parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_LSW = 32'hE000A008; +parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C; +parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0; + +parameter gpio__MASK_DATA_2_LSW = 32'hE000A010; +parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_2_MSW = 32'hE000A014; +parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_LSW = 32'hE000A018; +parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C; +parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF; + +parameter gpio__DATA_0 = 32'hE000A040; +parameter val_gpio__DATA_0 = 32'h00000000; +parameter mask_gpio__DATA_0 = 32'h00000000; + +parameter gpio__DATA_1 = 32'hE000A044; +parameter val_gpio__DATA_1 = 32'h00000000; +parameter mask_gpio__DATA_1 = 32'h00000000; + +parameter gpio__DATA_2 = 32'hE000A048; +parameter val_gpio__DATA_2 = 32'h00000000; +parameter mask_gpio__DATA_2 = 32'hFFFFFFFF; + +parameter gpio__DATA_3 = 32'hE000A04C; +parameter val_gpio__DATA_3 = 32'h00000000; +parameter mask_gpio__DATA_3 = 32'hFFFFFFFF; + +parameter gpio__DATA_0_RO = 32'hE000A060; +parameter val_gpio__DATA_0_RO = 32'h00000000; +parameter mask_gpio__DATA_0_RO = 32'h00000000; + +parameter gpio__DATA_1_RO = 32'hE000A064; +parameter val_gpio__DATA_1_RO = 32'h00000000; +parameter mask_gpio__DATA_1_RO = 32'h00000000; + +parameter gpio__DATA_2_RO = 32'hE000A068; +parameter val_gpio__DATA_2_RO = 32'h00000000; +parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF; + +parameter gpio__DATA_3_RO = 32'hE000A06C; +parameter val_gpio__DATA_3_RO = 32'h00000000; +parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF; + +parameter gpio__BYPM_0 = 32'hE000A200; +parameter val_gpio__BYPM_0 = 32'h00000000; +parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF; + +parameter gpio__DIRM_0 = 32'hE000A204; +parameter val_gpio__DIRM_0 = 32'h00000000; +parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF; + +parameter gpio__OEN_0 = 32'hE000A208; +parameter val_gpio__OEN_0 = 32'h00000000; +parameter mask_gpio__OEN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_0 = 32'hE000A20C; +parameter val_gpio__INT_MASK_0 = 32'h00000000; +parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_0 = 32'hE000A210; +parameter val_gpio__INT_EN_0 = 32'h00000000; +parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_0 = 32'hE000A214; +parameter val_gpio__INT_DIS_0 = 32'h00000000; +parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_0 = 32'hE000A218; +parameter val_gpio__INT_STAT_0 = 32'h00000000; +parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_0 = 32'hE000A21C; +parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_0 = 32'hE000A220; +parameter val_gpio__INT_POLARITY_0 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_0 = 32'hE000A224; +parameter val_gpio__INT_ANY_0 = 32'h00000000; +parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF; + +parameter gpio__BYPM_1 = 32'hE000A240; +parameter val_gpio__BYPM_1 = 32'h00000000; +parameter mask_gpio__BYPM_1 = 32'h003FFFFF; + +parameter gpio__DIRM_1 = 32'hE000A244; +parameter val_gpio__DIRM_1 = 32'h00000000; +parameter mask_gpio__DIRM_1 = 32'h003FFFFF; + +parameter gpio__OEN_1 = 32'hE000A248; +parameter val_gpio__OEN_1 = 32'h00000000; +parameter mask_gpio__OEN_1 = 32'h003FFFFF; + +parameter gpio__INT_MASK_1 = 32'hE000A24C; +parameter val_gpio__INT_MASK_1 = 32'h00000000; +parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF; + +parameter gpio__INT_EN_1 = 32'hE000A250; +parameter val_gpio__INT_EN_1 = 32'h00000000; +parameter mask_gpio__INT_EN_1 = 32'h003FFFFF; + +parameter gpio__INT_DIS_1 = 32'hE000A254; +parameter val_gpio__INT_DIS_1 = 32'h00000000; +parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF; + +parameter gpio__INT_STAT_1 = 32'hE000A258; +parameter val_gpio__INT_STAT_1 = 32'h00000000; +parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF; + +parameter gpio__INT_TYPE_1 = 32'hE000A25C; +parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF; +parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF; + +parameter gpio__INT_POLARITY_1 = 32'hE000A260; +parameter val_gpio__INT_POLARITY_1 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF; + +parameter gpio__INT_ANY_1 = 32'hE000A264; +parameter val_gpio__INT_ANY_1 = 32'h00000000; +parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF; + +parameter gpio__BYPM_2 = 32'hE000A280; +parameter val_gpio__BYPM_2 = 32'h00000000; +parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF; + +parameter gpio__DIRM_2 = 32'hE000A284; +parameter val_gpio__DIRM_2 = 32'h00000000; +parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF; + +parameter gpio__OEN_2 = 32'hE000A288; +parameter val_gpio__OEN_2 = 32'h00000000; +parameter mask_gpio__OEN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_2 = 32'hE000A28C; +parameter val_gpio__INT_MASK_2 = 32'h00000000; +parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_2 = 32'hE000A290; +parameter val_gpio__INT_EN_2 = 32'h00000000; +parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_2 = 32'hE000A294; +parameter val_gpio__INT_DIS_2 = 32'h00000000; +parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_2 = 32'hE000A298; +parameter val_gpio__INT_STAT_2 = 32'h00000000; +parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_2 = 32'hE000A29C; +parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_2 = 32'hE000A2A0; +parameter val_gpio__INT_POLARITY_2 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_2 = 32'hE000A2A4; +parameter val_gpio__INT_ANY_2 = 32'h00000000; +parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF; + +parameter gpio__BYPM_3 = 32'hE000A2C0; +parameter val_gpio__BYPM_3 = 32'h00000000; +parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF; + +parameter gpio__DIRM_3 = 32'hE000A2C4; +parameter val_gpio__DIRM_3 = 32'h00000000; +parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF; + +parameter gpio__OEN_3 = 32'hE000A2C8; +parameter val_gpio__OEN_3 = 32'h00000000; +parameter mask_gpio__OEN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_3 = 32'hE000A2CC; +parameter val_gpio__INT_MASK_3 = 32'h00000000; +parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_3 = 32'hE000A2D0; +parameter val_gpio__INT_EN_3 = 32'h00000000; +parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_3 = 32'hE000A2D4; +parameter val_gpio__INT_DIS_3 = 32'h00000000; +parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_3 = 32'hE000A2D8; +parameter val_gpio__INT_STAT_3 = 32'h00000000; +parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_3 = 32'hE000A2DC; +parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_3 = 32'hE000A2E0; +parameter val_gpio__INT_POLARITY_3 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_3 = 32'hE000A2E4; +parameter val_gpio__INT_ANY_3 = 32'h00000000; +parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_iou_switch__Remap = 32'hE0200000; +parameter val_gpv_iou_switch__Remap = 32'h00000000; +parameter mask_gpv_iou_switch__Remap = 32'h000000FF; + +parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008; +parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001; + +parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C; +parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001; + +parameter gpv_iou_switch__security4_qspi = 32'hE0200010; +parameter val_gpv_iou_switch__security4_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001; + +parameter gpv_iou_switch__security5_miou = 32'hE0200014; +parameter val_gpv_iou_switch__security5_miou = 32'h00000000; +parameter mask_gpv_iou_switch__security5_miou = 32'h00000001; + +parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018; +parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000; +parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF; + +parameter gpv_iou_switch__security7_smc = 32'hE020001C; +parameter val_gpv_iou_switch__security7_smc = 32'h00000000; +parameter mask_gpv_iou_switch__security7_smc = 32'h00000001; + +parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0; +parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004; +parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4; +parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8; +parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC; +parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0; +parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001; +parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4; +parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3; +parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8; +parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B; +parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC; +parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF; + +parameter gpv_iou_switch__component_id0 = 32'hE0201FF0; +parameter val_gpv_iou_switch__component_id0 = 32'h0000000D; +parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF; + +parameter gpv_iou_switch__component_id1 = 32'hE0201FF4; +parameter val_gpv_iou_switch__component_id1 = 32'h000000F0; +parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF; + +parameter gpv_iou_switch__component_id2 = 32'hE0201FF8; +parameter val_gpv_iou_switch__component_id2 = 32'h00000005; +parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF; + +parameter gpv_iou_switch__component_id3 = 32'hE0201FFC; +parameter val_gpv_iou_switch__component_id3 = 32'h000000B1; +parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044; +parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044; +parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100; +parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104; +parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108; +parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100; +parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104; +parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108; +parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100; +parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104; +parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108; +parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100; +parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104; +parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108; +parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100; +parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104; +parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100; +parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104; +parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108; +parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003; + + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C; +parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_cpu__max_ot = 32'hF8946110; +parameter val_gpv_qos301_cpu__max_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114; +parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_cpu__aw_p = 32'hF8946118; +parameter val_gpv_qos301_cpu__aw_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000; + +parameter gpv_qos301_cpu__aw_b = 32'hF894611C; +parameter val_gpv_qos301_cpu__aw_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__aw_r = 32'hF8946120; +parameter val_gpv_qos301_cpu__aw_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000; + +parameter gpv_qos301_cpu__ar_p = 32'hF8946124; +parameter val_gpv_qos301_cpu__ar_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000; + +parameter gpv_qos301_cpu__ar_b = 32'hF8946128; +parameter val_gpv_qos301_cpu__ar_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__ar_r = 32'hF894612C; +parameter val_gpv_qos301_cpu__ar_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C; +parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_dmac__max_ot = 32'hF8947110; +parameter val_gpv_qos301_dmac__max_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114; +parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_dmac__aw_p = 32'hF8947118; +parameter val_gpv_qos301_dmac__aw_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000; + +parameter gpv_qos301_dmac__aw_b = 32'hF894711C; +parameter val_gpv_qos301_dmac__aw_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__aw_r = 32'hF8947120; +parameter val_gpv_qos301_dmac__aw_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000; + +parameter gpv_qos301_dmac__ar_p = 32'hF8947124; +parameter val_gpv_qos301_dmac__ar_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000; + +parameter gpv_qos301_dmac__ar_b = 32'hF8947128; +parameter val_gpv_qos301_dmac__ar_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__ar_r = 32'hF894712C; +parameter val_gpv_qos301_dmac__ar_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_iou__qos_cntl = 32'hF894810C; +parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_iou__max_ot = 32'hF8948110; +parameter val_gpv_qos301_iou__max_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114; +parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_iou__aw_p = 32'hF8948118; +parameter val_gpv_qos301_iou__aw_p = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000; + +parameter gpv_qos301_iou__aw_b = 32'hF894811C; +parameter val_gpv_qos301_iou__aw_b = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__aw_r = 32'hF8948120; +parameter val_gpv_qos301_iou__aw_r = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000; + +parameter gpv_qos301_iou__ar_p = 32'hF8948124; +parameter val_gpv_qos301_iou__ar_p = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000; + +parameter gpv_qos301_iou__ar_b = 32'hF8948128; +parameter val_gpv_qos301_iou__ar_b = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__ar_r = 32'hF894812C; +parameter val_gpv_qos301_iou__ar_r = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_trustzone__Remap = 32'hF8900000; +parameter val_gpv_trustzone__Remap = 32'h00000000; +parameter mask_gpv_trustzone__Remap = 32'h000000C0; + +parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C; +parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001; + +parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020; +parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001; + +parameter gpv_trustzone__security_apb = 32'hF8900028; +parameter val_gpv_trustzone__security_apb = 32'h00000000; +parameter mask_gpv_trustzone__security_apb = 32'h0000003F; + + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c0__Control_reg0 = 32'hE0004000; +parameter val_i2c0__Control_reg0 = 32'h00000000; +parameter mask_i2c0__Control_reg0 = 32'h0000FFFF; + +parameter i2c0__Status_reg0 = 32'hE0004004; +parameter val_i2c0__Status_reg0 = 32'h00000000; +parameter mask_i2c0__Status_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_address_reg0 = 32'hE0004008; +parameter val_i2c0__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_data_reg0 = 32'hE000400C; +parameter val_i2c0__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c0__Interrupt_status_reg0 = 32'hE0004010; +parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c0__Transfer_size_reg0 = 32'hE0004014; +parameter val_i2c0__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018; +parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c0__Time_out_reg0 = 32'hE000401C; +parameter val_i2c0__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c0__Time_out_reg0 = 32'h000000FF; + +parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020; +parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024; +parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028; +parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c1__Control_reg0 = 32'hE0005000; +parameter val_i2c1__Control_reg0 = 32'h00000000; +parameter mask_i2c1__Control_reg0 = 32'h0000FFFF; + +parameter i2c1__Status_reg0 = 32'hE0005004; +parameter val_i2c1__Status_reg0 = 32'h00000000; +parameter mask_i2c1__Status_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_address_reg0 = 32'hE0005008; +parameter val_i2c1__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_data_reg0 = 32'hE000500C; +parameter val_i2c1__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c1__Interrupt_status_reg0 = 32'hE0005010; +parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c1__Transfer_size_reg0 = 32'hE0005014; +parameter val_i2c1__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018; +parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c1__Time_out_reg0 = 32'hE000501C; +parameter val_i2c1__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c1__Time_out_reg0 = 32'h000000FF; + +parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020; +parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024; +parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028; +parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter l2cache__reg0_cache_id = 32'hF8F02000; +parameter val_l2cache__reg0_cache_id = 32'h410000C8; +parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF; + +parameter l2cache__reg0_cache_type = 32'hF8F02004; +parameter val_l2cache__reg0_cache_type = 32'h9E300300; +parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF; + +parameter l2cache__reg1_control = 32'hF8F02100; +parameter val_l2cache__reg1_control = 32'h00000000; +parameter mask_l2cache__reg1_control = 32'h7FFFFFFF; + +parameter l2cache__reg1_aux_control = 32'hF8F02104; +parameter val_l2cache__reg1_aux_control = 32'h02050000; +parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_tag_ram_control = 32'hF8F02108; +parameter val_l2cache__reg1_tag_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_data_ram_control = 32'hF8F0210C; +parameter val_l2cache__reg1_data_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200; +parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204; +parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208; +parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C; +parameter val_l2cache__reg2_ev_counter1 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0 = 32'hF8F02210; +parameter val_l2cache__reg2_ev_counter0 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask = 32'hF8F02214; +parameter val_l2cache__reg2_int_mask = 32'h00000000; +parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask_status = 32'hF8F02218; +parameter val_l2cache__reg2_int_mask_status = 32'h00000000; +parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_raw_status = 32'hF8F0221C; +parameter val_l2cache__reg2_int_raw_status = 32'h00000000; +parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_clear = 32'hF8F02220; +parameter val_l2cache__reg2_int_clear = 32'h00000000; +parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF; + +parameter l2cache__reg7_cache_sync = 32'hF8F02730; +parameter val_l2cache__reg7_cache_sync = 32'h00000000; +parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_pa = 32'hF8F02770; +parameter val_l2cache__reg7_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_way = 32'hF8F0277C; +parameter val_l2cache__reg7_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_pa = 32'hF8F027B0; +parameter val_l2cache__reg7_clean_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_index = 32'hF8F027B8; +parameter val_l2cache__reg7_clean_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_way = 32'hF8F027BC; +parameter val_l2cache__reg7_clean_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0; +parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8; +parameter val_l2cache__reg7_clean_inv_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC; +parameter val_l2cache__reg7_clean_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900; +parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904; +parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908; +parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C; +parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910; +parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914; +parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918; +parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C; +parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920; +parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924; +parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928; +parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C; +parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930; +parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934; +parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938; +parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C; +parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_lock_line_en = 32'hF8F02950; +parameter val_l2cache__reg9_lock_line_en = 32'h00000000; +parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF; + +parameter l2cache__reg9_unlock_way = 32'hF8F02954; +parameter val_l2cache__reg9_unlock_way = 32'h00000000; +parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00; +parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001; +parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04; +parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000; +parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF; + +parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40; +parameter val_l2cache__reg15_debug_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60; +parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_power_ctrl = 32'hF8F02F80; +parameter val_l2cache__reg15_power_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF; + + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000; +parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002; +parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004; +parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501; +parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008; +parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000; +parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C; +parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000; +parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF; + +parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040; +parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000; +parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044; +parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000; +parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050; +parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F; +parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF; + +parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054; +parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000; +parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__ICCICR = 32'hF8F00100; +parameter val_mpcore__ICCICR = 32'h00000000; +parameter mask_mpcore__ICCICR = 32'hFFFFFFFF; + +parameter mpcore__ICCPMR = 32'hF8F00104; +parameter val_mpcore__ICCPMR = 32'h00000000; +parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF; + +parameter mpcore__ICCBPR = 32'hF8F00108; +parameter val_mpcore__ICCBPR = 32'h00000002; +parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIAR = 32'hF8F0010C; +parameter val_mpcore__ICCIAR = 32'h000003FF; +parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF; + +parameter mpcore__ICCEOIR = 32'hF8F00110; +parameter val_mpcore__ICCEOIR = 32'h00000000; +parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF; + +parameter mpcore__ICCRPR = 32'hF8F00114; +parameter val_mpcore__ICCRPR = 32'h000000FF; +parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF; + +parameter mpcore__ICCHPIR = 32'hF8F00118; +parameter val_mpcore__ICCHPIR = 32'h000003FF; +parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF; + +parameter mpcore__ICCABPR = 32'hF8F0011C; +parameter val_mpcore__ICCABPR = 32'h00000003; +parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR = 32'hF8F001FC; +parameter val_mpcore__ICCIDR = 32'h3901243B; +parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200; +parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204; +parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208; +parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C; +parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210; +parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214; +parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Auto_increment_Register = 32'hF8F00218; +parameter val_mpcore__Auto_increment_Register = 32'h00000000; +parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600; +parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604; +parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608; +parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C; +parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Load_Register = 32'hF8F00620; +parameter val_mpcore__Watchdog_Load_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624; +parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Control_Register = 32'hF8F00628; +parameter val_mpcore__Watchdog_Control_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C; +parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630; +parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634; +parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF; + +parameter mpcore__ICDDCR = 32'hF8F01000; +parameter val_mpcore__ICDDCR = 32'h00000000; +parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF; + +parameter mpcore__ICDICTR = 32'hF8F01004; +parameter val_mpcore__ICDICTR = 32'h00000C22; +parameter mask_mpcore__ICDICTR = 32'hE000FFFF; + +parameter mpcore__ICDIIDR = 32'hF8F01008; +parameter val_mpcore__ICDIIDR = 32'h0102043B; +parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF; + +parameter mpcore__ICDISR0 = 32'hF8F01080; +parameter val_mpcore__ICDISR0 = 32'h00000000; +parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR1 = 32'hF8F01084; +parameter val_mpcore__ICDISR1 = 32'h00000000; +parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR2 = 32'hF8F01088; +parameter val_mpcore__ICDISR2 = 32'h00000000; +parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER0 = 32'hF8F01100; +parameter val_mpcore__ICDISER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER1 = 32'hF8F01104; +parameter val_mpcore__ICDISER1 = 32'h00000000; +parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER2 = 32'hF8F01108; +parameter val_mpcore__ICDISER2 = 32'h00000000; +parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER0 = 32'hF8F01180; +parameter val_mpcore__ICDICER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER1 = 32'hF8F01184; +parameter val_mpcore__ICDICER1 = 32'h00000000; +parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER2 = 32'hF8F01188; +parameter val_mpcore__ICDICER2 = 32'h00000000; +parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR0 = 32'hF8F01200; +parameter val_mpcore__ICDISPR0 = 32'h00000000; +parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR1 = 32'hF8F01204; +parameter val_mpcore__ICDISPR1 = 32'h00000000; +parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR2 = 32'hF8F01208; +parameter val_mpcore__ICDISPR2 = 32'h00000000; +parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR0 = 32'hF8F01280; +parameter val_mpcore__ICDICPR0 = 32'h00000000; +parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR1 = 32'hF8F01284; +parameter val_mpcore__ICDICPR1 = 32'h00000000; +parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR2 = 32'hF8F01288; +parameter val_mpcore__ICDICPR2 = 32'h00000000; +parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR0 = 32'hF8F01300; +parameter val_mpcore__ICDABR0 = 32'h00000000; +parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR1 = 32'hF8F01304; +parameter val_mpcore__ICDABR1 = 32'h00000000; +parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR2 = 32'hF8F01308; +parameter val_mpcore__ICDABR2 = 32'h00000000; +parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR0 = 32'hF8F01400; +parameter val_mpcore__ICDIPR0 = 32'h00000000; +parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR1 = 32'hF8F01404; +parameter val_mpcore__ICDIPR1 = 32'h00000000; +parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR2 = 32'hF8F01408; +parameter val_mpcore__ICDIPR2 = 32'h00000000; +parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR3 = 32'hF8F0140C; +parameter val_mpcore__ICDIPR3 = 32'h00000000; +parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR4 = 32'hF8F01410; +parameter val_mpcore__ICDIPR4 = 32'h00000000; +parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR5 = 32'hF8F01414; +parameter val_mpcore__ICDIPR5 = 32'h00000000; +parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR6 = 32'hF8F01418; +parameter val_mpcore__ICDIPR6 = 32'h00000000; +parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR7 = 32'hF8F0141C; +parameter val_mpcore__ICDIPR7 = 32'h00000000; +parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR8 = 32'hF8F01420; +parameter val_mpcore__ICDIPR8 = 32'h00000000; +parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR9 = 32'hF8F01424; +parameter val_mpcore__ICDIPR9 = 32'h00000000; +parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR10 = 32'hF8F01428; +parameter val_mpcore__ICDIPR10 = 32'h00000000; +parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR11 = 32'hF8F0142C; +parameter val_mpcore__ICDIPR11 = 32'h00000000; +parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR12 = 32'hF8F01430; +parameter val_mpcore__ICDIPR12 = 32'h00000000; +parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR13 = 32'hF8F01434; +parameter val_mpcore__ICDIPR13 = 32'h00000000; +parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR14 = 32'hF8F01438; +parameter val_mpcore__ICDIPR14 = 32'h00000000; +parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR15 = 32'hF8F0143C; +parameter val_mpcore__ICDIPR15 = 32'h00000000; +parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR16 = 32'hF8F01440; +parameter val_mpcore__ICDIPR16 = 32'h00000000; +parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR17 = 32'hF8F01444; +parameter val_mpcore__ICDIPR17 = 32'h00000000; +parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR18 = 32'hF8F01448; +parameter val_mpcore__ICDIPR18 = 32'h00000000; +parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR19 = 32'hF8F0144C; +parameter val_mpcore__ICDIPR19 = 32'h00000000; +parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR20 = 32'hF8F01450; +parameter val_mpcore__ICDIPR20 = 32'h00000000; +parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR21 = 32'hF8F01454; +parameter val_mpcore__ICDIPR21 = 32'h00000000; +parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR22 = 32'hF8F01458; +parameter val_mpcore__ICDIPR22 = 32'h00000000; +parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR23 = 32'hF8F0145C; +parameter val_mpcore__ICDIPR23 = 32'h00000000; +parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR0 = 32'hF8F01800; +parameter val_mpcore__ICDIPTR0 = 32'h01010101; +parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR1 = 32'hF8F01804; +parameter val_mpcore__ICDIPTR1 = 32'h01010101; +parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR2 = 32'hF8F01808; +parameter val_mpcore__ICDIPTR2 = 32'h01010101; +parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR3 = 32'hF8F0180C; +parameter val_mpcore__ICDIPTR3 = 32'h01010101; +parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR4 = 32'hF8F01810; +parameter val_mpcore__ICDIPTR4 = 32'h01010101; +parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR5 = 32'hF8F01814; +parameter val_mpcore__ICDIPTR5 = 32'h01010101; +parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR6 = 32'hF8F01818; +parameter val_mpcore__ICDIPTR6 = 32'h01010101; +parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR7 = 32'hF8F0181C; +parameter val_mpcore__ICDIPTR7 = 32'h01010101; +parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR8 = 32'hF8F01820; +parameter val_mpcore__ICDIPTR8 = 32'h01010101; +parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR9 = 32'hF8F01824; +parameter val_mpcore__ICDIPTR9 = 32'h01010101; +parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR10 = 32'hF8F01828; +parameter val_mpcore__ICDIPTR10 = 32'h01010101; +parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR11 = 32'hF8F0182C; +parameter val_mpcore__ICDIPTR11 = 32'h01010101; +parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR12 = 32'hF8F01830; +parameter val_mpcore__ICDIPTR12 = 32'h01010101; +parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR13 = 32'hF8F01834; +parameter val_mpcore__ICDIPTR13 = 32'h01010101; +parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR14 = 32'hF8F01838; +parameter val_mpcore__ICDIPTR14 = 32'h01010101; +parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR15 = 32'hF8F0183C; +parameter val_mpcore__ICDIPTR15 = 32'h01010101; +parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR16 = 32'hF8F01840; +parameter val_mpcore__ICDIPTR16 = 32'h01010101; +parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR17 = 32'hF8F01844; +parameter val_mpcore__ICDIPTR17 = 32'h01010101; +parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR18 = 32'hF8F01848; +parameter val_mpcore__ICDIPTR18 = 32'h01010101; +parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR19 = 32'hF8F0184C; +parameter val_mpcore__ICDIPTR19 = 32'h01010101; +parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR20 = 32'hF8F01850; +parameter val_mpcore__ICDIPTR20 = 32'h01010101; +parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR21 = 32'hF8F01854; +parameter val_mpcore__ICDIPTR21 = 32'h01010101; +parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR22 = 32'hF8F01858; +parameter val_mpcore__ICDIPTR22 = 32'h01010101; +parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR23 = 32'hF8F0185C; +parameter val_mpcore__ICDIPTR23 = 32'h01010101; +parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR0 = 32'hF8F01C00; +parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA; +parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR1 = 32'hF8F01C04; +parameter val_mpcore__ICDICFR1 = 32'h7DC00000; +parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR2 = 32'hF8F01C08; +parameter val_mpcore__ICDICFR2 = 32'h55555555; +parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR3 = 32'hF8F01C0C; +parameter val_mpcore__ICDICFR3 = 32'h55555555; +parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR4 = 32'hF8F01C10; +parameter val_mpcore__ICDICFR4 = 32'h55555555; +parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR5 = 32'hF8F01C14; +parameter val_mpcore__ICDICFR5 = 32'h55555555; +parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF; + +parameter mpcore__ppi_status = 32'hF8F01D00; +parameter val_mpcore__ppi_status = 32'h00000000; +parameter mask_mpcore__ppi_status = 32'hFFFFFFFF; + +parameter mpcore__spi_status_0 = 32'hF8F01D04; +parameter val_mpcore__spi_status_0 = 32'h00000000; +parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF; + +parameter mpcore__spi_status_1 = 32'hF8F01D08; +parameter val_mpcore__spi_status_1 = 32'h00000000; +parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF; + +parameter mpcore__ICDSGIR = 32'hF8F01F00; +parameter val_mpcore__ICDSGIR = 32'h00000000; +parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR4 = 32'hF8F01FD0; +parameter val_mpcore__ICPIDR4 = 32'h00000004; +parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR5 = 32'hF8F01FD4; +parameter val_mpcore__ICPIDR5 = 32'h00000000; +parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR6 = 32'hF8F01FD8; +parameter val_mpcore__ICPIDR6 = 32'h00000000; +parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR7 = 32'hF8F01FDC; +parameter val_mpcore__ICPIDR7 = 32'h00000000; +parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR0 = 32'hF8F01FE0; +parameter val_mpcore__ICPIDR0 = 32'h00000090; +parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR1 = 32'hF8F01FE4; +parameter val_mpcore__ICPIDR1 = 32'h000000B3; +parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR2 = 32'hF8F01FE8; +parameter val_mpcore__ICPIDR2 = 32'h0000001B; +parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR3 = 32'hF8F01FEC; +parameter val_mpcore__ICPIDR3 = 32'h00000000; +parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR0 = 32'hF8F01FF0; +parameter val_mpcore__ICCIDR0 = 32'h0000000D; +parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR1 = 32'hF8F01FF4; +parameter val_mpcore__ICCIDR1 = 32'h000000F0; +parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR2 = 32'hF8F01FF8; +parameter val_mpcore__ICCIDR2 = 32'h00000005; +parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR3 = 32'hF8F01FFC; +parameter val_mpcore__ICCIDR3 = 32'h000000B1; +parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ocm__OCM_PARITY_CTRL = 32'hF800C000; +parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000; +parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF; + +parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004; +parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000; +parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF; + +parameter ocm__OCM_IRQ_STS = 32'hF800C008; +parameter val_ocm__OCM_IRQ_STS = 32'h00000000; +parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF; + +parameter ocm__OCM_CONTROL = 32'hF800C00C; +parameter val_ocm__OCM_CONTROL = 32'h00000000; +parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter qspi__Config_reg = 32'hE000D000; +parameter val_qspi__Config_reg = 32'h80000000; +parameter mask_qspi__Config_reg = 32'hFFFDFFFF; + +parameter qspi__Intr_status_REG = 32'hE000D004; +parameter val_qspi__Intr_status_REG = 32'h00000004; +parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_en_REG = 32'hE000D008; +parameter val_qspi__Intrpt_en_REG = 32'h00000000; +parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_dis_REG = 32'hE000D00C; +parameter val_qspi__Intrpt_dis_REG = 32'h00000000; +parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_mask_REG = 32'hE000D010; +parameter val_qspi__Intrpt_mask_REG = 32'h00000000; +parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF; + +parameter qspi__En_REG = 32'hE000D014; +parameter val_qspi__En_REG = 32'h00000000; +parameter mask_qspi__En_REG = 32'hFFFFFFFF; + +parameter qspi__Delay_REG = 32'hE000D018; +parameter val_qspi__Delay_REG = 32'h00000000; +parameter mask_qspi__Delay_REG = 32'hFFFFFFFF; + +parameter qspi__TXD0 = 32'hE000D01C; +parameter val_qspi__TXD0 = 32'h00000000; +parameter mask_qspi__TXD0 = 32'hFFFFFFFF; + +parameter qspi__Rx_data_REG = 32'hE000D020; +parameter val_qspi__Rx_data_REG = 32'h00000000; +parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF; + +parameter qspi__Slave_Idle_count_REG = 32'hE000D024; +parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF; +parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF; + +parameter qspi__TX_thres_REG = 32'hE000D028; +parameter val_qspi__TX_thres_REG = 32'h00000001; +parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__RX_thres_REG = 32'hE000D02C; +parameter val_qspi__RX_thres_REG = 32'h00000001; +parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__GPIO = 32'hE000D030; +parameter val_qspi__GPIO = 32'h00000001; +parameter mask_qspi__GPIO = 32'hFFFFFFFF; + +parameter qspi__LPBK_DLY_ADJ = 32'hE000D038; +parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033; +parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF; + +parameter qspi__TXD1 = 32'hE000D080; +parameter val_qspi__TXD1 = 32'h00000000; +parameter mask_qspi__TXD1 = 32'hFFFFFFFF; + +parameter qspi__TXD2 = 32'hE000D084; +parameter val_qspi__TXD2 = 32'h00000000; +parameter mask_qspi__TXD2 = 32'hFFFFFFFF; + +parameter qspi__TXD3 = 32'hE000D088; +parameter val_qspi__TXD3 = 32'h00000000; +parameter mask_qspi__TXD3 = 32'hFFFFFFFF; + +parameter qspi__LQSPI_CFG = 32'hE000D0A0; +parameter val_qspi__LQSPI_CFG = 32'h03A002EB; +parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF; + +parameter qspi__LQSPI_STS = 32'hE000D0A4; +parameter val_qspi__LQSPI_STS = 32'h00000000; +parameter mask_qspi__LQSPI_STS = 32'h000001FF; + +parameter qspi__MOD_ID = 32'hE000D0FC; +parameter val_qspi__MOD_ID = 32'h01090101; +parameter mask_qspi__MOD_ID = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd0__SDMA_system_address_register = 32'hE0100000; +parameter val_sd0__SDMA_system_address_register = 32'h00000000; +parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd0__Block_Size_Block_Count = 32'hE0100004; +parameter val_sd0__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd0__Argument = 32'hE0100008; +parameter val_sd0__Argument = 32'h00000000; +parameter mask_sd0__Argument = 32'hFFFFFFFF; + +parameter sd0__Transfer_Mode_Command = 32'hE010000C; +parameter val_sd0__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd0__Response0 = 32'hE0100010; +parameter val_sd0__Response0 = 32'h00000000; +parameter mask_sd0__Response0 = 32'hFFFFFFFF; + +parameter sd0__Response1 = 32'hE0100014; +parameter val_sd0__Response1 = 32'h00000000; +parameter mask_sd0__Response1 = 32'hFFFFFFFF; + +parameter sd0__Response2 = 32'hE0100018; +parameter val_sd0__Response2 = 32'h00000000; +parameter mask_sd0__Response2 = 32'hFFFFFFFF; + +parameter sd0__Response3 = 32'hE010001C; +parameter val_sd0__Response3 = 32'h00000000; +parameter mask_sd0__Response3 = 32'hFFFFFFFF; + +parameter sd0__Buffer_Data_Port = 32'hE0100020; +parameter val_sd0__Buffer_Data_Port = 32'h00000000; +parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd0__Present_State = 32'hE0100024; +parameter val_sd0__Present_State = 32'h01F20000; +parameter mask_sd0__Present_State = 32'h01FFFFFF; + +parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028; +parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C; +parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030; +parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034; +parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038; +parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd0__Auto_CMD12_error_status = 32'hE010003C; +parameter val_sd0__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd0__Capabilities = 32'hE0100040; +parameter val_sd0__Capabilities = 32'h69EC0080; +parameter mask_sd0__Capabilities = 32'h7FFFFFFF; + +parameter sd0__Maximum_current_capabilities = 32'hE0100048; +parameter val_sd0__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050; +parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd0__ADMA_error_status = 32'hE0100054; +parameter val_sd0__ADMA_error_status = 32'h00000000; +parameter mask_sd0__ADMA_error_status = 32'h00000007; + +parameter sd0__ADMA_system_address = 32'hE0100058; +parameter val_sd0__ADMA_system_address = 32'h00000000; +parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd0__Boot_Timeout_control = 32'hE0100060; +parameter val_sd0__Boot_Timeout_control = 32'h00000000; +parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd0__Debug_Selection = 32'hE0100064; +parameter val_sd0__Debug_Selection = 32'h00000000; +parameter mask_sd0__Debug_Selection = 32'h00000001; + +parameter sd0__SPI_interrupt_support = 32'hE01000F0; +parameter val_sd0__SPI_interrupt_support = 32'h00000000; +parameter mask_sd0__SPI_interrupt_support = 32'h000000FF; + +parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC; +parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd1__SDMA_system_address_register = 32'hE0101000; +parameter val_sd1__SDMA_system_address_register = 32'h00000000; +parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd1__Block_Size_Block_Count = 32'hE0101004; +parameter val_sd1__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd1__Argument = 32'hE0101008; +parameter val_sd1__Argument = 32'h00000000; +parameter mask_sd1__Argument = 32'hFFFFFFFF; + +parameter sd1__Transfer_Mode_Command = 32'hE010100C; +parameter val_sd1__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd1__Response0 = 32'hE0101010; +parameter val_sd1__Response0 = 32'h00000000; +parameter mask_sd1__Response0 = 32'hFFFFFFFF; + +parameter sd1__Response1 = 32'hE0101014; +parameter val_sd1__Response1 = 32'h00000000; +parameter mask_sd1__Response1 = 32'hFFFFFFFF; + +parameter sd1__Response2 = 32'hE0101018; +parameter val_sd1__Response2 = 32'h00000000; +parameter mask_sd1__Response2 = 32'hFFFFFFFF; + +parameter sd1__Response3 = 32'hE010101C; +parameter val_sd1__Response3 = 32'h00000000; +parameter mask_sd1__Response3 = 32'hFFFFFFFF; + +parameter sd1__Buffer_Data_Port = 32'hE0101020; +parameter val_sd1__Buffer_Data_Port = 32'h00000000; +parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd1__Present_State = 32'hE0101024; +parameter val_sd1__Present_State = 32'h01F20000; +parameter mask_sd1__Present_State = 32'h01FFFFFF; + +parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028; +parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C; +parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030; +parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034; +parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038; +parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd1__Auto_CMD12_error_status = 32'hE010103C; +parameter val_sd1__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd1__Capabilities = 32'hE0101040; +parameter val_sd1__Capabilities = 32'h69EC0080; +parameter mask_sd1__Capabilities = 32'h7FFFFFFF; + +parameter sd1__Maximum_current_capabilities = 32'hE0101048; +parameter val_sd1__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050; +parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd1__ADMA_error_status = 32'hE0101054; +parameter val_sd1__ADMA_error_status = 32'h00000000; +parameter mask_sd1__ADMA_error_status = 32'h00000007; + +parameter sd1__ADMA_system_address = 32'hE0101058; +parameter val_sd1__ADMA_system_address = 32'h00000000; +parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd1__Boot_Timeout_control = 32'hE0101060; +parameter val_sd1__Boot_Timeout_control = 32'h00000000; +parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd1__Debug_Selection = 32'hE0101064; +parameter val_sd1__Debug_Selection = 32'h00000000; +parameter mask_sd1__Debug_Selection = 32'h00000001; + +parameter sd1__SPI_interrupt_support = 32'hE01010F0; +parameter val_sd1__SPI_interrupt_support = 32'h00000000; +parameter mask_sd1__SPI_interrupt_support = 32'h000000FF; + +parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC; +parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter slcr__SCL = 32'hF8000000; +parameter val_slcr__SCL = 32'h00000000; +parameter mask_slcr__SCL = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCK = 32'hF8000004; +parameter val_slcr__SLCR_LOCK = 32'h00000000; +parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_UNLOCK = 32'hF8000008; +parameter val_slcr__SLCR_UNLOCK = 32'h00000000; +parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCKSTA = 32'hF800000C; +parameter val_slcr__SLCR_LOCKSTA = 32'h00000001; +parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CTRL = 32'hF8000100; +parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CTRL = 32'hF8000104; +parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CTRL = 32'hF8000108; +parameter val_slcr__IO_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__PLL_STATUS = 32'hF800010C; +parameter val_slcr__PLL_STATUS = 32'h0000003F; +parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CFG = 32'hF8000110; +parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CFG = 32'hF8000114; +parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CFG = 32'hF8000118; +parameter val_slcr__IO_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__PLL_BG_CTRL = 32'hF800011C; +parameter val_slcr__PLL_BG_CTRL = 32'h00000000; +parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF; + +parameter slcr__ARM_CLK_CTRL = 32'hF8000120; +parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400; +parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_CLK_CTRL = 32'hF8000124; +parameter val_slcr__DDR_CLK_CTRL = 32'h18400003; +parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DCI_CLK_CTRL = 32'hF8000128; +parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201; +parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__APER_CLK_CTRL = 32'hF800012C; +parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD; +parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB0_CLK_CTRL = 32'hF8000130; +parameter val_slcr__USB0_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB1_CLK_CTRL = 32'hF8000134; +parameter val_slcr__USB1_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138; +parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C; +parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_CLK_CTRL = 32'hF8000140; +parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_CLK_CTRL = 32'hF8000144; +parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_CLK_CTRL = 32'hF8000148; +parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21; +parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C; +parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821; +parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_CLK_CTRL = 32'hF8000150; +parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03; +parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_CLK_CTRL = 32'hF8000154; +parameter val_slcr__UART_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_CLK_CTRL = 32'hF8000158; +parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_CLK_CTRL = 32'hF800015C; +parameter val_slcr__CAN_CLK_CTRL = 32'h00501903; +parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160; +parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000; +parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DBG_CLK_CTRL = 32'hF8000164; +parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03; +parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__PCAP_CLK_CTRL = 32'hF8000168; +parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01; +parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C; +parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170; +parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CTRL = 32'hF8000174; +parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CNT = 32'hF8000178; +parameter val_slcr__FPGA0_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_STA = 32'hF800017C; +parameter val_slcr__FPGA0_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180; +parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CTRL = 32'hF8000184; +parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CNT = 32'hF8000188; +parameter val_slcr__FPGA1_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_STA = 32'hF800018C; +parameter val_slcr__FPGA1_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190; +parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CTRL = 32'hF8000194; +parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CNT = 32'hF8000198; +parameter val_slcr__FPGA2_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_STA = 32'hF800019C; +parameter val_slcr__FPGA2_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0; +parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4; +parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CNT = 32'hF80001A8; +parameter val_slcr__FPGA3_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_STA = 32'hF80001AC; +parameter val_slcr__FPGA3_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF; + +parameter slcr__SRST_UART_CTRL = 32'hF80001B0; +parameter val_slcr__SRST_UART_CTRL = 32'h00000000; +parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF; + +parameter slcr__BANDGAP_TRIM = 32'hF80001B8; +parameter val_slcr__BANDGAP_TRIM = 32'h0000001F; +parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF; + +parameter slcr__CC_TEST = 32'hF80001BC; +parameter val_slcr__CC_TEST = 32'h00000000; +parameter mask_slcr__CC_TEST = 32'hFFFFFFFF; + +parameter slcr__PLL_PREDIVISOR = 32'hF80001C0; +parameter val_slcr__PLL_PREDIVISOR = 32'h00000001; +parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF; + +parameter slcr__CLK_621_TRUE = 32'hF80001C4; +parameter val_slcr__CLK_621_TRUE = 32'h00000001; +parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1; + +parameter slcr__PICTURE_DBG = 32'hF80001D0; +parameter val_slcr__PICTURE_DBG = 32'h00000000; +parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4; +parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8; +parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF; + +parameter slcr__PSS_RST_CTRL = 32'hF8000200; +parameter val_slcr__PSS_RST_CTRL = 32'h00000000; +parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_RST_CTRL = 32'hF8000204; +parameter val_slcr__DDR_RST_CTRL = 32'h00000000; +parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_RST_CTRL = 32'hF8000208; +parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DMAC_RST_CTRL = 32'hF800020C; +parameter val_slcr__DMAC_RST_CTRL = 32'h00000000; +parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB_RST_CTRL = 32'hF8000210; +parameter val_slcr__USB_RST_CTRL = 32'h00000000; +parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM_RST_CTRL = 32'hF8000214; +parameter val_slcr__GEM_RST_CTRL = 32'h00000000; +parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_RST_CTRL = 32'hF8000218; +parameter val_slcr__SDIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_RST_CTRL = 32'hF800021C; +parameter val_slcr__SPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_RST_CTRL = 32'hF8000220; +parameter val_slcr__CAN_RST_CTRL = 32'h00000000; +parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__I2C_RST_CTRL = 32'hF8000224; +parameter val_slcr__I2C_RST_CTRL = 32'h00000000; +parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_RST_CTRL = 32'hF8000228; +parameter val_slcr__UART_RST_CTRL = 32'h00000000; +parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIO_RST_CTRL = 32'hF800022C; +parameter val_slcr__GPIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_RST_CTRL = 32'hF8000230; +parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_RST_CTRL = 32'hF8000234; +parameter val_slcr__SMC_RST_CTRL = 32'h00000000; +parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__OCM_RST_CTRL = 32'hF8000238; +parameter val_slcr__OCM_RST_CTRL = 32'h00000000; +parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RST_CTRL = 32'hF800023C; +parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000; +parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA_RST_CTRL = 32'hF8000240; +parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F; +parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244; +parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000; +parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__RS_AWDT_CTRL = 32'hF800024C; +parameter val_slcr__RS_AWDT_CTRL = 32'h00000000; +parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF; + +parameter slcr__RST_REASON = 32'hF8000250; +parameter val_slcr__RST_REASON = 32'h00000040; +parameter mask_slcr__RST_REASON = 32'hFFFFFFFF; + +parameter slcr__RST_REASON_CLR = 32'hF8000254; +parameter val_slcr__RST_REASON_CLR = 32'h00000000; +parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF; + +parameter slcr__REBOOT_STATUS = 32'hF8000258; +parameter val_slcr__REBOOT_STATUS = 32'h00400000; +parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF; + +parameter slcr__BOOT_MODE = 32'hF800025C; +parameter val_slcr__BOOT_MODE = 32'h00000000; +parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0; + +parameter slcr__APU_CTRL = 32'hF8000300; +parameter val_slcr__APU_CTRL = 32'h00000000; +parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF; + +parameter slcr__WDT_CLK_SEL = 32'hF8000304; +parameter val_slcr__WDT_CLK_SEL = 32'h00000000; +parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM0 = 32'hF8000400; +parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM1 = 32'hF8000404; +parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_ROM = 32'hF8000408; +parameter val_slcr__TZ_OCM_ROM = 32'h00000000; +parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF; + +parameter slcr__TZ_DDR_RAM = 32'hF8000430; +parameter val_slcr__TZ_DDR_RAM = 32'h00000000; +parameter mask_slcr__TZ_DDR_RAM = 32'h00000001; + +parameter slcr__TZ_DMA_NS = 32'hF8000440; +parameter val_slcr__TZ_DMA_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444; +parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448; +parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_GEM = 32'hF8000450; +parameter val_slcr__TZ_GEM = 32'h00000000; +parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF; + +parameter slcr__TZ_SDIO = 32'hF8000454; +parameter val_slcr__TZ_SDIO = 32'h00000000; +parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF; + +parameter slcr__TZ_USB = 32'hF8000458; +parameter val_slcr__TZ_USB = 32'h00000000; +parameter mask_slcr__TZ_USB = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_M = 32'hF8000484; +parameter val_slcr__TZ_FPGA_M = 32'h00000000; +parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_AFI = 32'hF8000488; +parameter val_slcr__TZ_FPGA_AFI = 32'h00000000; +parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF; + +parameter slcr__DBG_CTRL = 32'hF8000500; +parameter val_slcr__DBG_CTRL = 32'h00000000; +parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF; + +parameter slcr__PSS_IDCODE = 32'hF8000530; +parameter val_slcr__PSS_IDCODE = 32'h03720093; +parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF; + +parameter slcr__DDR_URGENT = 32'hF8000600; +parameter val_slcr__DDR_URGENT = 32'h00000000; +parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF; + +parameter slcr__DDR_CAL_START = 32'hF800060C; +parameter val_slcr__DDR_CAL_START = 32'h00000000; +parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF; + +parameter slcr__DDR_REF_START = 32'hF8000614; +parameter val_slcr__DDR_REF_START = 32'h00000000; +parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF; + +parameter slcr__DDR_CMD_STA = 32'hF8000618; +parameter val_slcr__DDR_CMD_STA = 32'h00000000; +parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF; + +parameter slcr__DDR_URGENT_SEL = 32'hF800061C; +parameter val_slcr__DDR_URGENT_SEL = 32'h00000000; +parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF; + +parameter slcr__DDR_DFI_STATUS = 32'hF8000620; +parameter val_slcr__DDR_DFI_STATUS = 32'h00000000; +parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_00 = 32'hF8000700; +parameter val_slcr__MIO_PIN_00 = 32'h00001601; +parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_01 = 32'hF8000704; +parameter val_slcr__MIO_PIN_01 = 32'h00001601; +parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_02 = 32'hF8000708; +parameter val_slcr__MIO_PIN_02 = 32'h00000601; +parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_03 = 32'hF800070C; +parameter val_slcr__MIO_PIN_03 = 32'h00000601; +parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_04 = 32'hF8000710; +parameter val_slcr__MIO_PIN_04 = 32'h00000601; +parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_05 = 32'hF8000714; +parameter val_slcr__MIO_PIN_05 = 32'h00000601; +parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_06 = 32'hF8000718; +parameter val_slcr__MIO_PIN_06 = 32'h00000601; +parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_07 = 32'hF800071C; +parameter val_slcr__MIO_PIN_07 = 32'h00000601; +parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_08 = 32'hF8000720; +parameter val_slcr__MIO_PIN_08 = 32'h00000601; +parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_09 = 32'hF8000724; +parameter val_slcr__MIO_PIN_09 = 32'h00001601; +parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_10 = 32'hF8000728; +parameter val_slcr__MIO_PIN_10 = 32'h00001601; +parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_11 = 32'hF800072C; +parameter val_slcr__MIO_PIN_11 = 32'h00001601; +parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_12 = 32'hF8000730; +parameter val_slcr__MIO_PIN_12 = 32'h00001601; +parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_13 = 32'hF8000734; +parameter val_slcr__MIO_PIN_13 = 32'h00001601; +parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_14 = 32'hF8000738; +parameter val_slcr__MIO_PIN_14 = 32'h00001601; +parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_15 = 32'hF800073C; +parameter val_slcr__MIO_PIN_15 = 32'h00001601; +parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_16 = 32'hF8000740; +parameter val_slcr__MIO_PIN_16 = 32'h00001601; +parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_17 = 32'hF8000744; +parameter val_slcr__MIO_PIN_17 = 32'h00001601; +parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_18 = 32'hF8000748; +parameter val_slcr__MIO_PIN_18 = 32'h00001601; +parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_19 = 32'hF800074C; +parameter val_slcr__MIO_PIN_19 = 32'h00001601; +parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_20 = 32'hF8000750; +parameter val_slcr__MIO_PIN_20 = 32'h00001601; +parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_21 = 32'hF8000754; +parameter val_slcr__MIO_PIN_21 = 32'h00001601; +parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_22 = 32'hF8000758; +parameter val_slcr__MIO_PIN_22 = 32'h00001601; +parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_23 = 32'hF800075C; +parameter val_slcr__MIO_PIN_23 = 32'h00001601; +parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_24 = 32'hF8000760; +parameter val_slcr__MIO_PIN_24 = 32'h00001601; +parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_25 = 32'hF8000764; +parameter val_slcr__MIO_PIN_25 = 32'h00001601; +parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_26 = 32'hF8000768; +parameter val_slcr__MIO_PIN_26 = 32'h00001601; +parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_27 = 32'hF800076C; +parameter val_slcr__MIO_PIN_27 = 32'h00001601; +parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_28 = 32'hF8000770; +parameter val_slcr__MIO_PIN_28 = 32'h00001601; +parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_29 = 32'hF8000774; +parameter val_slcr__MIO_PIN_29 = 32'h00001601; +parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_30 = 32'hF8000778; +parameter val_slcr__MIO_PIN_30 = 32'h00001601; +parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_31 = 32'hF800077C; +parameter val_slcr__MIO_PIN_31 = 32'h00001601; +parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_32 = 32'hF8000780; +parameter val_slcr__MIO_PIN_32 = 32'h00001601; +parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_33 = 32'hF8000784; +parameter val_slcr__MIO_PIN_33 = 32'h00001601; +parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_34 = 32'hF8000788; +parameter val_slcr__MIO_PIN_34 = 32'h00001601; +parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_35 = 32'hF800078C; +parameter val_slcr__MIO_PIN_35 = 32'h00001601; +parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_36 = 32'hF8000790; +parameter val_slcr__MIO_PIN_36 = 32'h00001601; +parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_37 = 32'hF8000794; +parameter val_slcr__MIO_PIN_37 = 32'h00001601; +parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_38 = 32'hF8000798; +parameter val_slcr__MIO_PIN_38 = 32'h00001601; +parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_39 = 32'hF800079C; +parameter val_slcr__MIO_PIN_39 = 32'h00001601; +parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_40 = 32'hF80007A0; +parameter val_slcr__MIO_PIN_40 = 32'h00001601; +parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_41 = 32'hF80007A4; +parameter val_slcr__MIO_PIN_41 = 32'h00001601; +parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_42 = 32'hF80007A8; +parameter val_slcr__MIO_PIN_42 = 32'h00001601; +parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_43 = 32'hF80007AC; +parameter val_slcr__MIO_PIN_43 = 32'h00001601; +parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_44 = 32'hF80007B0; +parameter val_slcr__MIO_PIN_44 = 32'h00001601; +parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_45 = 32'hF80007B4; +parameter val_slcr__MIO_PIN_45 = 32'h00001601; +parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_46 = 32'hF80007B8; +parameter val_slcr__MIO_PIN_46 = 32'h00001601; +parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_47 = 32'hF80007BC; +parameter val_slcr__MIO_PIN_47 = 32'h00001601; +parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_48 = 32'hF80007C0; +parameter val_slcr__MIO_PIN_48 = 32'h00001601; +parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_49 = 32'hF80007C4; +parameter val_slcr__MIO_PIN_49 = 32'h00001601; +parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_50 = 32'hF80007C8; +parameter val_slcr__MIO_PIN_50 = 32'h00001601; +parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_51 = 32'hF80007CC; +parameter val_slcr__MIO_PIN_51 = 32'h00001601; +parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_52 = 32'hF80007D0; +parameter val_slcr__MIO_PIN_52 = 32'h00001601; +parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_53 = 32'hF80007D4; +parameter val_slcr__MIO_PIN_53 = 32'h00001601; +parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF; + +parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800; +parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000; +parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF; + +parameter slcr__MIO_LOOPBACK = 32'hF8000804; +parameter val_slcr__MIO_LOOPBACK = 32'h00000000; +parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI0 = 32'hF800080C; +parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; +parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI1 = 32'hF8000810; +parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF; +parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF; + +parameter slcr__SD0_WP_CD_SEL = 32'hF8000830; +parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__SD1_WP_CD_SEL = 32'hF8000834; +parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__LVL_SHFTR_EN = 32'hF8000900; +parameter val_slcr__LVL_SHFTR_EN = 32'h00000000; +parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF; + +parameter slcr__OCM_CFG = 32'hF8000910; +parameter val_slcr__OCM_CFG = 32'h00000000; +parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF; + +parameter slcr__CPU0_RAM0 = 32'hF8000A00; +parameter val_slcr__CPU0_RAM0 = 32'h00020202; +parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM1 = 32'hF8000A04; +parameter val_slcr__CPU0_RAM1 = 32'h00020202; +parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM2 = 32'hF8000A08; +parameter val_slcr__CPU0_RAM2 = 32'h02020202; +parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF; + +parameter slcr__CPU1_RAM0 = 32'hF8000A0C; +parameter val_slcr__CPU1_RAM0 = 32'h00020202; +parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM1 = 32'hF8000A10; +parameter val_slcr__CPU1_RAM1 = 32'h00020202; +parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM2 = 32'hF8000A14; +parameter val_slcr__CPU1_RAM2 = 32'h02020202; +parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF; + +parameter slcr__SCU_RAM = 32'hF8000A18; +parameter val_slcr__SCU_RAM = 32'h00000002; +parameter mask_slcr__SCU_RAM = 32'h000000FF; + +parameter slcr__L2C_RAM = 32'hF8000A1C; +parameter val_slcr__L2C_RAM = 32'h00020202; +parameter mask_slcr__L2C_RAM = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30; +parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_USB01 = 32'hF8000A34; +parameter val_slcr__IOU_RAM_USB01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38; +parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C; +parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40; +parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44; +parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48; +parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909; +parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF; + +parameter slcr__DMAC_RAM = 32'hF8000A50; +parameter val_slcr__DMAC_RAM = 32'h00000009; +parameter mask_slcr__DMAC_RAM = 32'h000000FF; + +parameter slcr__AFI0_RAM0 = 32'hF8000A60; +parameter val_slcr__AFI0_RAM0 = 32'h09090909; +parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM1 = 32'hF8000A64; +parameter val_slcr__AFI0_RAM1 = 32'h09090909; +parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM2 = 32'hF8000A68; +parameter val_slcr__AFI0_RAM2 = 32'h00000909; +parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI1_RAM0 = 32'hF8000A6C; +parameter val_slcr__AFI1_RAM0 = 32'h09090909; +parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM1 = 32'hF8000A70; +parameter val_slcr__AFI1_RAM1 = 32'h09090909; +parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM2 = 32'hF8000A74; +parameter val_slcr__AFI1_RAM2 = 32'h00000909; +parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI2_RAM0 = 32'hF8000A78; +parameter val_slcr__AFI2_RAM0 = 32'h09090909; +parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM1 = 32'hF8000A7C; +parameter val_slcr__AFI2_RAM1 = 32'h09090909; +parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM2 = 32'hF8000A80; +parameter val_slcr__AFI2_RAM2 = 32'h00000909; +parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI3_RAM0 = 32'hF8000A84; +parameter val_slcr__AFI3_RAM0 = 32'h09090909; +parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM1 = 32'hF8000A88; +parameter val_slcr__AFI3_RAM1 = 32'h09090909; +parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM2 = 32'hF8000A8C; +parameter val_slcr__AFI3_RAM2 = 32'h00000909; +parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF; + +parameter slcr__OCM_RAM = 32'hF8000A90; +parameter val_slcr__OCM_RAM = 32'h01010101; +parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM0 = 32'hF8000A94; +parameter val_slcr__OCM_ROM0 = 32'h09090909; +parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM1 = 32'hF8000A98; +parameter val_slcr__OCM_ROM1 = 32'h09090909; +parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RAM = 32'hF8000AA0; +parameter val_slcr__DEVCI_RAM = 32'h00000909; +parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF; + +parameter slcr__CSG_RAM = 32'hF8000AB0; +parameter val_slcr__CSG_RAM = 32'h00000001; +parameter mask_slcr__CSG_RAM = 32'h000000FF; + +parameter slcr__GPIOB_CTRL = 32'hF8000B00; +parameter val_slcr__GPIOB_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04; +parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08; +parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C; +parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10; +parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14; +parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18; +parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40; +parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44; +parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA0 = 32'hF8000B48; +parameter val_slcr__DDRIOB_DATA0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C; +parameter val_slcr__DDRIOB_DATA1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50; +parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54; +parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_CLOCK = 32'hF8000B58; +parameter val_slcr__DDRIOB_CLOCK = 32'h00000800; +parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C; +parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68; +parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C; +parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000; +parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70; +parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020; +parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74; +parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000; +parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF; + + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter smcc__memc_status = 32'hE000E000; +parameter val_smcc__memc_status = 32'h00000000; +parameter mask_smcc__memc_status = 32'h00001FFF; + +parameter smcc__memif_cfg = 32'hE000E004; +parameter val_smcc__memif_cfg = 32'h00011205; +parameter mask_smcc__memif_cfg = 32'h0003FFFF; + +parameter smcc__memc_cfg_set = 32'hE000E008; +parameter val_smcc__memc_cfg_set = 32'h00000000; +parameter mask_smcc__memc_cfg_set = 32'h00000000; + +parameter smcc__memc_cfg_clr = 32'hE000E00C; +parameter val_smcc__memc_cfg_clr = 32'h00000000; +parameter mask_smcc__memc_cfg_clr = 32'h00000000; + +parameter smcc__direct_cmd = 32'hE000E010; +parameter val_smcc__direct_cmd = 32'h00000000; +parameter mask_smcc__direct_cmd = 32'h00000000; + +parameter smcc__set_cycles = 32'hE000E014; +parameter val_smcc__set_cycles = 32'h00000000; +parameter mask_smcc__set_cycles = 32'h00000000; + +parameter smcc__set_opmode = 32'hE000E018; +parameter val_smcc__set_opmode = 32'h00000000; +parameter mask_smcc__set_opmode = 32'h00000000; + +parameter smcc__refresh_period_0 = 32'hE000E020; +parameter val_smcc__refresh_period_0 = 32'h00000000; +parameter mask_smcc__refresh_period_0 = 32'h0000000F; + +parameter smcc__refresh_period_1 = 32'hE000E024; +parameter val_smcc__refresh_period_1 = 32'h00000000; +parameter mask_smcc__refresh_period_1 = 32'h0000000F; + +parameter smcc__sram_cycles0_0 = 32'hE000E100; +parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF; + +parameter smcc__opmode0_0 = 32'hE000E104; +parameter val_smcc__opmode0_0 = 32'hE2FE0800; +parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF; + +parameter smcc__sram_cycles0_1 = 32'hE000E120; +parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF; + +parameter smcc__opmode0_1 = 32'hE000E124; +parameter val_smcc__opmode0_1 = 32'hE4FE0800; +parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF; + +parameter smcc__nand_cycles1_0 = 32'hE000E180; +parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC; +parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF; + +parameter smcc__opmode1_0 = 32'hE000E184; +parameter val_smcc__opmode1_0 = 32'hE1FF0001; +parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF; + +parameter smcc__user_status = 32'hE000E200; +parameter val_smcc__user_status = 32'h00000000; +parameter mask_smcc__user_status = 32'h000000FF; + +parameter smcc__user_config = 32'hE000E204; +parameter val_smcc__user_config = 32'h00000000; +parameter mask_smcc__user_config = 32'h00000000; + +parameter smcc__ecc_status_0 = 32'hE000E300; +parameter val_smcc__ecc_status_0 = 32'h00000000; +parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_0 = 32'hE000E304; +parameter val_smcc__ecc_memcfg_0 = 32'h00000000; +parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_0 = 32'hE000E308; +parameter val_smcc__ecc_memcommand1_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_0 = 32'hE000E30C; +parameter val_smcc__ecc_memcommand2_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_0 = 32'hE000E310; +parameter val_smcc__ecc_addr0_0 = 32'h00000000; +parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_0 = 32'hE000E314; +parameter val_smcc__ecc_addr1_0 = 32'h00000000; +parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_0 = 32'hE000E318; +parameter val_smcc__ecc_value0_0 = 32'h00000000; +parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_0 = 32'hE000E31C; +parameter val_smcc__ecc_value1_0 = 32'h00000000; +parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_0 = 32'hE000E320; +parameter val_smcc__ecc_value2_0 = 32'h00000000; +parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_0 = 32'hE000E324; +parameter val_smcc__ecc_value3_0 = 32'h00000000; +parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_status_1 = 32'hE000E400; +parameter val_smcc__ecc_status_1 = 32'h00000000; +parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_1 = 32'hE000E404; +parameter val_smcc__ecc_memcfg_1 = 32'h00000043; +parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_1 = 32'hE000E408; +parameter val_smcc__ecc_memcommand1_1 = 32'h01300080; +parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_1 = 32'hE000E40C; +parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585; +parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_1 = 32'hE000E410; +parameter val_smcc__ecc_addr0_1 = 32'h00000000; +parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_1 = 32'hE000E414; +parameter val_smcc__ecc_addr1_1 = 32'h00000000; +parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_1 = 32'hE000E418; +parameter val_smcc__ecc_value0_1 = 32'h00000000; +parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_1 = 32'hE000E41C; +parameter val_smcc__ecc_value1_1 = 32'h00000000; +parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_1 = 32'hE000E420; +parameter val_smcc__ecc_value2_1 = 32'h00000000; +parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_1 = 32'hE000E424; +parameter val_smcc__ecc_value3_1 = 32'h00000000; +parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF; + +parameter smcc__integration_test = 32'hE000EE00; +parameter val_smcc__integration_test = 32'h00000000; +parameter mask_smcc__integration_test = 32'hFFFFFFFF; + +parameter smcc__periph_id_0 = 32'hE000EFE0; +parameter val_smcc__periph_id_0 = 32'h00000053; +parameter mask_smcc__periph_id_0 = 32'h000000FF; + +parameter smcc__periph_id_1 = 32'hE000EFE4; +parameter val_smcc__periph_id_1 = 32'h00000013; +parameter mask_smcc__periph_id_1 = 32'h000000FF; + +parameter smcc__periph_id_2 = 32'hE000EFE8; +parameter val_smcc__periph_id_2 = 32'h00000054; +parameter mask_smcc__periph_id_2 = 32'h000000FF; + +parameter smcc__periph_id_3 = 32'hE000EFEC; +parameter val_smcc__periph_id_3 = 32'h00000000; +parameter mask_smcc__periph_id_3 = 32'h00000001; + +parameter smcc__pcell_id_0 = 32'hE000EFF0; +parameter val_smcc__pcell_id_0 = 32'h0000000D; +parameter mask_smcc__pcell_id_0 = 32'h000000FF; + +parameter smcc__pcell_id_1 = 32'hE000EFF4; +parameter val_smcc__pcell_id_1 = 32'h000000F0; +parameter mask_smcc__pcell_id_1 = 32'h000000FF; + +parameter smcc__pcell_id_2 = 32'hE000EFF8; +parameter val_smcc__pcell_id_2 = 32'h00000005; +parameter mask_smcc__pcell_id_2 = 32'h000000FF; + +parameter smcc__pcell_id_3 = 32'hE000EFFC; +parameter val_smcc__pcell_id_3 = 32'h000000B1; +parameter mask_smcc__pcell_id_3 = 32'h000000FF; + + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi0__Config_reg0 = 32'hE0006000; +parameter val_spi0__Config_reg0 = 32'h00020000; +parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intr_status_reg0 = 32'hE0006004; +parameter val_spi0__Intr_status_reg0 = 32'h00000004; +parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_en_reg0 = 32'hE0006008; +parameter val_spi0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_dis_reg0 = 32'hE000600C; +parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_mask_reg0 = 32'hE0006010; +parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi0__En_reg0 = 32'hE0006014; +parameter val_spi0__En_reg0 = 32'h00000000; +parameter mask_spi0__En_reg0 = 32'hFFFFFFFF; + +parameter spi0__Delay_reg0 = 32'hE0006018; +parameter val_spi0__Delay_reg0 = 32'h00000000; +parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi0__Tx_data_reg0 = 32'hE000601C; +parameter val_spi0__Tx_data_reg0 = 32'h00000000; +parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Rx_data_reg0 = 32'hE0006020; +parameter val_spi0__Rx_data_reg0 = 32'h00000000; +parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024; +parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi0__TX_thres_reg0 = 32'hE0006028; +parameter val_spi0__TX_thres_reg0 = 32'h00000001; +parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__RX_thres_reg0 = 32'hE000602C; +parameter val_spi0__RX_thres_reg0 = 32'h00000001; +parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__Mod_id_reg0 = 32'hE00060FC; +parameter val_spi0__Mod_id_reg0 = 32'h00090106; +parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi1__Config_reg0 = 32'hE0007000; +parameter val_spi1__Config_reg0 = 32'h00020000; +parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intr_status_reg0 = 32'hE0007004; +parameter val_spi1__Intr_status_reg0 = 32'h00000004; +parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_en_reg0 = 32'hE0007008; +parameter val_spi1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_dis_reg0 = 32'hE000700C; +parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_mask_reg0 = 32'hE0007010; +parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi1__En_reg0 = 32'hE0007014; +parameter val_spi1__En_reg0 = 32'h00000000; +parameter mask_spi1__En_reg0 = 32'hFFFFFFFF; + +parameter spi1__Delay_reg0 = 32'hE0007018; +parameter val_spi1__Delay_reg0 = 32'h00000000; +parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi1__Tx_data_reg0 = 32'hE000701C; +parameter val_spi1__Tx_data_reg0 = 32'h00000000; +parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Rx_data_reg0 = 32'hE0007020; +parameter val_spi1__Rx_data_reg0 = 32'h00000000; +parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024; +parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi1__TX_thres_reg0 = 32'hE0007028; +parameter val_spi1__TX_thres_reg0 = 32'h00000001; +parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__RX_thres_reg0 = 32'hE000702C; +parameter val_spi1__RX_thres_reg0 = 32'h00000001; +parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__Mod_id_reg0 = 32'hE00070FC; +parameter val_spi1__Mod_id_reg0 = 32'h00090106; +parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter swdt__MODE = 32'hF8005000; +parameter val_swdt__MODE = 32'h000001C2; +parameter mask_swdt__MODE = 32'h00FFFFFF; + +parameter swdt__CONTROL = 32'hF8005004; +parameter val_swdt__CONTROL = 32'h03FFC3FC; +parameter mask_swdt__CONTROL = 32'h03FFFFFF; + +parameter swdt__RESTART = 32'hF8005008; +parameter val_swdt__RESTART = 32'h00000000; +parameter mask_swdt__RESTART = 32'h0000FFFF; + +parameter swdt__STATUS = 32'hF800500C; +parameter val_swdt__STATUS = 32'h00000000; +parameter mask_swdt__STATUS = 32'h00000001; + + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc0__Clock_Control_1 = 32'hF8001000; +parameter val_ttc0__Clock_Control_1 = 32'h00000000; +parameter mask_ttc0__Clock_Control_1 = 32'h0000007F; + +parameter ttc0__Clock_Control_2 = 32'hF8001004; +parameter val_ttc0__Clock_Control_2 = 32'h00000000; +parameter mask_ttc0__Clock_Control_2 = 32'h0000007F; + +parameter ttc0__Clock_Control_3 = 32'hF8001008; +parameter val_ttc0__Clock_Control_3 = 32'h00000000; +parameter mask_ttc0__Clock_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Control_1 = 32'hF800100C; +parameter val_ttc0__Counter_Control_1 = 32'h00000021; +parameter mask_ttc0__Counter_Control_1 = 32'h0000007F; + +parameter ttc0__Counter_Control_2 = 32'hF8001010; +parameter val_ttc0__Counter_Control_2 = 32'h00000021; +parameter mask_ttc0__Counter_Control_2 = 32'h0000007F; + +parameter ttc0__Counter_Control_3 = 32'hF8001014; +parameter val_ttc0__Counter_Control_3 = 32'h00000021; +parameter mask_ttc0__Counter_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Value_1 = 32'hF8001018; +parameter val_ttc0__Counter_Value_1 = 32'h00000000; +parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_2 = 32'hF800101C; +parameter val_ttc0__Counter_Value_2 = 32'h00000000; +parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_3 = 32'hF8001020; +parameter val_ttc0__Counter_Value_3 = 32'h00000000; +parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_1 = 32'hF8001024; +parameter val_ttc0__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_2 = 32'hF8001028; +parameter val_ttc0__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_3 = 32'hF800102C; +parameter val_ttc0__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_1 = 32'hF8001030; +parameter val_ttc0__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_2 = 32'hF8001034; +parameter val_ttc0__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_3 = 32'hF8001038; +parameter val_ttc0__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_1 = 32'hF800103C; +parameter val_ttc0__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_2 = 32'hF8001040; +parameter val_ttc0__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_3 = 32'hF8001044; +parameter val_ttc0__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_1 = 32'hF8001048; +parameter val_ttc0__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_2 = 32'hF800104C; +parameter val_ttc0__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_3 = 32'hF8001050; +parameter val_ttc0__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Interrupt_Register_1 = 32'hF8001054; +parameter val_ttc0__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_2 = 32'hF8001058; +parameter val_ttc0__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_3 = 32'hF800105C; +parameter val_ttc0__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_1 = 32'hF8001060; +parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_2 = 32'hF8001064; +parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_3 = 32'hF8001068; +parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc0__Event_Control_Timer_1 = 32'hF800106C; +parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_2 = 32'hF8001070; +parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_3 = 32'hF8001074; +parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc0__Event_Register_1 = 32'hF8001078; +parameter val_ttc0__Event_Register_1 = 32'h00000000; +parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF; + +parameter ttc0__Event_Register_2 = 32'hF800107C; +parameter val_ttc0__Event_Register_2 = 32'h00000000; +parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF; + +parameter ttc0__Event_Register_3 = 32'hF8001080; +parameter val_ttc0__Event_Register_3 = 32'h00000000; +parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc1__Clock_Control_1 = 32'hF8002000; +parameter val_ttc1__Clock_Control_1 = 32'h00000000; +parameter mask_ttc1__Clock_Control_1 = 32'h0000007F; + +parameter ttc1__Clock_Control_2 = 32'hF8002004; +parameter val_ttc1__Clock_Control_2 = 32'h00000000; +parameter mask_ttc1__Clock_Control_2 = 32'h0000007F; + +parameter ttc1__Clock_Control_3 = 32'hF8002008; +parameter val_ttc1__Clock_Control_3 = 32'h00000000; +parameter mask_ttc1__Clock_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Control_1 = 32'hF800200C; +parameter val_ttc1__Counter_Control_1 = 32'h00000021; +parameter mask_ttc1__Counter_Control_1 = 32'h0000007F; + +parameter ttc1__Counter_Control_2 = 32'hF8002010; +parameter val_ttc1__Counter_Control_2 = 32'h00000021; +parameter mask_ttc1__Counter_Control_2 = 32'h0000007F; + +parameter ttc1__Counter_Control_3 = 32'hF8002014; +parameter val_ttc1__Counter_Control_3 = 32'h00000021; +parameter mask_ttc1__Counter_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Value_1 = 32'hF8002018; +parameter val_ttc1__Counter_Value_1 = 32'h00000000; +parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_2 = 32'hF800201C; +parameter val_ttc1__Counter_Value_2 = 32'h00000000; +parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_3 = 32'hF8002020; +parameter val_ttc1__Counter_Value_3 = 32'h00000000; +parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_1 = 32'hF8002024; +parameter val_ttc1__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_2 = 32'hF8002028; +parameter val_ttc1__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_3 = 32'hF800202C; +parameter val_ttc1__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_1 = 32'hF8002030; +parameter val_ttc1__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_2 = 32'hF8002034; +parameter val_ttc1__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_3 = 32'hF8002038; +parameter val_ttc1__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_1 = 32'hF800203C; +parameter val_ttc1__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_2 = 32'hF8002040; +parameter val_ttc1__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_3 = 32'hF8002044; +parameter val_ttc1__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_1 = 32'hF8002048; +parameter val_ttc1__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_2 = 32'hF800204C; +parameter val_ttc1__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_3 = 32'hF8002050; +parameter val_ttc1__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Interrupt_Register_1 = 32'hF8002054; +parameter val_ttc1__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_2 = 32'hF8002058; +parameter val_ttc1__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_3 = 32'hF800205C; +parameter val_ttc1__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_1 = 32'hF8002060; +parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_2 = 32'hF8002064; +parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_3 = 32'hF8002068; +parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc1__Event_Control_Timer_1 = 32'hF800206C; +parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_2 = 32'hF8002070; +parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_3 = 32'hF8002074; +parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc1__Event_Register_1 = 32'hF8002078; +parameter val_ttc1__Event_Register_1 = 32'h00000000; +parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF; + +parameter ttc1__Event_Register_2 = 32'hF800207C; +parameter val_ttc1__Event_Register_2 = 32'h00000000; +parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF; + +parameter ttc1__Event_Register_3 = 32'hF8002080; +parameter val_ttc1__Event_Register_3 = 32'h00000000; +parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart0__Control_reg0 = 32'hE0000000; +parameter val_uart0__Control_reg0 = 32'h00000128; +parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF; + +parameter uart0__mode_reg0 = 32'hE0000004; +parameter val_uart0__mode_reg0 = 32'h00000000; +parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_en_reg0 = 32'hE0000008; +parameter val_uart0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_dis_reg0 = 32'hE000000C; +parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_mask_reg0 = 32'hE0000010; +parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014; +parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018; +parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C; +parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020; +parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart0__Modem_ctrl_reg0 = 32'hE0000024; +parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart0__Modem_sts_reg0 = 32'hE0000028; +parameter val_uart0__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart0__Modem_sts_reg0 = 32'h00000000; + +parameter uart0__Channel_sts_reg0 = 32'hE000002C; +parameter val_uart0__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__TX_RX_FIFO0 = 32'hE0000030; +parameter val_uart0__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034; +parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart0__Flow_delay_reg0 = 32'hE0000038; +parameter val_uart0__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C; +parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040; +parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044; +parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart1__Control_reg0 = 32'hE0001000; +parameter val_uart1__Control_reg0 = 32'h00000128; +parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF; + +parameter uart1__mode_reg0 = 32'hE0001004; +parameter val_uart1__mode_reg0 = 32'h00000000; +parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_en_reg0 = 32'hE0001008; +parameter val_uart1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_dis_reg0 = 32'hE000100C; +parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_mask_reg0 = 32'hE0001010; +parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014; +parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018; +parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C; +parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020; +parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart1__Modem_ctrl_reg0 = 32'hE0001024; +parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart1__Modem_sts_reg0 = 32'hE0001028; +parameter val_uart1__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart1__Modem_sts_reg0 = 32'h00000000; + +parameter uart1__Channel_sts_reg0 = 32'hE000102C; +parameter val_uart1__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__TX_RX_FIFO0 = 32'hE0001030; +parameter val_uart1__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034; +parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart1__Flow_delay_reg0 = 32'hE0001038; +parameter val_uart1__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C; +parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040; +parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044; +parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb0__ID = 32'hE0002000; +parameter val_usb0__ID = 32'hE441FA05; +parameter mask_usb0__ID = 32'hFFFFFFFF; + +parameter usb0__HWGENERAL = 32'hE0002004; +parameter val_usb0__HWGENERAL = 32'h00000083; +parameter mask_usb0__HWGENERAL = 32'h00000FFF; + +parameter usb0__HWHOST = 32'hE0002008; +parameter val_usb0__HWHOST = 32'h10020001; +parameter mask_usb0__HWHOST = 32'hFFFFFFFF; + +parameter usb0__HWDEVICE = 32'hE000200C; +parameter val_usb0__HWDEVICE = 32'h00000019; +parameter mask_usb0__HWDEVICE = 32'h0000003F; + +parameter usb0__HWTXBUF = 32'hE0002010; +parameter val_usb0__HWTXBUF = 32'h80060A10; +parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF; + +parameter usb0__HWRXBUF = 32'hE0002014; +parameter val_usb0__HWRXBUF = 32'h00000A10; +parameter mask_usb0__HWRXBUF = 32'hFF00FFFF; + +parameter usb0__GPTIMER0LD = 32'hE0002080; +parameter val_usb0__GPTIMER0LD = 32'h00000000; +parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER0CTRL = 32'hE0002084; +parameter val_usb0__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb0__GPTIMER1LD = 32'hE0002088; +parameter val_usb0__GPTIMER1LD = 32'h00000000; +parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER1CTRL = 32'hE000208C; +parameter val_usb0__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb0__SBUSCFG = 32'hE0002090; +parameter val_usb0__SBUSCFG = 32'h00000003; +parameter mask_usb0__SBUSCFG = 32'h00000007; + +parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100; +parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb0__HCSPARAMS = 32'hE0002104; +parameter val_usb0__HCSPARAMS = 32'h00010011; +parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb0__HCCPARAMS = 32'hE0002108; +parameter val_usb0__HCCPARAMS = 32'h00000006; +parameter mask_usb0__HCCPARAMS = 32'h0000FFFF; + +parameter usb0__DCIVERSION = 32'hE0002120; +parameter val_usb0__DCIVERSION = 32'h00000001; +parameter mask_usb0__DCIVERSION = 32'h0000FFFF; + +parameter usb0__DCCPARAMS = 32'hE0002124; +parameter val_usb0__DCCPARAMS = 32'h0000018C; +parameter mask_usb0__DCCPARAMS = 32'h000001FF; + +parameter usb0__USBCMD = 32'hE0002140; +parameter val_usb0__USBCMD = 32'h00000B00; +parameter mask_usb0__USBCMD = 32'h00FFFFFF; + +parameter usb0__USBSTS = 32'hE0002144; +parameter val_usb0__USBSTS = 32'h00000000; +parameter mask_usb0__USBSTS = 32'h03FFFFFF; + +parameter usb0__USBINTR = 32'hE0002148; +parameter val_usb0__USBINTR = 32'h00000000; +parameter mask_usb0__USBINTR = 32'h03FF0FFF; + +parameter usb0__FRINDEX = 32'hE000214C; +parameter val_usb0__FRINDEX = 32'h00000000; +parameter mask_usb0__FRINDEX = 32'h00003FFF; + +parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154; +parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158; +parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb0__TTCTRL = 32'hE000215C; +parameter val_usb0__TTCTRL = 32'h00000000; +parameter mask_usb0__TTCTRL = 32'hFFFFFFFF; + +parameter usb0__BURSTSIZE = 32'hE0002160; +parameter val_usb0__BURSTSIZE = 32'h00001010; +parameter mask_usb0__BURSTSIZE = 32'h0001FFFF; + +parameter usb0__TXFILLTUNING = 32'hE0002164; +parameter val_usb0__TXFILLTUNING = 32'h00020000; +parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF; + +parameter usb0__TXTTFILLTUNING = 32'hE0002168; +parameter val_usb0__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb0__IC_USB = 32'hE000216C; +parameter val_usb0__IC_USB = 32'h00000000; +parameter mask_usb0__IC_USB = 32'hFFFFFFFF; + +parameter usb0__ULPI_VIEWPORT = 32'hE0002170; +parameter val_usb0__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAK = 32'hE0002178; +parameter val_usb0__ENDPTNAK = 32'h00000000; +parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAKEN = 32'hE000217C; +parameter val_usb0__ENDPTNAKEN = 32'h00000000; +parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb0__CONFIGFLAG = 32'hE0002180; +parameter val_usb0__CONFIGFLAG = 32'h00000001; +parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb0__PORTSC1 = 32'hE0002184; +parameter val_usb0__PORTSC1 = 32'h00000000; +parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF; + +parameter usb0__OTGSC = 32'hE00021A4; +parameter val_usb0__OTGSC = 32'h00000020; +parameter mask_usb0__OTGSC = 32'hFFFFFFFF; + +parameter usb0__USBMODE = 32'hE00021A8; +parameter val_usb0__USBMODE = 32'h00000000; +parameter mask_usb0__USBMODE = 32'h0000FFFF; + +parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC; +parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb0__ENDPTPRIME = 32'hE00021B0; +parameter val_usb0__ENDPTPRIME = 32'h00000000; +parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb0__ENDPTFLUSH = 32'hE00021B4; +parameter val_usb0__ENDPTFLUSH = 32'h00000000; +parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb0__ENDPTSTAT = 32'hE00021B8; +parameter val_usb0__ENDPTSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb0__ENDPTCOMPLETE = 32'hE00021BC; +parameter val_usb0__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb0__ENDPTCTRL0 = 32'hE00021C0; +parameter val_usb0__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL1 = 32'hE00021C4; +parameter val_usb0__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL2 = 32'hE00021C8; +parameter val_usb0__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL3 = 32'hE00021CC; +parameter val_usb0__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL4 = 32'hE00021D0; +parameter val_usb0__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL5 = 32'hE00021D4; +parameter val_usb0__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL6 = 32'hE00021D8; +parameter val_usb0__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL7 = 32'hE00021DC; +parameter val_usb0__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL8 = 32'hE00021E0; +parameter val_usb0__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL9 = 32'hE00021E4; +parameter val_usb0__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL10 = 32'hE00021E8; +parameter val_usb0__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL11 = 32'hE00021EC; +parameter val_usb0__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL12 = 32'hE00021F0; +parameter val_usb0__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF; + + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb1__ID = 32'hE0003000; +parameter val_usb1__ID = 32'hE441FA05; +parameter mask_usb1__ID = 32'hFFFFFFFF; + +parameter usb1__HWGENERAL = 32'hE0003004; +parameter val_usb1__HWGENERAL = 32'h00000083; +parameter mask_usb1__HWGENERAL = 32'h00000FFF; + +parameter usb1__HWHOST = 32'hE0003008; +parameter val_usb1__HWHOST = 32'h10020001; +parameter mask_usb1__HWHOST = 32'hFFFFFFFF; + +parameter usb1__HWDEVICE = 32'hE000300C; +parameter val_usb1__HWDEVICE = 32'h00000019; +parameter mask_usb1__HWDEVICE = 32'h0000003F; + +parameter usb1__HWTXBUF = 32'hE0003010; +parameter val_usb1__HWTXBUF = 32'h80060A10; +parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF; + +parameter usb1__HWRXBUF = 32'hE0003014; +parameter val_usb1__HWRXBUF = 32'h00000A10; +parameter mask_usb1__HWRXBUF = 32'hFF00FFFF; + +parameter usb1__GPTIMER0LD = 32'hE0003080; +parameter val_usb1__GPTIMER0LD = 32'h00000000; +parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER0CTRL = 32'hE0003084; +parameter val_usb1__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb1__GPTIMER1LD = 32'hE0003088; +parameter val_usb1__GPTIMER1LD = 32'h00000000; +parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER1CTRL = 32'hE000308C; +parameter val_usb1__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb1__SBUSCFG = 32'hE0003090; +parameter val_usb1__SBUSCFG = 32'h00000003; +parameter mask_usb1__SBUSCFG = 32'h00000007; + +parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100; +parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb1__HCSPARAMS = 32'hE0003104; +parameter val_usb1__HCSPARAMS = 32'h00010011; +parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb1__HCCPARAMS = 32'hE0003108; +parameter val_usb1__HCCPARAMS = 32'h00000006; +parameter mask_usb1__HCCPARAMS = 32'h0000FFFF; + +parameter usb1__DCIVERSION = 32'hE0003120; +parameter val_usb1__DCIVERSION = 32'h00000001; +parameter mask_usb1__DCIVERSION = 32'h0000FFFF; + +parameter usb1__DCCPARAMS = 32'hE0003124; +parameter val_usb1__DCCPARAMS = 32'h0000018C; +parameter mask_usb1__DCCPARAMS = 32'h000001FF; + +parameter usb1__USBCMD = 32'hE0003140; +parameter val_usb1__USBCMD = 32'h00000B00; +parameter mask_usb1__USBCMD = 32'h00FFFFFF; + +parameter usb1__USBSTS = 32'hE0003144; +parameter val_usb1__USBSTS = 32'h00000000; +parameter mask_usb1__USBSTS = 32'h03FFFFFF; + +parameter usb1__USBINTR = 32'hE0003148; +parameter val_usb1__USBINTR = 32'h00000000; +parameter mask_usb1__USBINTR = 32'h03FF0FFF; + +parameter usb1__FRINDEX = 32'hE000314C; +parameter val_usb1__FRINDEX = 32'h00000000; +parameter mask_usb1__FRINDEX = 32'h00003FFF; + +parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154; +parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158; +parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb1__TTCTRL = 32'hE000315C; +parameter val_usb1__TTCTRL = 32'h00000000; +parameter mask_usb1__TTCTRL = 32'hFFFFFFFF; + +parameter usb1__BURSTSIZE = 32'hE0003160; +parameter val_usb1__BURSTSIZE = 32'h00001010; +parameter mask_usb1__BURSTSIZE = 32'h0001FFFF; + +parameter usb1__TXFILLTUNING = 32'hE0003164; +parameter val_usb1__TXFILLTUNING = 32'h00020000; +parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF; + +parameter usb1__TXTTFILLTUNING = 32'hE0003168; +parameter val_usb1__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb1__IC_USB = 32'hE000316C; +parameter val_usb1__IC_USB = 32'h00000000; +parameter mask_usb1__IC_USB = 32'hFFFFFFFF; + +parameter usb1__ULPI_VIEWPORT = 32'hE0003170; +parameter val_usb1__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAK = 32'hE0003178; +parameter val_usb1__ENDPTNAK = 32'h00000000; +parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAKEN = 32'hE000317C; +parameter val_usb1__ENDPTNAKEN = 32'h00000000; +parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb1__CONFIGFLAG = 32'hE0003180; +parameter val_usb1__CONFIGFLAG = 32'h00000001; +parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb1__PORTSC1 = 32'hE0003184; +parameter val_usb1__PORTSC1 = 32'h00000000; +parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF; + +parameter usb1__OTGSC = 32'hE00031A4; +parameter val_usb1__OTGSC = 32'h00000020; +parameter mask_usb1__OTGSC = 32'hFFFFFFFF; + +parameter usb1__USBMODE = 32'hE00031A8; +parameter val_usb1__USBMODE = 32'h00000000; +parameter mask_usb1__USBMODE = 32'h0000FFFF; + +parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC; +parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb1__ENDPTPRIME = 32'hE00031B0; +parameter val_usb1__ENDPTPRIME = 32'h00000000; +parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb1__ENDPTFLUSH = 32'hE00031B4; +parameter val_usb1__ENDPTFLUSH = 32'h00000000; +parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb1__ENDPTSTAT = 32'hE00031B8; +parameter val_usb1__ENDPTSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb1__ENDPTCOMPLETE = 32'hE00031BC; +parameter val_usb1__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb1__ENDPTCTRL0 = 32'hE00031C0; +parameter val_usb1__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL1 = 32'hE00031C4; +parameter val_usb1__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL2 = 32'hE00031C8; +parameter val_usb1__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL3 = 32'hE00031CC; +parameter val_usb1__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL4 = 32'hE00031D0; +parameter val_usb1__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL5 = 32'hE00031D4; +parameter val_usb1__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL6 = 32'hE00031D8; +parameter val_usb1__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL7 = 32'hE00031DC; +parameter val_usb1__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL8 = 32'hE00031E0; +parameter val_usb1__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL9 = 32'hE00031E4; +parameter val_usb1__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL10 = 32'hE00031E8; +parameter val_usb1__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL11 = 32'hE00031EC; +parameter val_usb1__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL12 = 32'hE00031F0; +parameter val_usb1__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF; diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_unused_ports.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_unused_ports.v new file mode 100644 index 0000000..8fe7c25 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_5_unused_ports.v @@ -0,0 +1,433 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_unused_ports.v + * + * Date : 2012-11 + * + * Description : Semantic checks for unused ports. + * + *****************************************************************************/ + +/* CAN */ +assign CAN0_PHY_TX = 0; +assign CAN1_PHY_TX = 0; +always @(CAN0_PHY_RX or CAN1_PHY_RX) +begin + if(CAN0_PHY_RX | CAN1_PHY_RX) + $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* ETHERNET */ +/* ------------------------------------------- */ + +assign ENET0_GMII_TX_EN = 0; +assign ENET0_GMII_TX_ER = 0; +assign ENET0_MDIO_MDC = 0; +assign ENET0_MDIO_O = 0; /// confirm +assign ENET0_MDIO_T = 0; +assign ENET0_PTP_DELAY_REQ_RX = 0; +assign ENET0_PTP_DELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_REQ_RX = 0; +assign ENET0_PTP_PDELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_RESP_RX = 0; +assign ENET0_PTP_PDELAY_RESP_TX = 0; +assign ENET0_PTP_SYNC_FRAME_RX = 0; +assign ENET0_PTP_SYNC_FRAME_TX = 0; +assign ENET0_SOF_RX = 0; +assign ENET0_SOF_TX = 0; +assign ENET0_GMII_TXD = 0; +always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or + ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or + ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD) +begin + if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | + ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER | + ENET0_GMII_TX_CLK | ENET0_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +assign ENET1_GMII_TX_EN = 0; +assign ENET1_GMII_TX_ER = 0; +assign ENET1_MDIO_MDC = 0; +assign ENET1_MDIO_O = 0;/// confirm +assign ENET1_MDIO_T = 0; +assign ENET1_PTP_DELAY_REQ_RX = 0; +assign ENET1_PTP_DELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_REQ_RX = 0; +assign ENET1_PTP_PDELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_RESP_RX = 0; +assign ENET1_PTP_PDELAY_RESP_TX = 0; +assign ENET1_PTP_SYNC_FRAME_RX = 0; +assign ENET1_PTP_SYNC_FRAME_TX = 0; +assign ENET1_SOF_RX = 0; +assign ENET1_SOF_TX = 0; +assign ENET1_GMII_TXD = 0; +always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or + ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or + ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD) +begin + if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | + ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER | + ENET1_GMII_TX_CLK | ENET1_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* GPIO */ +/* ------------------------------------------- */ + +assign GPIO_O = 0; +assign GPIO_T = 0; +always@(GPIO_I) +begin +if(GPIO_I !== 0) + $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* I2C */ +/* ------------------------------------------- */ + +assign I2C0_SDA_O = 0; +assign I2C0_SDA_T = 0; +assign I2C0_SCL_O = 0; +assign I2C0_SCL_T = 0; +assign I2C1_SDA_O = 0; +assign I2C1_SDA_T = 0; +assign I2C1_SCL_O = 0; +assign I2C1_SCL_T = 0; +always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I ) +begin + if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I) + $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* JTAG */ +/* ------------------------------------------- */ + +assign PJTAG_TD_T = 0; +assign PJTAG_TD_O = 0; +always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I) +begin + if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I) + $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SDIO */ +/* ------------------------------------------- */ + +assign SDIO0_CLK = 0; +assign SDIO0_CMD_O = 0; +assign SDIO0_CMD_T = 0; +assign SDIO0_DATA_O = 0; +assign SDIO0_DATA_T = 0; +assign SDIO0_LED = 0; +assign SDIO0_BUSPOW = 0; +assign SDIO0_BUSVOLT = 0; +always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP ) +begin + if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +assign SDIO1_CLK = 0; +assign SDIO1_CMD_O = 0; +assign SDIO1_CMD_T = 0; +assign SDIO1_DATA_O = 0; +assign SDIO1_DATA_T = 0; +assign SDIO1_LED = 0; +assign SDIO1_BUSPOW = 0; +assign SDIO1_BUSVOLT = 0; +always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP ) +begin + if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SPI */ +/* ------------------------------------------- */ + +assign SPI0_SCLK_O = 0; +assign SPI0_SCLK_T = 0; +assign SPI0_MOSI_O = 0; +assign SPI0_MOSI_T = 0; +assign SPI0_MISO_O = 0; +assign SPI0_MISO_T = 0; +assign SPI0_SS_O = 0; /// confirm +assign SPI0_SS1_O = 0;/// confirm +assign SPI0_SS2_O = 0;/// confirm +assign SPI0_SS_T = 0; +always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I) +begin + if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +assign SPI1_SCLK_O = 0; +assign SPI1_SCLK_T = 0; +assign SPI1_MOSI_O = 0; +assign SPI1_MOSI_T = 0; +assign SPI1_MISO_O = 0; +assign SPI1_MISO_T = 0; +assign SPI1_SS_O = 0; +assign SPI1_SS1_O = 0; +assign SPI1_SS2_O = 0; +assign SPI1_SS_T = 0; +always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I) +begin + if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* UART */ +/* ------------------------------------------- */ +/// confirm +assign UART0_DTRN = 0; +assign UART0_RTSN = 0; +assign UART0_TX = 0; +always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX) +begin + if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +assign UART1_DTRN = 0; +assign UART1_RTSN = 0; +assign UART1_TX = 0; +always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX) +begin + if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TTC */ +/* ------------------------------------------- */ + +assign TTC0_WAVE0_OUT = 0; +assign TTC0_WAVE1_OUT = 0; +assign TTC0_WAVE2_OUT = 0; +always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN) +begin + if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +assign TTC1_WAVE0_OUT = 0; +assign TTC1_WAVE1_OUT = 0; +assign TTC1_WAVE2_OUT = 0; +always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN) +begin + if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* WDT */ +/* ------------------------------------------- */ + +assign WDT_RST_OUT = 0; +always@(WDT_CLK_IN) +begin + if(WDT_CLK_IN) + $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TRACE */ +/* ------------------------------------------- */ + +assign TRACE_CTL = 0; +assign TRACE_DATA = 0; +always@(TRACE_CLK) +begin + if(TRACE_CLK) + $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* USB */ +/* ------------------------------------------- */ +assign USB0_PORT_INDCTL = 0; +assign USB0_VBUS_PWRSELECT = 0; +always@(USB0_VBUS_PWRFAULT) +begin + if(USB0_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +assign USB1_PORT_INDCTL = 0; +assign USB1_VBUS_PWRSELECT = 0; +always@(USB1_VBUS_PWRFAULT) +begin + if(USB1_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +always@(SRAM_INTIN) +begin + if(SRAM_INTIN) + $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DMA */ +/* ------------------------------------------- */ + +assign DMA0_DATYPE = 0; +assign DMA0_DAVALID = 0; +assign DMA0_DRREADY = 0; +assign DMA0_RSTN = 0; +always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE) +begin + if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA1_DATYPE = 0; +assign DMA1_DAVALID = 0; +assign DMA1_DRREADY = 0; +assign DMA1_RSTN = 0; +always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE) +begin + if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA2_DATYPE = 0; +assign DMA2_DAVALID = 0; +assign DMA2_DRREADY = 0; +assign DMA2_RSTN = 0; +always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE) +begin + if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA3_DATYPE = 0; +assign DMA3_DAVALID = 0; +assign DMA3_DRREADY = 0; +assign DMA3_RSTN = 0; +always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE) +begin + if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FTM */ +/* ------------------------------------------- */ + +assign FTMT_F2P_TRIGACK = 0; +assign FTMT_P2F_TRIG = 0; +assign FTMT_P2F_DEBUG = 0; +always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or + FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK) +begin + if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK) + $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* EVENT */ +/* ------------------------------------------- */ + +assign EVENT_EVENTO = 0; +assign EVENT_STANDBYWFE = 0; +assign EVENT_STANDBYWFI = 0; +always@(EVENT_EVENTI) +begin + if(EVENT_EVENTI) + $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MIO */ +/* ------------------------------------------- */ + +always@(MIO) +begin + if(MIO !== 0) + $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FCLK_TRIG */ +/* ------------------------------------------- */ + +always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N ) +begin + if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N ) + $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MISC */ +/* ------------------------------------------- */ + +always@(FPGA_IDLE_N) +begin + if(FPGA_IDLE_N) + $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR); +end + +always@(DDR_ARB) +begin + if(DDR_ARB !== 0) + $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR); +end + +always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ ) +begin + if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) + $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DDR */ +/* ------------------------------------------- */ + +assign DDR_WEB = 0; +always@(DDR_Clk or DDR_CS_n) +begin +if(!DDR_CS_n) + $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* IRQ_P2F */ +/* ------------------------------------------- */ + +assign IRQ_P2F_DMAC_ABORT = 0; +assign IRQ_P2F_DMAC0 = 0; +assign IRQ_P2F_DMAC1 = 0; +assign IRQ_P2F_DMAC2 = 0; +assign IRQ_P2F_DMAC3 = 0; +assign IRQ_P2F_DMAC4 = 0; +assign IRQ_P2F_DMAC5 = 0; +assign IRQ_P2F_DMAC6 = 0; +assign IRQ_P2F_DMAC7 = 0; +assign IRQ_P2F_SMC = 0; +assign IRQ_P2F_QSPI = 0; +assign IRQ_P2F_CTI = 0; +assign IRQ_P2F_GPIO = 0; +assign IRQ_P2F_USB0 = 0; +assign IRQ_P2F_ENET0 = 0; +assign IRQ_P2F_ENET_WAKE0 = 0; +assign IRQ_P2F_SDIO0 = 0; +assign IRQ_P2F_I2C0 = 0; +assign IRQ_P2F_SPI0 = 0; +assign IRQ_P2F_UART0 = 0; +assign IRQ_P2F_CAN0 = 0; +assign IRQ_P2F_USB1 = 0; +assign IRQ_P2F_ENET1 = 0; +assign IRQ_P2F_ENET_WAKE1 = 0; +assign IRQ_P2F_SDIO1 = 0; +assign IRQ_P2F_I2C1 = 0; +assign IRQ_P2F_SPI1 = 0; +assign IRQ_P2F_UART1 = 0; +assign IRQ_P2F_CAN1 = 0; diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v new file mode 100644 index 0000000..4700b2d --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v @@ -0,0 +1,978 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_afi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM + * from Cadence. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_afi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_REQ_DDR, + RD_REQ_OCM, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_BYTES, + RD_QOS, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + S_RDISSUECAP1_EN, + S_WRISSUECAP1_EN, + S_RCOUNT, + S_WCOUNT, + S_RACOUNT, + S_WACOUNT + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + + `include "processing_system7_bfm_v2_0_5_local_params.v" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter int_cntr_width = clogb2(max_outstanding_transactions)+1; + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_cache_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output [max_burst_bits-1:0] WR_DATA; + output [addr_width-1:0] WR_ADDR; + output [max_transfer_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM; + output reg[max_transfer_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR; + output [axi_qos_width-1:0] WR_QOS; + output reg [axi_qos_width-1:0] RD_QOS; + + input S_RDISSUECAP1_EN; + input S_WRISSUECAP1_EN; + + output [7:0] S_RCOUNT; + output [7:0] S_WCOUNT; + output [2:0] S_RACOUNT; + output [5:0] S_WACOUNT; + + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + + real s_aclk_period; + + cdn_axi3_slave_bfm #(slave_name, + data_bus_width, + address_bus_width, + id_bus_width, + slave_base_address, + (slave_high_address- slave_base_address), + max_outstanding_transactions, + 0, ///MEMORY_MODEL_MODE, + exclusive_access_supported) + slave (.ACLK (S_ACLK), + .ARESETn (S_RESETN), /// confirm this + // Write Address Channel + .AWID (S_AWID), + .AWADDR (S_AWADDR), + .AWLEN (S_AWLEN), + .AWSIZE (S_AWSIZE), + .AWBURST (S_AWBURST), + .AWLOCK (S_AWLOCK), + .AWCACHE (S_AWCACHE), + .AWPROT (S_AWPROT), + .AWVALID (net_AWVALID), + .AWREADY (S_AWREADY), + // Write Data Channel Signals. + .WID (S_WID), + .WDATA (S_WDATA), + .WSTRB (S_WSTRB), + .WLAST (S_WLAST), + .WVALID (net_WVALID), + .WREADY (S_WREADY), + // Write Response Channel Signals. + .BID (S_BID), + .BRESP (S_BRESP), + .BVALID (S_BVALID), + .BREADY (S_BREADY), + // Read Address Channel Signals. + .ARID (S_ARID), + .ARADDR (S_ARADDR), + .ARLEN (S_ARLEN), + .ARSIZE (S_ARSIZE), + .ARBURST (S_ARBURST), + .ARLOCK (S_ARLOCK), + .ARCACHE (S_ARCACHE), + .ARPROT (S_ARPROT), + .ARVALID (net_ARVALID), + .ARREADY (S_ARREADY), + // Read Data Channel Signals. + .RID (S_RID), + .RDATA (S_RDATA), + .RRESP (S_RRESP), + .RLAST (S_RLAST), + .RVALID (S_RVALID), + .RREADY (S_RREADY)); + + + wire wr_intr_fifo_full; + reg temp_wr_intr_fifo_full; + + /* Interconnect WR_FIFO model instance */ + processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR); + + /* Register the async 'full' signal to S_ACLK clock */ + always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full; + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* Internal nets/regs for calling slave BFM API's*/ + reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1]; + reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0; + real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received + + /* Address Write Channel handshake*/ + reg[int_cntr_width-1:0] aw_cnt = 0;// + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1]; + reg aw_flag [0:max_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1]; + reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* keep track of count values */ + reg[7:0] wcount; + reg[5:0] wacount; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + + always@(S_RESETN) + begin + if(S_RESETN) begin + @(posedge S_ACLK); + s_aclk_period = $time; + @(posedge S_ACLK); + s_aclk_period = $time - s_aclk_period; + end + end + /*--------------------------------------------------------------------------------*/ + + initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin + slave.set_channel_level_info(0); + slave.set_function_level_info(0); + end + slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + //if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* Set ARQoS to be used */ + task set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + ar_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_wr_lat_number = afi_wr_min; + AVG_CASE : get_wr_lat_number = afi_wr_avg; + WORST_CASE : get_wr_lat_number = afi_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min); + 2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg); + default : get_wr_lat_number = ($random()%60+ afi_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : get_rd_lat_number = afi_rd_min; + AVG_CASE : get_rd_lat_number = afi_rd_avg; + WORST_CASE : get_rd_lat_number = afi_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min); + 2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg); + default : get_rd_lat_number = ($random()%60+ afi_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + $stop; + end + end + + /*--------------------------------------------------------------------------------*/ + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0; + + assign S_WCOUNT = wcount; + assign S_WACOUNT = wacount; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic wrfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - wcount; + if(fifo_space_left < fifo_space_exp) + wrfifo_full = 1; + else + wrfifo_full = 0; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(S_AWVALID) begin + awvalid_receive_time[aw_time_cnt] = $time; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; + else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; + end + end + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + wacount = 0; + end else begin + if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin + slave.RECEIVE_WRITE_ADDRESS(0, + id_invalid, + awaddr[aw_cnt[int_cntr_width-2:0]], + awlen[aw_cnt[int_cntr_width-2:0]], + awsize[aw_cnt[int_cntr_width-2:0]], + awbrst[aw_cnt[int_cntr_width-2:0]], + awlock[aw_cnt[int_cntr_width-2:0]], + awcache[aw_cnt[int_cntr_width-2:0]], + awprot[aw_cnt[int_cntr_width-2:0]], + awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID. + aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1; + aw_cnt = aw_cnt + 1; + wacount = wacount + 1; + end // if (!aw_fifo_full) + end /// if else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin + if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + end + end else begin + if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + end + end /// if + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); + end + else if(decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bits-1:0] temp_wr_data; + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_fifo_wr_ptr = 0; + wcount = 0; + end else begin + enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; + wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0; + + bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]); + /* Fill AFI_WR_data FIFO */ + if(bresp === AXI_OK ) begin + if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ; + end + valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]; + end else + valid_data_bytes = 0; + temp_wr_data = aligned_wr_data; + wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes}; + wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1; + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + wr_delayed = 1'b0; + if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID + fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response + ); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + wr_latency_count = get_wr_lat_number(1); + end + end // else + end//always + /*--------------------------------------------------------------------------------*/ + + /* Write Response Channel handshake */ + reg wr_int_state; + /* Reading from the wr_fifo and sending to Interconnect fifo*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_int_state = 1'b0; + wr_bresp_cnt = 0; + wr_fifo_rd_ptr = 0; + end else begin + case(wr_int_state) + 1'b0 : begin + wr_int_state = 1'b0; + if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin + wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes + wr_int_state = 1'b1; + /* start filling the write response fifo at the same time */ + fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp + wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length + wacount = wacount - 1; + wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + end + end + 1'b1 : begin + wr_int_state = 0; + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + +/* READ CHANNELS */ +/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info + +/* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1]; + reg ar_flag [0:max_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1]; + reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_rresp; + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + + reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes + reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + reg [7:0] rcount; + reg [2:0] racount; + + wire rd_intr_fifo_full, rd_intr_fifo_empty; + wire read_fifo_empty; + + /* signals to communicate with interconnect RD_FIFO model */ + reg rd_req, invalid_rd_req; + + /* REad control Info + 56:25 : Address (32) + 24:22 : Size (3) + 21:20 : BRST (2) + 19:16 : LEN (4) + 15:10 : RID (6) + 9:8 : RRSP (2) + 7:0 : byte cnt (8) + */ + reg [rd_info_bits-1:0] read_control_info; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data; + reg temp_rd_intr_fifo_empty; + + processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR); + + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign S_RCOUNT = rcount; + assign S_RACOUNT = racount; + + /* Register the asynch signal empty coming from Interconnect READ FIFO */ + always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty; + + // FIFO_STATUS (only if AFI port) 1- full + function automatic rdfifo_full ; + input [axi_len_width:0] fifo_space_exp; + integer fifo_space_left; + begin + fifo_space_left = afi_fifo_locations - rcount; + if(fifo_space_left < fifo_space_exp) + rdfifo_full = 1; + else + rdfifo_full = 0; + end + endfunction + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(S_ARVALID) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID && S_ARREADY) begin + if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos; + else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; + end + end + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + racount = 0; + end else begin + if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full + slave.RECEIVE_READ_ADDRESS(0, + id_invalid, + araddr[ar_cnt[int_cntr_width-2:0]], + arlen[ar_cnt[int_cntr_width-2:0]], + arsize[ar_cnt[int_cntr_width-2:0]], + arbrst[ar_cnt[int_cntr_width-2:0]], + arlock[ar_cnt[int_cntr_width-2:0]], + arcache[ar_cnt[int_cntr_width-2:0]], + arprot[ar_cnt[int_cntr_width-2:0]], + arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID. + ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1; + ar_cnt = ar_cnt+1; + racount = racount + 1; + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg rd_fifo_state; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + rd_req = 0; + invalid_rd_req= 0; + RD_QOS = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + invalid_rd_req = 0; + if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition + ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0; + rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]); + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]]; + + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]]; + rd_fifo_state = WAIT_RD_VALID; + rd_req = 1; + racount = racount - 1; + read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes }; + wr_rresp_cnt = wr_rresp_cnt + 1; + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + rd_req = 0; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin + RD_REQ_DDR = 1'b0; + RD_REQ_OCM = 1'b0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* thread to fill in the AFI RD_FIFO */ + reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + reg tmp_state; + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + rcount = 0; + tmp_state = 0; + end else begin + case(tmp_state) + 0 : begin + tmp_state = 0; + if(!temp_rd_intr_fifo_empty) begin + rd_intr_fifo.read_mem(temp_rd_data); + tmp_state = 1; + end + end + 1 : begin + tmp_state = 1; + if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin + read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length + tmp_state = 0; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ + + reg[max_burst_bytes_width:0] rd_v_b; + reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes + reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + /* Read Data Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin + rd_delayed = 1; + end + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt] = 1'b0; + tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]]; + rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); + temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb]; + if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin + get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b); + temp_read_data = aligned_rd_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb]; + end + slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb], + tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], + tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb], + tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb], + tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb], + temp_read_data, + temp_read_rsp); + rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ; + rresp_time_cnt = rresp_time_cnt+1; + rd_latency_count = get_rd_lat_number(1); + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + end + end /// else + end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v new file mode 100644 index 0000000..2a22ee5 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v @@ -0,0 +1,151 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_hp0_1.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_hp0_1( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_dv_ddr_hp1, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp0; +input [max_burst_bits-1:0] wr_data_hp0; +input [addr_width-1:0] wr_addr_hp0; +input [max_burst_bytes_width:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [addr_width-1:0] rd_addr_hp0; +input [max_burst_bytes_width:0] rd_bytes_hp0; +output [max_burst_bits-1:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [max_burst_bits-1:0] wr_data_hp1; +input [addr_width-1:0] wr_addr_hp1; +input [max_burst_bytes_width:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [addr_width-1:0] rd_addr_hp1; +input [max_burst_bytes_width:0] rd_bytes_hp1; +output [max_burst_bits-1:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .prt_dv1(wr_dv_ddr_hp0), + .prt_dv2(wr_dv_ddr_hp1), + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_ack1(wr_ack_ddr_hp0), + .prt_ack2(wr_ack_ddr_hp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .prt_req1(rd_req_ddr_hp0), + .prt_req2(rd_req_ddr_hp1), + .prt_data1(rd_data_ddr_hp0), + .prt_data2(rd_data_ddr_hp1), + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_dv1(rd_dv_ddr_hp0), + .prt_dv2(rd_dv_ddr_hp1), + .prt_qos(ddr_rd_qos), + .prt_req(ddr_rd_req), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v new file mode 100644 index 0000000..b382764 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v @@ -0,0 +1,151 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_hp2_3.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between RD/WR requests from 2 ports. + * Used for modelling the Top_Interconnect switch. + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_hp2_3( + sw_clk, + rstn, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_dv_ddr_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + ddr_rd_qos, + ddr_wr_qos, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input sw_clk; +input rstn; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; +input [axi_qos_width-1:0] r_qos_hp3; +input [axi_qos_width-1:0] ddr_rd_qos; +input [axi_qos_width-1:0] ddr_wr_qos; + +output wr_ack_ddr_hp2; +input [max_burst_bits-1:0] wr_data_hp2; +input [addr_width-1:0] wr_addr_hp2; +input [max_burst_bytes_width:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [addr_width-1:0] rd_addr_hp2; +input [max_burst_bytes_width:0] rd_bytes_hp2; +output [max_burst_bits-1:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [max_burst_bits-1:0] wr_data_hp3; +input [addr_width-1:0] wr_addr_hp3; +input [max_burst_bytes_width:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [addr_width-1:0] rd_addr_hp3; +input [max_burst_bytes_width:0] rd_bytes_hp3; +output [max_burst_bits-1:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + + + + +processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_hp2), + .qos2(w_qos_hp3), + .prt_dv1(wr_dv_ddr_hp2), + .prt_dv2(wr_dv_ddr_hp3), + .prt_data1(wr_data_hp2), + .prt_data2(wr_data_hp3), + .prt_addr1(wr_addr_hp2), + .prt_addr2(wr_addr_hp3), + .prt_bytes1(wr_bytes_hp2), + .prt_bytes2(wr_bytes_hp3), + .prt_ack1(wr_ack_ddr_hp2), + .prt_ack2(wr_ack_ddr_hp3), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_hp2), + .qos2(r_qos_hp3), + .prt_req1(rd_req_ddr_hp2), + .prt_req2(rd_req_ddr_hp3), + .prt_data1(rd_data_ddr_hp2), + .prt_data2(rd_data_ddr_hp3), + .prt_addr1(rd_addr_hp2), + .prt_addr2(rd_addr_hp3), + .prt_bytes1(rd_bytes_hp2), + .prt_bytes2(rd_bytes_hp3), + .prt_dv1(rd_dv_ddr_hp2), + .prt_dv2(rd_dv_ddr_hp3), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v new file mode 100644 index 0000000..367518d --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v @@ -0,0 +1,154 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_rd.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 read requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_rd( + rstn, + sw_clk, + + qos1, + qos2, + + prt_req1, + prt_req2, + prt_bytes1, + prt_bytes2, + prt_addr1, + prt_addr2, + prt_data1, + prt_data2, + prt_dv1, + prt_dv2, + + prt_req, + prt_qos, + prt_addr, + prt_bytes, + prt_data, + prt_dv + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input prt_req1, prt_req2; +input [addr_width-1:0] prt_addr1, prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2; +output reg prt_dv1, prt_dv2; +output reg [max_burst_bits-1:0] prt_data1,prt_data2; + +output reg prt_req; +output reg [axi_qos_width-1:0] prt_qos; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +input [max_burst_bits-1:0] prt_data; +input prt_dv; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11; +reg [1:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_req = 0; + if(prt_req1 && !prt_req2) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(!prt_req1 && prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req1 && prt_req2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_addr = prt_addr2; + prt_qos = qos2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + if(prt_dv) begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + prt_req = 0; + if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + if(prt_dv) begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + prt_req = 0; + if(prt_req1) begin + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_dv_low; + //state = wait_req; + end + end + end + + wait_dv_low:begin + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + state = wait_dv_low; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd_4.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd_4.v new file mode 100644 index 0000000..7cb0eb5 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd_4.v @@ -0,0 +1,254 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_rd_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 read requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_rd_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_req1, + prt_req2, + prt_req3, + prt_req4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_dv + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv; +output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req; +input [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101; +reg [2:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_addr = prt_addr4; + prt_qos = qos4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv1 = 1'b1; + prt_data1 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_dv1 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv2 = 1'b1; + prt_data2 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_req4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + prt_req = 1; + prt_addr = prt_addr1; + prt_qos = qos1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv4 = 1'b0; + if(prt_dv)begin + prt_dv3 = 1'b1; + prt_data3 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_req1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + if(prt_dv)begin + prt_dv4 = 1'b1; + prt_data4 = prt_data; + //state = wait_req; + state = wait_dv_low; + prt_req = 1'b0; + if(prt_req1) begin + state = serv_req1; + prt_qos = qos1; + prt_req = 1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_req2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_req3) begin + prt_req = 1; + prt_addr = prt_addr3; + prt_qos = qos3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_dv_low:begin + state = wait_dv_low; + prt_dv1 = 1'b0; + prt_dv2 = 1'b0; + prt_dv3 = 1'b0; + prt_dv4 = 1'b0; + if(!prt_dv) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v new file mode 100644 index 0000000..a370fd4 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v @@ -0,0 +1,152 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_wr.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 2 write requests from 2 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_wr( + rstn, + sw_clk, + qos1, + qos2, + prt_dv1, + prt_dv2, + prt_data1, + prt_data2, + prt_addr1, + prt_addr2, + prt_bytes1, + prt_bytes2, + prt_ack1, + prt_ack2, + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2; +input [max_burst_bits-1:0] prt_data1,prt_data2; +input [addr_width-1:0] prt_addr1,prt_addr2; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2; +input prt_dv1, prt_dv2, prt_ack; +output reg prt_ack1,prt_ack2,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; + +parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11; +reg [1:0] state,temp_state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_req = 1'b0; + if(prt_dv1 && !prt_dv2) begin + state = serv_req1; + prt_req = 1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + prt_qos = qos1; + end else if(!prt_dv1 && prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv1 && prt_dv2) begin + if(qos1 > qos2) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else if(qos1 < qos2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + if(prt_ack) begin + prt_ack1 = 1'b1; + prt_req = 0; + if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end else begin + // state = wait_req; + state = wait_ack_low; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + if(prt_ack) begin + prt_ack2 = 1'b1; + prt_req = 0; + if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end else begin + state = wait_ack_low; + // state = wait_req; + end + end + end + wait_ack_low:begin + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + state = wait_ack_low; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v new file mode 100644 index 0000000..7dc6b7a --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v @@ -0,0 +1,265 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_arb_wr_4.v + * + * Date : 2012-11 + * + * Description : Module that arbitrates between 4 write requests from 4 ports. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_arb_wr_4( + rstn, + sw_clk, + + qos1, + qos2, + qos3, + qos4, + + prt_dv1, + prt_dv2, + prt_dv3, + prt_dv4, + + prt_data1, + prt_data2, + prt_data3, + prt_data4, + + prt_addr1, + prt_addr2, + prt_addr3, + prt_addr4, + + prt_bytes1, + prt_bytes2, + prt_bytes3, + prt_bytes4, + + prt_ack1, + prt_ack2, + prt_ack3, + prt_ack4, + + prt_qos, + prt_req, + prt_data, + prt_addr, + prt_bytes, + prt_ack + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" +input rstn, sw_clk; +input [axi_qos_width-1:0] qos1,qos2,qos3,qos4; +input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4; +input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4; +input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4; +input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack; +output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req; +output reg [max_burst_bits-1:0] prt_data; +output reg [addr_width-1:0] prt_addr; +output reg [max_burst_bytes_width:0] prt_bytes; +output reg [axi_qos_width-1:0] prt_qos; +parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101; +reg [2:0] state; + +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + state = wait_req; + prt_req = 1'b0; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_qos = 0; +end else begin + case(state) + wait_req:begin + state = wait_req; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + serv_req1:begin + state = serv_req1; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack1 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv2) begin + state = serv_req2; + prt_qos = qos2; + prt_req = 1; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + state = serv_req3; + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + state = serv_req4; + end + end + end + serv_req2:begin + state = serv_req2; + prt_ack1 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack2 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv3) begin + state = serv_req3; + prt_qos = qos3; + prt_req = 1; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + end else if(prt_dv4) begin + state = serv_req4; + prt_req = 1; + prt_qos = qos4; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + state = serv_req1; + end + end + end + serv_req3:begin + state = serv_req3; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack4 = 1'b0; + if(prt_ack)begin + prt_ack3 = 1'b1; +// state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv4) begin + state = serv_req4; + prt_qos = qos4; + prt_req = 1; + prt_data = prt_data4; + prt_addr = prt_addr4; + prt_bytes = prt_bytes4; + end else if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + state = serv_req2; + end + end + end + serv_req4:begin + state = serv_req4; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + if(prt_ack)begin + prt_ack4 = 1'b1; + //state = wait_req; + state = wait_ack_low; + prt_req = 0; + if(prt_dv1) begin + state = serv_req1; + prt_req = 1; + prt_qos = qos1; + prt_data = prt_data1; + prt_addr = prt_addr1; + prt_bytes = prt_bytes1; + end else if(prt_dv2) begin + state = serv_req2; + prt_req = 1; + prt_qos = qos2; + prt_data = prt_data2; + prt_addr = prt_addr2; + prt_bytes = prt_bytes2; + end else if(prt_dv3) begin + prt_req = 1; + prt_qos = qos3; + prt_data = prt_data3; + prt_addr = prt_addr3; + prt_bytes = prt_bytes3; + state = serv_req3; + end + end + end + wait_ack_low:begin + state = wait_ack_low; + prt_ack1 = 1'b0; + prt_ack2 = 1'b0; + prt_ack3 = 1'b0; + prt_ack4 = 1'b0; + if(!prt_ack) + state = wait_req; + end + endcase +end /// if else +end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v new file mode 100644 index 0000000..b593c79 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v @@ -0,0 +1,679 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_axi_master.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Master port interface. + * It uses AXI3 Master BFM + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_axi_master ( + M_RESETN, + M_ARVALID, + M_AWVALID, + M_BREADY, + M_RREADY, + M_WLAST, + M_WVALID, + M_ARID, + M_AWID, + M_WID, + M_ARBURST, + M_ARLOCK, + M_ARSIZE, + M_AWBURST, + M_AWLOCK, + M_AWSIZE, + M_ARPROT, + M_AWPROT, + M_ARADDR, + M_AWADDR, + M_WDATA, + M_ARCACHE, + M_ARLEN, + M_AWCACHE, + M_AWLEN, + M_ARQOS, // not connected to AXI BFM + M_AWQOS, // not connected to AXI BFM + M_WSTRB, + M_ACLK, + M_ARREADY, + M_AWREADY, + M_BVALID, + M_RLAST, + M_RVALID, + M_WREADY, + M_BID, + M_RID, + M_BRESP, + M_RRESP, + M_RDATA + +); + parameter enable_this_port = 0; + parameter master_name = "Master"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter EXCL_ID = 12'hC00; + `include "processing_system7_bfm_v2_0_5_local_params.v" + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + + input M_RESETN; + + output M_ARVALID; + output M_AWVALID; + output M_BREADY; + output M_RREADY; + output M_WLAST; + output M_WVALID; + output [id_bus_width-1:0] M_ARID; + output [id_bus_width-1:0] M_AWID; + output [id_bus_width-1:0] M_WID; + output [axi_brst_type_width-1:0] M_ARBURST; + output [axi_lock_width-1:0] M_ARLOCK; + output [axi_size_width-1:0] M_ARSIZE; + output [axi_brst_type_width-1:0] M_AWBURST; + output [axi_lock_width-1:0] M_AWLOCK; + output [axi_size_width-1:0] M_AWSIZE; + output [axi_prot_width-1:0] M_ARPROT; + output [axi_prot_width-1:0] M_AWPROT; + output [address_bus_width-1:0] M_ARADDR; + output [address_bus_width-1:0] M_AWADDR; + output [data_bus_width-1:0] M_WDATA; + output [axi_cache_width-1:0] M_ARCACHE; + output [axi_len_width-1:0] M_ARLEN; + output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM + output [axi_cache_width-1:0] M_AWCACHE; + output [axi_len_width-1:0] M_AWLEN; + output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM + output [(data_bus_width/8)-1:0] M_WSTRB; + input M_ACLK; + input M_ARREADY; + input M_AWREADY; + input M_BVALID; + input M_RLAST; + input M_RVALID; + input M_WREADY; + input [id_bus_width-1:0] M_BID; + input [id_bus_width-1:0] M_RID; + input [axi_rsp_width-1:0] M_BRESP; + input [axi_rsp_width-1:0] M_RRESP; + input [data_bus_width-1:0] M_RDATA; + + wire net_RESETN; + wire net_RVALID; + wire net_BVALID; + reg DEBUG_INFO = 1'b1; + reg STOP_ON_ERROR = 1'b1; + + integer use_id_no = 0; + + assign M_ARQOS = 'b0; + assign M_AWQOS = 'b0; + assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0; + assign net_RVALID = enable_this_port ? M_RVALID : 1'b0; + assign net_BVALID = enable_this_port ? M_BVALID : 1'b0; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name); + end + end + + initial master.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge M_ACLK); + if(!enable_this_port) begin + master.set_channel_level_info(0); + master.set_function_level_info(0); + end + master.RESPONSE_TIMEOUT = 0; + end + + cdn_axi3_master_bfm #(master_name, + data_bus_width, + address_bus_width, + id_bus_width, + max_outstanding_transactions, + exclusive_access_supported) + + master (.ACLK (M_ACLK), + .ARESETn (net_RESETN), /// confirm this + // Write Address Channel + .AWID (M_AWID), + .AWADDR (M_AWADDR), + .AWLEN (M_AWLEN), + .AWSIZE (M_AWSIZE), + .AWBURST (M_AWBURST), + .AWLOCK (M_AWLOCK), + .AWCACHE (M_AWCACHE), + .AWPROT (M_AWPROT), + .AWVALID (M_AWVALID), + .AWREADY (M_AWREADY), + // Write Data Channel Signals. + .WID (M_WID), + .WDATA (M_WDATA), + .WSTRB (M_WSTRB), + .WLAST (M_WLAST), + .WVALID (M_WVALID), + .WREADY (M_WREADY), + // Write Response Channel Signals. + .BID (M_BID), + .BRESP (M_BRESP), + .BVALID (net_BVALID), + .BREADY (M_BREADY), + // Read Address Channel Signals. + .ARID (M_ARID), + .ARADDR (M_ARADDR), + .ARLEN (M_ARLEN), + .ARSIZE (M_ARSIZE), + .ARBURST (M_ARBURST), + .ARLOCK (M_ARLOCK), + .ARCACHE (M_ARCACHE), + .ARPROT (M_ARPROT), + .ARVALID (M_ARVALID), + .ARREADY (M_ARREADY), + // Read Data Channel Signals. + .RID (M_RID), + .RDATA (M_RDATA), + .RRESP (M_RRESP), + .RLAST (M_RLAST), + .RVALID (net_RVALID), + .RREADY (M_RREADY)); + + +/* Call to BFM APIs */ +task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.READ_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,response); + else + master.READ_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.WRITE_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); + else + master.WRITE_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + if(enable_this_port)begin + if(lck !== AXI_NRML) + master.WRITE_BURST_CONCURRENT(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response); + else + master.WRITE_BURST_CONCURRENT(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response); + end else begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end +endtask + +/* local */ +function automatic[id_bus_width-1:0] get_id; +input dummy; +begin + case(use_id_no) + // l2m1 (CPU000) + 0 : get_id = 12'b11_000_000_00_00; + 1 : get_id = 12'b11_010_000_00_00; + 2 : get_id = 12'b11_011_000_00_00; + 3 : get_id = 12'b11_100_000_00_00; + 4 : get_id = 12'b11_101_000_00_00; + 5 : get_id = 12'b11_110_000_00_00; + 6 : get_id = 12'b11_111_000_00_00; + // l2m1 (CPU001) + 7 : get_id = 12'b11_000_001_00_00; + 8 : get_id = 12'b11_010_001_00_00; + 9 : get_id = 12'b11_011_001_00_00; + 10 : get_id = 12'b11_100_001_00_00; + 11 : get_id = 12'b11_101_001_00_00; + 12 : get_id = 12'b11_110_001_00_00; + 13 : get_id = 12'b11_111_001_00_00; + endcase + if(use_id_no == 13) + use_id_no = 0; + else + use_id_no = use_id_no+1; +end +endfunction + +/* Write data from file */ +task automatic write_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] wr_size; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] wresp,rwrsp; +reg [addr_width-1:0] addr; +reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data; +integer bytes; +integer trnsfr_bytes; +integer wr_fd; +integer succ; +integer trnsfr_lngth; +reg concurrent; + +reg [id_bus_width-1:0] wr_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + bytes = wr_size; + wresp = 0; + concurrent = $random; + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_bytes = (axi_burst_len * data_bus_width/8); + else + trnsfr_bytes = bytes; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + wr_id = get_id(1); + wr_fd = $fopen(file_name,"r"); + + while (bytes > 0) begin + repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction + wr_data = wr_data >> data_bus_width; + succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) .. + end + if(concurrent) + master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); + else + master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes >= (axi_burst_len * data_bus_width/8) ) + trnsfr_bytes = (axi_burst_len * data_bus_width/8); // + else + trnsfr_bytes = bytes; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + wresp = wresp | rwrsp; + end /// while + response = wresp; +end +end +endtask + +/* Read data to file */ +task automatic read_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] rd_size; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] rresp, rrrsp; +reg [addr_width-1:0] addr; +integer bytes; +integer trnsfr_lngth; +reg [(axi_burst_len*data_bus_width)-1 :0] rd_data; +integer rd_fd; +reg [id_bus_width-1:0] rd_id; + +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + + addr = start_addr; + rresp = 0; + bytes = rd_size; + + rd_id = get_id(1'b1); + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + rd_fd = $fopen(file_name,"w"); + + while (bytes > 0) begin + master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp); + repeat(trnsfr_lngth+1) begin + $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]); + rd_data = rd_data >> data_bus_width; + end + + addr = addr + (trnsfr_lngth+1)*4; + + if(bytes >= (axi_burst_len * data_bus_width/8) ) + bytes = bytes - (axi_burst_len * data_bus_width/8); // + else + bytes = 0; + + if(bytes > (axi_burst_len * data_bus_width/8)) + trnsfr_lngth = axi_burst_len-1; + else if(bytes%(data_bus_width/8) == 0) + trnsfr_lngth = bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = bytes/(data_bus_width/8); + + rresp = rresp | rrrsp; + end /// while + response = rresp; +end +end +endtask + +/* Write data (used for transfer size <= 128 Bytes */ +task automatic write_data; +input [addr_width-1:0] start_addr; +input [max_transfer_bytes_width:0] wr_size; +input [(max_transfer_bytes*8)-1:0] w_data; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] wresp,rwrsp; +reg [addr_width-1:0] addr; +reg [7:0] bytes,tmp_bytes; +integer trnsfr_bytes; +reg [(max_transfer_bytes*8)-1:0] wr_data; +integer trnsfr_lngth; +reg concurrent; + +reg [id_bus_width-1:0] wr_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; + +integer pad_bytes; +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + addr = start_addr; + bytes = wr_size; + wresp = 0; + wr_data = w_data; + concurrent = $random; + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + wr_id = get_id(1); + if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address + trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + + while (bytes > 0) begin + if(concurrent) + master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); + else + master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp); + wr_data = wr_data >> (trnsfr_bytes*8); + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + wresp = wresp | rwrsp; + end /// while + response = wresp; +end +end +endtask + +/* Read data (used for transfer size <= 128 Bytes */ +task automatic read_data; +input [addr_width-1:0] start_addr; +input [max_transfer_bytes_width:0] rd_size; +output [(max_transfer_bytes*8)-1:0] r_data; +output [axi_rsp_width-1:0] response; +reg [axi_rsp_width-1:0] rresp,rdrsp; +reg [addr_width-1:0] addr; +reg [max_transfer_bytes_width:0] bytes,tmp_bytes; +integer trnsfr_bytes; +reg [(max_transfer_bytes*8)-1 : 0] rd_data; +reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data; +integer total_rcvd_bytes; +integer trnsfr_lngth; +integer i; +reg [id_bus_width-1:0] rd_id; + +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; + +integer pad_bytes; + +begin +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; +end else begin + addr = start_addr; + bytes = rd_size; + rresp = 0; + total_rcvd_bytes = 0; + rd_data = 0; + rd_id = get_id(1'b1); + + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0]; + + if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = axi_burst_len-1; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + while (bytes > 0) begin + master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp); + for(i = 0; i < trnsfr_bytes; i = i+1) begin + rd_data = rd_data >> 8; + rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0]; + rcv_rd_data = rcv_rd_data >> 8; + total_rcvd_bytes = total_rcvd_bytes+1; + end + bytes = bytes - trnsfr_bytes; + addr = addr + trnsfr_bytes; + if(bytes > (axi_burst_len * data_bus_width/8)) begin + trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; + trnsfr_lngth = 15; + end else begin + trnsfr_bytes = bytes; + tmp_bytes = bytes + pad_bytes;//start_addr[1:0]; + if(tmp_bytes%(data_bus_width/8) == 0) + trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1; + else + trnsfr_lngth = tmp_bytes/(data_bus_width/8); + end + rresp = rresp | rdrsp; + end /// while + rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8; + r_data = rd_data; + response = rresp; +end +end +endtask + + +/* Wait Register Update in PL */ +/* Issue a series of 1 burst length reads until the expected data pattern is received */ + +task automatic wait_reg_update; +input [addr_width-1:0] addri; +input [data_width-1:0] datai; +input [data_width-1:0] maski; +input [int_width-1:0] time_interval; +input [int_width-1:0] time_out; +output [data_width-1:0] data_o; +output upd_done; + +reg [addr_width-1:0] addr; +reg [data_width-1:0] data_i; +reg [data_width-1:0] mask_i; +integer time_int; +integer timeout; + +reg [axi_rsp_width-1:0] rdrsp; +reg [id_bus_width-1:0] rd_id; +reg [axi_size_width-1:0] siz; +reg [axi_brst_type_width-1:0] burst; +reg [axi_lock_width-1:0] lck; +reg [axi_cache_width-1:0] cache; +reg [axi_prot_width-1:0] prot; +reg [data_width-1:0] rcv_data; +integer trnsfr_lngth; +reg rd_loop; +reg timed_out; +integer i; +integer cycle_cnt; + +begin +addr = addri; +data_i = datai; +mask_i = maski; +time_int = time_interval; +timeout = time_out; +timed_out = 0; +cycle_cnt = 0; + +if(!enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name); + upd_done = 0; + if(STOP_ON_ERROR) $stop; +end else begin + rd_id = get_id(1'b1); + siz = 2; + burst = 1; + lck = 0; + cache = 0; + prot = 0; + trnsfr_lngth = 0; + rd_loop = 1; + fork + begin + while(!timed_out & rd_loop) begin + cycle_cnt = cycle_cnt + 1; + if(cycle_cnt >= timeout) timed_out = 1; + @(posedge M_ACLK); + end + end + begin + while (rd_loop) begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr); + master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp); + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data); + if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out) + rd_loop = 0; + else + repeat(time_int) @(posedge M_ACLK); + end /// while + end + join + data_o = rcv_data & ~mask_i; + if(timed_out) begin + $display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name); + if(STOP_ON_ERROR) $stop; + end else + upd_done = 1; +end +end +endtask + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v new file mode 100644 index 0000000..ad66e5c --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v @@ -0,0 +1,935 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_axi_slave.v + * + * Date : 2012-11 + * + * Description : Model that acts as PS AXI Slave port interface. + * It uses AXI3 Slave BFM + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_axi_slave ( + S_RESETN, + + S_ARREADY, + S_AWREADY, + S_BVALID, + S_RLAST, + S_RVALID, + S_WREADY, + S_BRESP, + S_RRESP, + S_RDATA, + S_BID, + S_RID, + S_ACLK, + S_ARVALID, + S_AWVALID, + S_BREADY, + S_RREADY, + S_WLAST, + S_WVALID, + S_ARBURST, + S_ARLOCK, + S_ARSIZE, + S_AWBURST, + S_AWLOCK, + S_AWSIZE, + S_ARPROT, + S_AWPROT, + S_ARADDR, + S_AWADDR, + S_WDATA, + S_ARCACHE, + S_ARLEN, + S_AWCACHE, + S_AWLEN, + S_WSTRB, + S_ARID, + S_AWID, + S_WID, + + S_AWQOS, + S_ARQOS, + + SW_CLK, + WR_DATA_ACK_OCM, + WR_DATA_ACK_DDR, + WR_ADDR, + WR_DATA, + WR_BYTES, + WR_DATA_VALID_OCM, + WR_DATA_VALID_DDR, + WR_QOS, + + RD_QOS, + RD_REQ_DDR, + RD_REQ_OCM, + RD_REQ_REG, + RD_ADDR, + RD_DATA_OCM, + RD_DATA_DDR, + RD_DATA_REG, + RD_BYTES, + RD_DATA_VALID_OCM, + RD_DATA_VALID_DDR, + RD_DATA_VALID_REG + +); + parameter enable_this_port = 0; + parameter slave_name = "Slave"; + parameter data_bus_width = 32; + parameter address_bus_width = 32; + parameter id_bus_width = 6; + parameter slave_base_address = 0; + parameter slave_high_address = 4; + parameter max_outstanding_transactions = 8; + parameter exclusive_access_supported = 0; + parameter max_wr_outstanding_transactions = 8; + parameter max_rd_outstanding_transactions = 8; + + `include "processing_system7_bfm_v2_0_5_local_params.v" + + /* Local parameters only for this module */ + /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles. + This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported. + 1-bit extra width than the no.of.bits needed to represent the outstanding transactions + Extra bit helps in generating the empty and full flags + */ + parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1); + parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1); + + /* RESP data */ + parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; + parameter rsp_lsb = 0; + parameter rsp_msb = axi_rsp_width-1; + parameter rsp_id_lsb = rsp_msb + 1; + parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1; + + input S_RESETN; + + output S_ARREADY; + output S_AWREADY; + output S_BVALID; + output S_RLAST; + output S_RVALID; + output S_WREADY; + output [axi_rsp_width-1:0] S_BRESP; + output [axi_rsp_width-1:0] S_RRESP; + output [data_bus_width-1:0] S_RDATA; + output [id_bus_width-1:0] S_BID; + output [id_bus_width-1:0] S_RID; + input S_ACLK; + input S_ARVALID; + input S_AWVALID; + input S_BREADY; + input S_RREADY; + input S_WLAST; + input S_WVALID; + input [axi_brst_type_width-1:0] S_ARBURST; + input [axi_lock_width-1:0] S_ARLOCK; + input [axi_size_width-1:0] S_ARSIZE; + input [axi_brst_type_width-1:0] S_AWBURST; + input [axi_lock_width-1:0] S_AWLOCK; + input [axi_size_width-1:0] S_AWSIZE; + input [axi_prot_width-1:0] S_ARPROT; + input [axi_prot_width-1:0] S_AWPROT; + input [address_bus_width-1:0] S_ARADDR; + input [address_bus_width-1:0] S_AWADDR; + input [data_bus_width-1:0] S_WDATA; + input [axi_cache_width-1:0] S_ARCACHE; + input [axi_cache_width-1:0] S_ARLEN; + + input [axi_qos_width-1:0] S_ARQOS; + + input [axi_cache_width-1:0] S_AWCACHE; + input [axi_len_width-1:0] S_AWLEN; + + input [axi_qos_width-1:0] S_AWQOS; + input [(data_bus_width/8)-1:0] S_WSTRB; + input [id_bus_width-1:0] S_ARID; + input [id_bus_width-1:0] S_AWID; + input [id_bus_width-1:0] S_WID; + + input SW_CLK; + input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; + output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; + output reg [max_burst_bits-1:0] WR_DATA; + output reg [addr_width-1:0] WR_ADDR; + output reg [max_burst_bytes_width:0] WR_BYTES; + output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG; + output reg [addr_width-1:0] RD_ADDR; + input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG; + output reg[max_burst_bytes_width:0] RD_BYTES; + input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG; + output reg [axi_qos_width-1:0] WR_QOS, RD_QOS; + wire net_ARVALID; + wire net_AWVALID; + wire net_WVALID; + + real s_aclk_period; + + cdn_axi3_slave_bfm #(slave_name, + data_bus_width, + address_bus_width, + id_bus_width, + slave_base_address, + (slave_high_address- slave_base_address), + max_outstanding_transactions, + 0, ///MEMORY_MODEL_MODE, + exclusive_access_supported) + slave (.ACLK (S_ACLK), + .ARESETn (S_RESETN), /// confirm this + // Write Address Channel + .AWID (S_AWID), + .AWADDR (S_AWADDR), + .AWLEN (S_AWLEN), + .AWSIZE (S_AWSIZE), + .AWBURST (S_AWBURST), + .AWLOCK (S_AWLOCK), + .AWCACHE (S_AWCACHE), + .AWPROT (S_AWPROT), + .AWVALID (net_AWVALID), + .AWREADY (S_AWREADY), + // Write Data Channel Signals. + .WID (S_WID), + .WDATA (S_WDATA), + .WSTRB (S_WSTRB), + .WLAST (S_WLAST), + .WVALID (net_WVALID), + .WREADY (S_WREADY), + // Write Response Channel Signals. + .BID (S_BID), + .BRESP (S_BRESP), + .BVALID (S_BVALID), + .BREADY (S_BREADY), + // Read Address Channel Signals. + .ARID (S_ARID), + .ARADDR (S_ARADDR), + .ARLEN (S_ARLEN), + .ARSIZE (S_ARSIZE), + .ARBURST (S_ARBURST), + .ARLOCK (S_ARLOCK), + .ARCACHE (S_ARCACHE), + .ARPROT (S_ARPROT), + .ARVALID (net_ARVALID), + .ARREADY (S_ARREADY), + // Read Data Channel Signals. + .RID (S_RID), + .RDATA (S_RDATA), + .RRESP (S_RRESP), + .RLAST (S_RLAST), + .RVALID (S_RVALID), + .RREADY (S_RREADY)); + + /* Latency type and Debug/Error Control */ + reg[1:0] latency_type = RANDOM_CASE; + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1'b1; + + /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */ + reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1]; + reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0; + wire wr_fifo_empty; + + /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/ + reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0; + real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received + reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received + + /* Address Write Channel handshake*/ + reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1]; + reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1]; + reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1]; + reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1]; + reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1]; + reg aw_flag [0:max_wr_outstanding_transactions-1]; + reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1]; + reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1]; + reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1]; + wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached) + + /* internal fifos to store burst write data, ID & strobes*/ + reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1]; + reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer + reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received + wire wd_fifo_full; + + /* Write Data Channel and Write Response handshake signals*/ + reg [int_wr_cntr_width-1:0] wd_cnt = 0; + reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data; + reg [addr_width-1:0] aligned_wr_addr; + reg [max_burst_bytes_width:0] valid_data_bytes; + reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0; + reg [axi_rsp_width-1:0] bresp; + reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response + reg enable_write_bresp; + reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0; + integer wr_latency_count; + reg wr_delayed; + wire bresp_fifo_empty; + + /* states for managing read/write to WR_FIFO */ + parameter SEND_DATA = 0, WAIT_ACK = 1; + reg state; + + /* Qos*/ + reg [axi_qos_width-1:0] ar_qos, aw_qos; + + initial begin + if(DEBUG_INFO) begin + if(enable_this_port) + $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name); + else + $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name); + end + end + + initial slave.set_disable_reset_value_checks(1); + initial begin + repeat(2) @(posedge S_ACLK); + if(!enable_this_port) begin + slave.set_channel_level_info(0); + slave.set_function_level_info(0); + end + slave.RESPONSE_TIMEOUT = 0; + end + /*--------------------------------------------------------------------------------*/ + + /* Set Latency type to be used */ + task set_latency_type; + input[1:0] lat; + begin + if(enable_this_port) + latency_type = lat; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set ARQoS to be used */ + task set_arqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + ar_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name); + end + + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Set AWQoS to be used */ + task set_awqos; + input[axi_qos_width-1:0] qos; + begin + if(enable_this_port) + aw_qos = qos; + else begin + if(DEBUG_INFO) + $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name); + end + end + endtask + /*--------------------------------------------------------------------------------*/ + /* get the wr latency number */ + function [31:0] get_wr_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min; + AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); + 2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); + default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* get the rd latency number */ + function [31:0] get_rd_lat_number; + input dummy; + reg[1:0] temp; + begin + case(latency_type) + BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min; + AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg; + WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max; + default : begin // RANDOM_CASE + temp = $random; + case(temp) + 2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); + 2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); + default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); + endcase + end + endcase + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Clock cycle time period */ + always@(S_RESETN) + begin + if(S_RESETN) begin + @(posedge S_ACLK); + s_aclk_period = $time; + @(posedge S_ACLK); + s_aclk_period = $time - s_aclk_period; + end + end + /*--------------------------------------------------------------------------------*/ + + /* Check for any WRITE/READs when this port is disabled */ + always@(S_AWVALID or S_WVALID or S_ARVALID) + begin + if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin + $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name); + $stop; + end + end + + /*--------------------------------------------------------------------------------*/ + + + assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0; + assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0; + assign net_WVALID = enable_this_port ? S_WVALID : 1'b0; + + assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0; + assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this + assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0; + + + /* Store the awvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID ) + begin + if(!S_RESETN) + aw_time_cnt = 0; + else begin + if(S_AWVALID) begin + awvalid_receive_time[aw_time_cnt] = $time; + awvalid_flag[aw_time_cnt] = 1'b1; + aw_time_cnt = aw_time_cnt + 1; + if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_AWVALID && S_AWREADY) begin + if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; + else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(aw_fifo_full) + begin + if(aw_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Write Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + aw_cnt = 0; + end else begin + if(!aw_fifo_full) begin + slave.RECEIVE_WRITE_ADDRESS(0, + id_invalid, + awaddr[aw_cnt[int_wr_cntr_width-2:0]], + awlen[aw_cnt[int_wr_cntr_width-2:0]], + awsize[aw_cnt[int_wr_cntr_width-2:0]], + awbrst[aw_cnt[int_wr_cntr_width-2:0]], + awlock[aw_cnt[int_wr_cntr_width-2:0]], + awcache[aw_cnt[int_wr_cntr_width-2:0]], + awprot[aw_cnt[int_wr_cntr_width-2:0]], + awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID. + aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1; + aw_cnt = aw_cnt + 1; + if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1]; + aw_cnt[int_wr_cntr_width-2:0] = 0; + end + end // if (!aw_fifo_full) + end /// if else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Write Data Channel Handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wd_cnt = 0; + end else begin + if(!wd_fifo_full && S_WVALID) begin + slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, + burst_data[wd_cnt[int_wr_cntr_width-2:0]], + burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]); + wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1; + wd_cnt = wd_cnt + 1; + if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1]; + wd_cnt[int_wr_cntr_width-2:0] = 0; + end + end /// if + end /// else + end /// always + /*--------------------------------------------------------------------------------*/ + + /* Align the wrap data for write transaction */ + task automatic get_wrap_aligned_wr_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + output [addr_width-1:0] start_addr; /// aligned start address + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8)); + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data << 8; + temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8]; + wrp_data = wrp_data << 8; + wrp_bytes = wrp_bytes - 1; + end + wrp_bytes = addr - start_addr; + wrp_data = b_data << (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + /* Calculate the Response for each read/write transaction */ + function [axi_rsp_width-1:0] calculate_resp; + input rd_wr; // indicates Read(1) or Write(0) transaction + input [addr_width-1:0] awaddr; + input [axi_prot_width-1:0] awprot; + reg [axi_rsp_width-1:0] rsp; + begin + rsp = AXI_OK; + /* Address Decode */ + if(decode_address(awaddr) === INVALID_MEM_TYPE) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr); + end + if(!rd_wr && decode_address(awaddr) === REG_MEM) begin + rsp = AXI_SLV_ERR; //slave error + $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr); + end + if(secure_access_enabled && awprot[1]) + rsp = AXI_DEC_ERR; // decode error + calculate_resp = rsp; + end + endfunction + /*--------------------------------------------------------------------------------*/ + + /* Store the Write response for each write transaction */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + wr_bresp_cnt = 0; + wr_fifo_wr_ptr = 0; + end else begin + enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + /* calculate bresp only when AWVALID && WLAST is received */ + if(enable_write_bresp) begin + aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0; + + bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]); + fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp}; + /* Fill WR data FIFO */ + if(bresp === AXI_OK) begin + if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data + get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address + end else begin + aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ; + end + valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]; + end else + valid_data_bytes = 0; + + wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes}; + wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; + wr_bresp_cnt = wr_bresp_cnt+1; + if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1]; + wr_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + end + end // else + end // always + /*--------------------------------------------------------------------------------*/ + + /* Send Write Response Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + rd_bresp_cnt = 0; + wr_latency_count = get_wr_lat_number(1); + wr_delayed = 0; + bresp_time_cnt = 0; + end else begin + wr_delayed = 1'b0; + if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count)) + wr_delayed = 1; + if(!bresp_fifo_empty && wr_delayed) begin + slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID + fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response + ); + wr_delayed = 0; + awvalid_flag[bresp_time_cnt] = 1'b0; + bresp_time_cnt = bresp_time_cnt+1; + rd_bresp_cnt = rd_bresp_cnt + 1; + if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin + rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1]; + rd_bresp_cnt[int_wr_cntr_width-2:0] = 0; + end + if(bresp_time_cnt === max_wr_outstanding_transactions) begin + bresp_time_cnt = 0; + end + wr_latency_count = get_wr_lat_number(1); + end + end // else + end//always + /*--------------------------------------------------------------------------------*/ + + /* Reading from the wr_fifo */ + always@(negedge S_RESETN or posedge SW_CLK) begin + if(!S_RESETN) begin + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + wr_fifo_rd_ptr = 0; + state = SEND_DATA; + WR_QOS = 0; + end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 0; + WR_DATA_VALID_DDR = 0; + if(!wr_fifo_empty) begin + WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb]; + state = WAIT_ACK; + case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + wr_fifo_rd_ptr = wr_fifo_rd_ptr+1; + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase + end + end + /*--------------------------------------------------------------------------------*/ +/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/ + +/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/ + + /* READ CHANNELS */ + /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */ + reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0; + real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received + reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info + + /* various FIFOs for storing the ADDR channel info */ + reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1]; + reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1]; + reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1]; + reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1]; + reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1]; + reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1]; + reg ar_flag [0:max_rd_outstanding_transactions-1]; + reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1]; + reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1]; + reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1]; + wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached) + + reg [int_rd_cntr_width-1:0] rd_cnt = 0; + reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0; + reg [axi_rsp_width-1:0] rresp; + reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response + + /* Send Read Response & Data Channel handshake */ + integer rd_latency_count; + reg rd_delayed; + + reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data .. + reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0; + wire read_fifo_full; + + assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0; + assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0; + assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0; + + /* Store the arvalid receive time --- necessary for calculating the bresp latency */ + always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID ) + begin + if(!S_RESETN) + ar_time_cnt = 0; + else begin + if(S_ARVALID) begin + arvalid_receive_time[ar_time_cnt] = $time; + arvalid_flag[ar_time_cnt] = 1'b1; + ar_time_cnt = ar_time_cnt + 1; + if(ar_time_cnt === max_rd_outstanding_transactions) + ar_time_cnt = 0; + end + end // else + end /// always + /*--------------------------------------------------------------------------------*/ + always@(posedge S_ACLK) + begin + if(net_ARVALID && S_ARREADY) begin + if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos; + else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; + end + end + /*--------------------------------------------------------------------------------*/ + + always@(ar_fifo_full) + begin + if(ar_fifo_full && DEBUG_INFO) + $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions); + end + /*--------------------------------------------------------------------------------*/ + + /* Address Read Channel handshake*/ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN) begin + ar_cnt = 0; + end else begin + if(!ar_fifo_full) begin + slave.RECEIVE_READ_ADDRESS(0, + id_invalid, + araddr[ar_cnt[int_rd_cntr_width-2:0]], + arlen[ar_cnt[int_rd_cntr_width-2:0]], + arsize[ar_cnt[int_rd_cntr_width-2:0]], + arbrst[ar_cnt[int_rd_cntr_width-2:0]], + arlock[ar_cnt[int_rd_cntr_width-2:0]], + arcache[ar_cnt[int_rd_cntr_width-2:0]], + arprot[ar_cnt[int_rd_cntr_width-2:0]], + arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID. + ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1; + ar_cnt = ar_cnt+1; + if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin + ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1]; + ar_cnt[int_rd_cntr_width-2:0] = 0; + end + end /// if(!ar_fifo_full) + end /// if else + end /// always*/ + /*--------------------------------------------------------------------------------*/ + + /* Align Wrap data for read transaction*/ + task automatic get_wrap_aligned_rd_data; + output [(data_bus_width*axi_burst_len)-1:0] aligned_data; + input [addr_width-1:0] addr; + input [(data_bus_width*axi_burst_len)-1:0] b_data; + input [max_burst_bytes_width:0] v_bytes; + reg [addr_width-1:0] start_addr; + reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data; + integer wrp_bytes; + integer i; + begin + start_addr = (addr/v_bytes) * v_bytes; + wrp_bytes = addr - start_addr; + wrp_data = b_data; + temp_data = 0; + while(wrp_bytes > 0) begin /// get the data that is wrapped + temp_data = temp_data >> 8; + temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0]; + wrp_data = wrp_data >> 8; + wrp_bytes = wrp_bytes - 1; + end + temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8)); + wrp_bytes = addr - start_addr; + wrp_data = b_data >> (wrp_bytes*8); + + aligned_data = (temp_data | wrp_data); + end + endtask + /*--------------------------------------------------------------------------------*/ + + parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1; + reg [addr_width-1:0] temp_read_address; + reg [max_burst_bytes_width:0] temp_rd_valid_bytes; + reg rd_fifo_state; + reg invalid_rd_req; + /* get the data from memory && also calculate the rresp*/ + always@(negedge S_RESETN or posedge SW_CLK) + begin + if(!S_RESETN)begin + rd_fifo_wr_ptr = 0; + wr_rresp_cnt =0; + rd_fifo_state = RD_DATA_REQ; + temp_rd_valid_bytes = 0; + temp_read_address = 0; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + end else begin + case(rd_fifo_state) + RD_DATA_REQ : begin + rd_fifo_state = RD_DATA_REQ; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin + ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0; + rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp}; + temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8; + + if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin + temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes; + else + temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + if(rresp === AXI_OK) begin + case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]); + OCM_MEM : RD_REQ_OCM = 1; + DDR_MEM : RD_REQ_DDR = 1; + REG_MEM : RD_REQ_REG = 1; + default : invalid_rd_req = 1; + endcase + end else + invalid_rd_req = 1; + + RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]; + RD_BYTES = temp_rd_valid_bytes; + rd_fifo_state = WAIT_RD_VALID; + wr_rresp_cnt = wr_rresp_cnt + 1; + if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin + wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1]; + wr_rresp_cnt[int_rd_cntr_width-2:0] = 0; + end + end + end + WAIT_RD_VALID : begin + rd_fifo_state = WAIT_RD_VALID; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin + if(RD_DATA_VALID_DDR) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR; + else if(RD_DATA_VALID_OCM) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM; + else if(RD_DATA_VALID_REG) + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG; + else + read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0; + rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1; + RD_REQ_DDR = 0; + RD_REQ_OCM = 0; + RD_REQ_REG = 0; + RD_QOS = 0; + invalid_rd_req = 0; + rd_fifo_state = RD_DATA_REQ; + end + end + endcase + end /// else + end /// always + + /*--------------------------------------------------------------------------------*/ + reg[max_burst_bytes_width:0] rd_v_b; + reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data; + reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data; + reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp; + + /* Read Data Channel handshake */ + always@(negedge S_RESETN or posedge S_ACLK) + begin + if(!S_RESETN)begin + rd_fifo_rd_ptr = 0; + rd_cnt = 0; + rd_latency_count = get_rd_lat_number(1); + rd_delayed = 0; + rresp_time_cnt = 0; + rd_v_b = 0; + end else begin + if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) + rd_delayed = 1; + if(!read_fifo_empty && rd_delayed)begin + rd_delayed = 0; + arvalid_flag[rresp_time_cnt] = 1'b0; + rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]])); + temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]]; + rd_fifo_rd_ptr = rd_fifo_rd_ptr+1; + + if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin + get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b); + temp_read_data = temp_wrap_data; + end + temp_read_rsp = 0; + repeat(axi_burst_len) begin + temp_read_rsp = temp_read_rsp >> axi_rsp_width; + temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb]; + end + slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]], + araddr[rd_cnt[int_rd_cntr_width-2:0]], + arlen[rd_cnt[int_rd_cntr_width-2:0]], + arsize[rd_cnt[int_rd_cntr_width-2:0]], + arbrst[rd_cnt[int_rd_cntr_width-2:0]], + temp_read_data, + temp_read_rsp); + rd_cnt = rd_cnt + 1; + rresp_time_cnt = rresp_time_cnt+1; + if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0; + if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin + rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1]; + rd_cnt[int_rd_cntr_width-2:0] = 0; + end + rd_latency_count = get_rd_lat_number(1); + end + end /// else + end /// always +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ddrc.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ddrc.v new file mode 100644 index 0000000..e4cd917 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ddrc.v @@ -0,0 +1,268 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_ddrc.v + * + * Date : 2012-11 + * + * Description : Module that acts as controller for sparse memory (DDR). + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_ddrc( + rstn, + sw_clk, + +/* Goes to port 0 of DDR */ + ddr_wr_ack_port0, + ddr_wr_dv_port0, + ddr_rd_req_port0, + ddr_rd_dv_port0, + ddr_wr_addr_port0, + ddr_wr_data_port0, + ddr_wr_bytes_port0, + ddr_rd_addr_port0, + ddr_rd_data_port0, + ddr_rd_bytes_port0, + ddr_wr_qos_port0, + ddr_rd_qos_port0, + + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3 + +); + +`include "processing_system7_bfm_v2_0_5_local_params.v" + +input rstn; +input sw_clk; + +output ddr_wr_ack_port0; +input ddr_wr_dv_port0; +input ddr_rd_req_port0; +output ddr_rd_dv_port0; +input[addr_width-1:0] ddr_wr_addr_port0; +input[max_burst_bits-1:0] ddr_wr_data_port0; +input[max_burst_bytes_width:0] ddr_wr_bytes_port0; +input[addr_width-1:0] ddr_rd_addr_port0; +output[max_burst_bits-1:0] ddr_rd_data_port0; +input[max_burst_bytes_width:0] ddr_rd_bytes_port0; +input [axi_qos_width-1:0] ddr_wr_qos_port0; +input [axi_qos_width-1:0] ddr_rd_qos_port0; + +output ddr_wr_ack_port1; +input ddr_wr_dv_port1; +input ddr_rd_req_port1; +output ddr_rd_dv_port1; +input[addr_width-1:0] ddr_wr_addr_port1; +input[max_burst_bits-1:0] ddr_wr_data_port1; +input[max_burst_bytes_width:0] ddr_wr_bytes_port1; +input[addr_width-1:0] ddr_rd_addr_port1; +output[max_burst_bits-1:0] ddr_rd_data_port1; +input[max_burst_bytes_width:0] ddr_rd_bytes_port1; +input[axi_qos_width-1:0] ddr_wr_qos_port1; +input[axi_qos_width-1:0] ddr_rd_qos_port1; + +output ddr_wr_ack_port2; +input ddr_wr_dv_port2; +input ddr_rd_req_port2; +output ddr_rd_dv_port2; +input[addr_width-1:0] ddr_wr_addr_port2; +input[max_burst_bits-1:0] ddr_wr_data_port2; +input[max_burst_bytes_width:0] ddr_wr_bytes_port2; +input[addr_width-1:0] ddr_rd_addr_port2; +output[max_burst_bits-1:0] ddr_rd_data_port2; +input[max_burst_bytes_width:0] ddr_rd_bytes_port2; +input[axi_qos_width-1:0] ddr_wr_qos_port2; +input[axi_qos_width-1:0] ddr_rd_qos_port2; + +output ddr_wr_ack_port3; +input ddr_wr_dv_port3; +input ddr_rd_req_port3; +output ddr_rd_dv_port3; +input[addr_width-1:0] ddr_wr_addr_port3; +input[max_burst_bits-1:0] ddr_wr_data_port3; +input[max_burst_bytes_width:0] ddr_wr_bytes_port3; +input[addr_width-1:0] ddr_rd_addr_port3; +output[max_burst_bits-1:0] ddr_rd_data_port3; +input[max_burst_bytes_width:0] ddr_rd_bytes_port3; +input[axi_qos_width-1:0] ddr_wr_qos_port3; +input[axi_qos_width-1:0] ddr_rd_qos_port3; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_wr_qos_port0), + .qos2(ddr_wr_qos_port1), + .qos3(ddr_wr_qos_port2), + .qos4(ddr_wr_qos_port3), + + .prt_dv1(ddr_wr_dv_port0), + .prt_dv2(ddr_wr_dv_port1), + .prt_dv3(ddr_wr_dv_port2), + .prt_dv4(ddr_wr_dv_port3), + + .prt_data1(ddr_wr_data_port0), + .prt_data2(ddr_wr_data_port1), + .prt_data3(ddr_wr_data_port2), + .prt_data4(ddr_wr_data_port3), + + .prt_addr1(ddr_wr_addr_port0), + .prt_addr2(ddr_wr_addr_port1), + .prt_addr3(ddr_wr_addr_port2), + .prt_addr4(ddr_wr_addr_port3), + + .prt_bytes1(ddr_wr_bytes_port0), + .prt_bytes2(ddr_wr_bytes_port1), + .prt_bytes3(ddr_wr_bytes_port2), + .prt_bytes4(ddr_wr_bytes_port3), + + .prt_ack1(ddr_wr_ack_port0), + .prt_ack2(ddr_wr_ack_port1), + .prt_ack3(ddr_wr_ack_port2), + .prt_ack4(ddr_wr_ack_port3), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ddr_rd_qos_port0), + .qos2(ddr_rd_qos_port1), + .qos3(ddr_rd_qos_port2), + .qos4(ddr_rd_qos_port3), + + .prt_req1(ddr_rd_req_port0), + .prt_req2(ddr_rd_req_port1), + .prt_req3(ddr_rd_req_port2), + .prt_req4(ddr_rd_req_port3), + + .prt_data1(ddr_rd_data_port0), + .prt_data2(ddr_rd_data_port1), + .prt_data3(ddr_rd_data_port2), + .prt_data4(ddr_rd_data_port3), + + .prt_addr1(ddr_rd_addr_port0), + .prt_addr2(ddr_rd_addr_port1), + .prt_addr3(ddr_rd_addr_port2), + .prt_addr4(ddr_rd_addr_port3), + + .prt_bytes1(ddr_rd_bytes_port0), + .prt_bytes2(ddr_rd_bytes_port1), + .prt_bytes3(ddr_rd_bytes_port2), + .prt_bytes4(ddr_rd_bytes_port3), + + .prt_dv1(ddr_rd_dv_port0), + .prt_dv2(ddr_rd_dv_port1), + .prt_dv3(ddr_rd_dv_port2), + .prt_dv4(ddr_rd_dv_port3), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_5_sparse_mem ddr(); + +reg [1:0] state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + ddr.write_mem(wr_data , wr_addr, wr_bytes); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ddr.read_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v new file mode 100644 index 0000000..c2bba19 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v @@ -0,0 +1,300 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_fmsw_gp.v + * + * Date : 2012-11 + * + * Description : Mimics FMSW switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_fmsw_gp( + sw_clk, + rstn, + + w_qos_gp0, + r_qos_gp0, + wr_ack_ocm_gp0, + wr_ack_ddr_gp0, + wr_data_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ocm_gp0, + wr_dv_ddr_gp0, + rd_req_ocm_gp0, + rd_req_ddr_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ocm_gp0, + rd_data_ddr_gp0, + rd_data_reg_gp0, + rd_dv_ocm_gp0, + rd_dv_ddr_gp0, + rd_dv_reg_gp0, + + w_qos_gp1, + r_qos_gp1, + wr_ack_ocm_gp1, + wr_ack_ddr_gp1, + wr_data_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ocm_gp1, + wr_dv_ddr_gp1, + rd_req_ocm_gp1, + rd_req_ddr_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ocm_gp1, + rd_data_ddr_gp1, + rd_data_reg_gp1, + rd_dv_ocm_gp1, + rd_dv_ddr_gp1, + rd_dv_reg_gp1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + ddr_wr_ack, + ddr_wr_dv, + ddr_rd_req, + ddr_rd_dv, + + reg_rd_req, + reg_rd_dv, + + ocm_wr_qos, + ddr_wr_qos, + ocm_rd_qos, + ddr_rd_qos, + reg_rd_qos, + + ocm_wr_addr, + ocm_wr_data, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes, + + ddr_wr_addr, + ddr_wr_data, + ddr_wr_bytes, + ddr_rd_addr, + ddr_rd_data, + ddr_rd_bytes, + + reg_rd_addr, + reg_rd_data, + reg_rd_bytes + +); + +`include "processing_system7_bfm_v2_0_5_local_params.v" + +input sw_clk; +input rstn; + +input [axi_qos_width-1:0]w_qos_gp0; +input [axi_qos_width-1:0]r_qos_gp0; +input [axi_qos_width-1:0]w_qos_gp1; +input [axi_qos_width-1:0]r_qos_gp1; + +output [axi_qos_width-1:0]ocm_wr_qos; +output [axi_qos_width-1:0]ocm_rd_qos; +output [axi_qos_width-1:0]ddr_wr_qos; +output [axi_qos_width-1:0]ddr_rd_qos; +output [axi_qos_width-1:0]reg_rd_qos; + +output wr_ack_ocm_gp0; +output wr_ack_ddr_gp0; +input [max_burst_bits-1:0] wr_data_gp0; +input [addr_width-1:0] wr_addr_gp0; +input [max_burst_bytes_width:0] wr_bytes_gp0; +output wr_dv_ocm_gp0; +output wr_dv_ddr_gp0; + +input rd_req_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_reg_gp0; +input [addr_width-1:0] rd_addr_gp0; +input [max_burst_bytes_width:0] rd_bytes_gp0; +output [max_burst_bits-1:0] rd_data_ocm_gp0; +output [max_burst_bits-1:0] rd_data_ddr_gp0; +output [max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ocm_gp0; +output rd_dv_ddr_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ocm_gp1; +output wr_ack_ddr_gp1; +input [max_burst_bits-1:0] wr_data_gp1; +input [addr_width-1:0] wr_addr_gp1; +input [max_burst_bytes_width:0] wr_bytes_gp1; +output wr_dv_ocm_gp1; +output wr_dv_ddr_gp1; + +input rd_req_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_reg_gp1; +input [addr_width-1:0] rd_addr_gp1; +input [max_burst_bytes_width:0] rd_bytes_gp1; +output [max_burst_bits-1:0] rd_data_ocm_gp1; +output [max_burst_bits-1:0] rd_data_ddr_gp1; +output [max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ocm_gp1; +output rd_dv_ddr_gp1; +output rd_dv_reg_gp1; + + +input ocm_wr_ack; +output ocm_wr_dv; +output [addr_width-1:0]ocm_wr_addr; +output [max_burst_bits-1:0]ocm_wr_data; +output [max_burst_bytes_width:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [max_burst_bits-1:0] ocm_rd_data; +output ocm_rd_req; +output [addr_width-1:0] ocm_rd_addr; +output [max_burst_bytes_width:0] ocm_rd_bytes; + +input ddr_wr_ack; +output ddr_wr_dv; +output [addr_width-1:0]ddr_wr_addr; +output [max_burst_bits-1:0]ddr_wr_data; +output [max_burst_bytes_width:0]ddr_wr_bytes; + +input ddr_rd_dv; +input [max_burst_bits-1:0] ddr_rd_data; +output ddr_rd_req; +output [addr_width-1:0] ddr_rd_addr; +output [max_burst_bytes_width:0] ddr_rd_bytes; + +input reg_rd_dv; +input [max_burst_bits-1:0] reg_rd_data; +output reg_rd_req; +output [addr_width-1:0] reg_rd_addr; +output [max_burst_bytes_width:0] reg_rd_bytes; + + + +processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ocm_gp0), + .prt_dv2(wr_dv_ocm_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ocm_gp0), + .prt_ack2(wr_ack_ocm_gp1), + .prt_req(ocm_wr_dv), + .prt_qos(ocm_wr_qos), + .prt_data(ocm_wr_data), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) +); + +processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(w_qos_gp0), + .qos2(w_qos_gp1), + .prt_dv1(wr_dv_ddr_gp0), + .prt_dv2(wr_dv_ddr_gp1), + .prt_data1(wr_data_gp0), + .prt_data2(wr_data_gp1), + .prt_addr1(wr_addr_gp0), + .prt_addr2(wr_addr_gp1), + .prt_bytes1(wr_bytes_gp0), + .prt_bytes2(wr_bytes_gp1), + .prt_ack1(wr_ack_ddr_gp0), + .prt_ack2(wr_ack_ddr_gp1), + .prt_req(ddr_wr_dv), + .prt_qos(ddr_wr_qos), + .prt_data(ddr_wr_data), + .prt_addr(ddr_wr_addr), + .prt_bytes(ddr_wr_bytes), + .prt_ack(ddr_wr_ack) +); + +processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ocm_gp0), + .prt_req2(rd_req_ocm_gp1), + .prt_data1(rd_data_ocm_gp0), + .prt_data2(rd_data_ocm_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ocm_gp0), + .prt_dv2(rd_dv_ocm_gp1), + .prt_req(ocm_rd_req), + .prt_qos(ocm_rd_qos), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) +); + +processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_ddr_gp0), + .prt_req2(rd_req_ddr_gp1), + .prt_data1(rd_data_ddr_gp0), + .prt_data2(rd_data_ddr_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_ddr_gp0), + .prt_dv2(rd_dv_ddr_gp1), + .prt_req(ddr_rd_req), + .prt_qos(ddr_rd_qos), + .prt_data(ddr_rd_data), + .prt_addr(ddr_rd_addr), + .prt_bytes(ddr_rd_bytes), + .prt_dv(ddr_rd_dv) +); + +processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(r_qos_gp0), + .qos2(r_qos_gp1), + .prt_req1(rd_req_reg_gp0), + .prt_req2(rd_req_reg_gp1), + .prt_data1(rd_data_reg_gp0), + .prt_data2(rd_data_reg_gp1), + .prt_addr1(rd_addr_gp0), + .prt_addr2(rd_addr_gp1), + .prt_bytes1(rd_bytes_gp0), + .prt_bytes2(rd_bytes_gp1), + .prt_dv1(rd_dv_reg_gp0), + .prt_dv2(rd_dv_reg_gp1), + .prt_req(reg_rd_req), + .prt_qos(reg_rd_qos), + .prt_data(reg_rd_data), + .prt_addr(reg_rd_addr), + .prt_bytes(reg_rd_bytes), + .prt_dv(reg_rd_dv) +); + + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_clock.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_clock.v new file mode 100644 index 0000000..85c95c6 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_clock.v @@ -0,0 +1,58 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_gen_clock.v + * + * Date : 2012-11 + * + * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_gen_clock( + ps_clk, + sw_clk, + + fclk_clk3, + fclk_clk2, + fclk_clk1, + fclk_clk0 +); + +input ps_clk; +output sw_clk; + +output fclk_clk3; +output fclk_clk2; +output fclk_clk1; +output fclk_clk0; + +parameter freq_clk3 = 50; +parameter freq_clk2 = 50; +parameter freq_clk1 = 50; +parameter freq_clk0 = 50; + +reg clk0 = 1'b0; +reg clk1 = 1'b0; +reg clk2 = 1'b0; +reg clk3 = 1'b0; +reg sw_clk = 1'b0; + +assign fclk_clk0 = clk0; +assign fclk_clk1 = clk1; +assign fclk_clk2 = clk2; +assign fclk_clk3 = clk3; + +real clk3_p = (1000.00/freq_clk3)/2; +real clk2_p = (1000.00/freq_clk2)/2; +real clk1_p = (1000.00/freq_clk1)/2; +real clk0_p = (1000.00/freq_clk0)/2; + +always #(clk3_p) clk3 = !clk3; +always #(clk2_p) clk2 = !clk2; +always #(clk1_p) clk1 = !clk1; +always #(clk0_p) clk0 = !clk0; + +always #(0.5) sw_clk = !sw_clk; + + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v new file mode 100644 index 0000000..db3bca2 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v @@ -0,0 +1,225 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_gen_reset.v + * + * Date : 2012-11 + * + * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the + * respective clocks. + *****************************************************************************/ + `timescale 1ns/1ps +module processing_system7_bfm_v2_0_5_gen_reset( + por_rst_n, + sys_rst_n, + rst_out_n, + + m_axi_gp0_clk, + m_axi_gp1_clk, + s_axi_gp0_clk, + s_axi_gp1_clk, + s_axi_hp0_clk, + s_axi_hp1_clk, + s_axi_hp2_clk, + s_axi_hp3_clk, + s_axi_acp_clk, + + m_axi_gp0_rstn, + m_axi_gp1_rstn, + s_axi_gp0_rstn, + s_axi_gp1_rstn, + s_axi_hp0_rstn, + s_axi_hp1_rstn, + s_axi_hp2_rstn, + s_axi_hp3_rstn, + s_axi_acp_rstn, + + fclk_reset3_n, + fclk_reset2_n, + fclk_reset1_n, + fclk_reset0_n, + + fpga_acp_reset_n, + fpga_gp_m0_reset_n, + fpga_gp_m1_reset_n, + fpga_gp_s0_reset_n, + fpga_gp_s1_reset_n, + fpga_hp_s0_reset_n, + fpga_hp_s1_reset_n, + fpga_hp_s2_reset_n, + fpga_hp_s3_reset_n + +); + +input por_rst_n; +input sys_rst_n; +input m_axi_gp0_clk; +input m_axi_gp1_clk; +input s_axi_gp0_clk; +input s_axi_gp1_clk; +input s_axi_hp0_clk; +input s_axi_hp1_clk; +input s_axi_hp2_clk; +input s_axi_hp3_clk; +input s_axi_acp_clk; + +output reg m_axi_gp0_rstn; +output reg m_axi_gp1_rstn; +output reg s_axi_gp0_rstn; +output reg s_axi_gp1_rstn; +output reg s_axi_hp0_rstn; +output reg s_axi_hp1_rstn; +output reg s_axi_hp2_rstn; +output reg s_axi_hp3_rstn; +output reg s_axi_acp_rstn; + +output rst_out_n; +output fclk_reset3_n; +output fclk_reset2_n; +output fclk_reset1_n; +output fclk_reset0_n; + +output fpga_acp_reset_n; +output fpga_gp_m0_reset_n; +output fpga_gp_m1_reset_n; +output fpga_gp_s0_reset_n; +output fpga_gp_s1_reset_n; +output fpga_hp_s0_reset_n; +output fpga_hp_s1_reset_n; +output fpga_hp_s2_reset_n; +output fpga_hp_s3_reset_n; + +reg [31:0] fabric_rst_n; + +reg r_m_axi_gp0_rstn; +reg r_m_axi_gp1_rstn; +reg r_s_axi_gp0_rstn; +reg r_s_axi_gp1_rstn; +reg r_s_axi_hp0_rstn; +reg r_s_axi_hp1_rstn; +reg r_s_axi_hp2_rstn; +reg r_s_axi_hp3_rstn; +reg r_s_axi_acp_rstn; + +assign rst_out_n = por_rst_n & sys_rst_n; + +assign fclk_reset0_n = !fabric_rst_n[0]; +assign fclk_reset1_n = !fabric_rst_n[1]; +assign fclk_reset2_n = !fabric_rst_n[2]; +assign fclk_reset3_n = !fabric_rst_n[3]; + +assign fpga_acp_reset_n = !fabric_rst_n[24]; + +assign fpga_hp_s3_reset_n = !fabric_rst_n[23]; +assign fpga_hp_s2_reset_n = !fabric_rst_n[22]; +assign fpga_hp_s1_reset_n = !fabric_rst_n[21]; +assign fpga_hp_s0_reset_n = !fabric_rst_n[20]; + +assign fpga_gp_s1_reset_n = !fabric_rst_n[17]; +assign fpga_gp_s0_reset_n = !fabric_rst_n[16]; +assign fpga_gp_m1_reset_n = !fabric_rst_n[13]; +assign fpga_gp_m0_reset_n = !fabric_rst_n[12]; + +task fpga_soft_reset; +input[31:0] reset_ctrl; + begin + fabric_rst_n[0] = reset_ctrl[0]; + fabric_rst_n[1] = reset_ctrl[1]; + fabric_rst_n[2] = reset_ctrl[2]; + fabric_rst_n[3] = reset_ctrl[3]; + + fabric_rst_n[12] = reset_ctrl[12]; + fabric_rst_n[13] = reset_ctrl[13]; + fabric_rst_n[16] = reset_ctrl[16]; + fabric_rst_n[17] = reset_ctrl[17]; + + fabric_rst_n[20] = reset_ctrl[20]; + fabric_rst_n[21] = reset_ctrl[21]; + fabric_rst_n[22] = reset_ctrl[22]; + fabric_rst_n[23] = reset_ctrl[23]; + + fabric_rst_n[24] = reset_ctrl[24]; + end +endtask + +always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f; + +always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp0_rstn = 1'b0; + else + m_axi_gp0_rstn = 1'b1; + end + +always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + m_axi_gp1_rstn = 1'b0; + else + m_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp0_rstn = 1'b0; + else + s_axi_gp0_rstn = 1'b1; + end + +always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_gp1_rstn = 1'b0; + else + s_axi_gp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp0_rstn = 1'b0; + else + s_axi_hp0_rstn = 1'b1; + end + +always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp1_rstn = 1'b0; + else + s_axi_hp1_rstn = 1'b1; + end + +always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp2_rstn = 1'b0; + else + s_axi_hp2_rstn = 1'b1; + end + +always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_hp3_rstn = 1'b0; + else + s_axi_hp3_rstn = 1'b1; + end + +always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n)) + begin + if (!(por_rst_n & sys_rst_n)) + s_axi_acp_rstn = 1'b0; + else + s_axi_acp_rstn = 1'b1; + end + + +always@(*) begin + if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin + $display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state"); + $finish(); + end +end + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v new file mode 100644 index 0000000..6cc868f --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v @@ -0,0 +1,662 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_interconnect_model.v + * + * Date : 2012-11 + * + * Description : Mimics Top_interconnect Switch. + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_interconnect_model ( + rstn, + sw_clk, + + w_qos_gp0, + w_qos_gp1, + w_qos_hp0, + w_qos_hp1, + w_qos_hp2, + w_qos_hp3, + + r_qos_gp0, + r_qos_gp1, + r_qos_hp0, + r_qos_hp1, + r_qos_hp2, + r_qos_hp3, + + wr_ack_ddr_gp0, + wr_ack_ocm_gp0, + wr_data_gp0, + wr_addr_gp0, + wr_bytes_gp0, + wr_dv_ddr_gp0, + wr_dv_ocm_gp0, + + rd_req_ddr_gp0, + rd_req_ocm_gp0, + rd_req_reg_gp0, + rd_addr_gp0, + rd_bytes_gp0, + rd_data_ddr_gp0, + rd_data_ocm_gp0, + rd_data_reg_gp0, + rd_dv_ddr_gp0, + rd_dv_ocm_gp0, + rd_dv_reg_gp0, + + wr_ack_ddr_gp1, + wr_ack_ocm_gp1, + wr_data_gp1, + wr_addr_gp1, + wr_bytes_gp1, + wr_dv_ddr_gp1, + wr_dv_ocm_gp1, + rd_req_ddr_gp1, + rd_req_ocm_gp1, + rd_req_reg_gp1, + rd_addr_gp1, + rd_bytes_gp1, + rd_data_ddr_gp1, + rd_data_ocm_gp1, + rd_data_reg_gp1, + rd_dv_ddr_gp1, + rd_dv_ocm_gp1, + rd_dv_reg_gp1, + + wr_ack_ddr_hp0, + wr_ack_ocm_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + wr_dv_ocm_hp0, + rd_req_ddr_hp0, + rd_req_ocm_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_data_ocm_hp0, + rd_dv_ddr_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_ack_ocm_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + wr_dv_ocm_hp1, + rd_req_ddr_hp1, + rd_req_ocm_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_ack_ocm_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + wr_dv_ocm_hp2, + rd_req_ddr_hp2, + rd_req_ocm_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_ack_ocm_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + wr_dv_ocm_hp3, + rd_req_ddr_hp3, + rd_req_ocm_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ddr_hp3, + rd_data_ocm_hp3, + rd_dv_ddr_hp3, + rd_dv_ocm_hp3, + +/* Goes to port 1 of DDR */ + ddr_wr_ack_port1, + ddr_wr_dv_port1, + ddr_rd_req_port1, + ddr_rd_dv_port1, + ddr_wr_addr_port1, + ddr_wr_data_port1, + ddr_wr_bytes_port1, + ddr_rd_addr_port1, + ddr_rd_data_port1, + ddr_rd_bytes_port1, + ddr_wr_qos_port1, + ddr_rd_qos_port1, + +/* Goes to port2 of DDR */ + ddr_wr_ack_port2, + ddr_wr_dv_port2, + ddr_rd_req_port2, + ddr_rd_dv_port2, + ddr_wr_addr_port2, + ddr_wr_data_port2, + ddr_wr_bytes_port2, + ddr_rd_addr_port2, + ddr_rd_data_port2, + ddr_rd_bytes_port2, + ddr_wr_qos_port2, + ddr_rd_qos_port2, + +/* Goes to port3 of DDR */ + ddr_wr_ack_port3, + ddr_wr_dv_port3, + ddr_rd_req_port3, + ddr_rd_dv_port3, + ddr_wr_addr_port3, + ddr_wr_data_port3, + ddr_wr_bytes_port3, + ddr_rd_addr_port3, + ddr_rd_data_port3, + ddr_rd_bytes_port3, + ddr_wr_qos_port3, + ddr_rd_qos_port3, + +/* Goes to port1 of OCM */ + ocm_wr_qos_port1, + ocm_rd_qos_port1, + ocm_wr_dv_port1, + ocm_wr_data_port1, + ocm_wr_addr_port1, + ocm_wr_bytes_port1, + ocm_wr_ack_port1, + ocm_rd_req_port1, + ocm_rd_data_port1, + ocm_rd_addr_port1, + ocm_rd_bytes_port1, + ocm_rd_dv_port1, + +/* Goes to port1 for RegMap */ + reg_rd_qos_port1, + reg_rd_req_port1, + reg_rd_data_port1, + reg_rd_addr_port1, + reg_rd_bytes_port1, + reg_rd_dv_port1 + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" + +input rstn; +input sw_clk; + +input [axi_qos_width-1:0] w_qos_gp0; +input [axi_qos_width-1:0] w_qos_gp1; +input [axi_qos_width-1:0] w_qos_hp0; +input [axi_qos_width-1:0] w_qos_hp1; +input [axi_qos_width-1:0] w_qos_hp2; +input [axi_qos_width-1:0] w_qos_hp3; + +input [axi_qos_width-1:0] r_qos_gp0; +input [axi_qos_width-1:0] r_qos_gp1; +input [axi_qos_width-1:0] r_qos_hp0; +input [axi_qos_width-1:0] r_qos_hp1; +input [axi_qos_width-1:0] r_qos_hp2; +input [axi_qos_width-1:0] r_qos_hp3; + +output [axi_qos_width-1:0] ocm_wr_qos_port1; +output [axi_qos_width-1:0] ocm_rd_qos_port1; + +output wr_ack_ddr_gp0; +output wr_ack_ocm_gp0; +input[max_burst_bits-1:0] wr_data_gp0; +input[addr_width-1:0] wr_addr_gp0; +input[max_burst_bytes_width:0] wr_bytes_gp0; +input wr_dv_ddr_gp0; +input wr_dv_ocm_gp0; +input rd_req_ddr_gp0; +input rd_req_ocm_gp0; +input rd_req_reg_gp0; +input[addr_width-1:0] rd_addr_gp0; +input[max_burst_bytes_width:0] rd_bytes_gp0; +output[max_burst_bits-1:0] rd_data_ddr_gp0; +output[max_burst_bits-1:0] rd_data_ocm_gp0; +output[max_burst_bits-1:0] rd_data_reg_gp0; +output rd_dv_ddr_gp0; +output rd_dv_ocm_gp0; +output rd_dv_reg_gp0; + +output wr_ack_ddr_gp1; +output wr_ack_ocm_gp1; +input[max_burst_bits-1:0] wr_data_gp1; +input[addr_width-1:0] wr_addr_gp1; +input[max_burst_bytes_width:0] wr_bytes_gp1; +input wr_dv_ddr_gp1; +input wr_dv_ocm_gp1; +input rd_req_ddr_gp1; +input rd_req_ocm_gp1; +input rd_req_reg_gp1; +input[addr_width-1:0] rd_addr_gp1; +input[max_burst_bytes_width:0] rd_bytes_gp1; +output[max_burst_bits-1:0] rd_data_ddr_gp1; +output[max_burst_bits-1:0] rd_data_ocm_gp1; +output[max_burst_bits-1:0] rd_data_reg_gp1; +output rd_dv_ddr_gp1; +output rd_dv_ocm_gp1; +output rd_dv_reg_gp1; + +output wr_ack_ddr_hp0; +output wr_ack_ocm_hp0; +input[max_burst_bits-1:0] wr_data_hp0; +input[addr_width-1:0] wr_addr_hp0; +input[max_burst_bytes_width:0] wr_bytes_hp0; +input wr_dv_ddr_hp0; +input wr_dv_ocm_hp0; +input rd_req_ddr_hp0; +input rd_req_ocm_hp0; +input[addr_width-1:0] rd_addr_hp0; +input[max_burst_bytes_width:0] rd_bytes_hp0; +output[max_burst_bits-1:0] rd_data_ddr_hp0; +output[max_burst_bits-1:0] rd_data_ocm_hp0; +output rd_dv_ddr_hp0; +output rd_dv_ocm_hp0; + +output wr_ack_ddr_hp1; +output wr_ack_ocm_hp1; +input[max_burst_bits-1:0] wr_data_hp1; +input[addr_width-1:0] wr_addr_hp1; +input[max_burst_bytes_width:0] wr_bytes_hp1; +input wr_dv_ddr_hp1; +input wr_dv_ocm_hp1; +input rd_req_ddr_hp1; +input rd_req_ocm_hp1; +input[addr_width-1:0] rd_addr_hp1; +input[max_burst_bytes_width:0] rd_bytes_hp1; +output[max_burst_bits-1:0] rd_data_ddr_hp1; +output[max_burst_bits-1:0] rd_data_ocm_hp1; +output rd_dv_ddr_hp1; +output rd_dv_ocm_hp1; + +output wr_ack_ddr_hp2; +output wr_ack_ocm_hp2; +input[max_burst_bits-1:0] wr_data_hp2; +input[addr_width-1:0] wr_addr_hp2; +input[max_burst_bytes_width:0] wr_bytes_hp2; +input wr_dv_ddr_hp2; +input wr_dv_ocm_hp2; +input rd_req_ddr_hp2; +input rd_req_ocm_hp2; +input[addr_width-1:0] rd_addr_hp2; +input[max_burst_bytes_width:0] rd_bytes_hp2; +output[max_burst_bits-1:0] rd_data_ddr_hp2; +output[max_burst_bits-1:0] rd_data_ocm_hp2; +output rd_dv_ddr_hp2; +output rd_dv_ocm_hp2; + +output wr_ack_ddr_hp3; +output wr_ack_ocm_hp3; +input[max_burst_bits-1:0] wr_data_hp3; +input[addr_width-1:0] wr_addr_hp3; +input[max_burst_bytes_width:0] wr_bytes_hp3; +input wr_dv_ddr_hp3; +input wr_dv_ocm_hp3; +input rd_req_ddr_hp3; +input rd_req_ocm_hp3; +input[addr_width-1:0] rd_addr_hp3; +input[max_burst_bytes_width:0] rd_bytes_hp3; +output[max_burst_bits-1:0] rd_data_ddr_hp3; +output[max_burst_bits-1:0] rd_data_ocm_hp3; +output rd_dv_ddr_hp3; +output rd_dv_ocm_hp3; + +/* Goes to port 1 of DDR */ +input ddr_wr_ack_port1; +output ddr_wr_dv_port1; +output ddr_rd_req_port1; +input ddr_rd_dv_port1; +output[addr_width-1:0] ddr_wr_addr_port1; +output[max_burst_bits-1:0] ddr_wr_data_port1; +output[max_burst_bytes_width:0] ddr_wr_bytes_port1; +output[addr_width-1:0] ddr_rd_addr_port1; +input[max_burst_bits-1:0] ddr_rd_data_port1; +output[max_burst_bytes_width:0] ddr_rd_bytes_port1; +output [axi_qos_width-1:0] ddr_wr_qos_port1; +output [axi_qos_width-1:0] ddr_rd_qos_port1; + +/* Goes to port2 of DDR */ +input ddr_wr_ack_port2; +output ddr_wr_dv_port2; +output ddr_rd_req_port2; +input ddr_rd_dv_port2; +output[addr_width-1:0] ddr_wr_addr_port2; +output[max_burst_bits-1:0] ddr_wr_data_port2; +output[max_burst_bytes_width:0] ddr_wr_bytes_port2; +output[addr_width-1:0] ddr_rd_addr_port2; +input[max_burst_bits-1:0] ddr_rd_data_port2; +output[max_burst_bytes_width:0] ddr_rd_bytes_port2; +output [axi_qos_width-1:0] ddr_wr_qos_port2; +output [axi_qos_width-1:0] ddr_rd_qos_port2; + +/* Goes to port3 of DDR */ +input ddr_wr_ack_port3; +output ddr_wr_dv_port3; +output ddr_rd_req_port3; +input ddr_rd_dv_port3; +output[addr_width-1:0] ddr_wr_addr_port3; +output[max_burst_bits-1:0] ddr_wr_data_port3; +output[max_burst_bytes_width:0] ddr_wr_bytes_port3; +output[addr_width-1:0] ddr_rd_addr_port3; +input[max_burst_bits-1:0] ddr_rd_data_port3; +output[max_burst_bytes_width:0] ddr_rd_bytes_port3; +output [axi_qos_width-1:0] ddr_wr_qos_port3; +output [axi_qos_width-1:0] ddr_rd_qos_port3; + +/* Goes to port1 of OCM */ +input ocm_wr_ack_port1; +output ocm_wr_dv_port1; +output ocm_rd_req_port1; +input ocm_rd_dv_port1; +output[max_burst_bits-1:0] ocm_wr_data_port1; +output[addr_width-1:0] ocm_wr_addr_port1; +output[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[max_burst_bits-1:0] ocm_rd_data_port1; +output[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bytes_width:0] ocm_rd_bytes_port1; + +/* Goes to port1 of REG */ +output [axi_qos_width-1:0] reg_rd_qos_port1; +output reg_rd_req_port1; +input reg_rd_dv_port1; +input[max_burst_bits-1:0] reg_rd_data_port1; +output[addr_width-1:0] reg_rd_addr_port1; +output[max_burst_bytes_width:0] reg_rd_bytes_port1; + +wire ocm_wr_dv_osw0; +wire ocm_wr_dv_osw1; +wire[max_burst_bits-1:0] ocm_wr_data_osw0; +wire[max_burst_bits-1:0] ocm_wr_data_osw1; +wire[addr_width-1:0] ocm_wr_addr_osw0; +wire[addr_width-1:0] ocm_wr_addr_osw1; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1; +wire ocm_wr_ack_osw0; +wire ocm_wr_ack_osw1; +wire ocm_rd_req_osw0; +wire ocm_rd_req_osw1; +wire[max_burst_bits-1:0] ocm_rd_data_osw0; +wire[max_burst_bits-1:0] ocm_rd_data_osw1; +wire[addr_width-1:0] ocm_rd_addr_osw0; +wire[addr_width-1:0] ocm_rd_addr_osw1; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0; +wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1; +wire ocm_rd_dv_osw0; +wire ocm_rd_dv_osw1; + +wire [axi_qos_width-1:0] ocm_wr_qos_osw0; +wire [axi_qos_width-1:0] ocm_wr_qos_osw1; +wire [axi_qos_width-1:0] ocm_rd_qos_osw0; +wire [axi_qos_width-1:0] ocm_rd_qos_osw1; + + +processing_system7_bfm_v2_0_5_fmsw_gp fmsw ( + .sw_clk(sw_clk), + .rstn(rstn), + + .w_qos_gp0(w_qos_gp0), + .r_qos_gp0(r_qos_gp0), + .wr_ack_ocm_gp0(wr_ack_ocm_gp0), + .wr_ack_ddr_gp0(wr_ack_ddr_gp0), + .wr_data_gp0(wr_data_gp0), + .wr_addr_gp0(wr_addr_gp0), + .wr_bytes_gp0(wr_bytes_gp0), + .wr_dv_ocm_gp0(wr_dv_ocm_gp0), + .wr_dv_ddr_gp0(wr_dv_ddr_gp0), + .rd_req_ocm_gp0(rd_req_ocm_gp0), + .rd_req_ddr_gp0(rd_req_ddr_gp0), + .rd_req_reg_gp0(rd_req_reg_gp0), + .rd_addr_gp0(rd_addr_gp0), + .rd_bytes_gp0(rd_bytes_gp0), + .rd_data_ddr_gp0(rd_data_ddr_gp0), + .rd_data_ocm_gp0(rd_data_ocm_gp0), + .rd_data_reg_gp0(rd_data_reg_gp0), + .rd_dv_ocm_gp0(rd_dv_ocm_gp0), + .rd_dv_ddr_gp0(rd_dv_ddr_gp0), + .rd_dv_reg_gp0(rd_dv_reg_gp0), + + .w_qos_gp1(w_qos_gp1), + .r_qos_gp1(r_qos_gp1), + .wr_ack_ocm_gp1(wr_ack_ocm_gp1), + .wr_ack_ddr_gp1(wr_ack_ddr_gp1), + .wr_data_gp1(wr_data_gp1), + .wr_addr_gp1(wr_addr_gp1), + .wr_bytes_gp1(wr_bytes_gp1), + .wr_dv_ocm_gp1(wr_dv_ocm_gp1), + .wr_dv_ddr_gp1(wr_dv_ddr_gp1), + .rd_req_ocm_gp1(rd_req_ocm_gp1), + .rd_req_ddr_gp1(rd_req_ddr_gp1), + .rd_req_reg_gp1(rd_req_reg_gp1), + .rd_addr_gp1(rd_addr_gp1), + .rd_bytes_gp1(rd_bytes_gp1), + .rd_data_ddr_gp1(rd_data_ddr_gp1), + .rd_data_ocm_gp1(rd_data_ocm_gp1), + .rd_data_reg_gp1(rd_data_reg_gp1), + .rd_dv_ocm_gp1(rd_dv_ocm_gp1), + .rd_dv_ddr_gp1(rd_dv_ddr_gp1), + .rd_dv_reg_gp1(rd_dv_reg_gp1), + + .ocm_wr_ack (ocm_wr_ack_osw0), + .ocm_wr_dv (ocm_wr_dv_osw0), + .ocm_rd_req (ocm_rd_req_osw0), + .ocm_rd_dv (ocm_rd_dv_osw0), + .ocm_wr_addr(ocm_wr_addr_osw0), + .ocm_wr_data(ocm_wr_data_osw0), + .ocm_wr_bytes(ocm_wr_bytes_osw0), + .ocm_rd_addr(ocm_rd_addr_osw0), + .ocm_rd_data(ocm_rd_data_osw0), + .ocm_rd_bytes(ocm_rd_bytes_osw0), + + .ocm_wr_qos(ocm_wr_qos_osw0), + .ocm_rd_qos(ocm_rd_qos_osw0), + + .ddr_wr_qos(ddr_wr_qos_port1), + .ddr_rd_qos(ddr_rd_qos_port1), + + .reg_rd_qos(reg_rd_qos_port1), + + .ddr_wr_ack(ddr_wr_ack_port1), + .ddr_wr_dv(ddr_wr_dv_port1), + .ddr_rd_req(ddr_rd_req_port1), + .ddr_rd_dv(ddr_rd_dv_port1), + .ddr_wr_addr(ddr_wr_addr_port1), + .ddr_wr_data(ddr_wr_data_port1), + .ddr_wr_bytes(ddr_wr_bytes_port1), + .ddr_rd_addr(ddr_rd_addr_port1), + .ddr_rd_data(ddr_rd_data_port1), + .ddr_rd_bytes(ddr_rd_bytes_port1), + + .reg_rd_req(reg_rd_req_port1), + .reg_rd_dv(reg_rd_dv_port1), + .reg_rd_addr(reg_rd_addr_port1), + .reg_rd_data(reg_rd_data_port1), + .reg_rd_bytes(reg_rd_bytes_port1) +); + + +processing_system7_bfm_v2_0_5_ssw_hp ssw( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_data_ocm_hp0(rd_data_ocm_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ocm_hp0(wr_ack_ocm_hp0), + .wr_dv_ocm_hp0(wr_dv_ocm_hp0), + .rd_req_ocm_hp0(rd_req_ocm_hp0), + .rd_dv_ocm_hp0(rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_data_ocm_hp1(rd_data_ocm_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .wr_ack_ocm_hp1(wr_ack_ocm_hp1), + .wr_dv_ocm_hp1(wr_dv_ocm_hp1), + .rd_req_ocm_hp1(rd_req_ocm_hp1), + .rd_dv_ocm_hp1(rd_dv_ocm_hp1), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_data_ocm_hp2(rd_data_ocm_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ocm_hp2(wr_ack_ocm_hp2), + .wr_dv_ocm_hp2(wr_dv_ocm_hp2), + .rd_req_ocm_hp2(rd_req_ocm_hp2), + .rd_dv_ocm_hp2(rd_dv_ocm_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_data_ocm_hp3(rd_data_ocm_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .wr_ack_ocm_hp3(wr_ack_ocm_hp3), + .wr_dv_ocm_hp3(wr_dv_ocm_hp3), + .rd_req_ocm_hp3(rd_req_ocm_hp3), + .rd_dv_ocm_hp3(rd_dv_ocm_hp3), + + .ddr_wr_ack0(ddr_wr_ack_port2), + .ddr_wr_dv0(ddr_wr_dv_port2), + .ddr_rd_req0(ddr_rd_req_port2), + .ddr_rd_dv0(ddr_rd_dv_port2), + .ddr_wr_addr0(ddr_wr_addr_port2), + .ddr_wr_data0(ddr_wr_data_port2), + .ddr_wr_bytes0(ddr_wr_bytes_port2), + .ddr_rd_addr0(ddr_rd_addr_port2), + .ddr_rd_data0(ddr_rd_data_port2), + .ddr_rd_bytes0(ddr_rd_bytes_port2), + .ddr_wr_qos0(ddr_wr_qos_port2), + .ddr_rd_qos0(ddr_rd_qos_port2), + + .ddr_wr_ack1(ddr_wr_ack_port3), + .ddr_wr_dv1(ddr_wr_dv_port3), + .ddr_rd_req1(ddr_rd_req_port3), + .ddr_rd_dv1(ddr_rd_dv_port3), + .ddr_wr_addr1(ddr_wr_addr_port3), + .ddr_wr_data1(ddr_wr_data_port3), + .ddr_wr_bytes1(ddr_wr_bytes_port3), + .ddr_rd_addr1(ddr_rd_addr_port3), + .ddr_rd_data1(ddr_rd_data_port3), + .ddr_rd_bytes1(ddr_rd_bytes_port3), + .ddr_wr_qos1(ddr_wr_qos_port3), + .ddr_rd_qos1(ddr_rd_qos_port3), + + .ocm_wr_qos(ocm_wr_qos_osw1), + .ocm_rd_qos(ocm_rd_qos_osw1), + + .ocm_wr_ack (ocm_wr_ack_osw1), + .ocm_wr_dv (ocm_wr_dv_osw1), + .ocm_rd_req (ocm_rd_req_osw1), + .ocm_rd_dv (ocm_rd_dv_osw1), + .ocm_wr_addr(ocm_wr_addr_osw1), + .ocm_wr_data(ocm_wr_data_osw1), + .ocm_wr_bytes(ocm_wr_bytes_osw1), + .ocm_rd_addr(ocm_rd_addr_osw1), + .ocm_rd_data(ocm_rd_data_osw1), + .ocm_rd_bytes(ocm_rd_bytes_osw1) + +); + +processing_system7_bfm_v2_0_5_arb_wr osw_wr ( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_wr_qos_osw0), /// chk + .qos2(ocm_wr_qos_osw1), /// chk + .prt_dv1(ocm_wr_dv_osw0), + .prt_dv2(ocm_wr_dv_osw1), + .prt_data1(ocm_wr_data_osw0), + .prt_data2(ocm_wr_data_osw1), + .prt_addr1(ocm_wr_addr_osw0), + .prt_addr2(ocm_wr_addr_osw1), + .prt_bytes1(ocm_wr_bytes_osw0), + .prt_bytes2(ocm_wr_bytes_osw1), + .prt_ack1(ocm_wr_ack_osw0), + .prt_ack2(ocm_wr_ack_osw1), + .prt_req(ocm_wr_dv_port1), + .prt_qos(ocm_wr_qos_port1), + .prt_data(ocm_wr_data_port1), + .prt_addr(ocm_wr_addr_port1), + .prt_bytes(ocm_wr_bytes_port1), + .prt_ack(ocm_wr_ack_port1) +); + +processing_system7_bfm_v2_0_5_arb_rd osw_rd( + .rstn(rstn), + .sw_clk(sw_clk), + .qos1(ocm_rd_qos_osw0), // chk + .qos2(ocm_rd_qos_osw1), // chk + .prt_req1(ocm_rd_req_osw0), + .prt_req2(ocm_rd_req_osw1), + .prt_data1(ocm_rd_data_osw0), + .prt_data2(ocm_rd_data_osw1), + .prt_addr1(ocm_rd_addr_osw0), + .prt_addr2(ocm_rd_addr_osw1), + .prt_bytes1(ocm_rd_bytes_osw0), + .prt_bytes2(ocm_rd_bytes_osw1), + .prt_dv1(ocm_rd_dv_osw0), + .prt_dv2(ocm_rd_dv_osw1), + .prt_req(ocm_rd_req_port1), + .prt_qos(ocm_rd_qos_port1), + .prt_data(ocm_rd_data_port1), + .prt_addr(ocm_rd_addr_port1), + .prt_bytes(ocm_rd_bytes_port1), + .prt_dv(ocm_rd_dv_port1) +); + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v new file mode 100644 index 0000000..474ebef --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v @@ -0,0 +1,99 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_intr_rd_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Reads between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_intr_rd_mem( +sw_clk, +rstn, + +full, +empty, + +req, +invalid_rd_req, +rd_info, + +RD_DATA_OCM, +RD_DATA_DDR, +RD_DATA_VALID_OCM, +RD_DATA_VALID_DDR + +); +`include "processing_system7_bfm_v2_0_5_local_params.v" + +input sw_clk, rstn; +output full, empty; + +input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; +input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; +input req, invalid_rd_req; +input [rd_info_bits-1:0] rd_info; + +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes +wire full, empty; + + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +/* read from the fifo */ +task read_mem; +output [rd_afi_fifo_bits-1:0] data; +begin + data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + rd_ptr[intr_cnt_width-2:0] = 0; + else + rd_ptr = rd_ptr + 1; +end +endtask + +reg state; +reg invalid_rd; +/* write in the fifo */ +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + state = 0; + invalid_rd = 0; +end else begin + case (state) + 0 : begin + state = 0; + invalid_rd = 0; + if(req)begin + state = 1; + invalid_rd = invalid_rd_req; + end + end + 1 : begin + state = 1; + if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin + if(RD_DATA_VALID_DDR) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info}; + else if(RD_DATA_VALID_OCM) + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info}; + else + rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; + state = 0; + invalid_rd = 0; + end + end + endcase +end +end + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v new file mode 100644 index 0000000..914bf9e --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v @@ -0,0 +1,105 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_intr_wr_mem.v + * + * Date : 2012-11 + * + * Description : Mimics interconnect for Writes between AFI and DDRC/OCM + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_intr_wr_mem( +sw_clk, +rstn, + +full, + +WR_DATA_ACK_OCM, +WR_DATA_ACK_DDR, +WR_ADDR, +WR_DATA, +WR_BYTES, +WR_QOS, +WR_DATA_VALID_OCM, +WR_DATA_VALID_DDR +); + +`include "processing_system7_bfm_v2_0_5_local_params.v" +/* local parameters for interconnect wr fifo model */ + +input sw_clk, rstn; +output full; + +input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; +output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; +output reg [max_burst_bits-1:0] WR_DATA; +output reg [addr_width-1:0] WR_ADDR; +output reg [max_burst_bytes_width:0] WR_BYTES; +output reg [axi_qos_width-1:0] WR_QOS; +reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; +reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; +wire empty; + +assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; +assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; + +parameter SEND_DATA = 0, WAIT_ACK = 1; +reg state; + +task automatic write_mem; +input [wr_fifo_data_bits-1:0] data; +begin + wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; + if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) + wr_ptr[intr_cnt_width-2:0] = 0; + else + wr_ptr = wr_ptr + 1; +end +endtask + +always@(negedge rstn or posedge sw_clk) +begin +if(!rstn) begin + wr_ptr = 0; + rd_ptr = 0; + WR_DATA_VALID_DDR = 1'b0; + WR_DATA_VALID_OCM = 1'b0; + WR_QOS = 0; + state = SEND_DATA; +end else begin + case(state) + SEND_DATA :begin + state = SEND_DATA; + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + if(!empty) begin + WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; + WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; + WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; + WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; + state = WAIT_ACK; + case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) + OCM_MEM : WR_DATA_VALID_OCM = 1; + DDR_MEM : WR_DATA_VALID_DDR = 1; + default : state = SEND_DATA; + endcase + if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin + rd_ptr[intr_cnt_width-2:0] = 0; + end else begin + rd_ptr = rd_ptr+1; + end + end + end + WAIT_ACK :begin + state = WAIT_ACK; + if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin + WR_DATA_VALID_OCM = 1'b0; + WR_DATA_VALID_DDR = 1'b0; + state = SEND_DATA; + end + end + endcase +end +end + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v new file mode 100644 index 0000000..0e259e1 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v @@ -0,0 +1,223 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_ocm_mem.v + * + * Date : 2012-11 + * + * Description : Mimics OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_ocm_mem(); +`include "processing_system7_bfm_v2_0_5_local_params.v" + +parameter mem_size = 32'h4_0000; /// 256 KB +parameter mem_addr_width = clogb2(mem_size/mem_width); + +reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory + +/* preload memory from file */ +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits); +endtask + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; + +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : ocm_memory[addr] = $random; + ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000; + ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF; + default : ocm_memory[addr] = $random; + endcase + addr = addr+1; +end +end +endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +reg [mem_addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ +if(bytes_left < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + post_pad_data = ocm_memory[addr]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + ocm_memory[addr] = temp_data; +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + temp_data = ocm_memory[addr]; + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + ocm_memory[addr] = temp_data; + addr = addr + 1; + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + ocm_memory[addr] = wr_temp_data[data_width-1:0]; + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + + post_pad_data = ocm_memory[addr]; + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + ocm_memory[addr] = temp_data; + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [mem_addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + +if(no_of_bytes < mem_width ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - (mem_width - pre_bytes); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr]; + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + temp_rd_data = ocm_memory[addr]; + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + rd_data = ocm_memory[addr]; + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v new file mode 100644 index 0000000..adcaece --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v @@ -0,0 +1,189 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_ocmc.v + * + * Date : 2012-11 + * + * Description : Controller for OCM model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_ocmc( + rstn, + sw_clk, + +/* Goes to port 0 of OCM */ + ocm_wr_ack_port0, + ocm_wr_dv_port0, + ocm_rd_req_port0, + ocm_rd_dv_port0, + ocm_wr_addr_port0, + ocm_wr_data_port0, + ocm_wr_bytes_port0, + ocm_rd_addr_port0, + ocm_rd_data_port0, + ocm_rd_bytes_port0, + ocm_wr_qos_port0, + ocm_rd_qos_port0, + + +/* Goes to port 1 of OCM */ + ocm_wr_ack_port1, + ocm_wr_dv_port1, + ocm_rd_req_port1, + ocm_rd_dv_port1, + ocm_wr_addr_port1, + ocm_wr_data_port1, + ocm_wr_bytes_port1, + ocm_rd_addr_port1, + ocm_rd_data_port1, + ocm_rd_bytes_port1, + ocm_wr_qos_port1, + ocm_rd_qos_port1 + +); + +`include "processing_system7_bfm_v2_0_5_local_params.v" +input rstn; +input sw_clk; + +output ocm_wr_ack_port0; +input ocm_wr_dv_port0; +input ocm_rd_req_port0; +output ocm_rd_dv_port0; +input[addr_width-1:0] ocm_wr_addr_port0; +input[max_burst_bits-1:0] ocm_wr_data_port0; +input[max_burst_bytes_width:0] ocm_wr_bytes_port0; +input[addr_width-1:0] ocm_rd_addr_port0; +output[max_burst_bits-1:0] ocm_rd_data_port0; +input[max_burst_bytes_width:0] ocm_rd_bytes_port0; +input [axi_qos_width-1:0] ocm_wr_qos_port0; +input [axi_qos_width-1:0] ocm_rd_qos_port0; + +output ocm_wr_ack_port1; +input ocm_wr_dv_port1; +input ocm_rd_req_port1; +output ocm_rd_dv_port1; +input[addr_width-1:0] ocm_wr_addr_port1; +input[max_burst_bits-1:0] ocm_wr_data_port1; +input[max_burst_bytes_width:0] ocm_wr_bytes_port1; +input[addr_width-1:0] ocm_rd_addr_port1; +output[max_burst_bits-1:0] ocm_rd_data_port1; +input[max_burst_bytes_width:0] ocm_rd_bytes_port1; +input[axi_qos_width-1:0] ocm_wr_qos_port1; +input[axi_qos_width-1:0] ocm_rd_qos_port1; + +wire [axi_qos_width-1:0] wr_qos; +wire wr_req; +wire [max_burst_bits-1:0] wr_data; +wire [addr_width-1:0] wr_addr; +wire [max_burst_bytes_width:0] wr_bytes; +reg wr_ack; + +wire [axi_qos_width-1:0] rd_qos; +reg [max_burst_bits-1:0] rd_data; +wire [addr_width-1:0] rd_addr; +wire [max_burst_bytes_width:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_wr_qos_port0), + .qos2(ocm_wr_qos_port1), + + .prt_dv1(ocm_wr_dv_port0), + .prt_dv2(ocm_wr_dv_port1), + + .prt_data1(ocm_wr_data_port0), + .prt_data2(ocm_wr_data_port1), + + .prt_addr1(ocm_wr_addr_port0), + .prt_addr2(ocm_wr_addr_port1), + + .prt_bytes1(ocm_wr_bytes_port0), + .prt_bytes2(ocm_wr_bytes_port1), + + .prt_ack1(ocm_wr_ack_port0), + .prt_ack2(ocm_wr_ack_port1), + + .prt_qos(wr_qos), + .prt_req(wr_req), + .prt_data(wr_data), + .prt_addr(wr_addr), + .prt_bytes(wr_bytes), + .prt_ack(wr_ack) + +); + +processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(ocm_rd_qos_port0), + .qos2(ocm_rd_qos_port1), + + .prt_req1(ocm_rd_req_port0), + .prt_req2(ocm_rd_req_port1), + + .prt_data1(ocm_rd_data_port0), + .prt_data2(ocm_rd_data_port1), + + .prt_addr1(ocm_rd_addr_port0), + .prt_addr2(ocm_rd_addr_port1), + + .prt_bytes1(ocm_rd_bytes_port0), + .prt_bytes2(ocm_rd_bytes_port1), + + .prt_dv1(ocm_rd_dv_port0), + .prt_dv2(ocm_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_5_ocm_mem ocm(); + +reg [1:0] state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + wr_ack <= 0; + rd_dv <= 0; + state <= 2'd0; +end else begin + case(state) + 0:begin + state <= 0; + wr_ack <= 0; + rd_dv <= 0; + if(wr_req) begin + ocm.write_mem(wr_data , wr_addr, wr_bytes); + wr_ack <= 1; + state <= 1; + end + if(rd_req) begin + ocm.read_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + wr_ack <= 0; + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v new file mode 100644 index 0000000..fdd58c3 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v @@ -0,0 +1,2010 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_processing_system7_bfm.v + * + * Date : 2012-11 + * + * Description : Processing_system7_bfm Top (zynq_bfm top) + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_processing_system7_bfm + ( + CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_EXT_INTIN, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_EXT_INTIN, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TD_I, + PJTAG_TD_T, + PJTAG_TD_O, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + USB0_PORT_INDCTL, + USB1_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB1_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_AWREADY, + S_AXI_ACP_ARREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA0_DRTYPE, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA1_DRTYPE, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_DRVALID, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA2_DRTYPE, + DMA3_DRTYPE, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG, + FTMT_F2P_TRIGACK, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK, + FTMT_P2F_TRIG, + FTMT_P2F_DEBUG, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FPGA_IDLE_N, + DDR_ARB, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + MIO, + DDR_Clk, + DDR_Clk_n, + DDR_CKE, + DDR_CS_n, + DDR_RAS_n, + DDR_CAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_ODT, + DDR_DRSTB, + DDR_DQ, + DDR_DM, + DDR_DQS, + DDR_DQS_n, + DDR_VRN, + DDR_VRP, + PS_SRSTB, + PS_CLK, + PS_PORB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1 + ); + + + /* parameters for gen_clk */ + parameter C_FCLK_CLK0_FREQ = 50; + parameter C_FCLK_CLK1_FREQ = 50; + parameter C_FCLK_CLK3_FREQ = 50; + parameter C_FCLK_CLK2_FREQ = 50; + + parameter C_HIGH_OCM_EN = 0; + + + /* parameters for HP ports */ + parameter C_USE_S_AXI_HP0 = 0; + parameter C_USE_S_AXI_HP1 = 0; + parameter C_USE_S_AXI_HP2 = 0; + parameter C_USE_S_AXI_HP3 = 0; + + parameter C_S_AXI_HP0_DATA_WIDTH = 32; + parameter C_S_AXI_HP1_DATA_WIDTH = 32; + parameter C_S_AXI_HP2_DATA_WIDTH = 32; + parameter C_S_AXI_HP3_DATA_WIDTH = 32; + + parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; + parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0; + parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; + +/* Do we need these + parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */ + + parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF; + + /* parameters for GP and ACP ports */ + parameter C_USE_M_AXI_GP0 = 0; + parameter C_USE_M_AXI_GP1 = 0; + parameter C_USE_S_AXI_GP0 = 1; + parameter C_USE_S_AXI_GP1 = 1; + + /* Do we need this? + parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0; + parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0; + + parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/ + + parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000; + + parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF; + parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF; + + parameter C_USE_S_AXI_ACP = 1; + parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000; + parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF; + + `include "processing_system7_bfm_v2_0_5_local_params.v" + + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0] ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_EXT_INTIN; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input [7:0] ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0] ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_EXT_INTIN; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input [7:0] ENET1_GMII_RXD; + input [63:0] GPIO_I; + output [63:0] GPIO_O; + output [63:0] GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TD_I; + output PJTAG_TD_T; + output PJTAG_TD_O; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0] SDIO0_DATA_I; + output [3:0] SDIO0_DATA_O; + output [3:0] SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0] SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0] SDIO1_DATA_I; + output [3:0] SDIO1_DATA_O; + output [3:0] SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0] SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [31:0] TRACE_DATA; + output [1:0] USB0_PORT_INDCTL; + output [1:0] USB1_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + output USB1_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID; + output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID; + output [1:0] M_AXI_GP0_ARBURST; + output [1:0] M_AXI_GP0_ARLOCK; + output [2:0] M_AXI_GP0_ARSIZE; + output [1:0] M_AXI_GP0_AWBURST; + output [1:0] M_AXI_GP0_AWLOCK; + output [2:0] M_AXI_GP0_AWSIZE; + output [2:0] M_AXI_GP0_ARPROT; + output [2:0] M_AXI_GP0_AWPROT; + output [31:0] M_AXI_GP0_ARADDR; + output [31:0] M_AXI_GP0_AWADDR; + output [31:0] M_AXI_GP0_WDATA; + output [3:0] M_AXI_GP0_ARCACHE; + output [3:0] M_AXI_GP0_ARLEN; + output [3:0] M_AXI_GP0_ARQOS; + output [3:0] M_AXI_GP0_AWCACHE; + output [3:0] M_AXI_GP0_AWLEN; + output [3:0] M_AXI_GP0_AWQOS; + output [3:0] M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID; + input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID; + input [1:0] M_AXI_GP0_BRESP; + input [1:0] M_AXI_GP0_RRESP; + input [31:0] M_AXI_GP0_RDATA; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID; + output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID; + output [1:0] M_AXI_GP1_ARBURST; + output [1:0] M_AXI_GP1_ARLOCK; + output [2:0] M_AXI_GP1_ARSIZE; + output [1:0] M_AXI_GP1_AWBURST; + output [1:0] M_AXI_GP1_AWLOCK; + output [2:0] M_AXI_GP1_AWSIZE; + output [2:0] M_AXI_GP1_ARPROT; + output [2:0] M_AXI_GP1_AWPROT; + output [31:0] M_AXI_GP1_ARADDR; + output [31:0] M_AXI_GP1_AWADDR; + output [31:0] M_AXI_GP1_WDATA; + output [3:0] M_AXI_GP1_ARCACHE; + output [3:0] M_AXI_GP1_ARLEN; + output [3:0] M_AXI_GP1_ARQOS; + output [3:0] M_AXI_GP1_AWCACHE; + output [3:0] M_AXI_GP1_AWLEN; + output [3:0] M_AXI_GP1_AWQOS; + output [3:0] M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID; + input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID; + input [1:0] M_AXI_GP1_BRESP; + input [1:0] M_AXI_GP1_RRESP; + input [31:0] M_AXI_GP1_RDATA; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0] S_AXI_GP0_BRESP; + output [1:0] S_AXI_GP0_RRESP; + output [31:0] S_AXI_GP0_RDATA; + output [5:0] S_AXI_GP0_BID; + output [5:0] S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0] S_AXI_GP0_ARBURST; + input [1:0] S_AXI_GP0_ARLOCK; + input [2:0] S_AXI_GP0_ARSIZE; + input [1:0] S_AXI_GP0_AWBURST; + input [1:0] S_AXI_GP0_AWLOCK; + input [2:0] S_AXI_GP0_AWSIZE; + input [2:0] S_AXI_GP0_ARPROT; + input [2:0] S_AXI_GP0_AWPROT; + input [31:0] S_AXI_GP0_ARADDR; + input [31:0] S_AXI_GP0_AWADDR; + input [31:0] S_AXI_GP0_WDATA; + input [3:0] S_AXI_GP0_ARCACHE; + input [3:0] S_AXI_GP0_ARLEN; + input [3:0] S_AXI_GP0_ARQOS; + input [3:0] S_AXI_GP0_AWCACHE; + input [3:0] S_AXI_GP0_AWLEN; + input [3:0] S_AXI_GP0_AWQOS; + input [3:0] S_AXI_GP0_WSTRB; + input [5:0] S_AXI_GP0_ARID; + input [5:0] S_AXI_GP0_AWID; + input [5:0] S_AXI_GP0_WID; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0] S_AXI_GP1_BRESP; + output [1:0] S_AXI_GP1_RRESP; + output [31:0] S_AXI_GP1_RDATA; + output [5:0] S_AXI_GP1_BID; + output [5:0] S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0] S_AXI_GP1_ARBURST; + input [1:0] S_AXI_GP1_ARLOCK; + input [2:0] S_AXI_GP1_ARSIZE; + input [1:0] S_AXI_GP1_AWBURST; + input [1:0] S_AXI_GP1_AWLOCK; + input [2:0] S_AXI_GP1_AWSIZE; + input [2:0] S_AXI_GP1_ARPROT; + input [2:0] S_AXI_GP1_AWPROT; + input [31:0] S_AXI_GP1_ARADDR; + input [31:0] S_AXI_GP1_AWADDR; + input [31:0] S_AXI_GP1_WDATA; + input [3:0] S_AXI_GP1_ARCACHE; + input [3:0] S_AXI_GP1_ARLEN; + input [3:0] S_AXI_GP1_ARQOS; + input [3:0] S_AXI_GP1_AWCACHE; + input [3:0] S_AXI_GP1_AWLEN; + input [3:0] S_AXI_GP1_AWQOS; + input [3:0] S_AXI_GP1_WSTRB; + input [5:0] S_AXI_GP1_ARID; + input [5:0] S_AXI_GP1_AWID; + input [5:0] S_AXI_GP1_WID; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0] S_AXI_ACP_BRESP; + output [1:0] S_AXI_ACP_RRESP; + output [2:0] S_AXI_ACP_BID; + output [2:0] S_AXI_ACP_RID; + output [63:0] S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0] S_AXI_ACP_ARID; + input [2:0] S_AXI_ACP_ARPROT; + input [2:0] S_AXI_ACP_AWID; + input [2:0] S_AXI_ACP_AWPROT; + input [2:0] S_AXI_ACP_WID; + input [31:0] S_AXI_ACP_ARADDR; + input [31:0] S_AXI_ACP_AWADDR; + input [3:0] S_AXI_ACP_ARCACHE; + input [3:0] S_AXI_ACP_ARLEN; + input [3:0] S_AXI_ACP_ARQOS; + input [3:0] S_AXI_ACP_AWCACHE; + input [3:0] S_AXI_ACP_AWLEN; + input [3:0] S_AXI_ACP_AWQOS; + input [1:0] S_AXI_ACP_ARBURST; + input [1:0] S_AXI_ACP_ARLOCK; + input [2:0] S_AXI_ACP_ARSIZE; + input [1:0] S_AXI_ACP_AWBURST; + input [1:0] S_AXI_ACP_AWLOCK; + input [2:0] S_AXI_ACP_AWSIZE; + input [4:0] S_AXI_ACP_ARUSER; + input [4:0] S_AXI_ACP_AWUSER; + input [63:0] S_AXI_ACP_WDATA; + input [7:0] S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0] S_AXI_HP0_BRESP; + output [1:0] S_AXI_HP0_RRESP; + output [5:0] S_AXI_HP0_BID; + output [5:0] S_AXI_HP0_RID; + output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA; + output [7:0] S_AXI_HP0_RCOUNT; + output [7:0] S_AXI_HP0_WCOUNT; + output [2:0] S_AXI_HP0_RACOUNT; + output [5:0] S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0] S_AXI_HP0_ARBURST; + input [1:0] S_AXI_HP0_ARLOCK; + input [2:0] S_AXI_HP0_ARSIZE; + input [1:0] S_AXI_HP0_AWBURST; + input [1:0] S_AXI_HP0_AWLOCK; + input [2:0] S_AXI_HP0_AWSIZE; + input [2:0] S_AXI_HP0_ARPROT; + input [2:0] S_AXI_HP0_AWPROT; + input [31:0] S_AXI_HP0_ARADDR; + input [31:0] S_AXI_HP0_AWADDR; + input [3:0] S_AXI_HP0_ARCACHE; + input [3:0] S_AXI_HP0_ARLEN; + input [3:0] S_AXI_HP0_ARQOS; + input [3:0] S_AXI_HP0_AWCACHE; + input [3:0] S_AXI_HP0_AWLEN; + input [3:0] S_AXI_HP0_AWQOS; + input [5:0] S_AXI_HP0_ARID; + input [5:0] S_AXI_HP0_AWID; + input [5:0] S_AXI_HP0_WID; + input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA; + input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0] S_AXI_HP1_BRESP; + output [1:0] S_AXI_HP1_RRESP; + output [5:0] S_AXI_HP1_BID; + output [5:0] S_AXI_HP1_RID; + output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA; + output [7:0] S_AXI_HP1_RCOUNT; + output [7:0] S_AXI_HP1_WCOUNT; + output [2:0] S_AXI_HP1_RACOUNT; + output [5:0] S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0] S_AXI_HP1_ARBURST; + input [1:0] S_AXI_HP1_ARLOCK; + input [2:0] S_AXI_HP1_ARSIZE; + input [1:0] S_AXI_HP1_AWBURST; + input [1:0] S_AXI_HP1_AWLOCK; + input [2:0] S_AXI_HP1_AWSIZE; + input [2:0] S_AXI_HP1_ARPROT; + input [2:0] S_AXI_HP1_AWPROT; + input [31:0] S_AXI_HP1_ARADDR; + input [31:0] S_AXI_HP1_AWADDR; + input [3:0] S_AXI_HP1_ARCACHE; + input [3:0] S_AXI_HP1_ARLEN; + input [3:0] S_AXI_HP1_ARQOS; + input [3:0] S_AXI_HP1_AWCACHE; + input [3:0] S_AXI_HP1_AWLEN; + input [3:0] S_AXI_HP1_AWQOS; + input [5:0] S_AXI_HP1_ARID; + input [5:0] S_AXI_HP1_AWID; + input [5:0] S_AXI_HP1_WID; + input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA; + input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0] S_AXI_HP2_BRESP; + output [1:0] S_AXI_HP2_RRESP; + output [5:0] S_AXI_HP2_BID; + output [5:0] S_AXI_HP2_RID; + output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA; + output [7:0] S_AXI_HP2_RCOUNT; + output [7:0] S_AXI_HP2_WCOUNT; + output [2:0] S_AXI_HP2_RACOUNT; + output [5:0] S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0] S_AXI_HP2_ARBURST; + input [1:0] S_AXI_HP2_ARLOCK; + input [2:0] S_AXI_HP2_ARSIZE; + input [1:0] S_AXI_HP2_AWBURST; + input [1:0] S_AXI_HP2_AWLOCK; + input [2:0] S_AXI_HP2_AWSIZE; + input [2:0] S_AXI_HP2_ARPROT; + input [2:0] S_AXI_HP2_AWPROT; + input [31:0] S_AXI_HP2_ARADDR; + input [31:0] S_AXI_HP2_AWADDR; + input [3:0] S_AXI_HP2_ARCACHE; + input [3:0] S_AXI_HP2_ARLEN; + input [3:0] S_AXI_HP2_ARQOS; + input [3:0] S_AXI_HP2_AWCACHE; + input [3:0] S_AXI_HP2_AWLEN; + input [3:0] S_AXI_HP2_AWQOS; + input [5:0] S_AXI_HP2_ARID; + input [5:0] S_AXI_HP2_AWID; + input [5:0] S_AXI_HP2_WID; + input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA; + input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0] S_AXI_HP3_BRESP; + output [1:0] S_AXI_HP3_RRESP; + output [5:0] S_AXI_HP3_BID; + output [5:0] S_AXI_HP3_RID; + output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA; + output [7:0] S_AXI_HP3_RCOUNT; + output [7:0] S_AXI_HP3_WCOUNT; + output [2:0] S_AXI_HP3_RACOUNT; + output [5:0] S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0] S_AXI_HP3_ARBURST; + input [1:0] S_AXI_HP3_ARLOCK; + input [2:0] S_AXI_HP3_ARSIZE; + input [1:0] S_AXI_HP3_AWBURST; + input [1:0] S_AXI_HP3_AWLOCK; + input [2:0] S_AXI_HP3_AWSIZE; + input [2:0] S_AXI_HP3_ARPROT; + input [2:0] S_AXI_HP3_AWPROT; + input [31:0] S_AXI_HP3_ARADDR; + input [31:0] S_AXI_HP3_AWADDR; + input [3:0] S_AXI_HP3_ARCACHE; + input [3:0] S_AXI_HP3_ARLEN; + input [3:0] S_AXI_HP3_ARQOS; + input [3:0] S_AXI_HP3_AWCACHE; + input [3:0] S_AXI_HP3_AWLEN; + input [3:0] S_AXI_HP3_AWQOS; + input [5:0] S_AXI_HP3_ARID; + input [5:0] S_AXI_HP3_AWID; + input [5:0] S_AXI_HP3_WID; + input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA; + input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB; + output [1:0] DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input [1:0] DMA0_DRTYPE; + output [1:0] DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input [1:0] DMA1_DRTYPE; + output [1:0] DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_DRVALID; + output [1:0] DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input [1:0] DMA2_DRTYPE; + input [1:0] DMA3_DRTYPE; + input [31:0] FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0] FTMD_TRACEIN_ATID; + input [3:0] FTMT_F2P_TRIG; + output [3:0] FTMT_F2P_TRIGACK; + input [31:0] FTMT_F2P_DEBUG; + input [3:0] FTMT_P2F_TRIGACK; + output [3:0] FTMT_P2F_TRIG; + output [31:0] FTMT_P2F_DEBUG; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input FPGA_IDLE_N; + input [3:0] DDR_ARB; + input [irq_width-1:0] IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output EVENT_EVENTO; + output [1:0] EVENT_STANDBYWFE; + output [1:0] EVENT_STANDBYWFI; + input EVENT_EVENTI; + inout [53:0] MIO; + inout DDR_Clk; + inout DDR_Clk_n; + inout DDR_CKE; + inout DDR_CS_n; + inout DDR_RAS_n; + inout DDR_CAS_n; + output DDR_WEB; + inout [2:0] DDR_BankAddr; + inout [14:0] DDR_Addr; + inout DDR_ODT; + inout DDR_DRSTB; + inout [31:0] DDR_DQ; + inout [3:0] DDR_DM; + inout [3:0] DDR_DQS; + inout [3:0] DDR_DQS_n; + inout DDR_VRN; + inout DDR_VRP; +/* Reset Input & Clock Input */ + input PS_SRSTB; + input PS_CLK; + input PS_PORB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + + + /* Internal wires/nets used for connectivity */ + wire net_rstn; + wire net_sw_clk; + wire net_ocm_clk; + wire net_arbiter_clk; + + wire net_axi_mgp0_rstn; + wire net_axi_mgp1_rstn; + wire net_axi_gp0_rstn; + wire net_axi_gp1_rstn; + wire net_axi_hp0_rstn; + wire net_axi_hp1_rstn; + wire net_axi_hp2_rstn; + wire net_axi_hp3_rstn; + wire net_axi_acp_rstn; + wire [4:0] net_axi_acp_awuser; + wire [4:0] net_axi_acp_aruser; + + + /* Dummy */ + assign net_axi_acp_awuser = S_AXI_ACP_AWUSER; + assign net_axi_acp_aruser = S_AXI_ACP_ARUSER; + + /* Global variables */ + reg DEBUG_INFO = 1; + reg STOP_ON_ERROR = 1; + + /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ + reg mem_update_key = 1; + reg reg_update_key_0 = 1; + reg reg_update_key_1 = 1; + + /* assignments and semantic checks for unused ports */ + `include "processing_system7_bfm_v2_0_5_unused_ports.v" + + /* include api definition */ + `include "processing_system7_bfm_v2_0_5_apis.v" + + /* Reset Generator */ + processing_system7_bfm_v2_0_5_gen_reset gen_rst(.por_rst_n(PS_PORB), + .sys_rst_n(PS_SRSTB), + .rst_out_n(net_rstn), + + .m_axi_gp0_clk(M_AXI_GP0_ACLK), + .m_axi_gp1_clk(M_AXI_GP1_ACLK), + .s_axi_gp0_clk(S_AXI_GP0_ACLK), + .s_axi_gp1_clk(S_AXI_GP1_ACLK), + .s_axi_hp0_clk(S_AXI_HP0_ACLK), + .s_axi_hp1_clk(S_AXI_HP1_ACLK), + .s_axi_hp2_clk(S_AXI_HP2_ACLK), + .s_axi_hp3_clk(S_AXI_HP3_ACLK), + .s_axi_acp_clk(S_AXI_ACP_ACLK), + + .m_axi_gp0_rstn(net_axi_mgp0_rstn), + .m_axi_gp1_rstn(net_axi_mgp1_rstn), + .s_axi_gp0_rstn(net_axi_gp0_rstn), + .s_axi_gp1_rstn(net_axi_gp1_rstn), + .s_axi_hp0_rstn(net_axi_hp0_rstn), + .s_axi_hp1_rstn(net_axi_hp1_rstn), + .s_axi_hp2_rstn(net_axi_hp2_rstn), + .s_axi_hp3_rstn(net_axi_hp3_rstn), + .s_axi_acp_rstn(net_axi_acp_rstn), + + .fclk_reset3_n(FCLK_RESET3_N), + .fclk_reset2_n(FCLK_RESET2_N), + .fclk_reset1_n(FCLK_RESET1_N), + .fclk_reset0_n(FCLK_RESET0_N), + + .fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP) + .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN), + .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN), + .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN), + .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN), + .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN), + .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN), + .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN), + .fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN) + ); + + /* Clock Generator */ + processing_system7_bfm_v2_0_5_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ) + gen_clk(.ps_clk(PS_CLK), + .sw_clk(net_sw_clk), + + .fclk_clk3(FCLK_CLK3), + .fclk_clk2(FCLK_CLK2), + .fclk_clk1(FCLK_CLK1), + .fclk_clk0(FCLK_CLK0) + ); + + wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1; + wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1; + wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1; + wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1; + wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1; + wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1; + + wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1; + wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1; + wire net_rd_req_reg_gp0, net_rd_req_reg_gp1; + wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1; + wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1; + wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1; + wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1; + wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1; + wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1; + wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1; + wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1; + wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1; + + wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3; + wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3; + wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3; + wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3; + wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3; + wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3; + wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3; + wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3; + + wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3; + wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3; + wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3; + wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3; + wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3; + wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3; + wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3; + wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3; + wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3; + + wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp; + wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp; + wire [max_burst_bits-1:0] net_wr_data_acp; + wire [addr_width-1:0] net_wr_addr_acp; + wire [max_burst_bytes_width:0] net_wr_bytes_acp; + wire [axi_qos_width-1:0] net_wr_qos_acp; + + wire net_rd_req_ddr_acp, net_rd_req_ocm_acp; + wire [addr_width-1:0] net_rd_addr_acp; + wire [max_burst_bytes_width:0] net_rd_bytes_acp; + wire [max_burst_bits-1:0] net_rd_data_ddr_acp; + wire [max_burst_bits-1:0] net_rd_data_ocm_acp; + wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp; + wire [axi_qos_width-1:0] net_rd_qos_acp; + + wire ocm_wr_ack_port0; + wire ocm_wr_dv_port0; + wire ocm_rd_req_port0; + wire ocm_rd_dv_port0; + wire [addr_width-1:0] ocm_wr_addr_port0; + wire [max_burst_bits-1:0] ocm_wr_data_port0; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port0; + wire [addr_width-1:0] ocm_rd_addr_port0; + wire [max_burst_bits-1:0] ocm_rd_data_port0; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port0; + wire [axi_qos_width-1:0] ocm_wr_qos_port0; + wire [axi_qos_width-1:0] ocm_rd_qos_port0; + + wire ocm_wr_ack_port1; + wire ocm_wr_dv_port1; + wire ocm_rd_req_port1; + wire ocm_rd_dv_port1; + wire [addr_width-1:0] ocm_wr_addr_port1; + wire [max_burst_bits-1:0] ocm_wr_data_port1; + wire [max_burst_bytes_width:0] ocm_wr_bytes_port1; + wire [addr_width-1:0] ocm_rd_addr_port1; + wire [max_burst_bits-1:0] ocm_rd_data_port1; + wire [max_burst_bytes_width:0] ocm_rd_bytes_port1; + wire [axi_qos_width-1:0] ocm_wr_qos_port1; + wire [axi_qos_width-1:0] ocm_rd_qos_port1; + + wire ddr_wr_ack_port0; + wire ddr_wr_dv_port0; + wire ddr_rd_req_port0; + wire ddr_rd_dv_port0; + wire[addr_width-1:0] ddr_wr_addr_port0; + wire[max_burst_bits-1:0] ddr_wr_data_port0; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port0; + wire[addr_width-1:0] ddr_rd_addr_port0; + wire[max_burst_bits-1:0] ddr_rd_data_port0; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port0; + wire [axi_qos_width-1:0] ddr_wr_qos_port0; + wire [axi_qos_width-1:0] ddr_rd_qos_port0; + + wire ddr_wr_ack_port1; + wire ddr_wr_dv_port1; + wire ddr_rd_req_port1; + wire ddr_rd_dv_port1; + wire[addr_width-1:0] ddr_wr_addr_port1; + wire[max_burst_bits-1:0] ddr_wr_data_port1; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port1; + wire[addr_width-1:0] ddr_rd_addr_port1; + wire[max_burst_bits-1:0] ddr_rd_data_port1; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port1; + wire[axi_qos_width-1:0] ddr_wr_qos_port1; + wire[axi_qos_width-1:0] ddr_rd_qos_port1; + + wire ddr_wr_ack_port2; + wire ddr_wr_dv_port2; + wire ddr_rd_req_port2; + wire ddr_rd_dv_port2; + wire[addr_width-1:0] ddr_wr_addr_port2; + wire[max_burst_bits-1:0] ddr_wr_data_port2; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port2; + wire[addr_width-1:0] ddr_rd_addr_port2; + wire[max_burst_bits-1:0] ddr_rd_data_port2; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port2; + wire[axi_qos_width-1:0] ddr_wr_qos_port2; + wire[axi_qos_width-1:0] ddr_rd_qos_port2; + + wire ddr_wr_ack_port3; + wire ddr_wr_dv_port3; + wire ddr_rd_req_port3; + wire ddr_rd_dv_port3; + wire[addr_width-1:0] ddr_wr_addr_port3; + wire[max_burst_bits-1:0] ddr_wr_data_port3; + wire[max_burst_bytes_width:0] ddr_wr_bytes_port3; + wire[addr_width-1:0] ddr_rd_addr_port3; + wire[max_burst_bits-1:0] ddr_rd_data_port3; + wire[max_burst_bytes_width:0] ddr_rd_bytes_port3; + wire[axi_qos_width-1:0] ddr_wr_qos_port3; + wire[axi_qos_width-1:0] ddr_rd_qos_port3; + + wire reg_rd_req_port0; + wire reg_rd_dv_port0; + wire[addr_width-1:0] reg_rd_addr_port0; + wire[max_burst_bits-1:0] reg_rd_data_port0; + wire[max_burst_bytes_width:0] reg_rd_bytes_port0; + wire [axi_qos_width-1:0] reg_rd_qos_port0; + + wire reg_rd_req_port1; + wire reg_rd_dv_port1; + wire[addr_width-1:0] reg_rd_addr_port1; + wire[max_burst_bits-1:0] reg_rd_data_port1; + wire[max_burst_bytes_width:0] reg_rd_bytes_port1; + wire [axi_qos_width-1:0] reg_rd_qos_port1; + + wire [11:0] M_AXI_GP0_AWID_FULL; + wire [11:0] M_AXI_GP0_WID_FULL; + wire [11:0] M_AXI_GP0_ARID_FULL; + + wire [11:0] M_AXI_GP0_BID_FULL; + wire [11:0] M_AXI_GP0_RID_FULL; + + wire [11:0] M_AXI_GP1_AWID_FULL; + wire [11:0] M_AXI_GP1_WID_FULL; + wire [11:0] M_AXI_GP1_ARID_FULL; + + wire [11:0] M_AXI_GP1_BID_FULL; + wire [11:0] M_AXI_GP1_RID_FULL; + + + function [5:0] compress_id; + input [11:0] id; + begin + compress_id = id[5:0]; + end + endfunction + + function [11:0] uncompress_id; + input [5:0] id; + begin + uncompress_id = {6'b110000, id[5:0]}; + end + endfunction + + assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; + assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; + assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; + assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; + assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; + + + assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; + assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; + assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; + assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; + assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; + + + + + processing_system7_bfm_v2_0_5_interconnect_model icm ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + .w_qos_gp0(net_wr_qos_gp0), + .w_qos_gp1(net_wr_qos_gp1), + .w_qos_hp0(net_wr_qos_hp0), + .w_qos_hp1(net_wr_qos_hp1), + .w_qos_hp2(net_wr_qos_hp2), + .w_qos_hp3(net_wr_qos_hp3), + + .r_qos_gp0(net_rd_qos_gp0), + .r_qos_gp1(net_rd_qos_gp1), + .r_qos_hp0(net_rd_qos_hp0), + .r_qos_hp1(net_rd_qos_hp1), + .r_qos_hp2(net_rd_qos_hp2), + .r_qos_hp3(net_rd_qos_hp3), + + /* GP Slave ports access */ + .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0), + .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0), + .wr_data_gp0(net_wr_data_gp0), + .wr_addr_gp0(net_wr_addr_gp0), + .wr_bytes_gp0(net_wr_bytes_gp0), + .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0), + .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0), + .rd_req_ddr_gp0(net_rd_req_ddr_gp0), + .rd_req_ocm_gp0(net_rd_req_ocm_gp0), + .rd_req_reg_gp0(net_rd_req_reg_gp0), + .rd_addr_gp0(net_rd_addr_gp0), + .rd_bytes_gp0(net_rd_bytes_gp0), + .rd_data_ddr_gp0(net_rd_data_ddr_gp0), + .rd_data_ocm_gp0(net_rd_data_ocm_gp0), + .rd_data_reg_gp0(net_rd_data_reg_gp0), + .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0), + .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0), + .rd_dv_reg_gp0(net_rd_dv_reg_gp0), + + .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1), + .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1), + .wr_data_gp1(net_wr_data_gp1), + .wr_addr_gp1(net_wr_addr_gp1), + .wr_bytes_gp1(net_wr_bytes_gp1), + .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1), + .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1), + .rd_req_ddr_gp1(net_rd_req_ddr_gp1), + .rd_req_ocm_gp1(net_rd_req_ocm_gp1), + .rd_req_reg_gp1(net_rd_req_reg_gp1), + .rd_addr_gp1(net_rd_addr_gp1), + .rd_bytes_gp1(net_rd_bytes_gp1), + .rd_data_ddr_gp1(net_rd_data_ddr_gp1), + .rd_data_ocm_gp1(net_rd_data_ocm_gp1), + .rd_data_reg_gp1(net_rd_data_reg_gp1), + .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1), + .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1), + .rd_dv_reg_gp1(net_rd_dv_reg_gp1), + + /* HP Slave ports access */ + .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0), + .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0), + .wr_data_hp0(net_wr_data_hp0), + .wr_addr_hp0(net_wr_addr_hp0), + .wr_bytes_hp0(net_wr_bytes_hp0), + .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0), + .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0), + .rd_req_ddr_hp0(net_rd_req_ddr_hp0), + .rd_req_ocm_hp0(net_rd_req_ocm_hp0), + .rd_addr_hp0(net_rd_addr_hp0), + .rd_bytes_hp0(net_rd_bytes_hp0), + .rd_data_ddr_hp0(net_rd_data_ddr_hp0), + .rd_data_ocm_hp0(net_rd_data_ocm_hp0), + .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0), + .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0), + + .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1), + .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1), + .wr_data_hp1(net_wr_data_hp1), + .wr_addr_hp1(net_wr_addr_hp1), + .wr_bytes_hp1(net_wr_bytes_hp1), + .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1), + .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1), + .rd_req_ddr_hp1(net_rd_req_ddr_hp1), + .rd_req_ocm_hp1(net_rd_req_ocm_hp1), + .rd_addr_hp1(net_rd_addr_hp1), + .rd_bytes_hp1(net_rd_bytes_hp1), + .rd_data_ddr_hp1(net_rd_data_ddr_hp1), + .rd_data_ocm_hp1(net_rd_data_ocm_hp1), + .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1), + .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1), + + .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2), + .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2), + .wr_data_hp2(net_wr_data_hp2), + .wr_addr_hp2(net_wr_addr_hp2), + .wr_bytes_hp2(net_wr_bytes_hp2), + .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2), + .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2), + .rd_req_ddr_hp2(net_rd_req_ddr_hp2), + .rd_req_ocm_hp2(net_rd_req_ocm_hp2), + .rd_addr_hp2(net_rd_addr_hp2), + .rd_bytes_hp2(net_rd_bytes_hp2), + .rd_data_ddr_hp2(net_rd_data_ddr_hp2), + .rd_data_ocm_hp2(net_rd_data_ocm_hp2), + .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2), + .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2), + + .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3), + .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3), + .wr_data_hp3(net_wr_data_hp3), + .wr_addr_hp3(net_wr_addr_hp3), + .wr_bytes_hp3(net_wr_bytes_hp3), + .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3), + .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3), + .rd_req_ddr_hp3(net_rd_req_ddr_hp3), + .rd_req_ocm_hp3(net_rd_req_ocm_hp3), + .rd_addr_hp3(net_rd_addr_hp3), + .rd_bytes_hp3(net_rd_bytes_hp3), + .rd_data_ddr_hp3(net_rd_data_ddr_hp3), + .rd_data_ocm_hp3(net_rd_data_ocm_hp3), + .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3), + .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3), + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1(ddr_wr_ack_port1), + .ddr_wr_dv_port1(ddr_wr_dv_port1), + .ddr_rd_req_port1(ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1(ddr_wr_qos_port1), + .ddr_rd_qos_port1(ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1), + + /* Goes to port 0 of REG */ + .reg_rd_qos_port1 (reg_rd_qos_port1) , + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1) + ); + + processing_system7_bfm_v2_0_5_ddrc ddrc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of DDR */ + .ddr_wr_ack_port0 (ddr_wr_ack_port0), + .ddr_wr_dv_port0 (ddr_wr_dv_port0), + .ddr_rd_req_port0 (ddr_rd_req_port0), + .ddr_rd_dv_port0 (ddr_rd_dv_port0), + + .ddr_wr_addr_port0(net_wr_addr_acp), + .ddr_wr_data_port0(net_wr_data_acp), + .ddr_wr_bytes_port0(net_wr_bytes_acp), + + .ddr_rd_addr_port0(net_rd_addr_acp), + .ddr_rd_bytes_port0(net_rd_bytes_acp), + + .ddr_rd_data_port0(ddr_rd_data_port0), + + .ddr_wr_qos_port0 (net_wr_qos_acp), + .ddr_rd_qos_port0 (net_rd_qos_acp), + + + /* Goes to port 1 of DDR */ + .ddr_wr_ack_port1 (ddr_wr_ack_port1), + .ddr_wr_dv_port1 (ddr_wr_dv_port1), + .ddr_rd_req_port1 (ddr_rd_req_port1), + .ddr_rd_dv_port1 (ddr_rd_dv_port1), + .ddr_wr_addr_port1(ddr_wr_addr_port1), + .ddr_wr_data_port1(ddr_wr_data_port1), + .ddr_wr_bytes_port1(ddr_wr_bytes_port1), + .ddr_rd_addr_port1(ddr_rd_addr_port1), + .ddr_rd_data_port1(ddr_rd_data_port1), + .ddr_rd_bytes_port1(ddr_rd_bytes_port1), + .ddr_wr_qos_port1 (ddr_wr_qos_port1), + .ddr_rd_qos_port1 (ddr_rd_qos_port1), + + /* Goes to port2 of DDR */ + .ddr_wr_ack_port2 (ddr_wr_ack_port2), + .ddr_wr_dv_port2 (ddr_wr_dv_port2), + .ddr_rd_req_port2 (ddr_rd_req_port2), + .ddr_rd_dv_port2 (ddr_rd_dv_port2), + .ddr_wr_addr_port2(ddr_wr_addr_port2), + .ddr_wr_data_port2(ddr_wr_data_port2), + .ddr_wr_bytes_port2(ddr_wr_bytes_port2), + .ddr_rd_addr_port2(ddr_rd_addr_port2), + .ddr_rd_data_port2(ddr_rd_data_port2), + .ddr_rd_bytes_port2(ddr_rd_bytes_port2), + .ddr_wr_qos_port2 (ddr_wr_qos_port2), + .ddr_rd_qos_port2 (ddr_rd_qos_port2), + + /* Goes to port3 of DDR */ + .ddr_wr_ack_port3 (ddr_wr_ack_port3), + .ddr_wr_dv_port3 (ddr_wr_dv_port3), + .ddr_rd_req_port3 (ddr_rd_req_port3), + .ddr_rd_dv_port3 (ddr_rd_dv_port3), + .ddr_wr_addr_port3(ddr_wr_addr_port3), + .ddr_wr_data_port3(ddr_wr_data_port3), + .ddr_wr_bytes_port3(ddr_wr_bytes_port3), + .ddr_rd_addr_port3(ddr_rd_addr_port3), + .ddr_rd_data_port3(ddr_rd_data_port3), + .ddr_rd_bytes_port3(ddr_rd_bytes_port3), + .ddr_wr_qos_port3 (ddr_wr_qos_port3), + .ddr_rd_qos_port3 (ddr_rd_qos_port3) + + ); + + processing_system7_bfm_v2_0_5_ocmc ocmc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of OCM */ + .ocm_wr_ack_port0 (ocm_wr_ack_port0), + .ocm_wr_dv_port0 (ocm_wr_dv_port0), + .ocm_rd_req_port0 (ocm_rd_req_port0), + .ocm_rd_dv_port0 (ocm_rd_dv_port0), + + .ocm_wr_addr_port0(net_wr_addr_acp), + .ocm_wr_data_port0(net_wr_data_acp), + .ocm_wr_bytes_port0(net_wr_bytes_acp), + + .ocm_rd_addr_port0(net_rd_addr_acp), + .ocm_rd_bytes_port0(net_rd_bytes_acp), + + .ocm_rd_data_port0(ocm_rd_data_port0), + + .ocm_wr_qos_port0 (net_wr_qos_acp), + .ocm_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of OCM */ + .ocm_wr_ack_port1 (ocm_wr_ack_port1), + .ocm_wr_dv_port1 (ocm_wr_dv_port1), + .ocm_rd_req_port1 (ocm_rd_req_port1), + .ocm_rd_dv_port1 (ocm_rd_dv_port1), + .ocm_wr_addr_port1(ocm_wr_addr_port1), + .ocm_wr_data_port1(ocm_wr_data_port1), + .ocm_wr_bytes_port1(ocm_wr_bytes_port1), + .ocm_rd_addr_port1(ocm_rd_addr_port1), + .ocm_rd_data_port1(ocm_rd_data_port1), + .ocm_rd_bytes_port1(ocm_rd_bytes_port1), + .ocm_wr_qos_port1(ocm_wr_qos_port1), + .ocm_rd_qos_port1(ocm_rd_qos_port1) + + ); + + processing_system7_bfm_v2_0_5_regc regc ( + .rstn(net_rstn), + .sw_clk(net_sw_clk), + + /* Goes to port 0 of REG */ + .reg_rd_req_port0 (reg_rd_req_port0), + .reg_rd_dv_port0 (reg_rd_dv_port0), + .reg_rd_addr_port0(net_rd_addr_acp), + .reg_rd_bytes_port0(net_rd_bytes_acp), + .reg_rd_data_port0(reg_rd_data_port0), + .reg_rd_qos_port0 (net_rd_qos_acp), + + /* Goes to port 1 of REG */ + .reg_rd_req_port1 (reg_rd_req_port1), + .reg_rd_dv_port1 (reg_rd_dv_port1), + .reg_rd_addr_port1(reg_rd_addr_port1), + .reg_rd_data_port1(reg_rd_data_port1), + .reg_rd_bytes_port1(reg_rd_bytes_port1), + .reg_rd_qos_port1(reg_rd_qos_port1) + + ); + + /* include axi_gp port instantiations */ + `include "processing_system7_bfm_v2_0_5_axi_gp.v" + + /* include axi_hp port instantiations */ + `include "processing_system7_bfm_v2_0_5_axi_hp.v" + + /* include axi_acp port instantiations */ + `include "processing_system7_bfm_v2_0_5_axi_acp.v" + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v new file mode 100644 index 0000000..1a2aeb6 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v @@ -0,0 +1,156 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_reg_map.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_reg_map(); + +`include "processing_system7_bfm_v2_0_5_local_params.v" + +/* Register definitions */ +`include "processing_system7_bfm_v2_0_5_reg_params.v" + +parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide +parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB + +`ifdef XSIM_ISIM + reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + parameter addr_offset_bits = 26; +`else + reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space + parameter addr_offset_bits = 27; +`endif + +/* preload reset_values from file */ +task automatic pre_load_rst_values; +input dummy; +begin + `include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/ +end +endtask + +/* writes the reset data into the reg memory */ +task automatic set_reset_data; +input [addr_width-1:0] address; +input [data_width-1:0] data; +reg [addr_width-1:0] addr; +begin +addr = address >> 2; +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 14 : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 15 : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* writes the data into the reg memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data; + 6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data; + endcase +`else + reg_mem[addr[addr_offset_bits-1:0]] = data; +`endif +end +endtask + +/* get the read data from reg mem */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[addr_width-1:addr_offset_bits]) + 6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]]; + 6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]]; + endcase +`else + data = reg_mem[addr[addr_offset_bits-1:0]]; +`endif +end +endtask + +/* read chunk of registers */ +task read_reg_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]); + +if(no_of_bytes < mem_width ) begin + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - mem_width; + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +initial +begin + pre_load_rst_values(1); +end + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v new file mode 100644 index 0000000..1b07539 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v @@ -0,0 +1,118 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_regc.v + * + * Date : 2012-11 + * + * Description : Controller for Register Map Memory + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_regc( + rstn, + sw_clk, + +/* Goes to port 0 of REG */ + reg_rd_req_port0, + reg_rd_dv_port0, + reg_rd_addr_port0, + reg_rd_data_port0, + reg_rd_bytes_port0, + reg_rd_qos_port0, + + +/* Goes to port 1 of REG */ + reg_rd_req_port1, + reg_rd_dv_port1, + reg_rd_addr_port1, + reg_rd_data_port1, + reg_rd_bytes_port1, + reg_rd_qos_port1 + +); + +input rstn; +input sw_clk; + +input reg_rd_req_port0; +output reg_rd_dv_port0; +input[31:0] reg_rd_addr_port0; +output[1023:0] reg_rd_data_port0; +input[7:0] reg_rd_bytes_port0; +input [3:0] reg_rd_qos_port0; + +input reg_rd_req_port1; +output reg_rd_dv_port1; +input[31:0] reg_rd_addr_port1; +output[1023:0] reg_rd_data_port1; +input[7:0] reg_rd_bytes_port1; +input[3:0] reg_rd_qos_port1; + +wire [3:0] rd_qos; +reg [1023:0] rd_data; +wire [31:0] rd_addr; +wire [7:0] rd_bytes; +reg rd_dv; +wire rd_req; + +processing_system7_bfm_v2_0_5_arb_rd reg_read_ports ( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(reg_rd_qos_port0), + .qos2(reg_rd_qos_port1), + + .prt_req1(reg_rd_req_port0), + .prt_req2(reg_rd_req_port1), + + .prt_data1(reg_rd_data_port0), + .prt_data2(reg_rd_data_port1), + + .prt_addr1(reg_rd_addr_port0), + .prt_addr2(reg_rd_addr_port1), + + .prt_bytes1(reg_rd_bytes_port0), + .prt_bytes2(reg_rd_bytes_port1), + + .prt_dv1(reg_rd_dv_port0), + .prt_dv2(reg_rd_dv_port1), + + .prt_qos(rd_qos), + .prt_req(rd_req), + .prt_data(rd_data), + .prt_addr(rd_addr), + .prt_bytes(rd_bytes), + .prt_dv(rd_dv) + +); + +processing_system7_bfm_v2_0_5_reg_map regm(); + +reg state; +always@(posedge sw_clk or negedge rstn) +begin +if(!rstn) begin + rd_dv <= 0; + state <= 0; +end else begin + case(state) + 0:begin + state <= 0; + rd_dv <= 0; + if(rd_req) begin + regm.read_reg_mem(rd_data,rd_addr, rd_bytes); + rd_dv <= 1; + state <= 1; + end + + end + 1:begin + rd_dv <= 0; + state <= 0; + end + + endcase +end /// if +end// always + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_sparse_mem.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_sparse_mem.v new file mode 100644 index 0000000..30cbbb9 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_sparse_mem.v @@ -0,0 +1,317 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_sparse_mem.v + * + * Date : 2012-11 + * + * Description : Sparse Memory Model + * + *****************************************************************************/ + +/*** WA for CR # 695818 ***/ +`ifdef XILINX_SIMULATOR + `define XSIM_ISIM +`endif +`ifdef XILINX_ISIM + `define XSIM_ISIM +`endif + + `timescale 1ns/1ps +module processing_system7_bfm_v2_0_5_sparse_mem(); + +`include "processing_system7_bfm_v2_0_5_local_params.v" + +parameter mem_size = 32'h4000_0000; /// 1GB mem size +parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM) + + +`ifdef XSIM_ISIM + reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem + reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem +`else + reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem +`endif + +event mem_updated; +reg check_we; +reg [addr_width-1:0] check_up_add; +reg [data_width-1:0] updated_data; + +/* preload memory from file */ +task automatic pre_load_mem_from_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +`ifdef XSIM_ISIM + case(start_addr[31:28]) + 4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits); + 4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits); + 4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits); + 4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits); + endcase +`else + $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits); +`endif +endtask + +/* preload memory with some random data */ +task automatic pre_load_mem; +input [1:0] data_type; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +begin +addr = start_addr >> shft_addr_bits; +for (i = 0; i < no_of_bytes; i = i + mem_width) begin + case(data_type) + ALL_RANDOM : set_data(addr , $random); + ALL_ZEROS : set_data(addr , 32'h0000_0000); + ALL_ONES : set_data(addr , 32'hFFFF_FFFF); + default : set_data(addr , $random); + endcase + addr = addr+1; +end +end +endtask + +/* wait for memory update at certain location */ +task automatic wait_mem_update; +input[addr_width-1:0] address; +output[data_width-1:0] dataout; +begin + check_up_add = address >> shft_addr_bits; + check_we = 1; + @(mem_updated); + dataout = updated_data; + check_we = 0; +end +endtask + +/* internal task to write data in memory */ +task automatic set_data; +input [addr_width-1:0] addr; +input [data_width-1:0] data; +begin +if(check_we && (addr === check_up_add)) begin + updated_data = data; + -> mem_updated; +end +`ifdef XSIM_ISIM + case(addr[31:26]) + 6'd0 : ddr_mem0[addr[25:0]] = data; + 6'd1 : ddr_mem1[addr[25:0]] = data; + 6'd2 : ddr_mem2[addr[25:0]] = data; + 6'd3 : ddr_mem3[addr[25:0]] = data; + endcase +`else + ddr_mem[addr] = data; +`endif +end +endtask + +/* internal task to read data from memory */ +task automatic get_data; +input [addr_width-1:0] addr; +output [data_width-1:0] data; +begin +`ifdef XSIM_ISIM + case(addr[31:26]) + 6'd0 : data = ddr_mem0[addr[25:0]]; + 6'd1 : data = ddr_mem1[addr[25:0]]; + 6'd2 : data = ddr_mem2[addr[25:0]]; + 6'd3 : data = ddr_mem3[addr[25:0]]; + endcase +`else + data = ddr_mem[addr]; +`endif +end +endtask + +/* Write memory */ +task write_mem; +input [max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width:0] no_of_bytes; +reg [addr_width-1:0] addr; +reg [max_burst_bits-1 :0] wr_temp_data; +reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data; +integer bytes_left; +integer pre_pad_bytes; +integer post_pad_bytes; +begin +addr = start_addr >> shft_addr_bits; +wr_temp_data = data; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); +`endif + +temp_data = wr_temp_data[data_width-1:0]; +bytes_left = no_of_bytes; +/* when the no. of bytes to be updated is less than mem_width */ +if(bytes_left < mem_width) begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + end + bytes_left = bytes_left + pre_pad_bytes; + end + /* This is needed for post padding the data ...*/ + post_pad_bytes = mem_width - bytes_left; + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); +end else begin + /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/ + if(start_addr[shft_addr_bits-1:0] > 0) begin + //temp_data = ddr_mem[addr]; + get_data(addr,temp_data); + pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0]; + repeat(pre_pad_bytes) temp_data = temp_data << 8; + repeat(pre_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = wr_temp_data[7:0]; + wr_temp_data = wr_temp_data >> 8; + bytes_left = bytes_left -1; + end + end else begin + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + /* first data word end */ + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); + addr = addr + 1; + while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes. + //ddr_mem[addr] = wr_temp_data[data_width-1:0]; + set_data(addr,wr_temp_data[data_width-1:0]); + addr = addr+1; + wr_temp_data = wr_temp_data >> data_width; + bytes_left = bytes_left - mem_width; + end + + //post_pad_data = ddr_mem[addr]; + get_data(addr,post_pad_data); + post_pad_bytes = mem_width - bytes_left; + /* This is needed for last transfer in unaliged burst */ + if(bytes_left > 0) begin + temp_data = wr_temp_data[data_width-1:0]; + repeat(post_pad_bytes) temp_data = temp_data << 8; + repeat(bytes_left) post_pad_data = post_pad_data >> 8; + repeat(post_pad_bytes) begin + temp_data = temp_data >> 8; + temp_data[data_width-1:data_width-8] = post_pad_data[7:0]; + post_pad_data = post_pad_data >> 8; + end + //ddr_mem[addr] = temp_data; + set_data(addr,temp_data); + end +end +`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); +`endif +end +endtask + +/* read_memory */ +task read_mem; +output[max_burst_bits-1 :0] data; +input [addr_width-1:0] start_addr; +input [max_burst_bytes_width :0] no_of_bytes; +integer i; +reg [addr_width-1:0] addr; +reg [data_width-1:0] temp_rd_data; +reg [max_burst_bits-1:0] temp_data; +integer pre_bytes; +integer bytes_left; +begin +addr = start_addr >> shft_addr_bits; +pre_bytes = start_addr[shft_addr_bits-1:0]; +bytes_left = no_of_bytes; + +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); +`endif + +/* Get first data ... if unaligned address */ +//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; +get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + +if(no_of_bytes < mem_width ) begin + temp_data = temp_data >> (pre_bytes * 8); + repeat(max_burst_bytes - mem_width) + temp_data = temp_data >> 8; + +end else begin + bytes_left = bytes_left - (mem_width - pre_bytes); + addr = addr+1; + /* Got first data */ + while (bytes_left > (mem_width-1) ) begin + temp_data = temp_data >> data_width; + //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr]; + get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]); + addr = addr+1; + bytes_left = bytes_left - mem_width; + end + + /* Get last valid data in the burst*/ + //temp_rd_data = ddr_mem[addr]; + get_data(addr,temp_rd_data); + while(bytes_left > 0) begin + temp_data = temp_data >> 8; + temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0]; + temp_rd_data = temp_rd_data >> 8; + bytes_left = bytes_left - 1; + end + /* align to the brst_byte length */ + repeat(max_burst_bytes - no_of_bytes) + temp_data = temp_data >> 8; +end +data = temp_data; +`ifdef XLNX_INT_DBG + $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); +`endif +end +endtask + +/* backdoor read to memory */ +task peek_mem_to_file; +input [(max_chars*8)-1:0] file_name; +input [addr_width-1:0] start_addr; +input [int_width-1:0] no_of_bytes; + +integer rd_fd; +integer bytes; +reg [addr_width-1:0] addr; +reg [data_width-1:0] rd_data; +begin +rd_fd = $fopen(file_name,"w"); +bytes = no_of_bytes; + +addr = start_addr >> shft_addr_bits; +while (bytes > 0) begin + get_data(addr,rd_data); + $fdisplayh(rd_fd,rd_data); + bytes = bytes - 4; + addr = addr + 1; +end +end +endtask + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ssw_hp.v b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ssw_hp.v new file mode 100644 index 0000000..c8e0705 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ssw_hp.v @@ -0,0 +1,443 @@ +/***************************************************************************** + * File : processing_system7_bfm_v2_0_5_ssw_hp.v + * + * Date : 2012-11 + * + * Description : SSW switch Model + * + *****************************************************************************/ + `timescale 1ns/1ps + +module processing_system7_bfm_v2_0_5_ssw_hp( + sw_clk, + rstn, + w_qos_hp0, + r_qos_hp0, + w_qos_hp1, + r_qos_hp1, + w_qos_hp2, + r_qos_hp2, + w_qos_hp3, + r_qos_hp3, + + wr_ack_ddr_hp0, + wr_data_hp0, + wr_addr_hp0, + wr_bytes_hp0, + wr_dv_ddr_hp0, + rd_req_ddr_hp0, + rd_addr_hp0, + rd_bytes_hp0, + rd_data_ddr_hp0, + rd_dv_ddr_hp0, + + rd_data_ocm_hp0, + wr_ack_ocm_hp0, + wr_dv_ocm_hp0, + rd_req_ocm_hp0, + rd_dv_ocm_hp0, + + wr_ack_ddr_hp1, + wr_data_hp1, + wr_addr_hp1, + wr_bytes_hp1, + wr_dv_ddr_hp1, + rd_req_ddr_hp1, + rd_addr_hp1, + rd_bytes_hp1, + rd_data_ddr_hp1, + rd_data_ocm_hp1, + rd_dv_ddr_hp1, + + wr_ack_ocm_hp1, + wr_dv_ocm_hp1, + rd_req_ocm_hp1, + rd_dv_ocm_hp1, + + wr_ack_ddr_hp2, + wr_data_hp2, + wr_addr_hp2, + wr_bytes_hp2, + wr_dv_ddr_hp2, + rd_req_ddr_hp2, + rd_addr_hp2, + rd_bytes_hp2, + rd_data_ddr_hp2, + rd_data_ocm_hp2, + rd_dv_ddr_hp2, + + wr_ack_ocm_hp2, + wr_dv_ocm_hp2, + rd_req_ocm_hp2, + rd_dv_ocm_hp2, + + wr_ack_ddr_hp3, + wr_data_hp3, + wr_addr_hp3, + wr_bytes_hp3, + wr_dv_ddr_hp3, + rd_req_ddr_hp3, + rd_addr_hp3, + rd_bytes_hp3, + rd_data_ocm_hp3, + rd_data_ddr_hp3, + rd_dv_ddr_hp3, + + wr_ack_ocm_hp3, + wr_dv_ocm_hp3, + rd_req_ocm_hp3, + rd_dv_ocm_hp3, + + ddr_wr_ack0, + ddr_wr_dv0, + ddr_rd_req0, + ddr_rd_dv0, + ddr_rd_qos0, + ddr_wr_qos0, + + ddr_wr_addr0, + ddr_wr_data0, + ddr_wr_bytes0, + ddr_rd_addr0, + ddr_rd_data0, + ddr_rd_bytes0, + + ddr_wr_ack1, + ddr_wr_dv1, + ddr_rd_req1, + ddr_rd_dv1, + ddr_rd_qos1, + ddr_wr_qos1, + ddr_wr_addr1, + ddr_wr_data1, + ddr_wr_bytes1, + ddr_rd_addr1, + ddr_rd_data1, + ddr_rd_bytes1, + + ocm_wr_ack, + ocm_wr_dv, + ocm_rd_req, + ocm_rd_dv, + + ocm_wr_qos, + ocm_rd_qos, + ocm_wr_addr, + ocm_wr_data, + ocm_wr_bytes, + ocm_rd_addr, + ocm_rd_data, + ocm_rd_bytes + + + +); + +input sw_clk; +input rstn; +input [3:0] w_qos_hp0; +input [3:0] r_qos_hp0; +input [3:0] w_qos_hp1; +input [3:0] r_qos_hp1; +input [3:0] w_qos_hp2; +input [3:0] r_qos_hp2; +input [3:0] w_qos_hp3; +input [3:0] r_qos_hp3; + +output [3:0] ddr_rd_qos0; +output [3:0] ddr_wr_qos0; +output [3:0] ddr_rd_qos1; +output [3:0] ddr_wr_qos1; +output [3:0] ocm_wr_qos; +output [3:0] ocm_rd_qos; + +output wr_ack_ddr_hp0; +input [1023:0] wr_data_hp0; +input [31:0] wr_addr_hp0; +input [7:0] wr_bytes_hp0; +output wr_dv_ddr_hp0; + +input rd_req_ddr_hp0; +input [31:0] rd_addr_hp0; +input [7:0] rd_bytes_hp0; +output [1023:0] rd_data_ddr_hp0; +output rd_dv_ddr_hp0; + +output wr_ack_ddr_hp1; +input [1023:0] wr_data_hp1; +input [31:0] wr_addr_hp1; +input [7:0] wr_bytes_hp1; +output wr_dv_ddr_hp1; + +input rd_req_ddr_hp1; +input [31:0] rd_addr_hp1; +input [7:0] rd_bytes_hp1; +output [1023:0] rd_data_ddr_hp1; +output rd_dv_ddr_hp1; + +output wr_ack_ddr_hp2; +input [1023:0] wr_data_hp2; +input [31:0] wr_addr_hp2; +input [7:0] wr_bytes_hp2; +output wr_dv_ddr_hp2; + +input rd_req_ddr_hp2; +input [31:0] rd_addr_hp2; +input [7:0] rd_bytes_hp2; +output [1023:0] rd_data_ddr_hp2; +output rd_dv_ddr_hp2; + +output wr_ack_ddr_hp3; +input [1023:0] wr_data_hp3; +input [31:0] wr_addr_hp3; +input [7:0] wr_bytes_hp3; +output wr_dv_ddr_hp3; + +input rd_req_ddr_hp3; +input [31:0] rd_addr_hp3; +input [7:0] rd_bytes_hp3; +output [1023:0] rd_data_ddr_hp3; +output rd_dv_ddr_hp3; + +input ddr_wr_ack0; +output ddr_wr_dv0; +output [31:0]ddr_wr_addr0; +output [1023:0]ddr_wr_data0; +output [7:0]ddr_wr_bytes0; + +input ddr_rd_dv0; +input [1023:0] ddr_rd_data0; +output ddr_rd_req0; +output [31:0] ddr_rd_addr0; +output [7:0] ddr_rd_bytes0; + +input ddr_wr_ack1; +output ddr_wr_dv1; +output [31:0]ddr_wr_addr1; +output [1023:0]ddr_wr_data1; +output [7:0]ddr_wr_bytes1; + +input ddr_rd_dv1; +input [1023:0] ddr_rd_data1; +output ddr_rd_req1; +output [31:0] ddr_rd_addr1; +output [7:0] ddr_rd_bytes1; + +output wr_ack_ocm_hp0; +input wr_dv_ocm_hp0; +input rd_req_ocm_hp0; +output rd_dv_ocm_hp0; +output [1023:0] rd_data_ocm_hp0; + +output wr_ack_ocm_hp1; +input wr_dv_ocm_hp1; +input rd_req_ocm_hp1; +output rd_dv_ocm_hp1; +output [1023:0] rd_data_ocm_hp1; + +output wr_ack_ocm_hp2; +input wr_dv_ocm_hp2; +input rd_req_ocm_hp2; +output rd_dv_ocm_hp2; +output [1023:0] rd_data_ocm_hp2; + +output wr_ack_ocm_hp3; +input wr_dv_ocm_hp3; +input rd_req_ocm_hp3; +output rd_dv_ocm_hp3; +output [1023:0] rd_data_ocm_hp3; + +input ocm_wr_ack; +output ocm_wr_dv; +output [31:0]ocm_wr_addr; +output [1023:0]ocm_wr_data; +output [7:0]ocm_wr_bytes; + +input ocm_rd_dv; +input [1023:0] ocm_rd_data; +output ocm_rd_req; +output [31:0] ocm_rd_addr; +output [7:0] ocm_rd_bytes; + +/* FOR DDR */ +processing_system7_bfm_v2_0_5_arb_hp0_1 ddr_hp01 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp0(w_qos_hp0), + .r_qos_hp0(r_qos_hp0), + .w_qos_hp1(w_qos_hp1), + .r_qos_hp1(r_qos_hp1), + + .wr_ack_ddr_hp0(wr_ack_ddr_hp0), + .wr_data_hp0(wr_data_hp0), + .wr_addr_hp0(wr_addr_hp0), + .wr_bytes_hp0(wr_bytes_hp0), + .wr_dv_ddr_hp0(wr_dv_ddr_hp0), + .rd_req_ddr_hp0(rd_req_ddr_hp0), + .rd_addr_hp0(rd_addr_hp0), + .rd_bytes_hp0(rd_bytes_hp0), + .rd_data_ddr_hp0(rd_data_ddr_hp0), + .rd_dv_ddr_hp0(rd_dv_ddr_hp0), + + .wr_ack_ddr_hp1(wr_ack_ddr_hp1), + .wr_data_hp1(wr_data_hp1), + .wr_addr_hp1(wr_addr_hp1), + .wr_bytes_hp1(wr_bytes_hp1), + .wr_dv_ddr_hp1(wr_dv_ddr_hp1), + .rd_req_ddr_hp1(rd_req_ddr_hp1), + .rd_addr_hp1(rd_addr_hp1), + .rd_bytes_hp1(rd_bytes_hp1), + .rd_data_ddr_hp1(rd_data_ddr_hp1), + .rd_dv_ddr_hp1(rd_dv_ddr_hp1), + + .ddr_wr_ack(ddr_wr_ack0), + .ddr_wr_dv(ddr_wr_dv0), + .ddr_rd_req(ddr_rd_req0), + .ddr_rd_dv(ddr_rd_dv0), + .ddr_rd_qos(ddr_rd_qos0), + .ddr_wr_qos(ddr_wr_qos0), + .ddr_wr_addr(ddr_wr_addr0), + .ddr_wr_data(ddr_wr_data0), + .ddr_wr_bytes(ddr_wr_bytes0), + .ddr_rd_addr(ddr_rd_addr0), + .ddr_rd_data(ddr_rd_data0), + .ddr_rd_bytes(ddr_rd_bytes0) +); + +/* FOR DDR */ +processing_system7_bfm_v2_0_5_arb_hp2_3 ddr_hp23 ( + .sw_clk(sw_clk), + .rstn(rstn), + .w_qos_hp2(w_qos_hp2), + .r_qos_hp2(r_qos_hp2), + .w_qos_hp3(w_qos_hp3), + .r_qos_hp3(r_qos_hp3), + + .wr_ack_ddr_hp2(wr_ack_ddr_hp2), + .wr_data_hp2(wr_data_hp2), + .wr_addr_hp2(wr_addr_hp2), + .wr_bytes_hp2(wr_bytes_hp2), + .wr_dv_ddr_hp2(wr_dv_ddr_hp2), + .rd_req_ddr_hp2(rd_req_ddr_hp2), + .rd_addr_hp2(rd_addr_hp2), + .rd_bytes_hp2(rd_bytes_hp2), + .rd_data_ddr_hp2(rd_data_ddr_hp2), + .rd_dv_ddr_hp2(rd_dv_ddr_hp2), + + .wr_ack_ddr_hp3(wr_ack_ddr_hp3), + .wr_data_hp3(wr_data_hp3), + .wr_addr_hp3(wr_addr_hp3), + .wr_bytes_hp3(wr_bytes_hp3), + .wr_dv_ddr_hp3(wr_dv_ddr_hp3), + .rd_req_ddr_hp3(rd_req_ddr_hp3), + .rd_addr_hp3(rd_addr_hp3), + .rd_bytes_hp3(rd_bytes_hp3), + .rd_data_ddr_hp3(rd_data_ddr_hp3), + .rd_dv_ddr_hp3(rd_dv_ddr_hp3), + + .ddr_wr_ack(ddr_wr_ack1), + .ddr_wr_dv(ddr_wr_dv1), + .ddr_rd_req(ddr_rd_req1), + .ddr_rd_dv(ddr_rd_dv1), + .ddr_rd_qos(ddr_rd_qos1), + .ddr_wr_qos(ddr_wr_qos1), + + .ddr_wr_addr(ddr_wr_addr1), + .ddr_wr_data(ddr_wr_data1), + .ddr_wr_bytes(ddr_wr_bytes1), + .ddr_rd_addr(ddr_rd_addr1), + .ddr_rd_data(ddr_rd_data1), + .ddr_rd_bytes(ddr_rd_bytes1) +); + + +/* FOR OCM_WR */ +processing_system7_bfm_v2_0_5_arb_wr_4 ocm_wr_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(w_qos_hp0), + .qos2(w_qos_hp1), + .qos3(w_qos_hp2), + .qos4(w_qos_hp3), + + .prt_dv1(wr_dv_ocm_hp0), + .prt_dv2(wr_dv_ocm_hp1), + .prt_dv3(wr_dv_ocm_hp2), + .prt_dv4(wr_dv_ocm_hp3), + + .prt_data1(wr_data_hp0), + .prt_data2(wr_data_hp1), + .prt_data3(wr_data_hp2), + .prt_data4(wr_data_hp3), + + .prt_addr1(wr_addr_hp0), + .prt_addr2(wr_addr_hp1), + .prt_addr3(wr_addr_hp2), + .prt_addr4(wr_addr_hp3), + + .prt_bytes1(wr_bytes_hp0), + .prt_bytes2(wr_bytes_hp1), + .prt_bytes3(wr_bytes_hp2), + .prt_bytes4(wr_bytes_hp3), + + .prt_ack1(wr_ack_ocm_hp0), + .prt_ack2(wr_ack_ocm_hp1), + .prt_ack3(wr_ack_ocm_hp2), + .prt_ack4(wr_ack_ocm_hp3), + + .prt_qos(ocm_wr_qos), + .prt_req(ocm_wr_dv), + .prt_data(ocm_wr_data), + .prt_addr(ocm_wr_addr), + .prt_bytes(ocm_wr_bytes), + .prt_ack(ocm_wr_ack) + +); + +/* FOR OCM_RD */ +processing_system7_bfm_v2_0_5_arb_rd_4 ocm_rd_hp( + .rstn(rstn), + .sw_clk(sw_clk), + + .qos1(r_qos_hp0), + .qos2(r_qos_hp1), + .qos3(r_qos_hp2), + .qos4(r_qos_hp3), + + .prt_req1(rd_req_ocm_hp0), + .prt_req2(rd_req_ocm_hp1), + .prt_req3(rd_req_ocm_hp2), + .prt_req4(rd_req_ocm_hp3), + + .prt_data1(rd_data_ocm_hp0), + .prt_data2(rd_data_ocm_hp1), + .prt_data3(rd_data_ocm_hp2), + .prt_data4(rd_data_ocm_hp3), + + .prt_addr1(rd_addr_hp0), + .prt_addr2(rd_addr_hp1), + .prt_addr3(rd_addr_hp2), + .prt_addr4(rd_addr_hp3), + + .prt_bytes1(rd_bytes_hp0), + .prt_bytes2(rd_bytes_hp1), + .prt_bytes3(rd_bytes_hp2), + .prt_bytes4(rd_bytes_hp3), + + .prt_dv1(rd_dv_ocm_hp0), + .prt_dv2(rd_dv_ocm_hp1), + .prt_dv3(rd_dv_ocm_hp2), + .prt_dv4(rd_dv_ocm_hp3), + + .prt_qos(ocm_rd_qos), + .prt_req(ocm_rd_req), + .prt_data(ocm_rd_data), + .prt_addr(ocm_rd_addr), + .prt_bytes(ocm_rd_bytes), + .prt_dv(ocm_rd_dv) + +); + + +endmodule diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.so b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +
+
+ +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/mem_init_files/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/README.txt new file mode 100644 index 0000000..567342e --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/compile.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/compile.do new file mode 100644 index 0000000..44b9900 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/compile.do @@ -0,0 +1,49 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/axi_infrastructure_v1_1_0 +vlib activehdl/smartconnect_v1_0 +vlib activehdl/axi_protocol_checker_v2_0_1 +vlib activehdl/axi_vip_v1_1_1 +vlib activehdl/processing_system7_vip_v1_0_3 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap axi_infrastructure_v1_1_0 activehdl/axi_infrastructure_v1_1_0 +vmap smartconnect_v1_0 activehdl/smartconnect_v1_0 +vmap axi_protocol_checker_v2_0_1 activehdl/axi_protocol_checker_v2_0_1 +vmap axi_vip_v1_1_1 activehdl/axi_vip_v1_1_1 +vmap processing_system7_vip_v1_0_3 activehdl/processing_system7_vip_v1_0_3 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axi_infrastructure_v1_1_0 -v2k5 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work smartconnect_v1_0 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ + +vlog -work axi_protocol_checker_v2_0_1 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ + +vlog -work axi_vip_v1_1_1 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ + +vlog -work processing_system7_vip_v1_0_3 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ +"../../../bd/system/sim/system.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/file_info.txt new file mode 100644 index 0000000..8bdec35 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/simulate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/simulate.do new file mode 100644 index 0000000..3520eb8 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+system -L xil_defaultlib -L xpm -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.system xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {system.udo} + +run -all + +endsim + +quit -force diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/system.sh new file mode 100644 index 0000000..dfb9108 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/system.sh @@ -0,0 +1,151 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy library.cfg file +copy_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/system.udo b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/system.udo new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/wave.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/README.txt new file mode 100644 index 0000000..fa1b6a6 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/file_info.txt new file mode 100644 index 0000000..f4ea12a --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" 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+processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/run.f b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/run.f new file mode 100644 index 0000000..9e8b203 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/run.f @@ -0,0 +1,31 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/axi_infrastructure_v1_1_0 \ + "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ +-endlib +-makelib ies_lib/smartconnect_v1_0 -sv \ + "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ +-endlib +-makelib ies_lib/axi_protocol_checker_v2_0_1 -sv \ + "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ +-endlib +-makelib ies_lib/axi_vip_v1_1_1 -sv \ + "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ +-endlib +-makelib ies_lib/processing_system7_vip_v1_0_3 -sv \ + "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ + "../../../bd/system/sim/system.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/system.sh new file mode 100644 index 0000000..c999df1 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/ies/system.sh @@ -0,0 +1,183 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm axi_infrastructure_v1_1_0 smartconnect_v1_0 axi_protocol_checker_v2_0_1 axi_vip_v1_1_1 processing_system7_vip_v1_0_3) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -reflib "$ref_lib_dir/xilinx_vip:xilinx_vip" \ + -top xil_defaultlib.system \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" \ + +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" \ + +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" \ + +incdir+"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" \ + +incdir+"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" \ + +incdir+"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" \ + +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/compile.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/compile.do new file mode 100644 index 0000000..8dd6f4c --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/compile.do @@ -0,0 +1,49 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/axi_infrastructure_v1_1_0 +vlib modelsim_lib/msim/smartconnect_v1_0 +vlib modelsim_lib/msim/axi_protocol_checker_v2_0_1 +vlib modelsim_lib/msim/axi_vip_v1_1_1 +vlib modelsim_lib/msim/processing_system7_vip_v1_0_3 + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm +vmap axi_infrastructure_v1_1_0 modelsim_lib/msim/axi_infrastructure_v1_1_0 +vmap smartconnect_v1_0 modelsim_lib/msim/smartconnect_v1_0 +vmap axi_protocol_checker_v2_0_1 modelsim_lib/msim/axi_protocol_checker_v2_0_1 +vmap axi_vip_v1_1_1 modelsim_lib/msim/axi_vip_v1_1_1 +vmap processing_system7_vip_v1_0_3 modelsim_lib/msim/processing_system7_vip_v1_0_3 + +vlog -work xil_defaultlib -64 -incr -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axi_infrastructure_v1_1_0 -64 -incr "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work smartconnect_v1_0 -64 -incr -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ + +vlog -work axi_protocol_checker_v2_0_1 -64 -incr -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ + +vlog -work axi_vip_v1_1_1 -64 -incr -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ + +vlog -work processing_system7_vip_v1_0_3 -64 -incr -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ +"../../../bd/system/sim/system.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/file_info.txt new file mode 100644 index 0000000..8bdec35 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/simulate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/simulate.do new file mode 100644 index 0000000..a2a65ad --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.system xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {system.udo} + +run -all + +quit -force diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/system.sh new file mode 100644 index 0000000..e5565c5 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/system.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/system.udo b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/system.udo new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/wave.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/compile.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/compile.do new file mode 100644 index 0000000..cc6b4b3 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/compile.do @@ -0,0 +1,49 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/axi_infrastructure_v1_1_0 +vlib questa_lib/msim/smartconnect_v1_0 +vlib questa_lib/msim/axi_protocol_checker_v2_0_1 +vlib questa_lib/msim/axi_vip_v1_1_1 +vlib questa_lib/msim/processing_system7_vip_v1_0_3 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap axi_infrastructure_v1_1_0 questa_lib/msim/axi_infrastructure_v1_1_0 +vmap smartconnect_v1_0 questa_lib/msim/smartconnect_v1_0 +vmap axi_protocol_checker_v2_0_1 questa_lib/msim/axi_protocol_checker_v2_0_1 +vmap axi_vip_v1_1_1 questa_lib/msim/axi_vip_v1_1_1 +vmap processing_system7_vip_v1_0_3 questa_lib/msim/processing_system7_vip_v1_0_3 + +vlog -work xil_defaultlib -64 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axi_infrastructure_v1_1_0 -64 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work smartconnect_v1_0 -64 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ + +vlog -work axi_protocol_checker_v2_0_1 -64 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ + +vlog -work axi_vip_v1_1_1 -64 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ + +vlog -work processing_system7_vip_v1_0_3 -64 -sv -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ +"../../../bd/system/sim/system.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/elaborate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/elaborate.do new file mode 100644 index 0000000..326ffde --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.system xil_defaultlib.glbl -o system_opt diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/file_info.txt new file mode 100644 index 0000000..8bdec35 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/simulate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/simulate.do new file mode 100644 index 0000000..1d2fe52 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib system_opt + +do {wave.do} + +view wave +view structure +view signals + +do {system.udo} + +run -all + +quit -force diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/system.sh new file mode 100644 index 0000000..41aca3d --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/system.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/system.udo b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/system.udo new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/wave.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/compile.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/compile.do new file mode 100644 index 0000000..9724ad8 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/compile.do @@ -0,0 +1,49 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/axi_infrastructure_v1_1_0 +vlib riviera/smartconnect_v1_0 +vlib riviera/axi_protocol_checker_v2_0_1 +vlib riviera/axi_vip_v1_1_1 +vlib riviera/processing_system7_vip_v1_0_3 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap axi_infrastructure_v1_1_0 riviera/axi_infrastructure_v1_1_0 +vmap smartconnect_v1_0 riviera/smartconnect_v1_0 +vmap axi_protocol_checker_v2_0_1 riviera/axi_protocol_checker_v2_0_1 +vmap axi_vip_v1_1_1 riviera/axi_vip_v1_1_1 +vmap processing_system7_vip_v1_0_3 riviera/processing_system7_vip_v1_0_3 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work axi_infrastructure_v1_1_0 -v2k5 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + +vlog -work smartconnect_v1_0 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ + +vlog -work axi_protocol_checker_v2_0_1 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ + +vlog -work axi_vip_v1_1_1 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ + +vlog -work processing_system7_vip_v1_0_3 -sv2k12 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" "+incdir+../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" "+incdir+E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ +"../../../bd/system/sim/system.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/file_info.txt new file mode 100644 index 0000000..8bdec35 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/simulate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/simulate.do new file mode 100644 index 0000000..3520eb8 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+system -L xil_defaultlib -L xpm -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.system xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {system.udo} + +run -all + +endsim + +quit -force diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/system.sh new file mode 100644 index 0000000..4589957 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/system.sh @@ -0,0 +1,151 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy library.cfg file +copy_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/system.udo b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/system.udo new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/wave.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/file_info.txt new file mode 100644 index 0000000..f4ea12a --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/file_info.txt @@ -0,0 +1,12 @@ +xpm_fifo.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +sc_util_v1_0_vl_rfs.sv,systemverilog,smartconnect_v1_0,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_protocol_checker_v2_0_vl_rfs.sv,systemverilog,axi_protocol_checker_v2_0_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_1,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_3,../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/simulate.do b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/system.sh new file mode 100644 index 0000000..dde4fbb --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/vcs/system.sh @@ -0,0 +1,251 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'system.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm axi_infrastructure_v1_1_0 smartconnect_v1_0 axi_protocol_checker_v2_0_1 axi_vip_v1_1_1 processing_system7_vip_v1_0_3) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv" \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Xilinx2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work smartconnect_v1_0 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work axi_protocol_checker_v2_0_1 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work axi_vip_v1_1_1 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work processing_system7_vip_v1_0_3 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" +incdir+"$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +incdir+"E:/Xilinx2017/Vivado/2017.4/data/xilinx_vip/include" \ + "$ref_dir/../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ + "$ref_dir/../../../bd/system/sim/system.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.system xil_defaultlib.glbl -o system_simv +} + +# RUN_STEP: +simulate() +{ + ./system_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key system_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc system_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/README.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/README.txt new file mode 100644 index 0000000..5cda077 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2017.4 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sat May 25 13:08:26 +0800 2019 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./system.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './system.sh' script. + +./system.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./system.sh -noclean_files + +For more information on the script, please type './system.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/cmd.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/elab.opt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/elab.opt new file mode 100644 index 0000000..76d3c81 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system xil_defaultlib.system xil_defaultlib.glbl -log elaborate.log diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/file_info.txt b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/file_info.txt new file mode 100644 index 0000000..8631221 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/file_info.txt @@ -0,0 +1,3 @@ +system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="$ref_dir/../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog"incdir="../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/glbl.v b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.dll new file mode 100644 index 0000000..870988e Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.so new file mode 100644 index 0000000..9e8be57 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libps7.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.dll b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.dll new file mode 100644 index 0000000..dd1d912 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.dll differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.so b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.so new file mode 100644 index 0000000..f7ccf59 Binary files /dev/null and b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/libremoteport.so differ diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.html b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.html new file mode 100644 index 0000000..a0eee88 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.html @@ -0,0 +1,137694 @@ + + + + +Zynq PS configuration detail + + + +

    +
    + +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z010 +
    +SpeedGrade + +-1 +
    +Part + +xc7z010clg400-1 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +Quad SPI Flash + +qspi_fbclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +GPIO + +gpio[9] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 10 + +GPIO + +gpio[10] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +GPIO + +gpio[14] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 15 + +GPIO + +gpio[15] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +GPIO + +gpio[28] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +GPIO + +gpio[29] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 30 + +GPIO + +gpio[30] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 31 + +GPIO + +gpio[31] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 32 + +GPIO + +gpio[32] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +GPIO + +gpio[33] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +GPIO + +gpio[34] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +GPIO + +gpio[35] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +GPIO + +gpio[36] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 37 + +GPIO + +gpio[37] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +GPIO + +gpio[38] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +GPIO + +gpio[39] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +GPIO + +gpio[46] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 0 + +cd + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 48 + +UART 1 + +tx + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 49 + +UART 1 + +rx + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 50 + +GPIO + +gpio[50] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +GPIO + +gpio[51] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41K256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.75 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +666.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +50.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a01 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a02 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +4 + +400000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +400500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +0 + +0 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +0 + +0 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +1 + +200000 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1ec044d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1a + +1a + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a0 + +2800 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4281a + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d2 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +12e0 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +12e1 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +2f + +2f0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +2f0037 + +SDIO 0 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0001034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0001018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0001000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0001004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0001034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0001018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0001000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0001004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    USB1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    ENET0 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET1 RESET

    +

    DIR MODE BANK 0

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C RESET

    +

    I2C0 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    I2C1 RESET

    +

    DIR MODE GPIO BANK0

    +

    DIR MODE GPIO BANK1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE

    +

    OUTPUT ENABLE

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.tcl b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.tcl new file mode 100644 index 0000000..e735d59 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init.tcl @@ -0,0 +1,832 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A01 + mask_write 0XF8000154 0x00003F33 0x00000A02 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281A + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000602 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003FFF 0x00001600 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x00001600 + mask_write 0XF800073C 0x00003FFF 0x00001600 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001200 + mask_write 0XF8000774 0x00003FFF 0x00001200 + mask_write 0XF8000778 0x00003FFF 0x00001200 + mask_write 0XF800077C 0x00003FFF 0x00001200 + mask_write 0XF8000780 0x00003FFF 0x00001200 + mask_write 0XF8000784 0x00003FFF 0x00001200 + mask_write 0XF8000788 0x00003FFF 0x00001200 + mask_write 0XF800078C 0x00003FFF 0x00001200 + mask_write 0XF8000790 0x00003FFF 0x00001200 + mask_write 0XF8000794 0x00003FFF 0x00001200 + mask_write 0XF8000798 0x00003FFF 0x00001200 + mask_write 0XF800079C 0x00003FFF 0x00001200 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001200 + mask_write 0XF80007BC 0x00003F01 0x00001201 + mask_write 0XF80007C0 0x00003FFF 0x000012E0 + mask_write 0XF80007C4 0x00003FFF 0x000012E1 + mask_write 0XF80007C8 0x00003FFF 0x00001200 + mask_write 0XF80007CC 0x00003FFF 0x00001200 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x002F0037 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init_gpl.h b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init_gpl.h new file mode 100644 index 0000000..1e0ef54 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/system.sh b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/system.sh new file mode 100644 index 0000000..1b00bfc --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/system.sh @@ -0,0 +1,217 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2017.4 (64-bit) +# +# Filename : system.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sat May 25 13:08:26 +0800 2019 +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# +# usage: system.sh [-help] +# usage: system.sh [-lib_map_path] +# usage: system.sh [-noclean_files] +# usage: system.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xvlog_opts="--relax -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xilinx_vip" + + +# Script info +echo -e "system.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system xil_defaultlib.system xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim system -key {Behavioral:sim_1:Functional:system} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Xilinx2017/Vivado/2017.4/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + ip_file="xsim_ip.ini" + src_file="$lib_map_path/ip/$ip_file" + if [[ -e $src_file ]]; then + cp $src_file $file + else + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb system.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./system.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: system.sh [-help]\n\ +Usage: system.sh [-lib_map_path]\n\ +Usage: system.sh [-reset_run]\n\ +Usage: system.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/vlog.prj b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/vlog.prj new file mode 100644 index 0000000..afca95c --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib --include "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl" --include "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog" --include "../../../../Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl" \ +"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \ +"../../../bd/system/sim/system.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/xsim.ini b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/xsim.ini new file mode 100644 index 0000000..56f31b2 --- /dev/null +++ b/Miz_sys/Miz_sys.ip_user_files/sim_scripts/system/xsim/xsim.ini @@ -0,0 +1,316 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +xbip_bram18k_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_4 +v_vcresampler_v1_0_9=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_9 +tsn_endpoint_ethernet_mac_v1_0_1=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_v1_0_1 +rs_encoder_v9_0_12=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_12 +processing_system7_vip_v1_0_3=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_3 +uhdsdi_gt_v1_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_0 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +mipi_csi2_rx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_7 +v_ccm_v6_0_14=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_14 +v_frmbuf_rd_v2_0_1=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_0_1 +xbip_utils_v3_0_8=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_8 +axis_register_slice_v1_1_15=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_15 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +fc32_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_5 +xfft_v7_2_6=$RDI_DATADIR/xsim/ip/xfft_v7_2_6 +dft_v4_0_14=$RDI_DATADIR/xsim/ip/dft_v4_0_14 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +tcc_decoder_3gppmm_v2_0_15=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_15 +hbm_v1_0_0=$RDI_DATADIR/xsim/ip/hbm_v1_0_0 +v_tpg_v7_0_9=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_9 +xbip_counter_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_4 +axi_hwicap_v3_0_19=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_19 +axi_protocol_checker_v1_1_16=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v1_1_16 +axis_protocol_checker_v1_1_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_1_15 +axi_amm_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_5 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_dwidth_converter_v2_1_15=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_15 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +xlconstant_v1_1_3=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_3 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +cmac_usplus_v2_3_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_3_2 +lte_3gpp_mimo_encoder_v4_0_12=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_12 +floating_point_v7_1_5=$RDI_DATADIR/xsim/ip/floating_point_v7_1_5 +c_mux_bit_v12_0_4=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_4 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_fifo_mm_s_v4_1_12=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_12 +gtwizard_ultrascale_v1_6_8=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_8 +axi_ethernetlite_v3_0_13=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_13 +ibert_lib_v1_0_4=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_4 +axi_register_slice_v2_1_15=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_15 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +system_cache_v4_0_3=$RDI_DATADIR/xsim/ip/system_cache_v4_0_3 +pl4_v13_0_11=$RDI_DATADIR/xsim/ip/pl4_v13_0_11 +microblaze_v10_0_5=$RDI_DATADIR/xsim/ip/microblaze_v10_0_5 +tmr_comparator_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_1 +fir_compiler_v5_2_4=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_4 +compact_gt_v1_0_1=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_1 +axi_epc_v2_0_18=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_18 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +axi_protocol_converter_v2_1_15=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_15 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +lte_ul_channel_decoder_v4_0_13=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_13 +g709_fec_v2_3_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_1 +c_compare_v12_0_4=$RDI_DATADIR/xsim/ip/c_compare_v12_0_4 +axis_broadcaster_v1_1_15=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_15 +lte_dl_channel_encoder_v3_0_13=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_13 +mailbox_v2_1_8=$RDI_DATADIR/xsim/ip/mailbox_v2_1_8 +v_demosaic_v1_0_1=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_1 +axi4stream_vip_v1_0_3=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_0_3 +axi_chip2chip_v5_0_1=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_1 +axi_mm2s_mapper_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_14 +vid_phy_controller_v2_1_1=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_1 +in_system_ibert_v1_0_5=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_5 +spdif_v2_0_18=$RDI_DATADIR/xsim/ip/spdif_v2_0_18 +xbip_accum_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_4 +c_mux_bus_v12_0_4=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_4 +c_counter_binary_v12_0_11=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_11 +axi_datamover_v5_1_17=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_17 +v_csc_v1_0_9=$RDI_DATADIR/xsim/ip/v_csc_v1_0_9 +tmr_sem_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_3 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_gamma_lut_v1_0_1=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_1 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +cic_compiler_v4_0_12=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_12 +gig_ethernet_pcs_pma_v16_1_2=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_2 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +axi_interconnect_v1_7_13=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_13 +xlconcat_v2_1_1=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_1 +tmr_voter_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_1 +g709_rs_decoder_v2_2_5=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_5 +axis_clock_converter_v1_1_16=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_16 +cmac_usplus_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_1 +c_addsub_v12_0_11=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_11 +xfft_v9_0_14=$RDI_DATADIR/xsim/ip/xfft_v9_0_14 +v_tc_v6_1_12=$RDI_DATADIR/xsim/ip/v_tc_v6_1_12 +axi_mcdma_v1_0_1=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_1 +duc_ddc_compiler_v3_0_13=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_13 +axi_perf_mon_v5_0_17=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_17 +rxaui_v4_4_2=$RDI_DATADIR/xsim/ip/rxaui_v4_4_2 +lte_3gpp_channel_estimator_v2_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_14 +xbip_pipe_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_4 +mipi_csi2_tx_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_3 +viterbi_v9_1_8=$RDI_DATADIR/xsim/ip/viterbi_v9_1_8 +convolution_v9_0_12=$RDI_DATADIR/xsim/ip/convolution_v9_0_12 +axi_usb2_device_v5_0_16=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_16 +axi_cdma_v4_1_15=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_15 +zynq_ultra_ps_e_vip_v1_0_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_1 +v_letterbox_v1_0_9=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_9 +v_mix_v2_0_1=$RDI_DATADIR/xsim/ip/v_mix_v2_0_1 +lmb_bram_if_cntlr_v4_0_14=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_14 +dds_compiler_v6_0_15=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_15 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_protocol_checker_v1_2_1=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_2_1 +axi_traffic_gen_v2_0_16=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_16 +ieee802d3_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_11 +axi_gpio_v2_0_17=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_17 +axis_switch_v1_1_15=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_15 +pci64_v5_0_9=$RDI_DATADIR/xsim/ip/pci64_v5_0_9 +v_cfa_v7_0_13=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_13 +v_enhance_v8_0_14=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_14 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +lib_bmg_v1_0_10=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_10 +sem_ultra_v3_1_6=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_6 +blk_mem_gen_v8_4_1=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_1 +ecc_v2_0_12=$RDI_DATADIR/xsim/ip/ecc_v2_0_12 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +axi_timer_v2_0_17=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_17 +axi_ethernet_buffer_v2_0_17=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_17 +pc_cfr_v6_0_6=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_6 +v_axi4s_vid_out_v4_0_8=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_8 +ten_gig_eth_mac_v15_1_4=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_4 +vfb_v1_0_9=$RDI_DATADIR/xsim/ip/vfb_v1_0_9 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +quadsgmii_v3_4_2=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_2 +v_smpte_uhdsdi_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_5 +floating_point_v7_0_14=$RDI_DATADIR/xsim/ip/floating_point_v7_0_14 +xxv_ethernet_v2_3_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_3_1 +xbip_dsp48_multacc_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_4 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +axi_ahblite_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_13 +axis_dwidth_converter_v1_1_14=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_14 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +lte_3gpp_mimo_decoder_v3_0_13=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_13 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +axi_mmu_v2_1_13=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_13 +axi_pcie_v2_8_7=$RDI_DATADIR/xsim/ip/axi_pcie_v2_8_7 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +prc_v1_2_1=$RDI_DATADIR/xsim/ip/prc_v1_2_1 +axi_uartlite_v2_0_19=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_19 +tcc_encoder_3gpplte_v4_0_13=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_13 +axi_timebase_wdt_v3_0_7=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_7 +can_v5_0_18=$RDI_DATADIR/xsim/ip/can_v5_0_18 +v_vid_in_axi4s_v4_0_7=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_7 +axi_vfifo_ctrl_v2_0_17=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_17 +div_gen_v5_1_12=$RDI_DATADIR/xsim/ip/div_gen_v5_1_12 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +tmr_inject_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_1 +fir_compiler_v7_2_10=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_10 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axis_combiner_v1_1_14=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_14 +xbip_dsp48_addsub_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_4 +lte_pucch_receiver_v2_0_13=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_13 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_rgb2ycrcb_v7_1_12=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_12 +v_gamma_v7_0_14=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_14 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fit_timer_v2_0_8=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_8 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +mutex_v2_1_8=$RDI_DATADIR/xsim/ip/mutex_v2_1_8 +ieee802d3_200g_rs_fec_v1_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_1 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +xil_common_vip_v1_0_0=$RDI_DATADIR/xsim/ip/xil_common_vip_v1_0_0 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +amm_axi_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_1 +displayport_v7_0_7=$RDI_DATADIR/xsim/ip/displayport_v7_0_7 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +gmii_to_rgmii_v4_0_5=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_5 +dist_mem_gen_v8_0_12=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_12 +xbip_dsp48_multadd_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_4 +rs_decoder_v9_0_13=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_13 +xdma_v4_0_1=$RDI_DATADIR/xsim/ip/xdma_v4_0_1 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +axi_traffic_gen_v3_0_1=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_1 +canfd_v1_0_8=$RDI_DATADIR/xsim/ip/canfd_v1_0_8 +l_ethernet_v2_3_1=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_1 +tri_mode_ethernet_mac_v9_0_10=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_10 +v_ycrcb2rgb_v7_1_12=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_12 +rst_vip_v1_0_0=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_0 +video_frame_crc_v1_0_0=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_0 +lte_rach_detector_v3_1_1=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_1 +axi_pcie3_v3_0_5=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_5 +cpri_v8_8_1=$RDI_DATADIR/xsim/ip/cpri_v8_8_1 +axi_msg_v1_0_1=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_1 +mult_gen_v12_0_13=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_13 +v_hscaler_v1_0_9=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_9 +axi_vip_v1_1_1=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_1 +flexo_100g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_5 +axi_tft_v2_0_19=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_19 +v_cresample_v4_0_13=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_13 +pr_decoupler_v1_0_5=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_5 +pci32_v5_0_9=$RDI_DATADIR/xsim/ip/pci32_v5_0_9 +mipi_dsi_tx_ctrl_v1_0_5=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_5 +jesd204c_v2_0_1=$RDI_DATADIR/xsim/ip/jesd204c_v2_0_1 +hdcp22_cipher_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_2 +c_shift_ram_v12_0_11=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_11 +v_vscaler_v1_0_9=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_9 +fifo_generator_v13_2_1=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_1 +g975_efec_i7_v2_0_16=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_16 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +lib_fifo_v1_0_10=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_10 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +xlslice_v1_0_1=$RDI_DATADIR/xsim/ip/xlslice_v1_0_1 +fec_5g_common_v1_0_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_0 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +axi_quad_spi_v3_2_14=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_14 +xbip_dsp48_mult_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_4 +ahblite_axi_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_13 +ten_gig_eth_pcs_pma_v6_0_11=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_11 +axis_data_fifo_v1_1_16=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_16 +iomodule_v3_1_3=$RDI_DATADIR/xsim/ip/iomodule_v3_1_3 +interlaken_v2_3_1=$RDI_DATADIR/xsim/ip/interlaken_v2_3_1 +tmr_manager_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_2 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +axi_utils_v2_0_4=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_4 +v_osd_v6_0_15=$RDI_DATADIR/xsim/ip/v_osd_v6_0_15 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi_protocol_checker_v2_0_1=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_1 +axis_accelerator_adapter_v2_1_12=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_12 +tcc_encoder_3gpp_v5_0_12=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_12 +g975_efec_i4_v1_0_14=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_14 +xbip_dsp48_acc_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_4 +ldpc_v1_0_1=$RDI_DATADIR/xsim/ip/ldpc_v1_0_1 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +axi4svideo_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_8 +ieee802d3_25g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_7 +c_accum_v12_0_11=$RDI_DATADIR/xsim/ip/c_accum_v12_0_11 +c_gate_bit_v12_0_4=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_4 +ieee802d3_400g_rs_fec_v1_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_1 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +axi_vdma_v6_3_3=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_3 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +axi_firewall_v1_0_3=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_3 +axi_uart16550_v2_0_17=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_17 +cordic_v6_0_13=$RDI_DATADIR/xsim/ip/cordic_v6_0_13 +axi_emc_v3_0_15=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_15 +axi_dma_v7_1_16=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_16 +xbip_dsp48_macro_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_15 +axis_interconnect_v1_1_14=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_14 +mdm_v3_2_12=$RDI_DATADIR/xsim/ip/mdm_v3_2_12 +ieee802d3_50g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_7 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +xbip_addsub_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_4 +sem_v4_1_10=$RDI_DATADIR/xsim/ip/sem_v4_1_10 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +v_hcresampler_v1_0_9=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_9 +cmpy_v6_0_14=$RDI_DATADIR/xsim/ip/cmpy_v6_0_14 +axi_data_fifo_v2_1_14=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_14 +ethernet_1_10_25g_v1_0_1=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v1_0_1 +mipi_dphy_v4_0_1=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_0_1 +switch_core_top_v1_0_4=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_4 +sid_v8_0_11=$RDI_DATADIR/xsim/ip/sid_v8_0_11 +util_reduced_logic_v2_0_3=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_3 +axis_subset_converter_v1_1_15=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_15 +axi_bram_ctrl_v4_0_13=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_13 +v_frmbuf_wr_v2_0_1=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_0_1 +lte_fft_v2_0_15=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_15 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +clk_vip_v1_0_0=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_0 +axi_sg_v4_1_8=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_8 +gtwizard_ultrascale_v1_7_2=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_2 +axi_vip_v1_0_4=$RDI_DATADIR/xsim/ip/axi_vip_v1_0_4 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +xpm=$RDI_DATADIR/xsim/ip/xpm +mii_to_rmii_v2_0_17=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_17 +cmac_v2_3_1=$RDI_DATADIR/xsim/ip/cmac_v2_3_1 +axi_intc_v4_1_10=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_10 +pc_cfr_v6_1_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_2 +proc_sys_reset_v5_0_12=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_12 +xbip_multadd_v3_0_11=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_11 +xaui_v12_3_2=$RDI_DATADIR/xsim/ip/xaui_v12_3_2 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +jesd204_v7_2_1=$RDI_DATADIR/xsim/ip/jesd204_v7_2_1 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +axi_iic_v2_0_18=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_18 +c_reg_fd_v12_0_4=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_4 +v_dual_splitter_v1_0_8=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_8 +axi_apb_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_13 +axi_crossbar_v2_1_16=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_16 +v_deinterlacer_v5_0_9=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_9 +tsn_temac_v1_0_2=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_2 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xhmc_v1_0_5=$RDI_DATADIR/xsim/ip/xhmc_v1_0_5 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +g709_rs_encoder_v2_2_4=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_4 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +usxgmii_v1_0_1=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_1 +rs_toolbox_v9_0_4=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_4 +srio_gen2_v4_1_2=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_2 +axi_clock_converter_v2_1_14=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_14 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +axi4stream_vip_v1_1_1=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_1 diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_1.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..c57c3e7 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_10.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..9a45bd5 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_11.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..493674c --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_12.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..a40cae5 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_13.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..d6ce69b --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_14.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..7c4b701 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_15.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..d5069f5 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_2.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..a7f0871 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_3.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..6d06249 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_4.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..2eb72f1 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_5.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..7f47080 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_6.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..7f47080 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_7.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..53a9328 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_8.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..427bb5b --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/.jobs/vrs_config_9.xml b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..01379b2 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.Vivado_Implementation.queue.rst b/Miz_sys/Miz_sys.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.init_design.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..3714b4e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.init_design.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.opt_design.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..3714b4e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.opt_design.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.place_design.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..3714b4e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.place_design.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.route_design.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..3714b4e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.route_design.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.vivado.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..66b75a3 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.vivado.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/.write_bitstream.begin.rst b/Miz_sys/Miz_sys.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..3714b4e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/.write_bitstream.end.rst b/Miz_sys/Miz_sys.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.js b/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.sh b/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Miz_sys/Miz_sys.runs/impl_1/gen_run.xml b/Miz_sys/Miz_sys.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..2ac7ff7 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/gen_run.xml @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/htr.txt b/Miz_sys/Miz_sys.runs/impl_1/htr.txt new file mode 100644 index 0000000..15c74cf --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace diff --git a/Miz_sys/Miz_sys.runs/impl_1/init_design.pb b/Miz_sys/Miz_sys.runs/impl_1/init_design.pb new file mode 100644 index 0000000..b9e5377 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/init_design.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/opt_design.pb b/Miz_sys/Miz_sys.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..2239987 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/opt_design.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/place_design.pb b/Miz_sys/Miz_sys.runs/impl_1/place_design.pb new file mode 100644 index 0000000..3f8a89e Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/place_design.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/project.wdf b/Miz_sys/Miz_sys.runs/impl_1/project.wdf new file mode 100644 index 0000000..8e615fe --- /dev/null +++ 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:35:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3537643330326165323166613433343638643837326462393761373737303431:506172656e742050412070726f6a656374204944:00 +eof:1040580474 diff --git a/Miz_sys/Miz_sys.runs/impl_1/route_design.pb b/Miz_sys/Miz_sys.runs/impl_1/route_design.pb new file mode 100644 index 0000000..d319369 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/route_design.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/rundef.js b/Miz_sys/Miz_sys.runs/impl_1/rundef.js new file mode 100644 index 0000000..a56692f --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64;E:/Xilinx2017/Vivado/2017.4/bin;"; +} else { + PathVal = "E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64;E:/Xilinx2017/Vivado/2017.4/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Miz_sys/Miz_sys.runs/impl_1/runme.bat b/Miz_sys/Miz_sys.runs/impl_1/runme.bat new file mode 100644 index 0000000..622b935 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Miz_sys/Miz_sys.runs/impl_1/runme.sh b/Miz_sys/Miz_sys.runs/impl_1/runme.sh new file mode 100644 index 0000000..6be89e2 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64:E:/Xilinx2017/Vivado/2017.4/bin +else + PATH=E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64:E:/Xilinx2017/Vivado/2017.4/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.bit b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.bit new file mode 100644 index 0000000..ca34eda Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.bit differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.hwdef b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.hwdef new file mode 100644 index 0000000..1eeeb32 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.hwdef differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.sysdef b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.sysdef new file mode 100644 index 0000000..d0aa0ab Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.sysdef differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.tcl b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.tcl new file mode 100644 index 0000000..ae6f533 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.tcl @@ -0,0 +1,175 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param simulator.modelsimInstallPath D:/modeltech64_10.6d/win64 + create_project -in_memory -part xc7z010clg400-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/wt [current_project] + set_property parent.project_path L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.xpr [current_project] + set_property ip_cache_permissions disable [current_project] + set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] + add_files -quiet L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.dcp + set_msg_config -source 4 -id {BD 41-1661} -limit 0 + set_param project.isImplRun true + add_files L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bd + set_param project.isImplRun false + set_param project.isImplRun true + link_design -top system_wrapper -part xc7z010clg400-1 + set_param project.isImplRun false + write_hwdef -force -file system_wrapper.hwdef + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force system_wrapper_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + implement_debug_core + place_design + write_checkpoint -force system_wrapper_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file system_wrapper_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force system_wrapper_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force system_wrapper_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] + catch { write_mem_info -force system_wrapper.mmi } + write_bitstream -force system_wrapper.bit + catch { write_sysdef -hwdef system_wrapper.hwdef -bitfile system_wrapper.bit -meminfo system_wrapper.mmi -file system_wrapper.sysdef } + catch {write_debug_probes -quiet -force system_wrapper} + catch {file copy -force system_wrapper.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.vdi b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.vdi new file mode 100644 index 0000000..9f4bc6d --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.vdi @@ -0,0 +1,365 @@ +#----------------------------------------------------------- +# Vivado v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Sat May 25 13:10:12 2019 +# Process ID: 15400 +# Current directory: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1 +# Command line: vivado.exe -log system_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace +# Log file: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper.vdi +# Journal file: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source system_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx2017/Vivado/2017.4/data/ip'. +Command: link_design -top system_wrapper -part xc7z010clg400-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-479] Netlist was created with Vivado 2017.4 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' +Finished Parsing XDC File [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 612.285 ; gain = 333.426 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.800 . Memory (MB): peak = 618.539 ; gain = 6.254 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: f6ab8773 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: f6ab8773 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 126f153ce + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.250 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 88 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 126f153ce + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.286 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 126f153ce + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.295 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1090.422 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: cbc93f3c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.365 . Memory (MB): peak = 1090.422 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 15fe2561f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1090.422 ; gain = 478.137 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.113 . Memory (MB): peak = 1090.422 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx +Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1092.766 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ecb84c30 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1092.766 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1098.730 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e6471117 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1100.789 ; gain = 8.023 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 10c654c2f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1109.441 ; gain = 16.676 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 10c654c2f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1109.441 ; gain = 16.676 +Phase 1 Placer Initialization | Checksum: 10c654c2f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1109.441 ; gain = 16.676 + +Phase 2 Final Placement Cleanup +Phase 2 Final Placement Cleanup | Checksum: 10c654c2f + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1109.441 ; gain = 16.676 +INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed +Ending Placer Task | Checksum: e6471117 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1109.441 ; gain = 16.676 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.114 . Memory (MB): peak = 1109.441 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt +report_io: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.101 . Memory (MB): peak = 1109.441 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1109.441 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1109.441 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 91e52a67 ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 15cca9cb4 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1176.340 ; gain = 66.898 +Post Restoration Checksum: NetGraph: ce5072d0 NumContArr: 8e7a29e4 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 2.1 Create Timer | Checksum: 15cca9cb4 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1189.809 ; gain = 80.367 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 15cca9cb4 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1196.609 ; gain = 87.168 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 15cca9cb4 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1196.609 ; gain = 87.168 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 186b8954d + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 +Phase 2 Router Initialization | Checksum: 186b8954d + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 +Phase 4 Rip-up And Reroute | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 +Phase 5 Delay and Skew Optimization | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 +Phase 6.1 Hold Fix Iter | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 +Phase 6 Post Hold Fix | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1199.363 ; gain = 89.922 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1201.441 ; gain = 92.000 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1201.441 ; gain = 92.000 + +Phase 10 Post Router Timing +Phase 10 Post Router Timing | Checksum: 1b6bfd3d2 + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1201.441 ; gain = 92.000 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1201.441 ; gain = 92.000 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1201.441 ; gain = 92.000 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.105 . Memory (MB): peak = 1201.441 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx +Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx +Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx +Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +64 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt +Command: write_bitstream -force system_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./system_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +80 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:31 . Memory (MB): peak = 1626.887 ; gain = 414.551 +INFO: [Common 17-206] Exiting Vivado at Sat May 25 13:11:57 2019... diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_clock_utilization_routed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_clock_utilization_routed.rpt new file mode 100644 index 0000000..d3be387 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_clock_utilization_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:26 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt +| Design : system_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +-------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 48 | 0 | 0 | 0 | +| BUFIO | 0 | 8 | 0 | 0 | 0 | +| BUFMR | 0 | 4 | 0 | 0 | 0 | +| BUFR | 0 | 8 | 0 | 0 | 0 | +| MMCM | 0 | 2 | 0 | 0 | 0 | +| PLL | 0 | 2 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------+----------------------------------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------+----------------------------------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y15 | n/a | 1 | 1 | 0 | 20.000 | clk_fpga_0 | system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | system_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------+----------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-----------------------------------------------------+-----------------------------------------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-----------------------------------------------------+-----------------------------------------------------------+ +| src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y1 | 1 | 0 | 20.000 | clk_fpga_0 | system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-----------------------------------------------------+-----------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------------+ +| g0 | BUFG/O | n/a | clk_fpga_0 | 20.000 | {0.000 10.000} | 1 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y15 [get_cells system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports + +# Clock net "system_i/processing_system7_0/inst/FCLK_CLK0" driven by instance "system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y15" +#startgroup +create_pblock {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0} +add_cells_to_pblock [get_pblocks {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/processing_system7_0/inst/FCLK_CLK0"}]]] +resize_pblock [get_pblocks {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_control_sets_placed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_control_sets_placed.rpt new file mode 100644 index 0000000..dfe28c7 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_control_sets_placed.rpt @@ -0,0 +1,57 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:04 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt +| Design : system_wrapper +| Device : xc7z010 +------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + ++--------+-----------------------+ +| Fanout | Number of ControlSets | ++--------+-----------------------+ + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.pb new file mode 100644 index 0000000..8ebaa78 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpt new file mode 100644 index 0000000..bc8e3c2 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:10:59 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx +| Design : system_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpx b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpx new file mode 100644 index 0000000..28267dd Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_opted.rpx differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.pb new file mode 100644 index 0000000..8ebaa78 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpt new file mode 100644 index 0000000..6752512 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:25 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx +| Design : system_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpx b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpx new file mode 100644 index 0000000..94fc85f Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_drc_routed.rpx differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_io_placed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_io_placed.rpt new file mode 100644 index 0000000..0c02e00 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_io_placed.rpt @@ -0,0 +1,442 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:04 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_io -file system_wrapper_io_placed.rpt +| Design : system_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg400 +| Package Version : FINAL 2012-10-23 +| Package Pin Delay Version : VERS. 2.0 2012-10-23 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 130 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | DDR_dm[0] | | PS_DDR_DM0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A2 | DDR_dq[2] | | PS_DDR_DQ2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| A4 | DDR_dq[3] | | PS_DDR_DQ3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A5 | FIXED_IO_mio[6] | | PS_MIO6_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A6 | FIXED_IO_mio[5] | | PS_MIO5_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A7 | FIXED_IO_mio[1] | | PS_MIO1_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A9 | FIXED_IO_mio[43] | | PS_MIO43_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A10 | FIXED_IO_mio[37] | | PS_MIO37_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A11 | FIXED_IO_mio[36] | | PS_MIO36_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A12 | FIXED_IO_mio[34] | | PS_MIO34_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| A14 | FIXED_IO_mio[32] | | PS_MIO32_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A15 | FIXED_IO_mio[26] | | PS_MIO26_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A16 | FIXED_IO_mio[24] | | PS_MIO24_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A17 | FIXED_IO_mio[20] | | PS_MIO20_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A19 | FIXED_IO_mio[16] | | PS_MIO16_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| B3 | DDR_dq[1] | | PS_DDR_DQ1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| B4 | DDR_reset_n | | PS_DDR_DRST_B_502 | INOUT | SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | +| B7 | FIXED_IO_mio[4] | | PS_MIO4_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B8 | FIXED_IO_mio[2] | | PS_MIO2_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B9 | FIXED_IO_mio[51] | | PS_MIO51_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B10 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS18 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B12 | FIXED_IO_mio[48] | | PS_MIO48_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B13 | FIXED_IO_mio[50] | | PS_MIO50_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B14 | FIXED_IO_mio[47] | | PS_MIO47_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B15 | FIXED_IO_mio[45] | | PS_MIO45_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| B17 | FIXED_IO_mio[22] | | PS_MIO22_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B18 | FIXED_IO_mio[18] | | PS_MIO18_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C1 | DDR_dq[6] | | PS_DDR_DQ6_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C3 | DDR_dq[0] | | PS_DDR_DQ0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | FIXED_IO_mio[14] | | PS_MIO14_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C6 | FIXED_IO_mio[11] | | PS_MIO11_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C7 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C8 | FIXED_IO_mio[15] | | PS_MIO15_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C10 | FIXED_IO_mio[52] | | PS_MIO52_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C11 | FIXED_IO_mio[53] | | PS_MIO53_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C12 | FIXED_IO_mio[49] | | PS_MIO49_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C13 | FIXED_IO_mio[29] | | PS_MIO29_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C15 | FIXED_IO_mio[30] | | PS_MIO30_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C16 | FIXED_IO_mio[28] | | PS_MIO28_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C17 | FIXED_IO_mio[41] | | PS_MIO41_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C18 | FIXED_IO_mio[39] | | PS_MIO39_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | | +| D1 | DDR_dq[5] | | PS_DDR_DQ5_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| D3 | DDR_dq[4] | | PS_DDR_DQ4_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| D4 | DDR_addr[13] | | PS_DDR_A13_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | FIXED_IO_mio[8] | | PS_MIO8_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D6 | FIXED_IO_mio[3] | | PS_MIO3_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | +| D8 | FIXED_IO_mio[7] | | PS_MIO7_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D9 | FIXED_IO_mio[12] | | PS_MIO12_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D10 | FIXED_IO_mio[19] | | PS_MIO19_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D11 | FIXED_IO_mio[23] | | PS_MIO23_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| D13 | FIXED_IO_mio[27] | | PS_MIO27_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D14 | FIXED_IO_mio[40] | | PS_MIO40_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D15 | FIXED_IO_mio[33] | | PS_MIO33_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D16 | FIXED_IO_mio[46] | | PS_MIO46_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E1 | DDR_dq[7] | | PS_DDR_DQ7_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E2 | DDR_dq[8] | | PS_DDR_DQ8_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E3 | DDR_dq[9] | | PS_DDR_DQ9_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E4 | DDR_addr[12] | | PS_DDR_A12_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| E6 | FIXED_IO_mio[0] | | PS_MIO0_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E8 | FIXED_IO_mio[13] | | PS_MIO13_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E9 | FIXED_IO_mio[10] | | PS_MIO10_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | | +| E12 | FIXED_IO_mio[42] | | PS_MIO42_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E13 | FIXED_IO_mio[38] | | PS_MIO38_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E14 | FIXED_IO_mio[17] | | PS_MIO17_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| E16 | FIXED_IO_mio[31] | | PS_MIO31_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F1 | DDR_dm[1] | | PS_DDR_DM1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | DDR_addr[14] | | PS_DDR_A14_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | DDR_addr[10] | | PS_DDR_A10_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | | +| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| F12 | FIXED_IO_mio[35] | | PS_MIO35_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F13 | FIXED_IO_mio[44] | | PS_MIO44_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F14 | FIXED_IO_mio[21] | | PS_MIO21_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F15 | FIXED_IO_mio[25] | | PS_MIO25_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| G3 | DDR_dq[10] | | PS_DDR_DQ10_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| G4 | DDR_addr[11] | | PS_DDR_A11_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | | +| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| G15 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H2 | DDR_dq[13] | | PS_DDR_DQ13_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H3 | DDR_dq[11] | | PS_DDR_DQ11_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| H5 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| H15 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J1 | DDR_dq[15] | | PS_DDR_DQ15_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | DDR_dq[12] | | PS_DDR_DQ12_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| J4 | DDR_addr[9] | | PS_DDR_A9_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | DDR_ba[2] | | PS_DDR_BA2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J15 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K1 | DDR_addr[8] | | PS_DDR_A8_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K2 | DDR_addr[1] | | PS_DDR_A1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | DDR_addr[3] | | PS_DDR_A3_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K4 | DDR_addr[7] | | PS_DDR_A7_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| L1 | DDR_addr[5] | | PS_DDR_A5_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | DDR_ck_p | | PS_DDR_CKP_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| L4 | DDR_addr[6] | | PS_DDR_A6_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L5 | DDR_ba[0] | | PS_DDR_BA0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M2 | DDR_ck_n | | PS_DDR_CKN_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M3 | DDR_addr[2] | | PS_DDR_A2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M4 | DDR_addr[4] | | PS_DDR_A4_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | DDR_we_n | | PS_DDR_WE_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N1 | DDR_cs_n | | PS_DDR_CS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | DDR_addr[0] | | PS_DDR_A0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | DDR_cke | | PS_DDR_CKE_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N5 | DDR_odt | | PS_DDR_ODT_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | | +| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P1 | DDR_dq[16] | | PS_DDR_DQ16_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| P3 | DDR_dq[17] | | PS_DDR_DQ17_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| P4 | DDR_ras_n | | PS_DDR_RAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | DDR_cas_n | | PS_DDR_CAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R1 | DDR_dq[19] | | PS_DDR_DQ19_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| R2 | DDR_dqs_p[2] | | PS_DDR_DQS_P2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| R3 | DDR_dq[18] | | PS_DDR_DQ18_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| R4 | DDR_ba[1] | | PS_DDR_BA1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | | +| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T1 | DDR_dm[2] | | PS_DDR_DM2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| T2 | DDR_dqs_n[2] | | PS_DDR_DQS_N2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T4 | DDR_dq[20] | | PS_DDR_DQ20_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| T5 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| T9 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| T17 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| U2 | DDR_dq[22] | | PS_DDR_DQ22_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| U3 | DDR_dq[23] | | PS_DDR_DQ23_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| U4 | DDR_dq[21] | | PS_DDR_DQ21_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| U5 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| U8 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| U9 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| U10 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U17 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V1 | DDR_dq[24] | | PS_DDR_DQ24_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| V2 | DDR_dq[30] | | PS_DDR_DQ30_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| V3 | DDR_dq[31] | | PS_DDR_DQ31_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| V5 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V6 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V7 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V8 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V10 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V11 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| V12 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| W1 | DDR_dq[26] | | PS_DDR_DQ26_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W3 | DDR_dq[29] | | PS_DDR_DQ29_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| W4 | DDR_dqs_n[3] | | PS_DDR_DQS_N3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| W5 | DDR_dqs_p[3] | | PS_DDR_DQS_P3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| W6 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W8 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| W9 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| W10 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| W11 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y1 | DDR_dm[3] | | PS_DDR_DM3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| Y2 | DDR_dq[28] | | PS_DDR_DQ28_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| Y3 | DDR_dq[25] | | PS_DDR_DQ25_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| Y4 | DDR_dq[27] | | PS_DDR_DQ27_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y7 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y8 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y9 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y12 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpt new file mode 100644 index 0000000..96f8bb1 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:26 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx +| Design : system_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpx b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpx new file mode 100644 index 0000000..c173ac2 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_methodology_drc_routed.rpx differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_opt.dcp b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_opt.dcp new file mode 100644 index 0000000..63cc877 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_opt.dcp differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_placed.dcp b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_placed.dcp new file mode 100644 index 0000000..ca43cb8 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_placed.dcp differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpt new file mode 100644 index 0000000..570ba2b --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpt @@ -0,0 +1,153 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:26 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx +| Design : system_wrapper +| Device : xc7z010clg400-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 1.649 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 1.529 | +| Device Static (W) | 0.120 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 66.0 | +| Junction Temperature (C) | 44.0 | +| Confidence Level | High | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++--------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++--------------+-----------+----------+-----------+-----------------+ +| Clocks | <0.001 | 3 | --- | --- | +| Slice Logic | 0.000 | 134 | --- | --- | +| Others | 0.000 | 134 | --- | --- | +| Signals | 0.000 | 0 | --- | --- | +| PS7 | 1.529 | 1 | --- | --- | +| Static Power | 0.120 | | | | +| Total | 1.649 | | | | ++--------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.007 | 0.000 | 0.007 | +| Vccaux | 1.800 | 0.008 | 0.000 | 0.008 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccpint | 1.000 | 0.747 | 0.717 | 0.030 | +| Vccpaux | 1.800 | 0.061 | 0.051 | 0.010 | +| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | +| Vcco_ddr | 1.500 | 0.459 | 0.457 | 0.002 | +| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | +| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+------------------------------------------------+--------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+------------------------------------------------+--------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | High | User specified more than 95% of inputs | | +| Internal nodes activity | High | User specified more than 25% of internal nodes | | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | High | | | ++-----------------------------+------------+------------------------------------------------+--------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++------------+-----------------------------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------+-----------------------------------------------------------+-----------------+ +| clk_fpga_0 | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 20.0 | ++------------+-----------------------------------------------------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++--------------------------+-----------+ +| Name | Power (W) | ++--------------------------+-----------+ +| system_wrapper | 1.529 | +| system_i | 1.529 | +| processing_system7_0 | 1.529 | +| inst | 1.529 | ++--------------------------+-----------+ + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpx b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpx new file mode 100644 index 0000000..6c3f3a9 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_routed.rpx differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_summary_routed.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_summary_routed.pb new file mode 100644 index 0000000..fc2769a Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_power_summary_routed.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.pb new file mode 100644 index 0000000..36c789f Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.rpt new file mode 100644 index 0000000..b34932c --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 264 : + # of nets not needing routing.......... : 130 : + # of internally routed nets........ : 130 : + # of routable nets..................... : 134 : + # of fully routed nets............. : 134 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_routed.dcp b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_routed.dcp new file mode 100644 index 0000000..515b303 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_routed.dcp differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpt new file mode 100644 index 0000000..3c4bd93 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpt @@ -0,0 +1,200 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:26 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation +| Design : system_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA 17.845 0.000 0 1 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk_fpga_0 {0.000 10.000} 20.000 50.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk_fpga_0 17.845 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_fpga_0 + To Clock: clk_fpga_0 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_fpga_0 +Waveform(ns): { 0.000 10.000 } +Period(ns): 20.000 +Sources: { system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y15 system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/I + + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpx b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpx new file mode 100644 index 0000000..da1f328 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_timing_summary_routed.rpx differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.pb b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.pb new file mode 100644 index 0000000..8d169b2 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.rpt b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.rpt new file mode 100644 index 0000000..7ad0e9e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/system_wrapper_utilization_placed.rpt @@ -0,0 +1,189 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:11:04 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb +| Design : system_wrapper +| Device : 7z010clg400-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 0 | 0 | 17600 | 0.00 | +| LUT as Logic | 0 | 0 | 17600 | 0.00 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 0 | 0 | 35200 | 0.00 | +| Register as Flip Flop | 0 | 0 | 35200 | 0.00 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 0 | 0 | 4400 | 0.00 | +| SLICEL | 0 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 0 | 0 | 17600 | 0.00 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 17600 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+--------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+--------+ +| Bonded IOB | 0 | 0 | 100 | 0.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 130 | 130 | 130 | 100.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+--------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+----------------------+ +| Ref Name | Used | Functional Category | ++----------+------+----------------------+ +| BIBUF | 130 | IO | +| PS7 | 1 | Specialized Resource | +| BUFG | 1 | Clock | ++----------+------+----------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.html b/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..f7e080f --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,1051 @@ +Device Usage Statistics Report +

    Device Usage Page (usage_statistics_webtalk.html)

    This HTML page displays the device usage statistics that will be sent to Xilinx.
    To see the actual file transmitted to Xilinx, please click here.

    + + + + + + + + + + + + + + + + + +
    software_version_and_target_device
    betaFALSEbuild_version2086221
    date_generatedSat May 25 13:11:41 2019os_platformWIN64
    product_versionVivado v2017.4 (64-bit)project_id57d302ae21fa43468d872db97a777041
    project_iteration8random_id11c70b66107c5fcf97945a358bbb3bfb
    registration_id11c70b66107c5fcf97945a358bbb3bfbroute_designTRUE
    target_devicexc7z010target_familyzynq
    target_packageclg400target_speed-1
    tool_flowVivado

    + + + + + + + + +
    user_environment
    cpu_nameIntel(R) Core(TM) i7-6700K CPU @ 4.00GHzcpu_speed4008 MHz
    os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
    system_ram25.000 GBtotal_processors1

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    vivado_usage
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    gui_handlers
    basedialog_cancel=4basedialog_no=1basedialog_ok=35basedialog_yes=5
    clkconfigtreetablepanel_clk_config_tree_table=6filesetpanel_file_set_panel_tree=45flownavigatortreepanel_flow_navigator_tree=1gettingstartedview_open_project=1
    gictreetablepanel_gic_tree_table=1ipstatussectionpanel_upgrade_selected=2mainmenumgr_export=28mainmenumgr_file=56
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    mioconfigtreetablepanel_mio_config_tree_table=12miotablepagepanel_mio_table=2newexporthardwaredialog_include_bitstream=6pacommandnames_create_top_hdl=1
    pacommandnames_export_hardware=8pacommandnames_generate_composite_file=3pacommandnames_launch_hardware=14pacommandnames_new_project=1
    pacommandnames_open_project=4pacommandnames_report_ip_status=1pacommandnames_reset_composite_file=2pacommandnames_run_bitgen=8
    pacommandnames_save_rsb_design=2partchooser_family_chooser=1partchooser_part_package_chooser=1partchooser_part_speed_chooser=1
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    reportipstatusinfodialog_report_ip_status=1settingsprojectgeneralpage_choose_device_for_your_project=1simpleoutputproductdialog_generate_output_products_immediately=5simpleoutputproductdialog_reset_output_products=2
    simpleoutputproductdialog_synthesize_design_globally=1touchpointsurveydialog_remind_me_later=1
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    java_command_handlers
    autoconnecttarget=1closetarget=1createtophdl=1customizersbblock=6
    editdelete=6managecompositetargets=6newexporthardware=12newlaunchhardware=19
    newproject=1openhardwaremanager=1openproject=5reportipstatus=3
    runbitgen=9saversbdesign=2toolssettings=1upgradeip=3
    + + + +
    other_data
    guimode=22
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    project_data
    constraintsetcount=0core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
    default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=5export_simulation_ies=5
    export_simulation_modelsim=5export_simulation_questa=5export_simulation_riviera=5export_simulation_vcs=5
    export_simulation_xsim=5implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
    launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
    launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=3synthesisstrategy=Vivado Synthesis Defaults
    target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
    +
    + + + + +
    unisim_transformation
    + + + + + + + + +
    post_unisim_transformation
    bibuf=130bufg=1gnd=3lut1=112
    ps7=1vcc=1
    +
    + + + + + + + + +
    pre_unisim_transformation
    bibuf=130bufg=1gnd=3lut1=112
    ps7=1vcc=1
    +

    + + + + + +
    ip_statistics
    + + + + + + + + + + + + + + + + + + + + + +
    IP_Integrator/1
    bdsource=USERcore_container=NAda_ps7_cnt=1iptotal=1
    maxhierdepth=0numblks=1numhdlrefblks=0numhierblks=0
    numhlsblks=0numnonxlnxblks=0numpkgbdblks=0numreposblks=1
    numsysgenblks=0synth_mode=Globalx_iplanguage=VERILOGx_iplibrary=BlockDiagram
    x_ipname=systemx_ipvendor=xilinx.comx_ipversion=1.00.a
    +
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    processing_system7_v5.5_user_configuration/1
    core_container=NAiptotal=1pcw_apu_clk_ratio_enable=6:2:1pcw_apu_peripheral_freqmhz=666.666666
    pcw_armpll_ctrl_fbdiv=40pcw_can0_grp_clk_enable=0pcw_can0_peripheral_clksrc=Externalpcw_can0_peripheral_enable=0
    pcw_can0_peripheral_freqmhz=-1pcw_can1_grp_clk_enable=0pcw_can1_peripheral_clksrc=Externalpcw_can1_peripheral_enable=0
    pcw_can1_peripheral_freqmhz=-1pcw_can_peripheral_clksrc=IO PLLpcw_can_peripheral_freqmhz=100pcw_cpu_cpu_pll_freqmhz=1333.333
    pcw_cpu_peripheral_clksrc=ARM PLLpcw_crystal_peripheral_freqmhz=33.333333pcw_dci_peripheral_clksrc=DDR PLLpcw_dci_peripheral_freqmhz=10.159
    pcw_ddr_ddr_pll_freqmhz=1066.667pcw_ddr_hpr_to_critical_priority_level=15pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)pcw_ddr_lpr_to_critical_priority_level=2
    pcw_ddr_peripheral_clksrc=DDR PLLpcw_ddr_port0_hpr_enable=0pcw_ddr_port1_hpr_enable=0pcw_ddr_port2_hpr_enable=0
    pcw_ddr_port3_hpr_enable=0pcw_ddr_write_to_critical_priority_level=2pcw_ddrpll_ctrl_fbdiv=32pcw_enet0_enet0_io=MIO 16 .. 27
    pcw_enet0_grp_mdio_enable=1pcw_enet0_peripheral_clksrc=IO PLLpcw_enet0_peripheral_enable=1pcw_enet0_peripheral_freqmhz=1000 Mbps
    pcw_enet0_reset_enable=0pcw_enet1_grp_mdio_enable=0pcw_enet1_peripheral_clksrc=IO PLLpcw_enet1_peripheral_enable=0
    pcw_enet1_peripheral_freqmhz=1000 Mbpspcw_enet1_reset_enable=0pcw_enet_reset_polarity=Active Lowpcw_fclk0_peripheral_clksrc=IO PLL
    pcw_fclk1_peripheral_clksrc=IO PLLpcw_fclk2_peripheral_clksrc=IO PLLpcw_fclk3_peripheral_clksrc=IO PLLpcw_fpga0_peripheral_freqmhz=50
    pcw_fpga1_peripheral_freqmhz=50pcw_fpga2_peripheral_freqmhz=50pcw_fpga3_peripheral_freqmhz=50pcw_fpga_fclk0_enable=1
    pcw_fpga_fclk1_enable=0pcw_fpga_fclk2_enable=0pcw_fpga_fclk3_enable=0pcw_gpio_emio_gpio_enable=0
    pcw_gpio_mio_gpio_enable=1pcw_gpio_mio_gpio_io=MIOpcw_gpio_peripheral_enable=0pcw_i2c0_grp_int_enable=0
    pcw_i2c0_peripheral_enable=0pcw_i2c0_reset_enable=0pcw_i2c1_grp_int_enable=0pcw_i2c1_peripheral_enable=0
    pcw_i2c1_reset_enable=0pcw_i2c_reset_polarity=Active Lowpcw_io_io_pll_freqmhz=1000.000pcw_iopll_ctrl_fbdiv=30
    pcw_irq_f2p_mode=DIRECTpcw_m_axi_gp0_freqmhz=50pcw_m_axi_gp1_freqmhz=10pcw_nand_cycles_t_ar=1
    pcw_nand_cycles_t_clr=1pcw_nand_cycles_t_rc=11pcw_nand_cycles_t_rea=1pcw_nand_cycles_t_rr=1
    pcw_nand_cycles_t_wc=11pcw_nand_cycles_t_wp=1pcw_nand_grp_d8_enable=0pcw_nand_peripheral_enable=0
    pcw_nor_cs0_t_ceoe=1pcw_nor_cs0_t_pc=1pcw_nor_cs0_t_rc=11pcw_nor_cs0_t_tr=1
    pcw_nor_cs0_t_wc=11pcw_nor_cs0_t_wp=1pcw_nor_cs0_we_time=0pcw_nor_cs1_t_ceoe=1
    pcw_nor_cs1_t_pc=1pcw_nor_cs1_t_rc=11pcw_nor_cs1_t_tr=1pcw_nor_cs1_t_wc=11
    pcw_nor_cs1_t_wp=1pcw_nor_cs1_we_time=0pcw_nor_grp_a25_enable=0pcw_nor_grp_cs0_enable=0
    pcw_nor_grp_cs1_enable=0pcw_nor_grp_sram_cs0_enable=0pcw_nor_grp_sram_cs1_enable=0pcw_nor_grp_sram_int_enable=0
    pcw_nor_peripheral_enable=0pcw_nor_sram_cs0_t_ceoe=1pcw_nor_sram_cs0_t_pc=1pcw_nor_sram_cs0_t_rc=11
    pcw_nor_sram_cs0_t_tr=1pcw_nor_sram_cs0_t_wc=11pcw_nor_sram_cs0_t_wp=1pcw_nor_sram_cs0_we_time=0
    pcw_nor_sram_cs1_t_ceoe=1pcw_nor_sram_cs1_t_pc=1pcw_nor_sram_cs1_t_rc=11pcw_nor_sram_cs1_t_tr=1
    pcw_nor_sram_cs1_t_wc=11pcw_nor_sram_cs1_t_wp=1pcw_nor_sram_cs1_we_time=0pcw_override_basic_clock=0
    pcw_pcap_peripheral_clksrc=IO PLLpcw_pcap_peripheral_freqmhz=200pcw_pjtag_peripheral_enable=0pcw_preset_bank0_voltage=LVCMOS 3.3V
    pcw_preset_bank1_voltage=LVCMOS 1.8Vpcw_qspi_grp_fbclk_enable=1pcw_qspi_grp_fbclk_io=MIO 8pcw_qspi_grp_io1_enable=0
    pcw_qspi_grp_single_ss_enable=1pcw_qspi_grp_single_ss_io=MIO 1 .. 6pcw_qspi_grp_ss1_enable=0pcw_qspi_internal_highaddress=0xFCFFFFFF
    pcw_qspi_peripheral_clksrc=IO PLLpcw_qspi_peripheral_enable=1pcw_qspi_peripheral_freqmhz=200pcw_qspi_qspi_io=MIO 1 .. 6
    pcw_s_axi_acp_freqmhz=10pcw_s_axi_gp0_freqmhz=10pcw_s_axi_gp1_freqmhz=10pcw_s_axi_hp0_data_width=64
    pcw_s_axi_hp0_freqmhz=10pcw_s_axi_hp1_data_width=64pcw_s_axi_hp1_freqmhz=10pcw_s_axi_hp2_data_width=64
    pcw_s_axi_hp2_freqmhz=10pcw_s_axi_hp3_data_width=64pcw_s_axi_hp3_freqmhz=10pcw_sd0_grp_cd_enable=1
    pcw_sd0_grp_cd_io=MIO 47pcw_sd0_grp_pow_enable=0pcw_sd0_grp_wp_enable=0pcw_sd0_peripheral_enable=1
    pcw_sd0_sd0_io=MIO 40 .. 45pcw_sd1_grp_cd_enable=0pcw_sd1_grp_pow_enable=0pcw_sd1_grp_wp_enable=0
    pcw_sd1_peripheral_enable=0pcw_sdio_peripheral_clksrc=IO PLLpcw_sdio_peripheral_freqmhz=100pcw_single_qspi_data_mode=x4
    pcw_smc_peripheral_clksrc=IO PLLpcw_smc_peripheral_freqmhz=100pcw_spi0_grp_ss0_enable=0pcw_spi0_grp_ss1_enable=0
    pcw_spi0_grp_ss2_enable=0pcw_spi0_peripheral_enable=0pcw_spi1_grp_ss0_enable=0pcw_spi1_grp_ss1_enable=0
    pcw_spi1_grp_ss2_enable=0pcw_spi1_peripheral_enable=0pcw_spi_peripheral_clksrc=IO PLLpcw_spi_peripheral_freqmhz=166.666666
    pcw_tpiu_peripheral_clksrc=Externalpcw_tpiu_peripheral_freqmhz=200pcw_trace_grp_16bit_enable=0pcw_trace_grp_2bit_enable=0
    pcw_trace_grp_32bit_enable=0pcw_trace_grp_4bit_enable=0pcw_trace_grp_8bit_enable=0pcw_trace_peripheral_enable=0
    pcw_ttc0_clk0_peripheral_clksrc=CPU_1Xpcw_ttc0_clk0_peripheral_freqmhz=133.333333pcw_ttc0_clk1_peripheral_clksrc=CPU_1Xpcw_ttc0_clk1_peripheral_freqmhz=133.333333
    pcw_ttc0_clk2_peripheral_clksrc=CPU_1Xpcw_ttc0_clk2_peripheral_freqmhz=133.333333pcw_ttc0_peripheral_enable=0pcw_ttc1_clk0_peripheral_clksrc=CPU_1X
    pcw_ttc1_clk0_peripheral_freqmhz=133.333333pcw_ttc1_clk1_peripheral_clksrc=CPU_1Xpcw_ttc1_clk1_peripheral_freqmhz=133.333333pcw_ttc1_clk2_peripheral_clksrc=CPU_1X
    pcw_ttc1_clk2_peripheral_freqmhz=133.333333pcw_ttc1_peripheral_enable=0pcw_ttc_peripheral_freqmhz=50pcw_uart0_baud_rate=115200
    pcw_uart0_grp_full_enable=0pcw_uart0_peripheral_enable=0pcw_uart1_baud_rate=115200pcw_uart1_grp_full_enable=0
    pcw_uart1_peripheral_enable=1pcw_uart1_uart1_io=MIO 48 .. 49pcw_uart_peripheral_clksrc=IO PLLpcw_uart_peripheral_freqmhz=100
    pcw_uiparam_ddr_adv_enable=0pcw_uiparam_ddr_al=0pcw_uiparam_ddr_bank_addr_count=3pcw_uiparam_ddr_bl=8
    pcw_uiparam_ddr_board_delay0=0.25pcw_uiparam_ddr_board_delay1=0.25pcw_uiparam_ddr_board_delay2=0.25pcw_uiparam_ddr_board_delay3=0.25
    pcw_uiparam_ddr_bus_width=32 Bitpcw_uiparam_ddr_cl=7pcw_uiparam_ddr_clock_0_length_mm=0pcw_uiparam_ddr_clock_0_package_length=61.0905
    pcw_uiparam_ddr_clock_0_propogation_delay=160pcw_uiparam_ddr_clock_1_length_mm=0pcw_uiparam_ddr_clock_1_package_length=61.0905pcw_uiparam_ddr_clock_1_propogation_delay=160
    pcw_uiparam_ddr_clock_2_length_mm=0pcw_uiparam_ddr_clock_2_package_length=61.0905pcw_uiparam_ddr_clock_2_propogation_delay=160pcw_uiparam_ddr_clock_3_length_mm=0
    pcw_uiparam_ddr_clock_3_package_length=61.0905pcw_uiparam_ddr_clock_3_propogation_delay=160pcw_uiparam_ddr_clock_stop_en=0pcw_uiparam_ddr_col_addr_count=10
    pcw_uiparam_ddr_cwl=6pcw_uiparam_ddr_device_capacity=4096 MBitspcw_uiparam_ddr_dq_0_length_mm=0pcw_uiparam_ddr_dq_0_package_length=64.1705
    pcw_uiparam_ddr_dq_0_propogation_delay=160pcw_uiparam_ddr_dq_1_length_mm=0pcw_uiparam_ddr_dq_1_package_length=63.686pcw_uiparam_ddr_dq_1_propogation_delay=160
    pcw_uiparam_ddr_dq_2_length_mm=0pcw_uiparam_ddr_dq_2_package_length=68.46pcw_uiparam_ddr_dq_2_propogation_delay=160pcw_uiparam_ddr_dq_3_length_mm=0
    pcw_uiparam_ddr_dq_3_package_length=105.4895pcw_uiparam_ddr_dq_3_propogation_delay=160pcw_uiparam_ddr_dqs_0_length_mm=0pcw_uiparam_ddr_dqs_0_package_length=68.4725
    pcw_uiparam_ddr_dqs_0_propogation_delay=160pcw_uiparam_ddr_dqs_1_length_mm=0pcw_uiparam_ddr_dqs_1_package_length=71.086pcw_uiparam_ddr_dqs_1_propogation_delay=160
    pcw_uiparam_ddr_dqs_2_length_mm=0pcw_uiparam_ddr_dqs_2_package_length=66.794pcw_uiparam_ddr_dqs_2_propogation_delay=160pcw_uiparam_ddr_dqs_3_length_mm=0
    pcw_uiparam_ddr_dqs_3_package_length=108.7385pcw_uiparam_ddr_dqs_3_propogation_delay=160pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0
    pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0pcw_uiparam_ddr_dram_width=16 Bitspcw_uiparam_ddr_ecc=Disabled
    pcw_uiparam_ddr_enable=1pcw_uiparam_ddr_freq_mhz=533.333333pcw_uiparam_ddr_high_temp=Normal (0-85)pcw_uiparam_ddr_memory_type=DDR 3
    pcw_uiparam_ddr_partno=MT41K256M16 RE-125pcw_uiparam_ddr_row_addr_count=15pcw_uiparam_ddr_speed_bin=DDR3_1066Fpcw_uiparam_ddr_t_faw=40.0
    pcw_uiparam_ddr_t_ras_min=35.0pcw_uiparam_ddr_t_rc=48.75pcw_uiparam_ddr_t_rcd=7pcw_uiparam_ddr_t_rp=7
    pcw_uiparam_ddr_train_data_eye=1pcw_uiparam_ddr_train_read_gate=1pcw_uiparam_ddr_train_write_level=1pcw_uiparam_ddr_use_internal_vref=0
    pcw_usb0_peripheral_enable=0pcw_usb0_peripheral_freqmhz=60pcw_usb0_reset_enable=0pcw_usb1_peripheral_enable=0
    pcw_usb1_peripheral_freqmhz=60pcw_usb1_reset_enable=0pcw_usb_reset_polarity=Active Lowpcw_use_cross_trigger=0
    pcw_use_m_axi_gp0=1pcw_use_m_axi_gp1=0pcw_use_s_axi_acp=0pcw_use_s_axi_gp0=0
    pcw_use_s_axi_gp1=0pcw_use_s_axi_hp0=0pcw_use_s_axi_hp1=0pcw_use_s_axi_hp2=0
    pcw_use_s_axi_hp3=0pcw_wdt_peripheral_clksrc=CPU_1Xpcw_wdt_peripheral_enable=0pcw_wdt_peripheral_freqmhz=133.333333
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    processing_system7_v5_5_processing_system7/1
    c_dm_width=4c_dq_width=32c_dqs_width=4c_emio_gpio_width=64
    c_en_emio_enet0=0c_en_emio_enet1=0c_en_emio_pjtag=0c_en_emio_trace=0
    c_fclk_clk0_buf=TRUEc_fclk_clk1_buf=FALSEc_fclk_clk2_buf=FALSEc_fclk_clk3_buf=FALSE
    c_gp0_en_modifiable_txn=0c_gp1_en_modifiable_txn=0c_include_acp_trans_check=0c_include_trace_buffer=0
    c_irq_f2p_mode=DIRECTc_m_axi_gp0_enable_static_remap=0c_m_axi_gp0_id_width=12c_m_axi_gp0_thread_id_width=12
    c_m_axi_gp1_enable_static_remap=0c_m_axi_gp1_id_width=12c_m_axi_gp1_thread_id_width=12c_mio_primitive=54
    c_num_f2p_intr_inputs=2c_package_name=clg400c_ps7_si_rev=PRODUCTIONc_s_axi_acp_aruser_val=31
    c_s_axi_acp_awuser_val=31c_s_axi_acp_id_width=3c_s_axi_gp0_id_width=6c_s_axi_gp1_id_width=6
    c_s_axi_hp0_data_width=64c_s_axi_hp0_id_width=6c_s_axi_hp1_data_width=64c_s_axi_hp1_id_width=6
    c_s_axi_hp2_data_width=64c_s_axi_hp2_id_width=6c_s_axi_hp3_data_width=64c_s_axi_hp3_id_width=6
    c_trace_buffer_clock_delay=12c_trace_buffer_fifo_size=128c_trace_internal_width=2c_trace_pipeline_width=8
    c_use_axi_nonsecure=0c_use_default_acp_user_val=0c_use_m_axi_gp0=1c_use_m_axi_gp1=0
    c_use_s_axi_acp=0c_use_s_axi_gp0=0c_use_s_axi_gp1=0c_use_s_axi_hp0=0
    c_use_s_axi_hp1=0c_use_s_axi_hp2=0c_use_s_axi_hp3=0core_container=NA
    iptotal=1use_trace_data_edge_detector=0x_ipcorerevision=6x_iplanguage=VERILOG
    x_iplibrary=ipx_ipname=processing_system7x_ipproduct=Vivado 2017.4x_ipsimlanguage=MIXED
    x_ipvendor=xilinx.comx_ipversion=5.5
    +

    + + + +
    report_drc
    + + + + + + + + + + + + + +
    command_line_options
    -append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
    -format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
    -ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
    +

    + + + +
    report_methodology
    + + + + + + + + + + + +
    command_line_options
    -append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
    -format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
    -waived=default::[not_specified]
    +

    + + + + +
    report_power
    + + + + + + + + + + + + + + + +
    command_line_options
    -advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
    -hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
    -return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
    -xpe=default::[not_specified]
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    usage
    airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
    board_layers=8to11 (8 to 11 Layers)board_selection=medium (10"x10")clocks=0.000197confidence_level_clock_activity=High
    confidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Highconfidence_level_io_activity=High
    confidence_level_overall=Highcustomer=TBDcustomer_class=TBDdevstatic=0.119646
    die=xc7z010clg400-1dsp_output_toggle=12.500000dynamic=1.529075effective_thetaja=11.5
    enable_probability=0.990000family=zynqff_toggle=12.500000flow_state=routed
    heatsink=noneinput_toggle=12.500000junction_temp=44.0 (C)logic=0.000000
    mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
    mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
    mgtvccaux_dynamic_current=0.000000mgtvccaux_static_current=0.000000mgtvccaux_total_current=0.000000mgtvccaux_voltage=1.800000
    netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=1.648721output_enable=1.000000
    output_load=5.000000output_toggle=12.500000package=clg400pct_clock_constrained=0.000000
    pct_inputs_defined=0platform=nt64process=typicalps7=1.528872
    ram_enable=50.000000ram_write=50.000000read_saif=Falseset/reset_probability=0.000000
    signal_rate=Falsesignals=0.000007simulation_file=Nonespeedgrade=-1
    static_prob=Falsetemp_grade=commercialthetajb=9.3 (C/W)thetasa=0.0 (C/W)
    toggle_rate=Falseuser_board_temp=25.0 (C)user_effective_thetaja=11.5user_junc_temp=44.0 (C)
    user_thetajb=9.3 (C/W)user_thetasa=0.0 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000
    vccadc_total_current=0.020000vccadc_voltage=1.800000vccaux_dynamic_current=0.000000vccaux_io_dynamic_current=0.000000
    vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.008067
    vccaux_total_current=0.008067vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000426
    vccbram_total_current=0.000426vccbram_voltage=1.000000vccint_dynamic_current=0.000203vccint_static_current=0.006917
    vccint_total_current=0.007120vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000
    vcco12_total_current=0.000000vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000
    vcco135_total_current=0.000000vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000
    vcco15_total_current=0.000000vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000
    vcco18_total_current=0.000000vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000
    vcco25_total_current=0.000000vcco25_voltage=2.500000vcco33_dynamic_current=0.000000vcco33_static_current=0.000000
    vcco33_total_current=0.000000vcco33_voltage=3.300000vcco_ddr_dynamic_current=0.456904vcco_ddr_static_current=0.002000
    vcco_ddr_total_current=0.458904vcco_ddr_voltage=1.500000vcco_mio0_dynamic_current=0.001750vcco_mio0_static_current=0.001000
    vcco_mio0_total_current=0.002750vcco_mio0_voltage=3.300000vcco_mio1_dynamic_current=0.002187vcco_mio1_static_current=0.001000
    vcco_mio1_total_current=0.003187vcco_mio1_voltage=1.800000vccpaux_dynamic_current=0.051039vccpaux_static_current=0.010330
    vccpaux_total_current=0.061369vccpaux_voltage=1.800000vccpint_dynamic_current=0.716954vccpint_static_current=0.029690
    vccpint_total_current=0.746644vccpint_voltage=1.000000vccpll_dynamic_current=0.013878vccpll_static_current=0.003000
    vccpll_total_current=0.016878vccpll_voltage=1.800000version=2017.4
    +

    + + + + + + + + + +
    report_utilization
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    clocking
    bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
    bufhce_available=48bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
    bufio_available=8bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
    bufmrce_available=4bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
    bufr_available=8bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
    mmcme2_adv_available=2mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
    plle2_adv_available=2plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
    +
    + + + + + + +
    dsp
    dsps_available=80dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    io_standard
    blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
    diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
    diff_sstl135_r=0diff_sstl15=1diff_sstl15_r=0diff_sstl18_i=0
    diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
    hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
    lvcmos18=1lvcmos25=0lvcmos33=1lvds_25=0
    lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
    ppds_25=0rsds_25=0sstl135=0sstl135_r=0
    sstl15=1sstl15_r=0sstl18_i=0sstl18_ii=0
    tmds_33=0
    +
    + + + + + + + + + + + + + + +
    memory
    block_ram_tile_available=60block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
    ramb18_available=120ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
    ramb36_fifo_available=60ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
    +
    + + + + + + + + +
    primitives
    bibuf_functional_category=IObibuf_used=130bufg_functional_category=Clockbufg_used=1
    ps7_functional_category=Specialized Resourceps7_used=1
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    slice_logic
    f7_muxes_available=8800f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
    f8_muxes_available=4400f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
    lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=0lut_as_logic_util_percentage=0.00
    lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
    register_as_flip_flop_available=35200register_as_flip_flop_fixed=0register_as_flip_flop_used=0register_as_flip_flop_util_percentage=0.00
    register_as_latch_available=35200register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
    slice_luts_available=17600slice_luts_fixed=0slice_luts_used=0slice_luts_util_percentage=0.00
    slice_registers_available=35200slice_registers_fixed=0slice_registers_used=0slice_registers_util_percentage=0.00
    lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=17600lut_as_logic_fixed=0
    lut_as_logic_used=0lut_as_logic_util_percentage=0.00lut_as_memory_available=6000lut_as_memory_fixed=0
    lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
    lut_flip_flop_pairs_available=17600lut_flip_flop_pairs_fixed=0lut_flip_flop_pairs_used=0lut_flip_flop_pairs_util_percentage=0.00
    slice_available=4400slice_fixed=0slice_used=0slice_util_percentage=0.00
    slicel_fixed=0slicel_used=0slicem_fixed=0slicem_used=0
    unique_control_sets_used=0
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    specific_feature
    bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
    capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
    dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
    efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
    frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
    icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
    startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
    xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
    +

    + + + +
    router
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    usage
    actual_expansions=65047bogomips=0bram18=0bram36=0
    bufg=0bufr=0congestion_level=0ctrls=0
    dsp=0effort=2estimated_expansions=26520ff=0
    global_clocks=1high_fanout_nets=1iob=0lut=0
    movable_instances=136nets=266pins=3571pll=0
    router_runtime=0.000000router_timing_driven=1threads=2timing_constraints_exist=1
    +

    + + + + +
    synthesis
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    command_line_options
    -assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
    -control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
    -fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
    -keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
    -max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
    -no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7z010clg400-1
    -resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
    -rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
    -top=system_wrapper-verilog_define=default::[not_specified]
    +
    + + + + + + +
    usage
    elapsed=00:00:55shls_ip=0memory_gain=670.180MBmemory_peak=947.707MB
    +

    + + diff --git a/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.xml b/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..4c61d8e --- /dev/null +++ b/Miz_sys/Miz_sys.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,980 @@ + + +
    +
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    +
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    +
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    +
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    +
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    +
    +
    +     diff --git a/Miz_sys/Miz_sys.runs/impl_1/vivado.pb b/Miz_sys/Miz_sys.runs/impl_1/vivado.pb new file mode 100644 index 0000000..3b48ccc Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/vivado.pb differ diff --git a/Miz_sys/Miz_sys.runs/impl_1/write_bitstream.pb b/Miz_sys/Miz_sys.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..04c68e5 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/impl_1/write_bitstream.pb differ diff --git a/Miz_sys/Miz_sys.runs/synth_1/.Vivado_Synthesis.queue.rst b/Miz_sys/Miz_sys.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/synth_1/.vivado.begin.rst b/Miz_sys/Miz_sys.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..1ca8f40 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Miz_sys/Miz_sys.runs/synth_1/.vivado.end.rst b/Miz_sys/Miz_sys.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.js b/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.sh b/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc b/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc new file mode 100644 index 0000000..18ae547 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc @@ -0,0 +1,13 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# Block Designs: bd/system/system.bd +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==system || ORIG_REF_NAME==system} -quiet] -quiet + +# IP: bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] -quiet + +# XDC: bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc +set_property DONT_TOUCH TRUE [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] {/inst } ]/inst ] -quiet] -quiet + +# XDC: bd/system/system_ooc.xdc diff --git a/Miz_sys/Miz_sys.runs/synth_1/gen_run.xml b/Miz_sys/Miz_sys.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..cc69566 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/gen_run.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.runs/synth_1/htr.txt b/Miz_sys/Miz_sys.runs/synth_1/htr.txt new file mode 100644 index 0000000..16a4b96 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl diff --git a/Miz_sys/Miz_sys.runs/synth_1/rundef.js b/Miz_sys/Miz_sys.runs/synth_1/rundef.js new file mode 100644 index 0000000..e8ebda2 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64;E:/Xilinx2017/Vivado/2017.4/bin;"; +} else { + PathVal = "E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64;E:/Xilinx2017/Vivado/2017.4/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Miz_sys/Miz_sys.runs/synth_1/runme.bat b/Miz_sys/Miz_sys.runs/synth_1/runme.bat new file mode 100644 index 0000000..622b935 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Miz_sys/Miz_sys.runs/synth_1/runme.sh b/Miz_sys/Miz_sys.runs/synth_1/runme.sh new file mode 100644 index 0000000..144e80a --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64:E:/Xilinx2017/Vivado/2017.4/bin +else + PATH=E:/Xilinx2017/SDK/2017.4/bin;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/bin/nt64;E:/Xilinx2017/Vivado/2017.4/ids_lite/ISE/lib/nt64:E:/Xilinx2017/Vivado/2017.4/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl diff --git a/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.dcp b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.dcp new file mode 100644 index 0000000..77c8405 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.dcp differ diff --git a/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.tcl b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.tcl new file mode 100644 index 0000000..14a8680 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.tcl @@ -0,0 +1,54 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath D:/modeltech64_10.6d/win64 +create_project -in_memory -part xc7z010clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.cache/wt [current_project] +set_property parent.project_path L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.xpr [current_project] +set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_cache_permissions disable [current_project] +read_verilog -library xil_defaultlib L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v +add_files L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bd +set_property used_in_implementation false [get_files -all l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] +set_property used_in_implementation false [get_files -all L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] + +synth_design -top system_wrapper -part xc7z010clg400-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef system_wrapper.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb" diff --git a/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.vds b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.vds new file mode 100644 index 0000000..e8fc5d3 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.vds @@ -0,0 +1,434 @@ +#----------------------------------------------------------- +# Vivado v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Sat May 25 13:08:49 2019 +# Process ID: 17824 +# Current directory: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1 +# Command line: vivado.exe -log system_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl +# Log file: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.vds +# Journal file: L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source system_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx2017/Vivado/2017.4/data/ip'. +Command: synth_design -top system_wrapper -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 17092 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 390.742 ; gain = 105.852 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'system_wrapper' [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] +INFO: [Synth 8-638] synthesizing module 'system' [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v:13] +INFO: [Synth 8-638] synthesizing module 'system_processing_system7_0_0' [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60] +INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_5_processing_system7' [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:161] + Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer + Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer + Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer + Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer + Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer + Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer + Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer + Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer + Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer + Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer + Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer + Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer + Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer + Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer + Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer + Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer + Parameter C_NUM_F2P_INTR_INPUTS bound to: 2 - type: integer + Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string + Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string + Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string + Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string + Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer + Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer + Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer + Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer + Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer + Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer + Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string + Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer + Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer + Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer + Parameter C_DQ_WIDTH bound to: 32 - type: integer + Parameter C_DQS_WIDTH bound to: 4 - type: integer + Parameter C_DM_WIDTH bound to: 4 - type: integer + Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer + Parameter C_PACKAGE_NAME bound to: clg400 - type: string + Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string + Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer + Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer + Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer + Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer + Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer + Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer + Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer + Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer + Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer + Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer + Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer + Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer + Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 0 - type: integer + Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 0 - type: integer +INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1347] +INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1348] +INFO: [Synth 8-638] synthesizing module 'BUFG' [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607] +INFO: [Synth 8-256] done synthesizing module 'BUFG' (1#1) [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607] +INFO: [Synth 8-638] synthesizing module 'BIBUF' [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:268] +INFO: [Synth 8-256] done synthesizing module 'BIBUF' (2#1) [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:268] +INFO: [Synth 8-638] synthesizing module 'PS7' [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:40559] +INFO: [Synth 8-256] done synthesizing module 'PS7' (3#1) [E:/Xilinx2017/Vivado/2017.4/scripts/rt/data/unisim_comp.v:40559] +INFO: [Synth 8-256] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:161] +WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:313] +INFO: [Synth 8-256] done synthesizing module 'system_processing_system7_0_0' (5#1) [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60] +WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'system_processing_system7_0_0' requires 62 connections, but only 34 given [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v:80] +INFO: [Synth 8-256] done synthesizing module 'system' (6#1) [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v:13] +INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (7#1) [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_COL +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_CRS +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_DV +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_ER +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[7] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[6] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[5] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[4] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[3] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[1] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[0] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_COL +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_CRS +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_DV +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_ER +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[7] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[6] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[5] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[4] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[3] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[1] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[0] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_ARSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_AWSIZE[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG3_N +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG2_N +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG1_N +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG0_N +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[31] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[30] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[29] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[28] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[27] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[26] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[25] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[24] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[23] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[22] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[21] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[20] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[19] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[18] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[17] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[16] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[15] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[14] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[13] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[12] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[11] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[10] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[9] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[8] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[7] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[6] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[5] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[4] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[3] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[1] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[0] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_VALID +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[3] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[1] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 443.477 ; gain = 158.586 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 443.477 ; gain = 158.586 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' +Finished Parsing XDC File [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [l:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 700.844 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 700.844 ; gain = 415.953 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 700.844 ; gain = 415.953 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for system_i/processing_system7_0/inst. (constraint file L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/dont_touch.xdc, line 11). +Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for system_i/processing_system7_0. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 700.844 ; gain = 415.953 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 700.844 ; gain = 415.953 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_COL +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_CRS +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_DV +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_ER +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[7] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[6] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[5] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[4] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[3] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[2] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[1] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[0] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_COL +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_CRS +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_DV +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_ER +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[7] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[6] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[5] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[4] +WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[3] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 700.844 ; gain = 415.953 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 921.688 ; gain = 636.797 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 941.559 ; gain = 656.668 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BIBUF | 130| +|2 |BUFG | 1| +|3 |LUT1 | 112| +|4 |PS7 | 1| ++------+------+------+ + +Report Instance Areas: ++------+-------------------------+-------------------------------------------+------+ +| |Instance |Module |Cells | ++------+-------------------------+-------------------------------------------+------+ +|1 |top | | 244| +|2 | system_i |system | 244| +|3 | processing_system7_0 |system_processing_system7_0_0 | 244| +|4 | inst |processing_system7_v5_5_processing_system7 | 244| ++------+-------------------------+-------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 947.707 ; gain = 662.816 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 79 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 947.707 ; gain = 405.449 +Synthesis Optimization Complete : Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 947.707 ; gain = 662.816 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +31 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:57 . Memory (MB): peak = 957.277 ; gain = 679.750 +INFO: [Common 17-1381] The checkpoint 'L:/REV2019/MZ7XAB/MZ7XA_7010/02_example_SOC/CH08_Intr_timer/Miz_sys/Miz_sys.runs/synth_1/system_wrapper.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 957.277 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sat May 25 13:10:04 2019... diff --git a/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.pb b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.pb new file mode 100644 index 0000000..bf73aaf Binary files /dev/null and b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.pb differ diff --git a/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.rpt b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.rpt new file mode 100644 index 0000000..f84fbd8 --- /dev/null +++ b/Miz_sys/Miz_sys.runs/synth_1/system_wrapper_utilization_synth.rpt @@ -0,0 +1,171 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +| Date : Sat May 25 13:10:04 2019 +| Host : LB-201810041430 running 64-bit major release (build 9200) +| Command : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb +| Design : system_wrapper +| Device : 7z010clg400-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 112 | 0 | 17600 | 0.64 | +| LUT as Logic | 112 | 0 | 17600 | 0.64 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 0 | 0 | 35200 | 0.00 | +| Register as Flip Flop | 0 | 0 | 35200 | 0.00 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+--------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+--------+ +| Bonded IOB | 0 | 0 | 100 | 0.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 130 | 0 | 130 | 100.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+--------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+----------------------+ +| Ref Name | Used | Functional Category | ++----------+------+----------------------+ +| BIBUF | 130 | IO | +| LUT1 | 112 | LUT | +| PS7 | 1 | Specialized Resource | +| BUFG | 1 | Clock | ++----------+------+----------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Miz_sys/Miz_sys.runs/synth_1/vivado.pb b/Miz_sys/Miz_sys.runs/synth_1/vivado.pb new file mode 100644 index 0000000..03892f4 Binary files /dev/null and b/Miz_sys/Miz_sys.runs/synth_1/vivado.pb differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.lock b/Miz_sys/Miz_sys.sdk/.metadata/.lock new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/com.xilinx.sdk.hw.ui/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/com.xilinx.sdk.hw.ui/dialog_settings.xml new file mode 100644 index 0000000..8442cb1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/com.xilinx.sdk.hw.ui/dialog_settings.xml @@ -0,0 +1,4 @@ + +
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    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer.1556982955302.pdom b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer.1556982955302.pdom new file mode 100644 index 0000000..f6d5072 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer.1556982955302.pdom differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer_bsp.1556982955327.pdom b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer_bsp.1556982955327.pdom new file mode 100644 index 0000000..ff7a7bc Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.core/Intr_Timer_bsp.1556982955327.pdom differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/Intr_Timer.sc b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/Intr_Timer.sc new file mode 100644 index 0000000..5a22e85 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/Intr_Timer.sc @@ -0,0 +1,1261 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c @@ -0,0 +1 @@ + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp @@ -0,0 +1 @@ + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml new file mode 100644 index 0000000..a3615fd --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml @@ -0,0 +1,20 @@ + +
    + + +
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    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/a067b096548a00191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/a067b096548a00191fc89b07d677db35 new file mode 100644 index 0000000..4177e2a --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/a067b096548a00191fc89b07d677db35 @@ -0,0 +1,16 @@ +#ifndef DATASCOPE_DP_H_ +#define DATASCOPE_DP_H_ + + +extern unsigned char DataScope_OutPut_Buffer[42]; //´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + + +void DataScope_Get_Channel_Data(float Data,unsigned char Channel); // дͨµÀÊý¾ÝÖÁ ´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + +unsigned char DataScope_Data_Generate(unsigned char Channel_Number); // ·¢ËÍÖ¡Êý¾ÝÉú³Éº¯Êý + + +#endif + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/b027fc72528a00191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/b027fc72528a00191fc89b07d677db35 new file mode 100644 index 0000000..d94afa3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/0/b027fc72528a00191fc89b07d677db35 @@ -0,0 +1,152 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" +#include "uartps_intr.h" + + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1024 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); + + Init_UartPsIntr(&UartPs,UART_DEVICE_ID); + UartPs_Setup_IntrSystem(&Intc, &UartPs, UART_INT_IRQ_ID); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(uint8_t order)//½×Êý +{ + uint16_t i,j,k; +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for(k=0; k < order ; k++) + { + uint32_t deebug=0; + for ( i = 0; i < N; i++) + { + for (j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } +} + +int main(void) +{ + f2 = f1 + 2000; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + XUartPs_Recv(&UartPs, RecvBuffer, TEST_BUFFER_SIZE); + cnt = 0; + + while(1) + { + lsm(8); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/12/b0592dee5a8a00191363dfa26739e172 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/12/b0592dee5a8a00191363dfa26739e172 new file mode 100644 index 0000000..8b1945d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/12/b0592dee5a8a00191363dfa26739e172 @@ -0,0 +1,157 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" +#include "uartps_intr.h" +#include "uart_debug.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1024 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); + + Init_UartPsIntr(&UartPs,UART_DEVICE_ID); + UartPs_Setup_IntrSystem(&Intc, &UartPs, UART_INT_IRQ_ID); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + //printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(uint8_t order)//½×Êý +{ + uint16_t i,j,k; +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for(k=0; k < order ; k++) + { + uint32_t deebug=0; + for ( i = 0; i < N; i++) + { + for (j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } +} + +int main(void) +{ + f2 = f1 + 2000; + lms_init(); + uint8_t Send_Count; + + printf("------------START-------------\n"); + init_intr_sys(); + XUartPs_Recv(&UartPs, RecvBuffer, TEST_BUFFER_SIZE); + cnt = 0; + while(1) + { + lsm(8); + lsm_clear(); + cnt++; + DataScope_Get_Channel_Data(0.2f, 1 ); + DataScope_Get_Channel_Data(0.3f, 2 ); + Send_Count = DataScope_Data_Generate(2); + XUartPs_Send(&UartPs, DataScope_OutPut_Buffer, Send_Count); + usleep(20*1000); + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/506ca4fd9c8700191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/506ca4fd9c8700191fc89b07d677db35 new file mode 100644 index 0000000..20ff603 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/506ca4fd9c8700191fc89b07d677db35 @@ -0,0 +1,129 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +int f1 = 10; +int fs = 1000; + +int f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5f*cosf(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sinf(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.1; + } +} + +void lsm(void) +{ + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } + + for (int i = 0; i < N; i++) + { + for (int j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (int j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + for (int i = 0; i < NN; i++) + { + w[i] = 0.1; + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + +} + +int main(void) +{ + f2 = f1 + 10; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/80d03738a28900191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/80d03738a28900191fc89b07d677db35 new file mode 100644 index 0000000..6db0f03 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/15/80d03738a28900191fc89b07d677db35 @@ -0,0 +1,132 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +int f1 = 15000; +int fs = 200000; + +int f2; +int t[N] = { 0 }; +int d[N] = { 0 }; +int xn[NN][N] = { 0 }; +int w[NN]; +int e[N] = { 0 }; +int y[N] = { 0 }; +int u = 0.009*8192; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 8192*1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 8192*1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 8192*0.01; + } +} + +void lsm(void) +{ + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = 8192*sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = 8192*cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } + + for (int i = 0; i < N; i++) + { + for (int j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (int j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + for (int i = 0; i < NN; i++) + { + w[i] = 8192*0.01; + } +} + +int main(void) +{ + f2 = f1 + 2000; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/19/50124057598a00191363dfa26739e172 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/19/50124057598a00191363dfa26739e172 new file mode 100644 index 0000000..f781f13 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/19/50124057598a00191363dfa26739e172 @@ -0,0 +1,16 @@ + + +#ifndef DATASCOPE_DP_H +#define DATASCOPE_DP_H + +extern unsigned char DataScope_OutPut_Buffer[42]; //´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + +void DataScope_Get_Channel_Data(float Data,unsigned char Channel); // дͨµÀÊý¾ÝÖÁ ´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + +unsigned char DataScope_Data_Generate(unsigned char Channel_Number); // ·¢ËÍÖ¡Êý¾ÝÉú³Éº¯Êý + + +#endif + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/1e/f0e000e8ad8900191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/1e/f0e000e8ad8900191fc89b07d677db35 new file mode 100644 index 0000000..19566bf --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/1e/f0e000e8ad8900191fc89b07d677db35 @@ -0,0 +1,145 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1024 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(uint8_t order)//½×Êý +{ + uint16_t i,j,k; +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for(k=0; k < order ; k++) + { + for ( i = 0; i < N; i++) + { + for (j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } +} + +int main(void) +{ + f2 = f1 + 2000; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(8); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/27/20656e7f9c8700191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/27/20656e7f9c8700191fc89b07d677db35 new file mode 100644 index 0000000..f47749d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/27/20656e7f9c8700191fc89b07d677db35 @@ -0,0 +1,124 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +int f1 = 10; +int fs = 1000; + +int f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5f*cosf(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sinf(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.1; + } +} + +void lsm(void) +{ + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } + + for (int i = 0; i < N; i++) + { + for (int j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (int j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y)); + memset(e,0,sizeof(e)); +} + +int main(void) +{ + f2 = f1 + 10; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/70dd35f3aa8900191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/70dd35f3aa8900191fc89b07d677db35 new file mode 100644 index 0000000..cfd008c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/70dd35f3aa8900191fc89b07d677db35 @@ -0,0 +1,132 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } +} + +void lsm(void) +{ + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } + + for (int i = 0; i < N; i++) + { + for (int j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (int j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } +} + +void lsm_clear(void) +{ + memset(y,0,sizeof(y[0])*N); + memset(e,0,sizeof(e[0])*N); + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } +} + +int main(void) +{ + f2 = f1 + 2000; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(); + lsm_clear(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/e0be8bf5ab8900191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/e0be8bf5ab8900191fc89b07d677db35 new file mode 100644 index 0000000..b8ea573 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/31/e0be8bf5ab8900191fc89b07d677db35 @@ -0,0 +1,144 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(uint8_t order)//½×Êý +{ +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for(uint8_t i=0;i 10) || (Channel == 0) ) return; //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + switch (Channel) + { + case 1: Float2Byte(&Data,DataScope_OutPut_Buffer,1); break; + case 2: Float2Byte(&Data,DataScope_OutPut_Buffer,5); break; + case 3: Float2Byte(&Data,DataScope_OutPut_Buffer,9); break; + case 4: Float2Byte(&Data,DataScope_OutPut_Buffer,13); break; + case 5: Float2Byte(&Data,DataScope_OutPut_Buffer,17); break; + case 6: Float2Byte(&Data,DataScope_OutPut_Buffer,21); break; + case 7: Float2Byte(&Data,DataScope_OutPut_Buffer,25); break; + case 8: Float2Byte(&Data,DataScope_OutPut_Buffer,29); break; + case 9: Float2Byte(&Data,DataScope_OutPut_Buffer,33); break; + case 10: Float2Byte(&Data,DataScope_OutPut_Buffer,37); break; + } + } +} + + +//º¯Êý˵Ã÷£ºÉú³É DataScopeV1.0 ÄÜÕýȷʶ±ðµÄÖ¡¸ñʽ +//Channel_Number£¬ÐèÒª·¢Ë͵ÄͨµÀ¸öÊý +//·µ»Ø·¢ËÍ»º³åÇøÊý¾Ý¸öÊý +//·µ»Ø0±íʾ֡¸ñʽÉú³Éʧ°Ü +unsigned char DataScope_Data_Generate(unsigned char Channel_Number) +{ + if ( (Channel_Number > 10) || (Channel_Number == 0) ) { return 0; } //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + DataScope_OutPut_Buffer[0] = '$'; //Ö¡Í· + + switch(Channel_Number) + { + case 1: DataScope_OutPut_Buffer[5] = 5; return 6; + case 2: DataScope_OutPut_Buffer[9] = 9; return 10; + case 3: DataScope_OutPut_Buffer[13] = 13; return 14; + case 4: DataScope_OutPut_Buffer[17] = 17; return 18; + case 5: DataScope_OutPut_Buffer[21] = 21; return 22; + case 6: DataScope_OutPut_Buffer[25] = 25; return 26; + case 7: DataScope_OutPut_Buffer[29] = 29; return 30; + case 8: DataScope_OutPut_Buffer[33] = 33; return 34; + case 9: DataScope_OutPut_Buffer[37] = 37; return 38; + case 10: DataScope_OutPut_Buffer[41] = 41; return 42; + } + } + return 0; +} + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/89/9055ea79988700191fc89b07d677db35 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/89/9055ea79988700191fc89b07d677db35 new file mode 100644 index 0000000..afcde5f --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/89/9055ea79988700191fc89b07d677db35 @@ -0,0 +1,117 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1000 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + printf("cnt = %d\r\n"); + cnt=0; +} + +int f1 = 10; +int fs = 1000; + +int f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5f*cosf(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sinf(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.1; + } +} + +void lsm(void) +{ + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } + +// for (int i = 0; i < N; i++) +// { +// for (int j = 0; j < NN; j++) +// { +// y[i] = y[i] + w[j] * xn[j][i]; +// } +// e[i] = d[i] - y[i]; +// for (int j = 0; j < NN; j++) +// { +// w[j] = w[j] + u*e[i] * xn[j][i]; +// } +// } +} + +int main(void) +{ + f2 = f1 + 10; + lms_init(); + + printf("------------START-------------\n"); + init_intr_sys(); + cnt = 0; + + while(1) + { + lsm(); + cnt++; + } +} + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/8a/20d65a615f8a00191363dfa26739e172 b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/8a/20d65a615f8a00191363dfa26739e172 new file mode 100644 index 0000000..79df5a3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/8a/20d65a615f8a00191363dfa26739e172 @@ -0,0 +1,166 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" +#include "uartps_intr.h" +#include "uart_debug.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1024 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); + + Init_UartPsIntr(&UartPs,UART_DEVICE_ID); + UartPs_Setup_IntrSystem(&Intc, &UartPs, UART_INT_IRQ_ID); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + //printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 200000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.009; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.01; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(uint8_t order)//½×Êý +{ + uint16_t i,j,k; +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for(k=0; k < order ; k++) + { + uint32_t deebug=0; + for ( i = 0; i < N; i++) + { + for (j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } + } +} + +void lsm_clear(void) +{ + uint8_t Send_Count; + for(int i=0;i 10) || (Channel == 0) ) return; //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + switch (Channel) + { + case 1: Float2Byte(&Data,DataScope_OutPut_Buffer,1); break; + case 2: Float2Byte(&Data,DataScope_OutPut_Buffer,5); break; + case 3: Float2Byte(&Data,DataScope_OutPut_Buffer,9); break; + case 4: Float2Byte(&Data,DataScope_OutPut_Buffer,13); break; + case 5: Float2Byte(&Data,DataScope_OutPut_Buffer,17); break; + case 6: Float2Byte(&Data,DataScope_OutPut_Buffer,21); break; + case 7: Float2Byte(&Data,DataScope_OutPut_Buffer,25); break; + case 8: Float2Byte(&Data,DataScope_OutPut_Buffer,29); break; + case 9: Float2Byte(&Data,DataScope_OutPut_Buffer,33); break; + case 10: Float2Byte(&Data,DataScope_OutPut_Buffer,37); break; + } + } +} + + +//º¯Êý˵Ã÷£ºÉú³É DataScopeV1.0 ÄÜÕýȷʶ±ðµÄÖ¡¸ñʽ +//Channel_Number£¬ÐèÒª·¢Ë͵ÄͨµÀ¸öÊý +//·µ»Ø·¢ËÍ»º³åÇøÊý¾Ý¸öÊý +//·µ»Ø0±íʾ֡¸ñʽÉú³Éʧ°Ü +unsigned char DataScope_Data_Generate(unsigned char Channel_Number) +{ + if ( (Channel_Number > 10) || (Channel_Number == 0) ) { return 0; } //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + DataScope_OutPut_Buffer[0] = '$'; //Ö¡Í· + + switch(Channel_Number) + { + case 1: DataScope_OutPut_Buffer[5] = 5; return 6; + case 2: DataScope_OutPut_Buffer[9] = 9; return 10; + case 3: DataScope_OutPut_Buffer[13] = 13; return 14; + case 4: DataScope_OutPut_Buffer[17] = 17; return 18; + case 5: DataScope_OutPut_Buffer[21] = 21; return 22; + case 6: DataScope_OutPut_Buffer[25] = 25; return 26; + case 7: DataScope_OutPut_Buffer[29] = 29; return 30; + case 8: DataScope_OutPut_Buffer[33] = 33; return 34; + case 9: DataScope_OutPut_Buffer[37] = 37; return 38; + case 10: DataScope_OutPut_Buffer[41] = 41; return 42; + } + } + return 0; +} + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer/.indexes/e4/history.index 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a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer/.syncinfo.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer/.syncinfo.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer/.syncinfo.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/a8/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/a8/properties.index new file mode 100644 index 0000000..20f5655 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/a8/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/33/e4/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/33/e4/properties.index new file mode 100644 index 0000000..926d4e0 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/33/e4/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/df/e4/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/df/e4/properties.index new file mode 100644 index 0000000..2fb5496 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/6b/c1/df/e4/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/properties.index new file mode 100644 index 0000000..100bcdc Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.indexes/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers new file mode 100644 index 0000000..28fc3fb Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.markers.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.syncinfo.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.syncinfo.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/Intr_Timer_bsp/.syncinfo.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.markers.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.markers.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.markers.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.syncinfo.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.syncinfo.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/.syncinfo.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.indexes/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.indexes/properties.index new file mode 100644 index 0000000..9c11a78 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.indexes/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.markers.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.markers.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.markers.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.syncinfo.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.syncinfo.snap new file mode 100644 index 0000000..c8b1e33 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.projects/system_wrapper_hw_platform_0/.syncinfo.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version new file mode 100644 index 0000000..25cb955 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index new file mode 100644 index 0000000..72db06f Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version new file mode 100644 index 0000000..6b2aaa7 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers new file mode 100644 index 0000000..e64cdde Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap new file mode 100644 index 0000000..5936caf Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/19.tree b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/19.tree new file mode 100644 index 0000000..2f80fea Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.root/19.tree differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources new file mode 100644 index 0000000..b09f744 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/19.snap b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/19.snap new file mode 100644 index 0000000..9f7607f Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.resources/19.snap differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.sdkterminal.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.sdkterminal.prefs new file mode 100644 index 0000000..c1015bb --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.sdkterminal.prefs @@ -0,0 +1,2 @@ +Last\ selected\ port\:=COM74 +eclipse.preferences.version=1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.tools.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.tools.prefs new file mode 100644 index 0000000..16a366f --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.tools.prefs @@ -0,0 +1,16 @@ +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.bss=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.data=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.data1=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.fixup=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.rodata=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.rodata1=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.sbss=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.sbss2=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.sdata=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.sdata2=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:.text=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:heap=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:heap-size=33554432 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:stack=ps7_ddr_0 +com.xilinx.sdk.linkgen.prefs.Intr_Timer\:stack-size=33554432 +eclipse.preferences.version=1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs new file mode 100644 index 0000000..04bc700 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs @@ -0,0 +1,2 @@ +com.xilinx.sdk.preference.invokecount=19 +eclipse.preferences.version=1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer.prefs new file mode 100644 index 0000000..9c00dc4 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer_bsp.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer_bsp.prefs new file mode 100644 index 0000000..9c00dc4 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Intr_Timer_bsp.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..aa2411d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs new file mode 100644 index 0000000..2c7c1b9 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +useAnnotationsPrefPage=true diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 0000000..c261648 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +properties/Intr_Timer.xilinx.gnu.armv7.exe.1601568776/xilinx.gnu.armv7.exe.debug.659059332=xilinx.gnu.armv7.cxx.toolchain.linker.debug.4897521\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.linker.debug.990712642\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.toolchain.archiver.178069379\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.debug.toolchain.1261902358\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.linker.debug.1043383739\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.compiler.debug.790174394\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.assembler.debug.1261108078\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.assembler.debug.998299525\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.toolchain.archiver.944145358\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.size.debug.1305987463\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.compiler.debug.1837608560\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.compiler.debug.589466818\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.debug.659059332\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.compiler.debug.302208710\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.size.debug.1562066553\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.linker.debug.1841356211\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.debug.toolchain.863168900\=rebuildState\\\=true\\r\\n\r\n +properties/Intr_Timer.xilinx.gnu.armv7.exe.1601568776/xilinx.gnu.armv7.exe.release.1329577227=xilinx.gnu.armv7.toolchain.archiver.106047535\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.compiler.release.507448560\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.size.release.383645556\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.release.toolchain.1870908474\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.linker.release.1440587335\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.compiler.release.194563130\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.assembler.release.1012113004\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.linker.release.131545115\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.release.1329577227\=rebuildState\\\=true\\r\\n\r\n +properties/Timer_Interrupt.xilinx.gnu.armv7.exe.1380148358/xilinx.gnu.armv7.exe.debug.2006319233=xilinx.gnu.armv7.cxx.toolchain.compiler.debug.976562529\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.linker.debug.212473213\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.linker.debug.1333264766\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.compiler.debug.1029423470\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.exe.debug.toolchain.1318227308\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.toolchain.archiver.330274453\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.exe.debug.2006319233\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.assembler.debug.432568542\=rebuildState\\\=false\\r\\n\r\nxilinx.gnu.armv7.size.debug.292903625\=rebuildState\\\=false\\r\\n\r\n +properties/Timer_Interrupt.xilinx.gnu.armv7.exe.1380148358/xilinx.gnu.armv7.exe.release.738092198=xilinx.gnu.armv7.toolchain.archiver.1989646052\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.linker.release.1236732140\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.linker.release.1535706644\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.cxx.toolchain.compiler.release.499576379\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.compiler.release.1855949228\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.release.toolchain.1245648129\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.exe.release.738092198\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.size.release.823256685\=rebuildState\\\=true\\r\\n\r\nxilinx.gnu.armv7.c.toolchain.assembler.release.1488531117\=rebuildState\\\=true\\r\\n\r\n diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 0000000..5e2da66 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..dffc6b5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +version=1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 0000000..3fccb34 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,7 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug,;org.eclipse.cdt.cdi.launch.localCLaunch,run,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug,; +eclipse.preferences.version=1 +org.eclipse.debug.core.PREF_BREAKPOINT_MANAGER_ENABLED_STATE=true +prefWatchExpressions=\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 0000000..cbf5de1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,12 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.MemoryView.orientation=0 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.save_dirty_editors_before_launch=always +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.BreakpointView=\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\r\n +pref_state_memento.org.eclipse.debug.ui.ExpressionView=\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.RegisterView=\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n\r\n\r\n +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|org.eclipse.tcf.debug.DetailPaneFactory\:org.eclipse.tcf.debug.DetailPaneFactory| +preferredTargets=default,org.eclipse.tcf.debug.toggleTCFBreakpoint\:default|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget,org.eclipse.tcf.debug.toggleTCFBreakpoint\:org.eclipse.tcf.debug.toggleTCFBreakpoint|org.eclipse.tcf.debug.toggleTCFBreakpoint\:org.eclipse.tcf.debug.toggleTCFBreakpoint|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs new file mode 100644 index 0000000..b91d667 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs @@ -0,0 +1,14 @@ +content_assist_proposals_background=255,255,255 +content_assist_proposals_foreground=0,0,0 +eclipse.preferences.version=1 +fontPropagated=true +org.eclipse.jdt.internal.ui.navigator.layout=2 +org.eclipse.jdt.ui.editor.tab.width= +org.eclipse.jdt.ui.formatterprofiles.version=12 +org.eclipse.jdt.ui.javadoclocations.migrated=true +org.eclipse.jface.textfont=1|Courier New|10.0|0|WINDOWS|1|0|0|0|0|0|0|0|0|1|0|0|0|0|Courier New; +proposalOrderMigrated=true +spelling_locale_initialized=true +tabWidthPropagated=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs new file mode 100644 index 0000000..f4fbb76 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs @@ -0,0 +1,4 @@ +activeuserprofiles=LB-201708051431;Team +eclipse.preferences.version=1 +org.eclipse.rse.systemtype.local.systemType.defaultUserId=Administrator +useridperkey=LB-201708051431.Local\=Administrator; diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs new file mode 100644 index 0000000..9510302 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.rse.preferences.order.connections=LB-201708051431.Local diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 0000000..56cd496 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 0000000..61f3bb8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 0000000..6c0c0cd --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,5 @@ +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1557052498481 +quickStart=false +tipsAndTricks=true diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 0000000..08076f2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 0000000..699e6a2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,2 @@ +//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false +eclipse.preferences.version=1 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.core/.launches/System Debugger using Debug_Intr_Timer.elf on Local.launch b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.core/.launches/System Debugger using Debug_Intr_Timer.elf on Local.launch new file mode 100644 index 0000000..ba576f6 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.core/.launches/System Debugger using Debug_Intr_Timer.elf on Local.launch @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 0000000..2493f00 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,16 @@ + +
    +
    + + + +
    +
    + + + + + + +
    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 0000000..9fa7f2d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi new file mode 100644 index 0000000..f47b8a1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -0,0 +1,3096 @@ + + + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration + ModelMigrationProcessor.001 + + + + + + + + topLevel + shellMaximized + + + + + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.rse.core.search.searchActionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.cdt.ui.SearchActionSet + persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.search.ui.views.SearchView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.ui.CView + persp.viewSC:org.eclipse.ui.views.ResourceNavigator + persp.viewSC:org.eclipse.ui.views.PropertySheet + persp.viewSC:org.eclipse.ui.views.TaskList + persp.viewSC:ilg.gnuarmeclipse.managedbuild.packs.ui.views.DocsView + persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.viewSC:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView + persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet + persp.perspSC:org.eclipse.debug.ui.DebugPerspective + persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.cdt.ui.buildConfigActionSet + persp.actionSet:org.eclipse.cdt.ui.NavigationActionSet + persp.actionSet:org.eclipse.cdt.ui.OpenActionSet + persp.actionSet:org.eclipse.cdt.ui.CodingActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.presentation + persp.showIn:org.eclipse.cdt.ui.includeBrowser + persp.showIn:org.eclipse.cdt.ui.CView + persp.showIn:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.cdt.ui.includeBrowser + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.newWizSC:com.xilinx.sdk.appwiz.AppWizard + persp.newWizSC:com.xilinx.sdk.profile.ui.wizards.ZpeProjectWizard + persp.newWizSC:com.xilinx.sdk.sw.ui.NewBspWizard + persp.actionSet:org.eclipse.debug.ui.debugActionSet + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Debug + + + + + + + + + + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.rse.core.search.searchActionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.debug.ui.debugActionSet + persp.viewSC:org.eclipse.debug.ui.DebugView + persp.viewSC:org.eclipse.debug.ui.VariableView + persp.viewSC:org.eclipse.debug.ui.BreakpointView + persp.viewSC:org.eclipse.debug.ui.ExpressionView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.ui.views.TaskList + persp.viewSC:org.eclipse.cdt.debug.ui.SignalsView + persp.viewSC:org.eclipse.debug.ui.RegisterView + persp.viewSC:org.eclipse.debug.ui.ModuleView + persp.viewSC:org.eclipse.debug.ui.MemoryView + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.debug.ui.executablesView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSet + persp.viewSC:org.eclipse.cdt.dsf.gdb.ui.tracecontrol.view + persp.viewSC:org.eclipse.cdt.dsf.debug.ui.disassembly.view + persp.perspSC:org.eclipse.cdt.ui.CPerspective + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.showIn:org.eclipse.egit.ui.RepositoriesView + + + + + + org.eclipse.e4.primaryNavigationStack + + + + + + + + + + + + + + + + + + + + + + org.eclipse.e4.secondaryNavigationStack + + + + + + + + + org.eclipse.e4.secondaryDataStack + active + noFocus + + + + + + + + + + + + + + + + + + + + + + + + View + categoryTag:Help + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Help + + + + org.eclipse.e4.primaryDataStack + EditorStack + + + Editor + com.xilinx.sdk.sw.MSSEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + + + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + + + + Editor + org.eclipse.cdt.dsf.ui.disassembly + removeOnHide + + menuContribution:popup + popup:#DisassemblyPartRulerContext + + + menuContribution:popup + popup:#DisassemblyPartContext + + + + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.ui.navigator.ProjectExplorer#PopupMenu + + + + + View + categoryTag:C/C++ + + + View + categoryTag:General + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.ui.views.ProblemView + popup:org.eclipse.ui.ide.MarkersView + + + + + View + categoryTag:General + + + + View + categoryTag:General + highlighted + active + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTGlobalBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTBuildConsole + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + + + + View + categoryTag:Xilinx + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Xilinx + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:com.xilinx.sdk.targetmanager.ui.TargetManagementView + + + + + + View + categoryTag:Xilinx + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:C/C++ Packs + + + View + categoryTag:Make + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.DebugView + + + menuContribution:popup + popup:org.eclipse.debug.ui.DebugView + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.BreakpointView + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.ExpressionView + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.RegisterView + + + + + + View + categoryTag:Xilinx + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Xilinx + + + View + categoryTag:Ant + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.ModuleView + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Java + + + View + categoryTag:Java + + + View + categoryTag:General + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + toolbarSeparator + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + toolbarSeparator + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + toolbarSeparator + + + + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Opaque + + + Opaque + + + Opaque + + + + Draggable + + + toolbarSeparator + + + + toolbarSeparator + + + + Draggable + + Opaque + + + Opaque + + + + stretch + SHOW_RESTORE_MENU + + + Draggable + HIDEABLE + SHOW_RESTORE_MENU + + + + + stretch + + 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persp.showIn:org.eclipse.cdt.ui.includeBrowser + persp.showIn:org.eclipse.cdt.ui.CView + persp.showIn:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.cdt.ui.includeBrowser + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.newWizSC:com.xilinx.sdk.appwiz.AppWizard + persp.newWizSC:com.xilinx.sdk.profile.ui.wizards.ZpeProjectWizard + persp.newWizSC:com.xilinx.sdk.sw.ui.NewBspWizard + + + + noFocus + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.core/nonChainingJarsCache differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.core/variablesAndContainers.dat b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.core/variablesAndContainers.dat new file mode 100644 index 0000000..434b89e Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.core/variablesAndContainers.dat differ diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml new file mode 100644 index 0000000..a4ee3cb --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml @@ -0,0 +1,2 @@ + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml new file mode 100644 index 0000000..9e390f5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml @@ -0,0 +1,2 @@ + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.history new file mode 100644 index 0000000..1f12d63 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.index new file mode 100644 index 0000000..0ad417b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/36/refactorings.index @@ -0,0 +1 @@ +1536293977165 Delete 3 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.history new file mode 100644 index 0000000..26d195c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.index new file mode 100644 index 0000000..18854e2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2018/9/38/refactorings.index @@ -0,0 +1 @@ +1537148889210 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.history new file mode 100644 index 0000000..05ab5ff --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.index new file mode 100644 index 0000000..83f0900 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/4/17/refactorings.index @@ -0,0 +1 @@ +1556182638113 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.history new file mode 100644 index 0000000..f2ca7d0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.index new file mode 100644 index 0000000..ab76244 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/18/refactorings.index @@ -0,0 +1,3 @@ +1556976599216 Delete 2 resources +1556983007493 Delete 2 resources +1556983709084 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.history new file mode 100644 index 0000000..e1ab8e9 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.index new file mode 100644 index 0000000..59071e8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/20/refactorings.index @@ -0,0 +1,2 @@ +1557976286380 Delete resource 'system_wrapper_hw_platform_1' +1557976630128 Delete resource 'system_wrapper_hw_platform_1' diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.history new file mode 100644 index 0000000..1676b06 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.index new file mode 100644 index 0000000..ab97b0d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/5/21/refactorings.index @@ -0,0 +1,2 @@ +1558684410266 Delete 2 resources +1558761711085 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.history new file mode 100644 index 0000000..9b47191 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.index new file mode 100644 index 0000000..bb35f88 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/23/refactorings.index @@ -0,0 +1 @@ +1559740614645 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.history b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.history new file mode 100644 index 0000000..eb4ec98 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.index b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.index new file mode 100644 index 0000000..48b47fe --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2019/6/24/refactorings.index @@ -0,0 +1,3 @@ +1560043304099 Delete resource 'Intr_Timer/src/DataScope_DP.h' +1560043336670 Delete resource 'Intr_Timer/src/DataScope_DP' +1560045193214 Delete 2 resources diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 0000000..c6ae8a9 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,12 @@ + +
    +
    + + +
    +
    + + + +
    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark new file mode 100644 index 0000000..e69de29 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/FP.local.files_0/node.properties b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/FP.local.files_0/node.properties new file mode 100644 index 0000000..cac4894 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/FP.local.files_0/node.properties @@ -0,0 +1,57 @@ +# RSE DOM Node +00-name=LB-201708051431\:local.files +01-type=FilterPool +03-attr.default=true +03-attr.deletable=true +03-attr.id=local.files +03-attr.nonRenamable=false +03-attr.owningParentName=null +03-attr.release=200 +03-attr.singleFilterStringOnly=false +03-attr.singleFilterStringOnlyESet=false +03-attr.stringsCaseSensitive=true +03-attr.supportsDuplicateFilterStrings=false +03-attr.supportsNestedFilters=true +03-attr.type=default +06-child.00000.00-name=My Home +06-child.00000.01-type=Filter +06-child.00000.03-attr.default=false +06-child.00000.03-attr.filterType=default +06-child.00000.03-attr.id=My Home +06-child.00000.03-attr.nonChangable=false +06-child.00000.03-attr.nonDeletable=false +06-child.00000.03-attr.nonRenamable=false +06-child.00000.03-attr.promptable=false +06-child.00000.03-attr.relativeOrder=0 +06-child.00000.03-attr.release=200 +06-child.00000.03-attr.singleFilterStringOnly=false +06-child.00000.03-attr.stringsCaseSensitive=false +06-child.00000.03-attr.stringsNonChangable=false +06-child.00000.03-attr.supportsDuplicateFilterStrings=false +06-child.00000.03-attr.supportsNestedFilters=true +06-child.00000.06-child.00000.00-name=C\:\\Users\\Administrator\\* +06-child.00000.06-child.00000.01-type=FilterString +06-child.00000.06-child.00000.03-attr.default=false +06-child.00000.06-child.00000.03-attr.string=C\:\\Users\\Administrator\\* +06-child.00000.06-child.00000.03-attr.type=default +06-child.00001.00-name=Drives +06-child.00001.01-type=Filter +06-child.00001.03-attr.default=false +06-child.00001.03-attr.filterType=default +06-child.00001.03-attr.id=Drives +06-child.00001.03-attr.nonChangable=false +06-child.00001.03-attr.nonDeletable=false +06-child.00001.03-attr.nonRenamable=false +06-child.00001.03-attr.promptable=false +06-child.00001.03-attr.relativeOrder=0 +06-child.00001.03-attr.release=200 +06-child.00001.03-attr.singleFilterStringOnly=false +06-child.00001.03-attr.stringsCaseSensitive=false +06-child.00001.03-attr.stringsNonChangable=false +06-child.00001.03-attr.supportsDuplicateFilterStrings=false +06-child.00001.03-attr.supportsNestedFilters=true +06-child.00001.06-child.00000.00-name=* +06-child.00001.06-child.00000.01-type=FilterString +06-child.00001.06-child.00000.03-attr.default=false +06-child.00001.06-child.00000.03-attr.string=* +06-child.00001.06-child.00000.03-attr.type=default diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/H.local_16/node.properties b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/H.local_16/node.properties new file mode 100644 index 0000000..9b4b55a --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/H.local_16/node.properties @@ -0,0 +1,25 @@ +# RSE DOM Node +00-name=Local +01-type=Host +03-attr.description= +03-attr.hostname=LOCALHOST +03-attr.offline=false +03-attr.promptable=false +03-attr.systemType=org.eclipse.rse.systemtype.local +03-attr.type=Local +06-child.00000.00-name=Local Connector Service +06-child.00000.01-type=ConnectorService +06-child.00000.03-attr.group=Local Connector Service +06-child.00000.03-attr.port=0 +06-child.00000.03-attr.useSSL=false +06-child.00000.06-child.00000.00-name=Local Files +06-child.00000.06-child.00000.01-type=SubSystem +06-child.00000.06-child.00000.03-attr.hidden=false +06-child.00000.06-child.00000.03-attr.type=local.files +06-child.00000.06-child.00000.06-child.00000.00-name=LB-201708051431___LB-201708051431\:local.files +06-child.00000.06-child.00000.06-child.00000.01-type=FilterPoolReference +06-child.00000.06-child.00000.06-child.00000.03-attr.refID=local.files +06-child.00000.06-child.00001.00-name=Local Shells +06-child.00000.06-child.00001.01-type=SubSystem +06-child.00000.06-child.00001.03-attr.hidden=false +06-child.00000.06-child.00001.03-attr.type=local.shells diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/node.properties b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/node.properties new file mode 100644 index 0000000..d2c76d3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.lb-201708051431_24576/node.properties @@ -0,0 +1,7 @@ +# RSE DOM Node +00-name=LB-201708051431 +01-type=Profile +03-attr.defaultPrivate=true +03-attr.isActive=true +05-ref.00000=FP.local.files_0 +05-ref.00001=H.local_16 diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.cdt.ui/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.cdt.ui/dialog_settings.xml new file mode 100644 index 0000000..9245f5d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.cdt.ui/dialog_settings.xml @@ -0,0 +1,9 @@ + +
    +
    + + + + +
    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug.ui/memview.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug.ui/memview.xml new file mode 100644 index 0000000..7a6d39d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug.ui/memview.xml @@ -0,0 +1,2 @@ + + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug/peers.ini b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug/peers.ini new file mode 100644 index 0000000..0dd65bf --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.tcf.debug/peers.ini @@ -0,0 +1,33 @@ +ServiceManagerID=e23ec803-7606-4177-b592-df36e5c5a19a +TransportName=TCP +PeerTypeId=HARDWARE_SERVER +UserName=Administrator +Port=3121 +Host=127.0.0.1 +OSName=Windows 10 +ID=Local +AgentID=e23ec803-7606-4177-b592-df36e5c5a19a +Name=Local + +ServiceManagerID=e23ec803-7606-4177-b592-df36e5c5a19a +TransportName=TCP +PeerTypeId=LINUX_TCF_AGENT +UserName=Administrator +Port=1534 +Host=192.168.0.1 +OSName=Windows 10 +ID=Linux Agent +AgentID=e23ec803-7606-4177-b592-df36e5c5a19a +Name=Linux Agent + +ServiceManagerID=e23ec803-7606-4177-b592-df36e5c5a19a +TransportName=TCP +PeerTypeId=QEMU_TCF_GDB_CLIENT +UserName=Administrator +Port=1138 +Host=127.0.0.1 +OSName=Windows 10 +ID=QEMU +AgentID=e23ec803-7606-4177-b592-df36e5c5a19a +Name=QEMU + diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 0000000..50f1edb --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
    +
    +
    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 0000000..2d916f8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,22 @@ + +
    +
    + + + +
    +
    + + + + + + + + + + +
    +
    +
    +
    diff --git a/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 0000000..94105d2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/.metadata/version.ini b/Miz_sys/Miz_sys.sdk/.metadata/version.ini new file mode 100644 index 0000000..991ddba --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.metadata/version.ini @@ -0,0 +1,3 @@ +#Sun Jun 09 09:34:05 CST 2019 +org.eclipse.core.runtime=2 +org.eclipse.platform=4.6.1.v20160907-1200 diff --git a/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_intr_timer.elf_on_local.tcl b/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_intr_timer.elf_on_local.tcl new file mode 100644 index 0000000..ec524f0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_intr_timer.elf_on_local.tcl @@ -0,0 +1,17 @@ +connect -url tcp:127.0.0.1:3121 +source F:/Code/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.tcl +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249855527"} -index 0 +rst -system +after 3000 +targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210249855527" && level==0} -index 1 +fpga -file F:/Code/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system_wrapper.bit +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249855527"} -index 0 +loadhw -hw F:/Code/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] +configparams force-mem-access 1 +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249855527"} -index 0 +ps7_init +ps7_post_config +targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210249855527"} -index 0 +dow F:/Code/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf +configparams force-mem-access 0 +bpadd -addr &main diff --git a/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_timer_interrupt.elf_on_local.tcl b/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_timer_interrupt.elf_on_local.tcl new file mode 100644 index 0000000..937cb47 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_using_debug_timer_interrupt.elf_on_local.tcl @@ -0,0 +1,17 @@ +connect -url tcp:127.0.0.1:3121 +source L:/XILINX_FPGA/02/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.tcl +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249854991"} -index 0 +rst -system +after 3000 +targets -set -filter {jtag_cable_name =~ "Digilent JTAG-HS1 210249854991" && level==0} -index 1 +fpga -file L:/XILINX_FPGA/02/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system_wrapper.bit +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249854991"} -index 0 +loadhw -hw L:/XILINX_FPGA/02/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] +configparams force-mem-access 1 +targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS1 210249854991"} -index 0 +ps7_init +ps7_post_config +targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210249854991"} -index 0 +dow L:/XILINX_FPGA/02/CH08_Intr_timer/Miz_sys/Miz_sys.sdk/Timer_Interrupt/Debug/Timer_Interrupt.elf +configparams force-mem-access 0 +bpadd -addr &main diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/.cproject b/Miz_sys/Miz_sys.sdk/Intr_Timer/.cproject new file mode 100644 index 0000000..2ad1aa3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/.cproject @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/.project b/Miz_sys/Miz_sys.sdk/Intr_Timer/.project new file mode 100644 index 0000000..e138d55 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/.project @@ -0,0 +1,26 @@ + + + Intr_Timer + Created by SDK v2017.4. Intr_Timer_bsp - ps7_cortexa9_0 + + Intr_Timer_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf new file mode 100644 index 0000000..144c891 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf.size b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf.size new file mode 100644 index 0000000..7e875a2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Intr_Timer.elf.size @@ -0,0 +1,2 @@ + text data bss dec hex filename + 50524 3792 67172728 67227044 401cda4 Intr_Timer.elf diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Xilinx.spec b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Xilinx.spec new file mode 100644 index 0000000..eb37de1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/Xilinx.spec @@ -0,0 +1,2 @@ +*startfile: +crti%O%s crtbegin%O%s diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/makefile new file mode 100644 index 0000000..821f6c7 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/makefile @@ -0,0 +1,65 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +ELFSIZE += \ +Intr_Timer.elf.size \ + + +# All Target +all: pre-build main-build + +# Main-build Target +main-build: Intr_Timer.elf secondary-outputs + +# Tool invocations +Intr_Timer.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: ARM v7 gcc linker' + arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../Intr_Timer_bsp/ps7_cortexa9_0/lib -o "Intr_Timer.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @echo 'Finished building target: $@' + @echo ' ' + +Intr_Timer.elf.size: Intr_Timer.elf + @echo 'Invoking: ARM v7 Print Size' + arm-none-eabi-size Intr_Timer.elf |tee "Intr_Timer.elf.size" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(EXECUTABLES)$(OBJS)$(S_UPPER_DEPS)$(C_DEPS)$(ELFSIZE) Intr_Timer.elf + -@echo ' ' + +pre-build: + -a9-linaro-pre-build-step + -@echo ' ' + +secondary-outputs: $(ELFSIZE) + +.PHONY: all clean dependents +.SECONDARY: main-build pre-build + +-include ../makefile.targets diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/objects.mk b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/objects.mk new file mode 100644 index 0000000..24a8ef2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -lm -Wl,--start-group,-lxil,-lgcc,-lc,--end-group + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/sources.mk b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/sources.mk new file mode 100644 index 0000000..18ed203 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/sources.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +LD_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +EXECUTABLES := +OBJS := +S_UPPER_DEPS := +C_DEPS := +ELFSIZE := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +src \ + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.d b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.d new file mode 100644 index 0000000..0572e90 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.d @@ -0,0 +1,90 @@ +src/main.o src/main.o: ../src/main.c ../src/timer_intr.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h \ + ../src/sys_intr.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h \ + ../src/uartps_intr.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../src/uart_debug.h + +../src/timer_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h: + +../src/sys_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h: + +../src/uartps_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../src/uart_debug.h: diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.o b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.o new file mode 100644 index 0000000..f382de5 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/main.o differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/subdir.mk b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/subdir.mk new file mode 100644 index 0000000..e82509e --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +LD_SRCS += \ +../src/lscript.ld + +C_SRCS += \ +../src/main.c \ +../src/sys_intr.c \ +../src/timer_intr.c \ +../src/uart_debug.c \ +../src/uartps_intr.c + +OBJS += \ +./src/main.o \ +./src/sys_intr.o \ +./src/timer_intr.o \ +./src/uart_debug.o \ +./src/uartps_intr.o + +C_DEPS += \ +./src/main.d \ +./src/sys_intr.d \ +./src/timer_intr.d \ +./src/uart_debug.d \ +./src/uartps_intr.d + + +# Each subdirectory must supply rules for building sources it contributes +src/%.o: ../src/%.c + @echo 'Building file: $<' + @echo 'Invoking: ARM v7 gcc compiler' + arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../Intr_Timer_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.d b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.d new file mode 100644 index 0000000..7829f00 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.d @@ -0,0 +1,51 @@ +src/sys_intr.o src/sys_intr.o: ../src/sys_intr.c ../src/sys_intr.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h + +../src/sys_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.o b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.o new file mode 100644 index 0000000..78bb2ac Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/sys_intr.o differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.d b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.d new file mode 100644 index 0000000..aed4296 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.d @@ -0,0 +1,60 @@ +src/timer_intr.o src/timer_intr.o: ../src/timer_intr.c \ + ../src/timer_intr.h ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h + +../src/timer_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h: diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.o b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.o new file mode 100644 index 0000000..f338778 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/timer_intr.o differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.d b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.d new file mode 100644 index 0000000..0d11b0b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.d @@ -0,0 +1 @@ +src/uart_debug.o src/uart_debug.o: ../src/uart_debug.c diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.o b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.o new file mode 100644 index 0000000..9d912e8 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uart_debug.o differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.d b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.d new file mode 100644 index 0000000..d93c42d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.d @@ -0,0 +1,64 @@ +src/uartps_intr.o src/uartps_intr.o: ../src/uartps_intr.c \ + ../src/uartps_intr.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h \ + ../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h + +../src/uartps_intr.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h: + +../../Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h: diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.o b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.o new file mode 100644 index 0000000..52ec727 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer/Debug/src/uartps_intr.o differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/README.txt b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/README.txt new file mode 100644 index 0000000..c4d32ef --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/README.txt @@ -0,0 +1 @@ +Empty application. Add your own sources. diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/Xilinx.spec b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/Xilinx.spec new file mode 100644 index 0000000..8eea377 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/Xilinx.spec @@ -0,0 +1,2 @@ +*startfile: +crti%O%s crtbegin%O%s diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/lscript.ld b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/lscript.ld new file mode 100644 index 0000000..a11b2fa --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/lscript.ld @@ -0,0 +1,288 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: */ +/* */ +/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A9 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000 + ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000 + ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000 + ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > ps7_ddr_0 + +.init : { + KEEP (*(.init)) +} > ps7_ddr_0 + +.fini : { + KEEP (*(.fini)) +} > ps7_ddr_0 + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ps7_ddr_0 + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > ps7_ddr_0 + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > ps7_ddr_0 + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ps7_ddr_0 + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > ps7_ddr_0 + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > ps7_ddr_0 + +.got : { + *(.got) +} > ps7_ddr_0 + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ps7_ddr_0 + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ps7_ddr_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > ps7_ddr_0 + +.eh_frame : { + *(.eh_frame) +} > ps7_ddr_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > ps7_ddr_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > ps7_ddr_0 + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > ps7_ddr_0 + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > ps7_ddr_0 + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > ps7_ddr_0 + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > ps7_ddr_0 + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > ps7_ddr_0 + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > ps7_ddr_0 + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ps7_ddr_0 + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > ps7_ddr_0 + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ps7_ddr_0 + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ps7_ddr_0 + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > ps7_ddr_0 + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > ps7_ddr_0 + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + . = ALIGN(16); + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > ps7_ddr_0 + +_end = .; +} + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/main.c b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/main.c new file mode 100644 index 0000000..f649629 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/main.c @@ -0,0 +1,162 @@ + +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn + * axi dma test + * +*/ + + +#include "timer_intr.h" +#include "sys_intr.h" +#include "math.h" +#include "stdio.h" +#include "uartps_intr.h" +#include "uart_debug.h" + +static XScuGic Intc; //GIC +static XScuTimer Timer;//timer + + +#define TIMER_LOAD_VALUE 0x13D92D3F //1S + +#define N 1024 +#define PI 3.141592 +#define NN 10 + +volatile int cnt; + + +int init_intr_sys(void) +{ + + Timer_init(&Timer,TIMER_LOAD_VALUE,0); + Init_Intr_System(&Intc); // initial interrupt system + Setup_Intr_Exception(&Intc); + Timer_Setup_Intr_System(&Intc,&Timer,TIMER_IRPT_INTR); + Timer_start(&Timer); + + Init_UartPsIntr(&UartPs,UART_DEVICE_ID); + UartPs_Setup_IntrSystem(&Intc, &UartPs, UART_INT_IRQ_ID); +} + +void TimerIntrHandler(void *CallBackRef) +{ + + XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef; + XScuTimer_ClearInterruptStatus(TimerInstancePtr); + //printf("cnt = %d\r\n",cnt); + cnt=0; +} + +float f1 = 15000; +float fs = 100000; + +float f2; +float t[N] = { 0 }; +float d[N] = { 0 }; +float xn[NN][N] = { 0 }; +float w[NN]; +float e[N] = { 0 }; +float y[N] = { 0 }; +float u = 0.008; + + +void lms_init(void) +{ + for (int i = 1; i < N; i++) + { + t[i] = t[i - 1] + 1.0 / fs; + } + + for (int i = 0; i < N; i++) + { + d[i] = 1.5*sin(2 * PI*t[i] * f2 + PI * 33 / 180) + 1.5*sin(2 * PI*t[i] * f1 + 162 * PI / 180); + } + + for (int i = 0; i < NN; i++) + { + w[i] = 0.1; + } + + for (int j = 0; j < NN / 2; j++) + { + for (int i = 0; i < N; i++) + { + xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); + xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); + } + } +} + +void lsm(void)//½×Êý +{ + uint16_t i,j,k; +// for (int j = 0; j < NN / 2; j++) +// { +// for (int i = 0; i < N; i++) +// { +// xn[2 * j + 0][i] = sin(2 * PI * t[i] * (2 * j + 1) * f2); +// xn[2 * j + 1][i] = cos(2 * PI * t[i] * (2 * j + 1) * f2); +// } +// } + + for ( i = 0; i < N; i++) + { + for (j = 0; j < NN; j++) + { + y[i] = y[i] + w[j] * xn[j][i]; + } + e[i] = d[i] - y[i]; + for (j = 0; j < NN; j++) + { + w[j] = w[j] + u*e[i] * xn[j][i]; + } + } +} + +void lsm_clear(void) +{ + uint8_t Send_Count; + for(int i=0;iCpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + return XST_SUCCESS; +} + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/sys_intr.h b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/sys_intr.h new file mode 100644 index 0000000..da905df --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/sys_intr.h @@ -0,0 +1,22 @@ + /*sys_intr.h + * Created on: 2016Äê11ÔÂ22ÈÕ + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn +*/ + +#ifndef SYS_INTR_H_ +#define SYS_INTR_H_ + +#include "xparameters.h" +#include "xil_exception.h" +#include "xdebug.h" +#include "xscugic.h" + + +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID + +int Init_Intr_System(XScuGic * IntcInstancePtr); +void setup_Intr_Exception(XScuGic * IntcInstancePtr); + +#endif /* SYS_INTR_H_ */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.c new file mode 100644 index 0000000..25081ab --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.c @@ -0,0 +1,42 @@ +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn +*/ + +#include "timer_intr.h" + +volatile int usec; + +void TimerIntrHandler(void *CallBackRef); + +void Timer_start(XScuTimer *TimerPtr) +{ + XScuTimer_Start(TimerPtr); +} + +void Timer_Setup_Intr_System(XScuGic *GicInstancePtr,XScuTimer *TimerInstancePtr, u16 TimerIntrId) +{ + XScuGic_Connect(GicInstancePtr, TimerIntrId, + (Xil_ExceptionHandler)TimerIntrHandler,//set up the timer interrupt + (void *)TimerInstancePtr); + + XScuGic_Enable(GicInstancePtr, TimerIntrId);//enable the interrupt for the Timer at GIC + XScuTimer_EnableInterrupt(TimerInstancePtr);//enable interrupt on the timer + } + +int Timer_init(XScuTimer *TimerPtr,u32 Load_Value,u32 DeviceId) +{ + XScuTimer_Config *TMRConfigPtr; //timer config + //˽Óж¨Ê±Æ÷³õʼ»¯ + TMRConfigPtr = XScuTimer_LookupConfig(DeviceId); + XScuTimer_CfgInitialize(TimerPtr, TMRConfigPtr,TMRConfigPtr->BaseAddr); + //XScuTimer_SelfTest(&Timer); + //¼ÓÔؼÆÊýÖÜÆÚ£¬Ë½Óж¨Ê±Æ÷µÄʱÖÓΪCPUµÄÒ»°ë£¬Îª333MHZ,Èç¹û¼ÆÊý1S,¼ÓÔØֵΪ1sx(333x1000x1000)(1/s)-1=0x13D92D3F + XScuTimer_LoadTimer(TimerPtr, Load_Value);//F8F00600+0=reg=F8F00600 + //×Ô¶¯×°ÔØ + XScuTimer_EnableAutoReload(TimerPtr);//F8F00600+8=reg=F8F00608 + + return 1; +} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.h b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.h new file mode 100644 index 0000000..d1a954a --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/timer_intr.h @@ -0,0 +1,28 @@ +/* + * + * www.osrc.cn + * www.milinker.com + * copyright by nan jin mi lian dian zi www.osrc.cn +*/ + +#ifndef TIMER_INTR_H_ +#define TIMER_INTR_H_ + +#include +#include "xadcps.h" +#include "xil_types.h" +#include "xscugic.h" +#include "xil_exception.h" +#include "xscutimer.h" + + +extern volatile int usec; + +//timer info +#define TIMER_DEVICE_ID XPAR_XSCUTIMER_0_DEVICE_ID +#define TIMER_IRPT_INTR XPAR_SCUTIMER_INTR + +void Timer_start(XScuTimer *TimerPtr); +void Timer_Setup_Intr_System(XScuGic *GicInstancePtr,XScuTimer *TimerInstancePtr, u16 TimerIntrId); +int Timer_init(XScuTimer *TimerPtr,u32 Load_Value,u32 DeviceId); +#endif /* TIMER_INTR_H_ */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.c b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.c new file mode 100644 index 0000000..7dd8876 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.c @@ -0,0 +1,92 @@ +/* + * uart_debug.c + * + * Created on: 2019Äê6ÔÂ9ÈÕ + * Author: sansi + */ + + +unsigned char DataScope_OutPut_Buffer[42] = {0}; //´®¿Ú·¢ËÍ»º³åÇø + + +//º¯Êý˵Ã÷£º½«µ¥¾«¶È¸¡µãÊý¾Ýת³É4×Ö½ÚÊý¾Ý²¢´æÈëÖ¸¶¨µØÖ· +//¸½¼Ó˵Ã÷£ºÓû§ÎÞÐèÖ±½Ó²Ù×÷´Ëº¯Êý +//target:Ä¿±êµ¥¾«¶ÈÊý¾Ý +//buf:´ýдÈëÊý×é +//beg:Ö¸¶¨´ÓÊý×éµÚ¼¸¸öÔªËØ¿ªÊ¼Ð´Èë +//º¯ÊýÎÞ·µ»Ø +void Float2Byte(float *target,unsigned char *buf,unsigned char beg) +{ + unsigned char *point; + point = (unsigned char*)target; //µÃµ½floatµÄµØÖ· + buf[beg] = point[0]; + buf[beg+1] = point[1]; + buf[beg+2] = point[2]; + buf[beg+3] = point[3]; +} + + +//º¯Êý˵Ã÷£º½«´ý·¢ËÍͨµÀµÄµ¥¾«¶È¸¡µãÊý¾ÝдÈë·¢ËÍ»º³åÇø +//Data£ºÍ¨µÀÊý¾Ý +//Channel£ºÑ¡ÔñͨµÀ£¨1-10£© +//º¯ÊýÎÞ·µ»Ø +void DataScope_Get_Channel_Data(float Data,unsigned char Channel) +{ + if ( (Channel > 10) || (Channel == 0) ) return; //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + switch (Channel) + { + case 1: Float2Byte(&Data,DataScope_OutPut_Buffer,1); break; + case 2: Float2Byte(&Data,DataScope_OutPut_Buffer,5); break; + case 3: Float2Byte(&Data,DataScope_OutPut_Buffer,9); break; + case 4: Float2Byte(&Data,DataScope_OutPut_Buffer,13); break; + case 5: Float2Byte(&Data,DataScope_OutPut_Buffer,17); break; + case 6: Float2Byte(&Data,DataScope_OutPut_Buffer,21); break; + case 7: Float2Byte(&Data,DataScope_OutPut_Buffer,25); break; + case 8: Float2Byte(&Data,DataScope_OutPut_Buffer,29); break; + case 9: Float2Byte(&Data,DataScope_OutPut_Buffer,33); break; + case 10: Float2Byte(&Data,DataScope_OutPut_Buffer,37); break; + } + } +} + + +//º¯Êý˵Ã÷£ºÉú³É DataScopeV1.0 ÄÜÕýȷʶ±ðµÄÖ¡¸ñʽ +//Channel_Number£¬ÐèÒª·¢Ë͵ÄͨµÀ¸öÊý +//·µ»Ø·¢ËÍ»º³åÇøÊý¾Ý¸öÊý +//·µ»Ø0±íʾ֡¸ñʽÉú³Éʧ°Ü +unsigned char DataScope_Data_Generate(unsigned char Channel_Number) +{ + if ( (Channel_Number > 10) || (Channel_Number == 0) ) { return 0; } //ͨµÀ¸öÊý´óÓÚ10»òµÈÓÚ0£¬Ö±½ÓÌø³ö£¬²»Ö´Ðк¯Êý + else + { + DataScope_OutPut_Buffer[0] = '$'; //Ö¡Í· + + switch(Channel_Number) + { + case 1: DataScope_OutPut_Buffer[5] = 5; return 6; + case 2: DataScope_OutPut_Buffer[9] = 9; return 10; + case 3: DataScope_OutPut_Buffer[13] = 13; return 14; + case 4: DataScope_OutPut_Buffer[17] = 17; return 18; + case 5: DataScope_OutPut_Buffer[21] = 21; return 22; + case 6: DataScope_OutPut_Buffer[25] = 25; return 26; + case 7: DataScope_OutPut_Buffer[29] = 29; return 30; + case 8: DataScope_OutPut_Buffer[33] = 33; return 34; + case 9: DataScope_OutPut_Buffer[37] = 37; return 38; + case 10: DataScope_OutPut_Buffer[41] = 41; return 42; + } + } + return 0; +} + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.h b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.h new file mode 100644 index 0000000..42141fd --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uart_debug.h @@ -0,0 +1,20 @@ +/* + * uart_debug.h + * + * Created on: 2019Äê6ÔÂ9ÈÕ + * Author: sansi + */ + +#ifndef SRC_UART_DEBUG_H_ +#define SRC_UART_DEBUG_H_ + + + +extern unsigned char DataScope_OutPut_Buffer[42]; //´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + +void DataScope_Get_Channel_Data(float Data,unsigned char Channel); // дͨµÀÊý¾ÝÖÁ ´ý·¢ËÍÖ¡Êý¾Ý»º´æÇø + +unsigned char DataScope_Data_Generate(unsigned char Channel_Number); // ·¢ËÍÖ¡Êý¾ÝÉú³Éº¯Êý + + +#endif /* SRC_UART_DEBUG_H_ */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.c new file mode 100644 index 0000000..07e3d20 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.c @@ -0,0 +1,160 @@ +/* + * uartps_intr.c + * + * Created on: 2019Äê05ÔÂ02ÈÕ + * www.osrc.cn + * copyright by cz123 msxbo +*/ +#include "uartps_intr.h" + + +int Init_UartPsIntr(XUartPs *UartInstPtr,u16 DeviceId ) +{ + int Status; + XUartPs_Config *Config; + u32 IntrMask; + + if (XGetPlatform_Info() == XPLAT_ZYNQ_ULTRA_MP) { +#ifdef XPAR_XUARTPS_1_DEVICE_ID + DeviceId = XPAR_XUARTPS_1_DEVICE_ID; +#endif + } + + Config = XUartPs_LookupConfig(DeviceId); + if (NULL == Config) { + return XST_FAILURE; + } + + Status = XUartPs_CfgInitialize(UartInstPtr, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + + /* + * Setup the handlers for the UART that will be called from the + * interrupt context when data has been sent and received, specify + * a pointer to the UART driver instance as the callback reference + * so the handlers are able to access the instance data + */ + XUartPs_SetHandler(UartInstPtr, (XUartPs_Handler)UartPs_Intr_Handler, UartInstPtr); + + /* + * Enable the interrupt of the UART so interrupts will occur, setup + * a local loopback so data that is sent will be received. + */ + IntrMask = + XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | XUARTPS_IXR_FRAMING | + XUARTPS_IXR_OVER | XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXFULL | + XUARTPS_IXR_RXOVR; + + if (UartInstPtr->Platform == XPLAT_ZYNQ_ULTRA_MP) { + IntrMask |= XUARTPS_IXR_RBRK; + } + + XUartPs_SetInterruptMask(UartInstPtr, IntrMask); + + XUartPs_SetRecvTimeout(UartInstPtr, 8); + + return XST_SUCCESS; +} + + +void UartPs_Intr_Handler(void *CallBackRef, u32 Event, unsigned int EventData) +{ + int i = 0; + /* All of the data has been sent */ + if (Event == XUARTPS_EVENT_SENT_DATA) { + TotalSentCount = EventData; + } + + /* All of the data has been received */ + if (Event == XUARTPS_EVENT_RECV_DATA) { + TotalReceivedCount = EventData; + if(TotalReceivedCount == TEST_BUFFER_SIZE) { + for(i=0;iCpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + /* + * interrupt for the device occurs, the device driver handler + * performs the specific interrupt processing for the device + */ + Status = XScuGic_Connect(IntcInstancePtr, UartIntrId, + (Xil_ExceptionHandler) XUartPs_InterruptHandler, + (void *) UartInstancePtr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Enable the interrupt for the device */ + XScuGic_Enable(IntcInstancePtr, UartIntrId); + + return XST_SUCCESS; +} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.h b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.h new file mode 100644 index 0000000..8e78e33 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer/src/uartps_intr.h @@ -0,0 +1,41 @@ +/* + * uartps_intr.h + * + * Created on: 2019Äê5ÔÂ3ÈÕ + * Author: Administrator + */ + +#ifndef SRC_UARTPS_INTR_H_ +#define SRC_UARTPS_INTR_H_ + +#include "xparameters.h" +#include "xplatform_info.h" +#include "xuartps.h" +#include "xil_exception.h" +#include "xil_printf.h" +#include "xscugic.h" + +int Init_UartPsIntr(XUartPs *UartInstPtr,u16 DeviceId); + +int UartPs_Setup_IntrSystem(XScuGic *IntcInstancePtr,XUartPs *UartInstancePtr,u16 UartIntrId); + +void UartPs_Intr_Handler(void *CallBackRef, u32 Event, unsigned int EventData); + + + +#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#define UART_INT_IRQ_ID XPAR_XUARTPS_1_INTR + +#define TEST_BUFFER_SIZE 10 + +XUartPs UartPs;//uart + +static u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ +static u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ + +volatile int TotalReceivedCount; +volatile int TotalSentCount; +int TotalErrorCount; + +#endif /* SRC_UARTPS_INTR_H_ */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.cproject b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.cproject new file mode 100644 index 0000000..44b8458 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.project b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.project new file mode 100644 index 0000000..d7fa7c4 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.project @@ -0,0 +1,75 @@ + + + Intr_Timer_bsp + Created by SDK v2017.4 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.sdkproject b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.sdkproject new file mode 100644 index 0000000..923eee0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=system_wrapper_hw_platform_0 +PROCESSOR=ps7_cortexa9_0 +MSS_FILE=system.mss diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/Makefile new file mode 100644 index 0000000..1ace345 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/Makefile @@ -0,0 +1,35 @@ +# Makefile generated by Xilinx. + +PROCESSOR = ps7_cortexa9_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +clean: $(addsuffix /make.clean,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra" + +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h new file mode 100644 index 0000000..2cee66b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_timer_hw.h: +* Timer related functions +* +******************************************************************************/ + +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H + +#include "profile.h" + +#ifdef PROC_PPC +#if defined __GNUC__ +# define SYNCHRONIZE_IO __asm__ volatile ("eieio") +#elif defined __DCC__ +# define SYNCHRONIZE_IO __asm volatile(" eieio") +#else +# define SYNCHRONIZE_IO +#endif +#endif + +#ifdef PROC_PPC +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } +#else +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } +#endif + +#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) + +#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) + +#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ + ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ + (RegisterValue)) + +#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PROC_PPC +#include "xexception_l.h" +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +#ifdef PROC_CORTEXA9 +#include "xscutimer_hw.h" +#include "xscugic.h" +#endif + +extern u32 timer_clk_ticks ; + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC + +#ifdef PPC_PIT_INTERRUPT +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ +#endif + +#ifdef PROC_PPC440 +#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE +#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS +#define XREG_SPR_PIT XREG_SPR_DEC +#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT +#endif + +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ + +#ifdef PPC_PIT_INTERRUPT +#define disable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ + timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ + mtspr(XREG_SPR_PIT, 0); \ + } +#else +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define enable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ + mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ + } +#else +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define timer_ack() \ + { \ + u32 val; \ + mtspr(XREG_SPR_PIT, timer_clk_ticks); \ + mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ + } +#else +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } +#endif + +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ + + + + +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ + } + +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/bspconfig.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/bspconfig.h new file mode 100644 index 0000000..50464da --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/bspconfig.h @@ -0,0 +1,40 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#define MICROBLAZE_PVR_NONE diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h new file mode 100644 index 0000000..7096a92 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef _MBLAZE_NT_TYPES_H +#define _MBLAZE_NT_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef char byte; +typedef short half; +typedef int word; +typedef unsigned char ubyte; +typedef unsigned short uhalf; +typedef unsigned int uword; +typedef ubyte boolean; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/profile.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/profile.h new file mode 100644 index 0000000..4cb07a7 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/profile.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef PROFILE_H +#define PROFILE_H 1 + +#include +#include "xil_types.h" +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(u32 frompc, u32 selfpc); +void profile_intr_handler( void ) ; +void _profile_init( void ); + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER u16 + +struct tostruct { + u32 selfpc; + s32 count; + s16 link; + u16 pad; +}; + +struct fromstruct { + u32 frompc ; + s16 link ; + u16 pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + s32 state; + + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ + + /* Call-graph Information */ + struct fromstruct *froms; + u32 fromssize; + struct tostruct *tos; + u32 tossize; + + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ +}; +extern struct gmonparam *_gmonparam; +extern s32 n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* PROFILE_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/sleep.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/sleep.h new file mode 100644 index 0000000..27add66 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/sleep.h @@ -0,0 +1,50 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int usleep(unsigned long useconds); +unsigned sleep(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/smc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/smc.h new file mode 100644 index 0000000..5a4d336 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/smc.h @@ -0,0 +1,114 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file smc.h +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+*
    +* +* @note None. +* +******************************************************************************/ + +#ifndef SMC_H /* prevent circular inclusions */ +#define SMC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory controller configuration register offset */ +#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */ + +/* Chip select configuration register offset */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */ + +/* User configuration register offset */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */ + +/* Integration test register offset */ +#define XSMCPSS_IT_OFFSET 0xE00U + +/* ID configuration register offset */ +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SMC_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/vectors.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/vectors.h new file mode 100644 index 0000000..bb599b5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/vectors.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void FIQInterrupt(void); +void IRQInterrupt(void); +#if !defined (__aarch64__) +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); +void UndefinedException(void); +#else +void SynchronousInterrupt(void); +void SErrorInterrupt(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h new file mode 100644 index 0000000..549bfff --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps.h @@ -0,0 +1,591 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps.h +* @addtogroup xadcps_v2_2 +* @{ +* @details +* +* The XAdcPs driver supports the Xilinx XADC/ADC device. +* +* The XADC/ADC device has the following features: +* - 10-bit, 200-KSPS (kilo samples per second) +* Analog-to-Digital Converter (ADC) +* - Monitoring of on-chip supply voltages and temperature +* - 1 dedicated differential analog-input pair and +* 16 auxiliary differential analog-input pairs +* - Automatic alarms based on user defined limits for the on-chip +* supply voltages and temperature +* - Automatic Channel Sequencer, programmable averaging, programmable +* acquisition time for the external inputs, unipolar or differential +* input selection for the external inputs +* - Inbuilt Calibration +* - Optional interrupt request generation +* +* +* The user should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the XADC/ADC device. +* +* +* XADC Channel Sequencer Modes +* +* The XADC Channel Sequencer supports the following operating modes: +* +* - Default : This is the default mode after power up. +* In this mode of operation the XADC operates in +* a sequence mode, monitoring the on chip sensors: +* Temperature, VCCINT, and VCCAUX. +* - One pass through sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers for a single pass and then stops. +* - Continuous cycling of sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers continuously. +* - Single channel mode: In this mode the XADC Channel +* Sequencer is disabled and the XADC operates in a +* Single Channel Mode. +* The XADC can operate either in a Continuous or Event +* driven sampling mode in the single channel mode. +* - Simultaneous Sampling Mode: In this mode the XADC Channel +* Sequencer will automatically sequence through eight fixed pairs +* of auxiliary analog input channels for simulataneous conversion. +* - Independent ADC mode: In this mode the first ADC (A) is used to +* is used to implement a fixed monitoring mode similar to the +* default mode but the alarm fucntions ar eenabled. +* The second ADC (B) is available to be used with external analog +* input channels only. +* +* Read the XADC spec for more information about the sequencer modes. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the XADC/ADC device. +* +* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC +* device. The user needs to first call the XAdcPs_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAdcPs_CfgInitialize() API. +* +* +* Interrupts +* +* The XADC/ADC device supports interrupt driven mode and the default +* operation mode is polling mode. +* +* The interrupt mode is available only if hardware is configured to support +* interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* device in interrupt mode. +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAdcPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* XADC/ADC device can be accessed through the JTAG port and the PLB +* interface. The driver implementation does not support the simultaneous access +* of the device by both these interfaces. The user has to care of this situation +* in the user application code. +* +*

    +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of xadcps
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+*
+*
    +* +*****************************************************************************/ +#ifndef XADCPS_H /* Prevent circular inclusions */ +#define XADCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xadcps_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Indexes for the different channels. + * @{ + */ +#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */ +#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */ +#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */ +#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ +#define XADCPS_CH_VREFP 0x4 /**< VREFP */ +#define XADCPS_CH_VREFN 0x5 /**< VREFN */ +#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */ +#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ +#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ +#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ +#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */ +#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */ +#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */ +#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ +#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ + +/*@}*/ + + +/** + * @name Indexes for reading the Calibration Coefficient Data. + * @{ + */ +#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */ +#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */ +#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ +/*@}*/ + + +/** + * @name Indexes for reading the Minimum/Maximum Measurement Data. + * @{ + */ +#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */ +#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */ +#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ +#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */ +#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */ +#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */ +#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ +#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */ +#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ +#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ +#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ +#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ +#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ +#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ + +/*@}*/ + + +/** + * @name Alarm Threshold(Limit) Register (ATR) indexes. + * @{ + */ +#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */ +#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */ +#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ +#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ +#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ + +/*@}*/ + + +/** + * @name Averaging to be done for the channels. + * @{ + */ +#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */ +#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */ +#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */ +#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */ + +/*@}*/ + + +/** + * @name Channel Sequencer Modes of operation + * @{ + */ +#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ +#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ +#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */ +#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */ +#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */ +#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */ + +/*@}*/ + + + +/** + * @name Power Down Modes + * @{ + */ +#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */ +#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */ +#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */ +/*@}*/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the XADC/ADC + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ +} XAdcPs_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every XADC/ADC device in the system. A pointer to + * a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAdcPs_Config Config; /**< XAdcPs_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + +} XAdcPs; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in Event Sampling mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in Event Sampling Mode. +* - FALSE if the device is in Continuous Sampling Mode. +* +* @note C-Style signature: +* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ + TRUE : FALSE)) + + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in External Mux mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in External Mux Mode. +* - FALSE if the device is NOT in External Mux Mode. +* +* @note C-Style signature: +* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro converts XADC Raw Data to Temperature(centigrades). +* +* @param AdcData is the Raw ADC Data from XADC. +* +* @return The Temperature in centigrades. +* +* @note C-Style signature: +* float XAdcPs_RawToTemperature(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToTemperature(AdcData) \ + ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) + +/****************************************************************************/ +/** +* +* This macro converts XADC/ADC Raw Data to Voltage(volts). +* +* @param AdcData is the XADC/ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XAdcPs_RawToVoltage(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToVoltage(AdcData) \ + ((((float)(AdcData))* (3.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts Temperature in centigrades to XADC/ADC Raw Data. +* +* @param Temperature is the Temperature in centigrades to be +* converted to XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_TemperatureToRaw(float Temperature); +* +*****************************************************************************/ +#define XAdcPs_TemperatureToRaw(Temperature) \ + ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) + +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to XADC/ADC Raw Data. +* +* @param Voltage is the Voltage in volts to be converted to +* XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_VoltageToRaw(float Voltage); +* +*****************************************************************************/ +#define XAdcPs_VoltageToRaw(Voltage) \ + ((int)((Voltage)*65536.0f/3.0f)) + + +/****************************************************************************/ +/** +* +* This macro is used for writing to the XADC Registers using the +* command FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); +* +*****************************************************************************/ +#define XAdcPs_WriteFifo(InstancePtr, Data) \ + XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_CMDFIFO_OFFSET, Data); + + +/****************************************************************************/ +/** +* +* This macro is used for reading from the XADC Registers using the +* data FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return Data read from the FIFO +* +* @note C-Style signature: +* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_ReadFifo(InstancePtr) \ + XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_RDFIFO_OFFSET); + + +/************************** Function Prototypes *****************************/ + + + +/** + * Functions in xadcps_sinit.c + */ +XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); + +/** + * Functions in xadcps.c + */ +int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, + XAdcPs_Config *ConfigPtr, + u32 EffectiveAddr); + + +u32 XAdcPs_GetStatus(XAdcPs *InstancePtr); + +u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr); + +void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr); + +void XAdcPs_Reset(XAdcPs *InstancePtr); + +u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); + +u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); + +u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); + +void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); +u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); + +int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, + u8 Channel, + int IncreaseAcqCycles, + int IsEventMode, + int IsDifferentialMode); + + +void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); +u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); +u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); +u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); + +void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); +u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); +u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); +u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); +u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); +u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); + +void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); +u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); + +void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); +void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode); + +int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr); + +void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel); + +void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode); + +u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_selftest.c + */ +int XAdcPs_SelfTest(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_intr.c + */ +void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); +void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); +u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); + +u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); +void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); + + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h new file mode 100644 index 0000000..55a47a4 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xadcps_hw.h @@ -0,0 +1,502 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps_hw.h +* @addtogroup xadcps_v2_2 +* @{ +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the XADC device through the Device +* Config Interface of the Zynq. +* +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+*
    +* +*****************************************************************************/ +#ifndef XADCPS_HW_H /* Prevent circular inclusions */ +#define XADCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of XADC in the Device Config + * + * The following constants provide access to each of the registers of the + * XADC device. + * @{ + */ + +#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */ +#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */ +#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */ +#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */ +#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */ +#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */ +#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */ + +/* @} */ + + + + + +/** @name XADC Config Register Bit definitions + * @{ + */ +#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */ +#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */ +#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */ +#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */ +#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */ +#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */ +#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between + * successive commands */ +/* @} */ + + +/** @name XADC Interrupt Status/Mask Register Bit definitions + * + * The definitions are same for the Interrupt Status Register and + * Interrupt Mask Register. They are defined only once. + * @{ + */ +#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */ +#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */ +#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */ +#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */ +#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */ +#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */ +#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */ +#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */ +#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */ +#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */ +#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */ +#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */ + +/* @} */ + + +/** @name XADC Miscellaneous Register Bit definitions + * @{ + */ +#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */ +#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */ +#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */ +#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */ +#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */ +#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */ +#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */ +#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */ +/* @} */ + + +/** @name XADC Miscellaneous Control Register Bit definitions + * @{ + */ +#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */ +#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */ +/* @} */ + + +/**@name Internal Register offsets of the XADC + * + * The following constants provide access to each of the internal registers of + * the XADC device. + * @{ + */ + +/* + * XADC Internal Channel Registers + */ +#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */ +#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */ +#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */ +#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */ +#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */ +#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */ +#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */ +#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */ +#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */ +#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */ +#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */ +#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */ +#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */ + +/* + * XADC External Channel Registers + */ +#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */ +#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */ +#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */ +#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */ +#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */ +#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */ +#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */ +#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */ +#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */ +#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */ +#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */ +#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */ +#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */ +#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */ +#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */ +#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */ + +/* + * XADC Registers for Maximum/Minimum data captured for the + * on chip Temperature/VCCINT/VCCAUX data. + */ +#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */ +#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */ +#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */ +#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */ +#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */ +#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */ +#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */ +#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */ +#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */ +#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */ +#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */ +#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */ +#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */ +#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */ + /* Undefined 0x2F to 0x3E */ +#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */ + +/* + * XADC Configuration Registers + */ +#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */ +#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */ +#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */ + +/* Test Registers 0x43 to 0x47 */ + +/* + * XADC Sequence Registers + */ +#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */ +#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */ +#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */ +#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */ +#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */ +#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */ +#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */ +#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */ + +/* + * XADC Alarm Threshold/Limit Registers (ATR) + */ +#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */ +#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */ +#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */ +#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */ +#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */ +#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */ +#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */ +#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */ +#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */ +#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */ + +/* Undefined 0x60 to 0x7F */ + +/*@}*/ + + + +/** + * @name Configuration Register 0 (CFR0) mask(s) + * @{ + */ +#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ +#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ +#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ +#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ +#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ +#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ +#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */ +#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */ +#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ +#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/ + * Continuous mode selection + */ +#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ +#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ + +/*@}*/ + +/** + * @name Configuration Register 1 (CFR1) mask(s) + * @{ + */ +#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ +#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ +#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ +#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ +#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ +#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */ +#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ +#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ +#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */ +#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */ +#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */ +#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */ +#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ +#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power + Supply Gain/Offset + Enable */ +#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power + Supply Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain + Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset + Enable */ +#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ +#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ +#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ +#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ +#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ +#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ + +/*@}*/ + +/** + * @name Configuration Register 2 (CFR2) mask(s) + * @{ + */ +#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /** +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility +* +* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h new file mode 100644 index 0000000..a732b23 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.h +* @addtogroup coresightps_dcc_v1_1 +* @{ +* @details +* +* CoreSight driver component. +* +* The coresight is a part of debug communication channel (DCC) group. Jtag UART +* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an +* ARM target in XSDB console before running the jtag terminal command. Using the +* coresight driver component, the output stream can be directed to a log file. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifndef __MICROBLAZE__ +#include + +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); + +u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +#endif +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h new file mode 100644 index 0000000..eff6cd8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9_v2_1 +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +******************************************************************************/ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xddrps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xddrps.h new file mode 100644 index 0000000..fe7adb0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xddrps.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps_v1_0 + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h new file mode 100644 index 0000000..650946b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdebug.h @@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg.h new file mode 100644 index 0000000..52f99a0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* @addtogroup devcfg_v3_3 +* @{ +* @details +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/10/17 Modified filename tag in interrupt and polled examples
+*                    to include them in doxygen examples.
+* 3.5   ms  04/18/17 Modified tcl file to add suffix U for all macros
+*                    definitions of devcfg in xparameters.h
+*       ms  08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
    +* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h new file mode 100644 index 0000000..c506ca5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h @@ -0,0 +1,395 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
    +* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps.h new file mode 100644 index 0000000..5a0c1a2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps.h @@ -0,0 +1,352 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* @addtogroup dmaps_v2_3 +* @{ +* @details +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * To avoid linking error,Declare all inline functions as extern for + * IAR compiler + */ +#ifdef __ICCARM__ +extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg); +extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps_hw.h new file mode 100644 index 0000000..628f1ec --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xdmaps_hw.h @@ -0,0 +1,293 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* @addtogroup dmaps_v2_3 +* @{ +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
    +* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps.h new file mode 100644 index 0000000..a19b7a1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps.h @@ -0,0 +1,806 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps_v3_4 +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ *
+ *
    + * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bd.h new file mode 100644 index 0000000..11f4a75 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bd.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps_v3_4 +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ *
    + * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#define XEMACPS_BD_NUM_WORDS 4U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#define XEMACPS_BD_NUM_WORDS 2U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bdring.h new file mode 100644 index 0000000..5a30ce3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_bdring.h @@ -0,0 +1,238 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.h +* @addtogroup emacps_v3_4 +* @{ +* +* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs +* DMA functionalities. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
    +* +******************************************************************************/ + +#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ +#define XEMACPS_BDRING_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************** Type Definitions *******************************/ + +/** This is an internal structure used to maintain the DMA list */ +typedef struct { + UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */ + UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */ + UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */ + u32 Length; /**< Total size of ring in bytes */ + u32 RunState; /**< Flag to indicate DMA is started */ + u32 Separation; /**< Number of bytes between the starting address + of adjacent BDs */ + XEmacPs_Bd *FreeHead; + /**< First BD in the free group */ + XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ + XEmacPs_Bd *HwHead; /**< First BD in the work group */ + XEmacPs_Bd *HwTail; /**< Last BD in the work group */ + XEmacPs_Bd *PostHead; + /**< First BD in the post-work group */ + XEmacPs_Bd *BdaRestart; + /**< BDA to load when channel is started */ + + u32 HwCnt; /**< Number of BDs in work group */ + u32 PreCnt; /**< Number of BDs in pre-work group */ + u32 FreeCnt; /**< Number of allocatable BDs in the free group */ + u32 PostCnt; /**< Number of BDs in post-work group */ + u32 AllCnt; /**< Total Number of BDs for channel */ +} XEmacPs_BdRing; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many BDs will fit +* in a BD list within the given memory constraints. +* +* The results of this macro can be provided to XEmacPs_BdRingCreate(). +* +* @param Alignment specifies what byte alignment the BDs must fall on and +* must be a power of 2 to get an accurate calculation (32, 64, 128,...) +* @param Bytes is the number of bytes to be used to store BDs. +* +* @return Number of BDs that can fit in the given memory area +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) +* +******************************************************************************/ +#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ + (u32)((Bytes) / (sizeof(XEmacPs_Bd))) + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many bytes of memory +* is required to contain a given number of BDs at a given alignment. +* +* @param Alignment specifies what byte alignment the BDs must fall on. This +* parameter must be a power of 2 to get an accurate calculation (32, 64, +* 128,...) +* @param NumBd is the number of BDs to calculate memory size requirements for +* +* @return The number of bytes of memory required to create a BD list with the +* given memory constraints. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) +* +******************************************************************************/ +#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ + (u32)(sizeof(XEmacPs_Bd) * (NumBd)) + +/****************************************************************************/ +/** +* Return the total number of BDs allocated by this channel with +* XEmacPs_BdRingCreate(). +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The total number of BDs allocated for this channel. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) + +/****************************************************************************/ +/** +* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- +* processing. +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The number of BDs currently allocatable. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) + +/****************************************************************************/ +/** +* Return the next BD from BdPtr in a list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on. +* +* @return The next BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ + (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \ + (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \ + (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation)) + +/****************************************************************************/ +/** +* Return the previous BD from BdPtr in the list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on +* +* @return The previous BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ + (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ + (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation)) + +/************************** Function Prototypes ******************************/ + +/* + * Scatter gather DMA related functions in xemacps_bdring.c + */ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount); +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction); +LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); + + +#ifdef __cplusplus +} +#endif + + +#endif /* end of protection macros */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_hw.h new file mode 100644 index 0000000..bf35234 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xemacps_hw.h @@ -0,0 +1,656 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_hw.h +* @addtogroup emacps_v3_4 +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. +* High-level driver functions are defined in xemacps.h. +* +* @note +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+*
    +* +******************************************************************************/ + +#ifndef XEMACPS_HW_H /* prevent circular inclusions */ +#define XEMACPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address + supported */ +#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */ + +#ifdef __aarch64__ +#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment + on the local bus */ +#else + +#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment + on the local bus */ +#endif +#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using + options that impose alignment + restrictions on the buffer data on + the local bus */ + +/** @name Direction identifiers + * + * These are used by several functions and callbacks that need + * to specify whether an operation specifies a send or receive channel. + * @{ + */ +#define XEMACPS_SEND 1U /**< send direction */ +#define XEMACPS_RECV 2U /**< receive direction */ +/*@}*/ + +/** @name MDC clock division + * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. + * @{ + */ +typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, + MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 +} XEmacPs_MdcDiv; + +/*@}*/ + +#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in + bytes, 64, 128, ... 10240 */ +#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U + +#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a + unit, this is HW setup */ + +#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */ +#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */ + +#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. Names are self explained here. + */ + +#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */ +#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */ +#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */ + +#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */ +#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */ +#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */ +#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */ +#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */ + +#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */ +#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */ +#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */ +#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */ + +#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */ +#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */ +#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */ + +#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */ + +#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */ +#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */ + +#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */ +#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */ +#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */ +#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */ +#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */ +#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */ +#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */ +#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */ + +#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */ +#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */ +#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */ +#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */ + +#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */ + +#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low + reg */ +#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High + reg */ + +#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes + transmitted counter */ +#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast + Frames counter*/ +#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast + Frame counter */ +#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted + Counter */ +#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames + Transmitted counter */ +#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte + Frames Transmitted + counter */ +#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte + Frames Transmitted + counter*/ +#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte + Frames transmitted + counter */ +#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte + Frames transmitted + counter */ +#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte + Frames transmitted + counter */ +#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than + 1519 byte Frames + transmitted counter */ +#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error + counter */ + +#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame + Counter */ +#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame + Counter */ +#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame + Counter */ +#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame + Counter */ +#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission + Frame Counter */ +#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense + Error Counter */ + +#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register + Low */ +#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register + High */ + +#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames + Received Counter */ +#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast + Frames Received Counter */ +#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast + Frames Received Counter */ +#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames + Received Counter */ +#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames + Received Counter */ +#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte + Frames Received Counter */ +#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte + Frames Received Counter */ +#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte + Frames Received Counter */ +#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte + Frames Received Counter */ +#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte + Frames Received Counter */ +#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte + Frames Received Counter */ +#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received + Counter */ +#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received + Counter */ +#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received + Counter */ +#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence + Error Counter */ +#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error + Counter */ +#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */ +#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */ +#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error + Counter */ +#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */ +#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error + Counter */ +#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error + Counter */ +#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error + Counter */ +#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter + offset, for clearing */ + +#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */ +#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */ +#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond + adjustment counter */ +#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond + increment counter */ +#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second + counter */ +#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit + nanosecond counter */ +#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second + counter */ +#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive + nanosecond counter */ +#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit + second counter */ +#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit + nanosecond counter */ +#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive + second counter */ +#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive + nanosecond counter */ + +#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status + reg */ +#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address + reg */ +#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address + reg */ +#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base + reg */ +#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base + reg */ +#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable + reg */ +#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable + reg */ +#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask + reg */ + +/* Define some bit positions for registers. */ + +/** @name network control register bit definitions + * @{ + */ +#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from + Rx SRAM */ +#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum + pause frame */ +#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */ +#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission + after current frame */ +#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */ + +#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to + stat counters */ +#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic + registers */ +#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic + registers */ +#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */ +#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */ +#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */ +#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */ +/*@}*/ + +/** @name network configuration register bit definitions + * @{ + */ +#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of + non-standard preamble */ +#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */ +#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */ +#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of + FCS error */ +#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */ +#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum + offload */ +#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause + Frames to memory */ +#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */ +#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */ +#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */ +#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from + received frames */ +#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U +/**< RX length error discard */ +#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */ +#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */ +#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */ +#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U +/**< External address match enable */ +#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */ +#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */ +#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte + frames reception */ +#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash + frames */ +#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash + frames */ +#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive + broadcast frames */ +#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */ +#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */ +#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN + frames */ +#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */ +#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */ +#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */ +/*@}*/ + +/** @name network status register bit definitaions + * @{ + */ +#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */ +#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */ +/*@}*/ + + +/** @name MAC address register word 1 mask + * @{ + */ +#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32] + bit[31:0] are in BOTTOM */ +/*@}*/ + + +/** @name DMA control register bit definitions + * @{ + */ +#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ +#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ +#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ +#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer + size */ +#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer + size */ +#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX + checksum offload */ +#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */ +#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */ +#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */ +#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */ +#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */ +#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */ +/*@}*/ + +/** @name transmit status register bit definitions + * @{ + */ +#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */ +#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */ +#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */ +#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted + mid frame */ +#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */ +#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */ +#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */ +#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */ + +#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_TXSR_URUN_MASK | \ + (u32)XEMACPS_TXSR_BUFEXH_MASK | \ + (u32)XEMACPS_TXSR_RXOVR_MASK | \ + (u32)XEMACPS_TXSR_FRAMERX_MASK | \ + (u32)XEMACPS_TXSR_USEDREAD_MASK) +/*@}*/ + +/** + * @name receive status register bit definitions + * @{ + */ +#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */ +#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */ +#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */ +#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */ + +#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_RXSR_RXOVR_MASK | \ + (u32)XEMACPS_RXSR_BUFFNA_MASK) +/*@}*/ + +/** + * @name Interrupt Q1 status register bit definitions + * @{ + */ +#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */ +#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */ + +#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \ + (u32)XEMACPS_INTQ1SR_TXERR_MASK) + +/*@}*/ + +/** + * @name interrupts bit definitions + * Bits definitions are same in XEMACPS_ISR_OFFSET, + * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET + * @{ + */ +#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */ +#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req + transmitted */ +#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */ +#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted + */ +#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */ +#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */ +#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */ +#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */ +#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */ +#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached + zero */ +#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */ +#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */ +#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */ +#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */ +#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or + no buffers*/ +#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */ +#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */ +#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */ +#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */ +#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */ +#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */ +#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */ + +#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \ + (u32)XEMACPS_IXR_RETRY_MASK | \ + (u32)XEMACPS_IXR_URUN_MASK) + + +#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \ + (u32)XEMACPS_IXR_RXUSED_MASK | \ + (u32)XEMACPS_IXR_RXOVR_MASK) + +/*@}*/ + +/** @name PHY Maintenance bit definitions + * @{ + */ +#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */ +#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */ +#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */ +#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */ +#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */ +#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */ +#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */ +#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */ +/*@}*/ + +/* Transmit buffer descriptor status words offset + * @{ + */ +#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */ +#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */ +#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */ + +/* + * @} + */ + +/* Transmit buffer descriptor status words bit positions. + * Transmit buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit address pointing to the location of + * the transmit data. + * The following register - word1, consists of various information to control + * the XEmacPs transmit process. After transmit, this is updated with status + * information, whether the frame was transmitted OK or why it had failed. + * @{ + */ +#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */ +#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */ +#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */ +#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */ +#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */ +#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */ +#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */ +#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */ +#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */ +/* + * @} + */ + +/* Receive buffer descriptor status words bit positions. + * Receive buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit word aligned address pointing to the + * address of the buffer. The lower two bits make up the wrap bit indicating + * the last descriptor and the ownership bit to indicate it has been used by + * the XEmacPs. + * The following register - word1, contains status information regarding why + * the frame was received (the filter match condition) as well as other + * useful info. + * @{ + */ +#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */ +#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */ +#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */ +#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */ +#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address + matched */ +#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */ +#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */ +#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */ +#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */ +#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */ +#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */ +#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */ +#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */ +#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */ +#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */ + +#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */ +#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */ +#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */ +/* + * @} + */ + +/* + * Define appropriate I/O access method to memory mapped I/O or other + * interface if necessary. + */ + +#define XEmacPs_In32 Xil_In32 +#define XEmacPs_Out32 Xil_Out32 + + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ + XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ + XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the emacps interface + */ +void XEmacPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus + } +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv.h new file mode 100644 index 0000000..3d97beb --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+*
    +* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv_standalone.h new file mode 100644 index 0000000..f186018 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xenv_standalone.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
    +* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef s32 XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + *

    + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops.h new file mode 100644 index 0000000..e778f9c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops.h @@ -0,0 +1,276 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops.h +* @addtogroup gpiops_v3_3 +* @{ +* @details +* +* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO +* Controller. +* +* The GPIO Controller supports the following features: +* - 4 banks +* - Masked writes (There are no masked reads) +* - Bypass mode +* - Configurable Interrupts (Level/Edge) +* +* This driver is intended to be RTOS and processor independent. Any needs for +* dynamic memory management, threads or thread mutual exclusion, virtual +* memory, or cache control must be satisfied by the layer above this driver. + +* This driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the GPIO. +* +* Interrupts +* +* The driver provides interrupt management functions and an interrupt handler. +* Users of this driver need to provide callback functions. An interrupt handler +* example is available with the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XGpioPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*       ms   04/05/17 Added tabspace for return statements in functions of
+*                     gpiops examples for proper documentation while
+*                     generating doxygen.
+* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
+*                     for zcu102 and zc702 boards in polled and interrupt
+*                     example, configured Interrupt pin to input pin for
+*                     proper functioning of interrupt example.
+*
    +* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ +/*@}*/ + +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ +#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */ + +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ +#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ +#endif + +#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a + * Zynq Ultrascale+ MP GPIO device + */ +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the + * Zynq Ultrascale+ MP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ + u32 Platform; /**< Platform data */ + u32 MaxPinNum; /**< Max pins in the GPIO device */ + u8 MaxBanks; /**< Max banks in a GPIO device */ +} XGpioPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* Functions in xgpiops.c */ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* Bank APIs in xgpiops.c */ +u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); +u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); + +/* Pin APIs in xgpiops.c */ +u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data); +void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction); +u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); +u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin); + +/* Diagnostic functions in xgpiops_selftest.c */ +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); + +/* Functions in xgpiops_intr.c */ +/* Bank APIs in xgpiops_intr.c */ +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer); +void XGpioPs_IntrHandler(XGpioPs *InstancePtr); + +/* Pin APIs in xgpiops_intr.c */ +void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin); + +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin); + +/* Functions in xgpiops_sinit.c */ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops_hw.h new file mode 100644 index 0000000..ff01906 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xgpiops_hw.h @@ -0,0 +1,164 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* @addtogroup gpiops_v3_3 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+*
    +* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */ +/* @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */ +/* @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 + +/** @name Interrupt type reset values for each bank + * @{ + */ +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU +#else +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU +#endif + +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */ +#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(u32 BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h new file mode 100644 index 0000000..add4124 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_assert.h @@ -0,0 +1,195 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* @addtogroup common_assert_apis Assert APIs and Macros +* +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+*
    +* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; +extern void Xil_Assert(const char8 *File, s32 Line); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to +* continue. +* +* @param Expression: expression to be evaluated. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accomodate tests so that asserts which fail allow execution +* to continue. +* +* @param Expression: expression to be evaluated. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache.h new file mode 100644 index 0000000..b6614d5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+*
    +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __GNUC__ + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#elif defined (__ICCARM__) + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_l.h new file mode 100644 index 0000000..fa92c6b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_l.h @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_l.h +* +* Contains L1 and L2 specific functions for the ARM cache functionality +* used by xcache.c. This functionality is being made available here for +* more sophisticated users. +* +* @addtogroup a9_cache_apis +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+*
    +* +******************************************************************************/ +#ifndef XIL_CACHE_MACH_H +#define XIL_CACHE_MACH_H + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_DCacheInvalidateLine(u32 adr); +void Xil_DCacheFlushLine(u32 adr); +void Xil_DCacheStoreLine(u32 adr); +void Xil_ICacheInvalidateLine(u32 adr); + +void Xil_L1DCacheEnable(void); +void Xil_L1DCacheDisable(void); +void Xil_L1DCacheInvalidate(void); +void Xil_L1DCacheInvalidateLine(u32 adr); +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len); +void Xil_L1DCacheFlush(void); +void Xil_L1DCacheFlushLine(u32 adr); +void Xil_L1DCacheFlushRange(u32 adr, u32 len); +void Xil_L1DCacheStoreLine(u32 adr); + +void Xil_L1ICacheEnable(void); +void Xil_L1ICacheDisable(void); +void Xil_L1ICacheInvalidate(void); +void Xil_L1ICacheInvalidateLine(u32 adr); +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len); + +void Xil_L2CacheEnable(void); +void Xil_L2CacheDisable(void); +void Xil_L2CacheInvalidate(void); +void Xil_L2CacheInvalidateLine(u32 adr); +void Xil_L2CacheInvalidateRange(u32 adr, u32 len); +void Xil_L2CacheFlush(void); +void Xil_L2CacheFlushLine(u32 adr); +void Xil_L2CacheFlushRange(u32 adr, u32 len); +void Xil_L2CacheStoreLine(u32 adr); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h new file mode 100644 index 0000000..6e8cfa7 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_errata.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_errata.h new file mode 100644 index 0000000..800fcd5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_errata.h @@ -0,0 +1,127 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support +* @{ +* Various ARM errata are handled in the standalone BSP. The implementation for +* errata handling follows ARM guidelines and is based on the open source Linux +* support for these errata. +* +* @note +* The errata handling is enabled by default. To disable handling of all the +* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To +* disable errata on a per-erratum basis, un-define relevant macros in +* xil_errata.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+*
    +* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +/** + * @name errata_definitions + * + * The errata conditions handled in the standalone BSP are listed below + * @{ + */ + +#define ENABLE_ARM_ERRATA 1 + +#ifdef ENABLE_ARM_ERRATA + +/** + * Errata No: 742230 + * Description: DMB operation may be faulty + */ +#define CONFIG_ARM_ERRATA_742230 1 + +/** + * Errata No: 743622 + * Description: Faulty hazard checking in the Store Buffer may lead + * to data corruption. + */ +#define CONFIG_ARM_ERRATA_743622 1 + +/** + * Errata No: 775420 + * Description: A data cache maintenance operation which aborts, + * might lead to deadlock + */ +#define CONFIG_ARM_ERRATA_775420 1 + +/** + * Errata No: 794073 + * Description: Speculative instruction fetches with MMU disabled + * might not comply with architectural requirements + */ +#define CONFIG_ARM_ERRATA_794073 1 + + +/** PL310 L2 Cache Errata */ + +/** + * Errata No: 588369 + * Description: Clean & Invalidate maintenance operations do not + * invalidate clean lines + */ +#define CONFIG_PL310_ERRATA_588369 1 + +/** + * Errata No: 727915 + * Description: Background Clean and Invalidate by Way operation + * can cause data corruption + */ +#define CONFIG_PL310_ERRATA_727915 1 + +/** + * Errata No: 753970 + * Description: Cache sync operation may be faulty + */ +#define CONFIG_PL310_ERRATA_753970 1 +/*@}*/ +#endif /* ENABLE_ARM_ERRATA */ + +#endif /* XIL_ERRATA_H */ +/** +* @} End of "addtogroup a9_errata". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h new file mode 100644 index 0000000..ad48222 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_exception.h @@ -0,0 +1,256 @@ +/****************************************************************************** +* +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+*
    +* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if !defined (__aarch64__) && !defined (ARMA53_32) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_hal.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_hal.h new file mode 100644 index 0000000..d4434d0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_hal.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h new file mode 100644 index 0000000..9c5aa43 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_io.h @@ -0,0 +1,345 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+*
    +******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +# else +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +# endif +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +# define INST_SYNC +# define DATA_SYNC +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +# else +# define Xil_In16BE Xil_In16 +# define Xil_In32BE Xil_In32 +# define Xil_Out16BE Xil_Out16 +# define Xil_Out32BE Xil_Out32 +# define Xil_Htons(Data) (Data) +# define Xil_Htonl(Data) (Data) +# define Xil_Ntohs(Data) (Data) +# define Xil_Ntohl(Data) (Data) +#endif +#else +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +#endif + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#else +static INLINE u16 Xil_In16LE(UINTPTR Addr) +#endif +#else +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#endif +{ + u16 value = Xil_In16(Addr); + return Xil_EndianSwap16(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#else +static INLINE u32 Xil_In32LE(UINTPTR Addr) +#endif +#else +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#endif +{ + u32 value = Xil_In32(Addr); + return Xil_EndianSwap32(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#else +static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) +#endif +#else +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#endif +{ + Value = Xil_EndianSwap16(Value); + Xil_Out16(Addr, Value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#else +static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) +#endif +#else +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#endif +{ + Value = Xil_EndianSwap32(Value); + Xil_Out32(Addr, Value); +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_macroback.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_macroback.h new file mode 100644 index 0000000..ebafde8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_macroback.h @@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mem.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mem.h new file mode 100644 index 0000000..a2d5e66 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mem.h @@ -0,0 +1,59 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.h +* +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations +* +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+*
    +* +*****************************************************************************/ + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); +/** +* @} End of "addtogroup common_mem_operation_api". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h new file mode 100644 index 0000000..c228c98 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register defintions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +* +* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ +#define XIL_MISC_RESET_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) +/**< SLCR USB reset control address register */ +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ +/**< SLCR GEM reset control address register */ +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) +/**< SLCR SMC reset control address register */ +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0DU + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x00000001U +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(void); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(void); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(void); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(void); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(void); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mmu.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mmu.h new file mode 100644 index 0000000..dd14b63 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_mmu.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions +* +* MMU functions equip users to enable MMU, disable MMU and modify default +* memory attributes of MMU table as per the need. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+*
    +* +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */ +#define STRONG_ORDERED 0xC02 /* Strongly ordered */ +#define DEVICE_MEMORY 0xC06 /* Device memory */ +#define RESERVED 0x0 /* reserved memory */ + +/* Normal write-through cacheable shareable */ +#define NORM_WT_CACHE 0x16DEA + +/* Normal write back cacheable shareable */ +#define NORM_WB_CACHE 0x15DE6 + +/* shareability attribute */ +#define SHAREABLE (0x1 << 16) +#define NON_SHAREABLE (~(0x1 << 16)) + +/* Execution type */ +#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMMU(void); +void Xil_DisableMMU(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ +/** +* @} End of "addtogroup a9_mmu_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h new file mode 100644 index 0000000..2be5c57 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_printf.h @@ -0,0 +1,44 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testcache.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testcache.h new file mode 100644 index 0000000..c35e9a4 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testcache.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* @addtogroup common_test_utils +*

    Cache test

    +* The xil_testcache.h file contains utility functions to test cache. +* +* @{ +* 
    +* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testio.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testio.h new file mode 100644 index 0000000..ad68ead --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testio.h @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testio.h +* +* @addtogroup common_test_utils Test Utilities +*

    I/O test

    +* The xil_testio.h file contains utility functions to test endian related memory +* IO functions. +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testmem.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testmem.h new file mode 100644 index 0000000..c204728 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_testmem.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* @addtogroup common_test_utils +* +*

    Memory test

    +* +* The xil_testmem.h file contains utility functions to test memory. +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* Following list describes the supported memory tests: +* +* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests. +* +* - XIL_TESTMEM_INCREMENT: This test +* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the +* test value for memory. +* +* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test +* uses a walking '1' as the test value for memory. +* @code +* location 1 = 0x00000001 +* location 2 = 0x00000002 +* ... +* @endcode +* +* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test. +* This test uses the inverse value of the walking ones test +* as the test value for memory. +* @code +* location 1 = 0xFFFFFFFE +* location 2 = 0xFFFFFFFD +* ... +*@endcode +* +* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test. +* This test uses the inverse of the address of the location under test +* as the test value for memory. +* +* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test. +* This test uses the provided patters as the test value for memory. +* If zero is provided as the pattern the test uses '0xDEADBEEF". +* +* @warning +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h new file mode 100644 index 0000000..8143aff --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xil_types.h @@ -0,0 +1,209 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+*
    +* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include +#include + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) + +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc.h new file mode 100644 index 0000000..735e26d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc.h @@ -0,0 +1,172 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xl2cc.h +* +* This file contains the address definitions for the PL310 Level-2 Cache +* Controller. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XL2CC_H_ +#define _XL2CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* L2CC Register Offsets */ +#define XPS_L2CC_ID_OFFSET 0x0000U +#define XPS_L2CC_TYPE_OFFSET 0x0004U +#define XPS_L2CC_CNTRL_OFFSET 0x0100U +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU + +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U + +#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */ + +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */ + +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */ + +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */ + +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */ + +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */ + +/* XPS_L2CC_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */ + +/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */ + +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */ + /* Cache replacement policy, Parity enable, */ + /* Event monitor bus enable and Way Size (64 KB) */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */ + +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */ + +/* Interrupt bit masks */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */ + +/* Address filtering mask and enable bit */ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/ + +/* Debug control bits */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */ + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc_counter.h new file mode 100644 index 0000000..8d0a61f --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xl2cc_counter.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.h +* +* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions +* +* xl2cc_counter.h contains APIs for configuring and controlling the event +* counters in PL310 L2 cache controller. +* PL310 has two event counters which can be used to count variety of events +* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions +* for different configurations which can be used for the event counters to +* count a set of events. +* +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+*
    +* +******************************************************************************/ + +#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ +#define L2CCCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* + * The following constants define the event codes for the event counters. + */ +#define XL2CC_CO 0x1 +#define XL2CC_DRHIT 0x2 +#define XL2CC_DRREQ 0x3 +#define XL2CC_DWHIT 0x4 +#define XL2CC_DWREQ 0x5 +#define XL2CC_DWTREQ 0x6 +#define XL2CC_IRHIT 0x7 +#define XL2CC_IRREQ 0x8 +#define XL2CC_WA 0x9 +#define XL2CC_IPFALLOC 0xa +#define XL2CC_EPFHIT 0xb +#define XL2CC_EPFALLOC 0xc +#define XL2CC_SRRCVD 0xd +#define XL2CC_SRCONF 0xe +#define XL2CC_EPFRCVD 0xf + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +void XL2cc_EventCtrInit(s32 Event0, s32 Event1); +void XL2cc_EventCtrStart(void); +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* L2CCCOUNTER_H */ +/** +* @} End of "addtogroup l2_event_counter_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h new file mode 100644 index 0000000..b0fc131 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters.h @@ -0,0 +1,389 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0U + +/* Definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 + +/******************************************************************/ + + +/* Definitions for peripheral PS7_DDR_0 */ +#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF + + +/******************************************************************/ + +/* Definitions for driver DEVCFG */ +#define XPAR_XDCFG_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Definitions for driver DMAPS */ +#define XPAR_XDMAPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PS7_DMA_NS */ +#define XPAR_PS7_DMA_NS_DEVICE_ID 0 +#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 +#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF + + +/* Definitions for peripheral PS7_DMA_S */ +#define XPAR_PS7_DMA_S_DEVICE_ID 1 +#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 +#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DMA_NS */ +#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID +#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 +#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF + +/* Canonical definitions for peripheral PS7_DMA_S */ +#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID +#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 +#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 + + +/******************************************************************/ + +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 + + +/******************************************************************/ + + +/* Definitions for peripheral PS7_AFI_0 */ +#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 +#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF + + +/* Definitions for peripheral PS7_AFI_1 */ +#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 +#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF + + +/* Definitions for peripheral PS7_AFI_2 */ +#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 +#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF + + +/* Definitions for peripheral PS7_AFI_3 */ +#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 +#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF + + +/* Definitions for peripheral PS7_DDRC_0 */ +#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 +#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF + + +/* Definitions for peripheral PS7_GLOBALTIMER_0 */ +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF + + +/* Definitions for peripheral PS7_GPV_0 */ +#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 +#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF + + +/* Definitions for peripheral PS7_INTC_DIST_0 */ +#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 +#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF + + +/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF + + +/* Definitions for peripheral PS7_L2CACHEC_0 */ +#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_OCMC_0 */ +#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 +#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF + + +/* Definitions for peripheral PS7_PL310_0 */ +#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_PMU_0 */ +#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 +#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF +#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 +#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF + + +/* Definitions for peripheral PS7_QSPI_LINEAR_0 */ +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF + + +/* Definitions for peripheral PS7_RAM_0 */ +#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Definitions for peripheral PS7_RAM_1 */ +#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PS7_SCUC_0 */ +#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 +#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC + + +/* Definitions for peripheral PS7_SLCR_0 */ +#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 +#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_GPIO_0 */ +#define XPAR_PS7_GPIO_0_DEVICE_ID 0 +#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 +#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Definitions for driver QSPIPS */ +#define XPAR_XQSPIPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_QSPI_0 */ +#define XPAR_PS7_QSPI_0_DEVICE_ID 0 +#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 +#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF +#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_QSPI_0 */ +#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 +#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF +#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Definitions for driver SCUTIMER */ +#define XPAR_XSCUTIMER_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 +#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID +#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Definitions for driver SCUWDT */ +#define XPAR_XSCUWDT_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 +#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID +#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SD_0 */ +#define XPAR_PS7_SD_0_DEVICE_ID 0 +#define XPAR_PS7_SD_0_BASEADDR 0xE0100000 +#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF +#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 100000000 +#define XPAR_PS7_SD_0_HAS_CD 1 +#define XPAR_PS7_SD_0_HAS_WP 0 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 + + +/******************************************************************/ + +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xE0100000 +#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 100000000 +#define XPAR_XSDPS_0_HAS_CD 1 +#define XPAR_XSDPS_0_HAS_WP 0 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_UART_1 */ +#define XPAR_PS7_UART_1_DEVICE_ID 0 +#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000 +#define XPAR_PS7_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_UART_1 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definitions for driver XADCPS */ +#define XPAR_XADCPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_XADC_0 */ +#define XPAR_PS7_XADC_0_DEVICE_ID 0 +#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 +#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_XADC_0 */ +#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID +#define XPAR_XADCPS_0_BASEADDR 0xF8007100 +#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +#endif /* end of protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h new file mode 100644 index 0000000..ea0d2bc --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xparameters_ps.h @@ -0,0 +1,333 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xE0000000U +#define XPS_UART1_BASEADDR 0xE0001000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U +#define XPS_I2C0_BASEADDR 0xE0004000U +#define XPS_I2C1_BASEADDR 0xE0005000U +#define XPS_SPI0_BASEADDR 0xE0006000U +#define XPS_SPI1_BASEADDR 0xE0007000U +#define XPS_CAN0_BASEADDR 0xE0008000U +#define XPS_CAN1_BASEADDR 0xE0009000U +#define XPS_GPIO_BASEADDR 0xE000A000U +#define XPS_GEM0_BASEADDR 0xE000B000U +#define XPS_GEM1_BASEADDR 0xE000C000U +#define XPS_QSPI_BASEADDR 0xE000D000U +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U +#define XPS_SDIO0_BASEADDR 0xE0100000U +#define XPS_SDIO1_BASEADDR 0xE0101000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_NAND_BASEADDR 0xE1000000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000U +#define XPS_TTC1_BASEADDR 0xF8002000U +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U +#define XPS_WDT_BASEADDR 0xF8005000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF8F00000U +#define XPS_L2CC_BASEADDR 0xF8F02000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_CORE_PARITY0_INT_ID 32U +#define XPS_CORE_PARITY1_INT_ID 33U +#define XPS_L2CC_INT_ID 34U +#define XPS_OCMINTR_INT_ID 35U +#define XPS_ECC_INT_ID 36U +#define XPS_PMU0_INT_ID 37U +#define XPS_PMU1_INT_ID 38U +#define XPS_SYSMON_INT_ID 39U +#define XPS_DVC_INT_ID 40U +#define XPS_WDT_INT_ID 41U +#define XPS_TTC0_0_INT_ID 42U +#define XPS_TTC0_1_INT_ID 43U +#define XPS_TTC0_2_INT_ID 44U +#define XPS_DMA0_ABORT_INT_ID 45U +#define XPS_DMA0_INT_ID 46U +#define XPS_DMA1_INT_ID 47U +#define XPS_DMA2_INT_ID 48U +#define XPS_DMA3_INT_ID 49U +#define XPS_SMC_INT_ID 50U +#define XPS_QSPI_INT_ID 51U +#define XPS_GPIO_INT_ID 52U +#define XPS_USB0_INT_ID 53U +#define XPS_GEM0_INT_ID 54U +#define XPS_GEM0_WAKE_INT_ID 55U +#define XPS_SDIO0_INT_ID 56U +#define XPS_I2C0_INT_ID 57U +#define XPS_SPI0_INT_ID 58U +#define XPS_UART0_INT_ID 59U +#define XPS_CAN0_INT_ID 60U +#define XPS_FPGA0_INT_ID 61U +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_TTC1_0_INT_ID 69U +#define XPS_TTC1_1_INT_ID 70U +#define XPS_TTC1_2_INT_ID 71U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_USB1_INT_ID 76U +#define XPS_GEM1_INT_ID 77U +#define XPS_GEM1_WAKE_INT_ID 78U +#define XPS_SDIO1_INT_ID 79U +#define XPS_I2C1_INT_ID 80U +#define XPS_SPI1_INT_ID 81U +#define XPS_UART1_INT_ID 82U +#define XPS_CAN1_INT_ID 83U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Private Peripheral Interrupts (PPI) */ +#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID + +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h new file mode 100644 index 0000000..0582222 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xplatform_info.h @@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* @addtogroup common_platform_info APIs to Get Platform Information +* +* The xplatform_info.h file contains definitions for various available Xilinx® +* platforms. Also, it contains prototype of APIs, which can be used to get the +* platform information. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+*
    +* +******************************************************************************/ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 + +#define XPLAT_INFO_MASK (0xF) +#define XPLAT_INFO_SHIFT (0xC) +#define XPS_VERSION_INFO_MASK (0xF) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) +u32 XGetPSVersion_Info(); +#endif + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpm_counter.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpm_counter.h new file mode 100644 index 0000000..45f0919 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpm_counter.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions +* +* Cortex A9 event counter functions can be utilized to configure and control +* the Cortex-A9 performance monitor events. +* +* Cortex-A9 performance monitor has six event counters which can be used to +* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines +* configurations XPM_CNTRCFGx which can be used to program the event counters +* to count a set of events. +* +* @note +* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is +* being used for time keeping. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+*
    +* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6U + +/* The following constants define the Cortex-A9 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00U + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03U + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04U + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05U + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06U + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07U + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09U + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0AU + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0BU + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0CU + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0DU + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10U + +/* + * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11U + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12U + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40U + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41U + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42U + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which also miss in all the other + * Cortex-A9 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50U + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which hit in another Cortex-A9 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-A9 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51U + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60U + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61U + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62U + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63U + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64U + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65U + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66U + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67U + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68U + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6EU + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70U + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71U + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72U + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73U + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74U + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80U + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83U + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85U + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86U + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8AU + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8BU + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90U + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91U + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92U + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93U + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0U + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1U + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2U + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3U + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4U + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5U + +/* + * The following constants define the configurations for Cortex-A9 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(s32 PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_event_counter_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h new file mode 100644 index 0000000..4ad9e5d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm.h @@ -0,0 +1,77 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a9_specific Cortex A9 Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexa9.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers, +* co-processor registers and Debug registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+*
    +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) + #include "xpseudo_asm_iccarm.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a9_specific". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h new file mode 100644 index 0000000..1b67263 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h @@ -0,0 +1,249 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+*
    +* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips.h new file mode 100644 index 0000000..139ce4d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips.h @@ -0,0 +1,799 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips.h +* @addtogroup qspips_v3_4 +* @{ +* @details +* +* This file contains the implementation of the XQspiPs driver. It supports only +* master mode. User documentation for the driver functions is contained in this +* file in the form of comment blocks at the front of each function. +* +* A QSPI device connects to an QSPI bus through a 4-wire serial interface. +* The QSPI bus is a full-duplex, synchronous bus that facilitates communication +* between one master and one slave. The device is always full-duplex, +* which means that for every byte sent, one is received, and vice-versa. +* The master controls the clock, so it can regulate when it wants to +* send or receive data. The slave is under control of the master, it must +* respond quickly since it has no control of the clock and must send/receive +* data as fast or as slow as the master does. +* +* Linear Mode +* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s +* functionality by adding a linear addressing scheme that allows the SPI flash +* memory subsystem to behave like a typical ROM device. The new feature hides +* the normal SPI protocol from a master reading from the SPI flash memory. The +* feature improves both the user friendliness and the overall read memory +* throughput over that of the current Quad-SPI Controller by lessening the +* amount of software overheads required and by the use of the faster AXI +* interface. +* +* Initialization & Configuration +* +* The XQspiPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find +* static configuration structure defined in xqspips_g.c. This is setup +* by the tools. For some operating systems the config structure will be +* initialized by the software and this call is not needed. +* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the provided virtual memory base address +* replaces the physical address present in the configuration structure. +* +* Multiple Masters +* +* More than one master can exist, but arbitration is the responsibility of +* the higher layer software. The device driver does not perform any type of +* arbitration. +* +* Modes of Operation +* +* There are four modes to perform a data transfer and the selection of a mode +* is based on Chip Select(CS) and Start. These two options individually, can +* be controlled either by software(Manual) or hardware(Auto). +* - Auto CS: Chip select is automatically asserted as soon as the first word +* is written into the TXFIFO and de asserted when the TXFIFO becomes +* empty +* - Manual CS: Software must assert and de assert CS. +* - Auto Start: Data transmission starts as soon as there is data in the +* TXFIFO and stalls when the TXFIFO is empty +* - Manual Start: Software must start data transmission at the beginning of +* the transaction or whenever the TXFIFO has become empty +* +* The preferred combination is Manual CS and Auto Start. +* In this combination, the software asserts CS before loading any data into +* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it +* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the +* data is available. If no further data, software disables CS. +* +* Risks/challenges of other combinations: +* - Manual CS and Manual Start: Manual Start bit should be set after each +* TXFIFO write otherwise there could be a race condition where the TXFIFO +* becomes empty before the new word is written. In that case the +* transmission stops. +* - Auto CS with Manual or Auto Start: It is very difficult for software to +* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. +* This results in a single transaction to be split into multiple pieces each +* with its own chip select. This will result in garbage data to be sent. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XQspiPs_InterruptHandler, to an interrupt system such that it will be +* called when an interrupt occurs. This function does not save and restore +* the processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Data Transmit Register/FIFO Underflow +* - Data Receive Register/FIFO Not Empty +* - Data Transmit Register/FIFO Overwater +* - Data Receive Register/FIFO Overrun +* +* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the +* QSPI device has transmitted the data available to transmit, and now its data +* register and FIFO is ready to accept more data. The driver uses this +* interrupt to indicate progress while sending data. The driver may have +* more data to send, in which case the data transmit register and FIFO is +* filled for subsequent transmission. When this interrupt arrives and all +* the data has been sent, the driver invokes the status callback with a +* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that +* all data has been sent. +* +* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, +* as slave, the QSPI device was required to transmit but there was no data +* available to transmit in the transmit register (or FIFO). This may not +* be an error if the master is not expecting data. But in the case where +* the master is expecting data, this serves as a notification of such a +* condition. The driver reports this condition to the upper layer +* software through the status handler. +* +* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI +* device received data and subsequently dropped the data because the data +* receive register and FIFO was full. The driver reports this condition to the +* upper layer software through the status handler. This likely indicates a +* problem with the higher layer protocol, or a problem with the slave +* performance. +* +* +* Polled Operation +* +* Transfer in polled mode is supported through a separate interface function +* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, +* this function blocks until all data has been sent/received. +* +* Device Busy +* +* Some operations are disallowed when the device is busy. The driver tracks +* whether a device is busy. The device is considered busy when a data transfer +* request is outstanding, and is considered not busy only when that transfer +* completes (or is aborted with a mode fault error). +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xqspips_g.c file or +* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry +* contains configuration information for an QSPI device, including the base +* address for the device. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied +* by the layer above this driver. +* +* NOTE: This driver was always tested with endianess set to little-endian. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/05/17 Modified Comment lines in functions of qspips
+*                    examples to recognize it as documentation block
+*                    and modified filename tag in
+*                    xqspips_dual_flash_stack_lqspi_example.c to include it in
+*                    doxygen examples.
+* 3.4   nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+*
    +* +******************************************************************************/ +#ifndef XQSPIPS_H /* prevent circular inclusions */ +#define XQSPIPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspips_hw.h" +#include + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options are supported to enable/disable certain features of + * an QSPI device. Each of the options is a bit mask, so more than one may be + * specified. + * + * + * The Active Low Clock option configures the device's clock polarity. + * Setting this option means the clock is active low and the SCK signal idles + * high. By default, the clock is active high and SCK idles low. + * + * The Clock Phase option configures the QSPI device for one of two + * transfer formats. A clock phase of 0, the default, means data is valid on + * the first SCK edge (rising or falling) after the slave select (SS) signal + * has been asserted. A clock phase of 1 means data is valid on the second SCK + * edge (rising or falling) after SS has been asserted. + * + * + * The QSPI Force Slave Select option is used to enable manual control of + * the slave select signal. + * 0: The SPI_SS signal is controlled by the QSPI controller during + * transfers. (Default) + * 1: The SPI_SS signal is forced active (driven low) regardless of any + * transfers in progress. + * + * NOTE: The driver will handle setting and clearing the Slave Select when + * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the + * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the + * processor cannot empty and refill the FIFOs before the TX FIFO is empty + * When the QSPI hardware is controlling the Slave Select signals, this + * will cause slave to be de-selected and terminate the transfer. + * + * The Manual Start option is used to enable manual control of + * the Start command to perform data transfer. + * 0: The Start command is controlled by the QSPI controller during + * transfers(Default). Data transmission starts as soon as there is data in + * the TXFIFO and stalls when the TXFIFO is empty + * 1: The Start command must be issued by software to perform data transfer. + * Bit 15 of Configuration register is used to issue Start command. This bit + * must be set whenever TXFIFO is filled with new data. + * + * NOTE: The driver will set the Manual Start Enable bit in Configuration + * Register, if Manual Start option is selected. Software will issue + * Manual Start command whenever TXFIFO is filled with data. When there is + * no further data, driver will clear the Manual Start Enable bit. + * + * @{ + */ +#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */ +#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */ +#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */ +#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */ +#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */ +#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */ +/*@}*/ + + +/** @name QSPI Clock Prescaler options + * The QSPI Clock Prescaler Configuration bits are used to program master mode + * bit rate. The bit rate can be programmed in divide-by-two decrements from + * pclk/2 to pclk/256. + * + * @{ + */ +#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */ + +/*@}*/ + + +/** @name Callback events + * + * These constants specify the handler events that are passed to + * a handler from the driver. These constants are not bit masks such that + * only one will be passed at a time to the handler. + * + * @{ + */ +#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */ +#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */ +#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because + RX FIFO full */ +/*@}*/ + +/** @name Flash commands + * + * The following constants define most of the commands supported by flash + * devices. Users can add more commands supported by the flash devices + * + * @{ + */ +#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */ +#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */ +#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */ +#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */ +#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ +#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */ +#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ +#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */ +#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */ +#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */ +#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ +#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ +#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ +#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */ +#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */ +#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */ +#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */ +/* Extende Address Register Write - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5 +/* Extende Address Register Read - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8 +#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4 +#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70 +#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50 +#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */ +#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */ + +/*@}*/ + +/** @name Instruction size + * + * The following constants define numbers 1 to 4. + * Used to identify whether TXD0,1,2 or 3 is to be used. + * + * @{ + */ +#define XQSPIPS_SIZE_ONE 1 +#define XQSPIPS_SIZE_TWO 2 +#define XQSPIPS_SIZE_THREE 3 +#define XQSPIPS_SIZE_FOUR 4 + +/*@}*/ + +/** @name ConnectionMode + * + * The following constants are the possible values of ConnectionMode in + * Config structure. + * + * @{ + */ +#define XQSPIPS_CONNECTION_MODE_SINGLE 0 +#define XQSPIPS_CONNECTION_MODE_STACKED 1 +#define XQSPIPS_CONNECTION_MODE_PARALLEL 2 + +/*@}*/ + +/** @name FIFO threshold value + * + * This is the Rx FIFO threshold (in words) that was found to be most + * optimal in terms of performance + * + * @{ + */ +#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32 + +/*@}*/ + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPI device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPs_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, + unsigned ByteCount); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ +} XQspiPs_Config; + +/** + * The XQspiPs driver instance data. The user is required to allocate a + * variable of this type for every QSPI device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + int RequestedBytes; /**< Number of bytes to transfer (state) */ + int RemainingBytes; /**< Number of bytes left to transfer(state) */ + u32 IsBusy; /**< A transfer is in progress (state) */ + XQspiPs_StatusHandler StatusHandler; + void *StatusRef; /**< Callback reference for status handler */ + u32 ShiftReadData; /**< Flag to indicate whether the data + * read from the Rx FIFO needs to be shifted + * in cases where the data is less than 4 + * bytes + */ +} XQspiPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Start Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualStart(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualChipSelect(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* Set the contents of the slave idle count register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are +* 0-255. +* +* @return None +* +* @note +* C-Style signature: +* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_* +* constants defined in xqspips_hw.h to interpret the bit-mask returned. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return An 8-bit value representing Slave Idle Count. +* +* @note C-Style signature: +* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetSlaveIdle(InstancePtr) \ + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the transmit FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_TXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the transmit FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Tx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetTXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the receive FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_RXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the receive FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Rx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetRXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Enable the device and uninhibit master transactions. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Enable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Enable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ + XQSPIPS_ER_ENABLE_MASK) + +/****************************************************************************/ +/** +* +* Disable the device. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Disable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Disable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) + +/****************************************************************************/ +/** +* +* Set the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written to the Linear QSPI +* configuration register. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, +* u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 32-bit value representing the contents of the LQSPI Config +* register. +* +* @note C-Style signature: +* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetLqspiConfigReg(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization function, implemented in xqspips_sinit.c + */ +XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); + +/* + * Functions implemented in xqspips.c + */ +int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config, + u32 EffectiveAddr); +void XQspiPs_Reset(XQspiPs *InstancePtr); +void XQspiPs_Abort(XQspiPs *InstancePtr); + +s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, + u32 ByteCount); +s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, + u8 *RecvBufPtr, u32 ByteCount); +int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, + u32 Address, unsigned ByteCount); + +int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); + +void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, + XQspiPs_StatusHandler FuncPtr); +void XQspiPs_InterruptHandler(void *InstancePtr); + +/* + * Functions for selftest, in xqspips_selftest.c + */ +int XQspiPs_SelfTest(XQspiPs *InstancePtr); + +/* + * Functions for options, in xqspips_options.c + */ +s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options); +u32 XQspiPs_GetOptions(XQspiPs *InstancePtr); + +s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); +u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); + +int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, + u8 DelayAfter, u8 DelayInit); +void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, + u8 *DelayAfter, u8 *DelayInit); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips_hw.h new file mode 100644 index 0000000..96c867a --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xqspips_hw.h @@ -0,0 +1,423 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips_hw.h +* @addtogroup qspips_v3_4 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xqspips.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+*
    +* +******************************************************************************/ +#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ +#define XQSPIPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an QSPI device. + * @{ + */ +#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ +#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ +#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ +#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ +#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ +#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ +#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ +#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ +#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ +#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ +#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ +#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ +#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ +#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ +#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ +#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ +#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ +#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ +#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ +#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ + +/* @} */ + +/** @name Configuration Register + * + * This register contains various control bits that + * affect the operation of the QSPI device. Read/Write. + * @{ + */ + +#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ +#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ +#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ +#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start + Enable */ +#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ +#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ +#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ +#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be + transferred */ +#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ +#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ +#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ + +#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ +#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ + +#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ + +#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ + +#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */ + +/* Deselect the Slave select line and set the transfer size to 32 at reset */ +#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \ + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK +#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \ + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK +/* @} */ + + +/** @name QSPI Interrupt Registers + * + * QSPI Status Register + * + * This register holds the interrupt status flags for an QSPI device. Some + * of the flags are level triggered, which means that they are set as long + * as the interrupt condition exists. Other flags are edge triggered, + * which means they are set once the interrupt condition occurs and remain + * set until they are cleared by software. The interrupts are cleared by + * writing a '1' to the interrupt bit position in the Status Register. + * Read/Write. + * + * QSPI Interrupt Enable Register + * + * This register is used to enable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Disable Register + * + * This register is used to disable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Mask Register + * + * This register shows the enabled/disabled interrupts of an QSPI device. + * Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Channel Interrupt Status Register + * @{ + */ + +#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ +#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ +#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ +#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ +#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ +#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ +#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts + mask */ +#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which + need write to clear */ +#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ +#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ +/* @} */ + + +/** @name Enable Register + * + * This register is used to enable or disable an QSPI device. + * Read/Write + * @{ + */ +#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ +/* @} */ + + +/** @name Delay Register + * + * This register is used to program timing delays in + * slave mode. Read/Write + * @{ + */ +#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select + between two words mask */ +#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select + between two words shift */ +#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers + mask */ +#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ +#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ +#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ +#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ +/* @} */ + +/** @name Slave Idle Count Registers + * + * This register defines the number of pclk cycles the slave waits for a the + * QSPI clock to become stable in quiescent state before it can detect the start + * of the next transfer in CPHA = 1 mode. + * Read/Write + * + * @{ + */ +#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ +/* @} */ + + +/** @name Transmit FIFO Watermark Register + * + * This register defines the watermark setting for the Transmit FIFO. + * + * @{ + */ +#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ +#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark + * register reset value */ + +/* @} */ + +/** @name Receive FIFO Watermark Register + * + * This register defines the watermark setting for the Receive FIFO. + * + * @{ + */ +#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ +#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark + * register reset value */ + +/* @} */ + +/** @name FIFO Depth + * + * This macro provides the depth of transmit FIFO and receive FIFO. + * + * @{ + */ +#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ +/* @} */ + + +/** @name Linear QSPI Configuration Register + * + * This register contains various control bits that + * affect the operation of the Linear QSPI controller. Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ +#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ +#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */ +#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ +#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ +#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ +#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes + between addr and return + read data */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ +/* @} */ + +/** @name Linear QSPI Status Register + * + * This register contains various status bits of the Linear QSPI controller. + * Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error + received */ +#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command + received */ +/* @} */ + + +/** @name Loopback Delay Adjust Register + * + * This register contains various bit masks of Loopback Delay Adjust Register. + * + * @{ + */ + +#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ + +/* @} */ + + +/** @name SLCR Register + * + * Register offsets from SLCR base address. + * + * @{ + */ + +#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */ +#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */ +#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */ + +/* @} */ + + +/** @name SLCR Register + * + * Bit Masks of above SLCR Registers . + * + * @{ + */ + +#ifndef XPAR_XSLCR_0_BASEADDR +#define XPAR_XSLCR_0_BASEADDR 0xF8000000 +#endif +#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/ +#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */ + +/* @} */ + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPs_In32 Xil_In32 +#define XQspiPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ + XQspiPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/************************** Function Prototypes ******************************/ + +/* + * Functions implemented in xqspips_hw.c + */ +void XQspiPs_ResetHw(u32 BaseAddress); +void XQspiPs_LinearInit(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h new file mode 100644 index 0000000..dc9a4eb --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h @@ -0,0 +1,591 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+*
    +* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h new file mode 100644 index 0000000..bf6cf7b --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic.h @@ -0,0 +1,366 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic.h +* @addtogroup scugic_v3_8 +* @{ +* @details +* +* The generic interrupt controller driver component. +* +* The interrupt controller driver uses the idea of priority for the various +* handlers. Priority is an integer within the range of 1 and 31 inclusive with +* default of 1 being the highest priority interrupt source. The priorities +* of the various sources can be dynamically altered as needed through +* hardware configuration. +* +* The generic interrupt controller supports the following +* features: +* +* - specific individual interrupt enabling/disabling +* - specific individual interrupt acknowledging +* - attaching specific callback function to handle interrupt source +* - assigning desired priority to interrupt source if default is not +* acceptable. +* +* Details about connecting the interrupt handler of the driver are contained +* in the source file specific to interrupt processing, xscugic_intr.c. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* Interrupt Vector Tables +* +* The device ID of the interrupt controller device is used by the driver as a +* direct index into the configuration data table. The user should populate the +* vector table with handlers and callbacks at run-time using the +* XScuGic_Connect() and XScuGic_Disconnect() functions. +* +* Each vector table entry corresponds to a device that can generate an +* interrupt. Each entry contains an interrupt handler function and an +* argument to be passed to the handler when an interrupt occurs. The +* user must use XScuGic_Connect() when the interrupt handler takes an +* argument other than the base address. +* +* Nested Interrupts Processing +* +* Nested interrupts are not supported by this driver. +* +* NOTE: +* The generic interrupt controller is not a part of the snoop control unit +* as indicated by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
+*                     definitions of scugic in xparameters.h
+* 3.8   mus  07/05/17 Updated scugic.tcl to add support for intrrupts connected
+*                     through util_reduced_vector IP(OR gate)
+*       mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+*                     the HandlerTable in XScuGic_ConfigTable to 0, it removes
+*                     the compilation warning in xscugic_g.c. Fix for CR#978736.
+*       mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
+*                     definitions for pl to ps interrupts.Fix for CR#980534
+*
+*
    +* +******************************************************************************/ + +#ifndef XSCUGIC_H /* prevent circular inclusions */ +#define XSCUGIC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_io.h" +#include "xscugic_hw.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +#define EFUSE_STATUS_OFFSET 0x10 +#define EFUSE_STATUS_CPU_MASK 0x80 + +#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) +#define ARMA9 +#endif +/**************************** Type Definitions *******************************/ + +/* The following data type defines each entry in an interrupt vector table. + * The callback reference is the base address of the interrupting device + * for the low level driver and an instance pointer for the high level driver. + */ +typedef struct +{ + Xil_InterruptHandler Handler; + void *CallBackRef; +} XScuGic_VectorTableEntry; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct +{ + u16 DeviceId; /**< Unique ID of device */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ + u32 DistBaseAddress; /**< Distributor Register base address */ + XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< + Vector table of interrupt handlers */ +} XScuGic_Config; + +/** + * The XScuGic driver instance data. The user is required to allocate a + * variable of this type for every intc device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + XScuGic_Config *Config; /**< Configuration table entry */ + u32 IsReady; /**< Device is initialized and ready */ + u32 UnhandledInterrupts; /**< Intc Statistics */ +} XScuGic; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ + (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) + +/************************** Function Prototypes ******************************/ + +/* + * Required functions in xscugic.c + */ + +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); + +void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); +void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); + +s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); + +void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); +/* + * Initialization functions in xscugic_sinit.c + */ +XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); + +/* + * Interrupt functions in xscugic_intr.c + */ +void XScuGic_InterruptHandler(XScuGic *InstancePtr); + +/* + * Self-test functions in xscugic_selftest.c + */ +s32 XScuGic_SelfTest(XScuGic *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h new file mode 100644 index 0000000..8d1b04c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscugic_hw.h @@ -0,0 +1,642 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic_hw.h +* @addtogroup scugic_v3_8 +* @{ +* +* This header file contains identifiers and HW access functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The driver functions/APIs are defined in xscugic.h. +* +* This GIC device has two parts, a distributor and CPU interface(s). Each part +* has separate register definition sections. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+*
    +* +******************************************************************************/ + +#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ +#define XSCUGIC_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +/* + * The maximum number of interrupts supported by the hardware. + */ +#ifdef __ARM_NEON__ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ +#else +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#endif + +/* + * The maximum priority value that can be used in the GIC. + */ +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ +#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable + Register */ +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID + Register */ +#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security + Register */ +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set + Register */ +#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target + Register 0x800-0x8FB */ +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register + 0xd04-0xd7C */ +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration + Register */ +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered + Interrupt Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an + INT_ID */ +#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianess + * of the GIC to be set. + * @{ + */ +#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issueing of software interrupts. + * @{ + */ +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control + Register */ +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure + Binary Point Register */ + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + +/** @name Priority Mask Register + * Priority Mask register definitions + * The CPU interface does not send interrupt if the level of the interrupt is + * lower than the level of the register. + * @{ + */ +/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */ +/* @} */ + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ +/* @} */ + +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interupt + */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */ +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + + +/****************************************************************************/ +/** +* +* Write the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data)))) + + +/****************************************************************************/ +/** +* +* Enable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* @return None. +* +* @note C-style signature: +* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + +/****************************************************************************/ +/** +* +* Disable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* +* @return None. +* +* @note C-style signature: +* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + + +/************************** Function Prototypes ******************************/ + +void XScuGic_DeviceInterruptHandler(void *DeviceId); +s32 XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 *Priority, u8 *Trigger); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h new file mode 100644 index 0000000..ea4ba79 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer.h +* @addtogroup scutimer_v2_1 +* @{ +* @details +* +* The timer driver supports the Cortex A9 private timer. +* +* The timer driver supports the following features: +* - Normal mode and Auto reload mode +* - Interrupts (Interrupt handler is not provided in this driver. Application +* has to register it's own handler) +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Timer. +* +* XScuTimer_CfgInitialize() API is used to initialize the Timer. The +* user needs to first call the XScuTimer_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuTimer_CfgInitialize() API. +* +* Interrupts +* +* The Timer hardware supports interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuTimer driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* NOTE: +* The timer is not a part of the snoop control unit as indicated by the +* prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
    +* +******************************************************************************/ +#ifndef XSCUTIMER_H /* prevent circular inclusions */ +#define XSCUTIMER_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscutimer_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuTimer_Config; + +/** + * The XScuTimer driver instance data. The user is required to allocate a + * variable of this type for every timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuTimer_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device timer is running */ +} XScuTimer; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Check if the timer has expired. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return +* - TRUE if the timer has expired. +* - FALSE if the timer has not expired. +* +* @note C-style signature: +* int XScuTimer_IsExpired(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_IsExpired(InstancePtr) \ + ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the timer. This macro will read the timer load register +* and writes the same value to load register to update the counter register. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_RestartTimer(InstancePtr) \ + XScuTimer_LoadTimer((InstancePtr), \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_LoadTimer(InstancePtr, Value) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. It can be called at any +* time. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetCounterValue(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + +/****************************************************************************/ +/** +* +* Disable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + +/****************************************************************************/ +/** +* +* Enable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + +/****************************************************************************/ +/** +* +* Disable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetInterruptStatus(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_ClearInterruptStatus(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscutimer_sinit.c + */ +XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscutimer_selftest.c + */ +s32 XScuTimer_SelfTest(XScuTimer *InstancePtr); + +/* + * Interface functions in xscutimer.c + */ +s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, + XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); +void XScuTimer_Start(XScuTimer *InstancePtr); +void XScuTimer_Stop(XScuTimer *InstancePtr); +void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); +u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h new file mode 100644 index 0000000..ac7b429 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscutimer_hw.h @@ -0,0 +1,287 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer_hw.h +* @addtogroup scutimer_v2_1 +* @{ +* +* This file contains the hardware interface to the Timer. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ +#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ +#define XSCUTIMER_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */ +#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */ +#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */ +#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt + Status Register */ +/* @} */ + +/** @name Timer Control register + * This register bits control the prescaler, Intr enable, + * auto-reload and timer enable. + * @{ + */ + +#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U +#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */ +#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */ +#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Timer counter register has reached zero. + * @{ + */ + +#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetLoadReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: +* u32 XScuTimer_GetLoadReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetLoadReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetCounterReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetCounterReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetControlReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: + u32 XScuTimer_GetControlReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetControlReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetIntrReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetIntrReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetIntrReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) + +/****************************************************************************/ +/** +* +* Read from the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt.h new file mode 100644 index 0000000..372bbc3 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt.h @@ -0,0 +1,383 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt.h +* @addtogroup scuwdt_v2_1 +* @{ +* @details +* +* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private +* watchdog timer hardware. +* +* The XScuWdt driver supports the following features: +* - Watchdog mode +* - Timer mode +* - Auto reload (timer mode only) +* +* The watchdog counter register is a down counter and starts decrementing when +* the watchdog is started. +* In watchdog mode, when the counter reaches 0, the Reset flag is set in the +* Reset status register and the WDRESETREQ pin is asserted, causing a system +* reset. The Reset flag is not reset by normal processor reset and is cleared +* when written with a value of 1. This enables the user to differentiate a +* normal reset and a reset caused by watchdog time-out. The user needs to call +* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. +* +* The IsWdtExpired function can be used to check if the watchdog was the cause +* of the last reset. In this situation, call Initialize then call IsWdtExpired. +* If the result is true, watchdog timeout caused the last system reset. The +* application then needs to clear the Reset flag. +* +* In timer mode, when the counter reaches 0, the Event flag is set in the +* Interrupt status register and if interrupts are enabled, interrupt ID 30 is +* set as pending in the interrupt distributor. The IsTimerExpired function +* is used to check if the watchdog counter has decremented to 0 in timer mode. +* If auto-reload mode is enabled, the Counter register is automatically reloaded +* from the Load register. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Watchdog Timer. +* +* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The +* user needs to first call the XScuWdt_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuWdt_CfgInitialize() API. +* +* Interrupts +* +* The SCU Watchdog Timer supports interrupts in Timer mode. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuWdt driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* NOTE: +* The watchdog timer is not a part of the snoop control unit as indicated +* by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
    +* +******************************************************************************/ +#ifndef XSCUWDT_H /* prevent circular inclusions */ +#define XSCUWDT_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscuwdt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuWdt_Config; + +/** + * The XScuWdt driver instance data. The user is required to allocate a + * variable of this type for every watchdog/timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuWdt_Config Config;/**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device watchdog timer is running */ +} XScuWdt; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog has timed-out and the last +* reset was caused by the watchdog reset. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsWdtExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_RST_STS_OFFSET) & \ + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog counter has reached 0 in timer +* mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsTimerExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_ISR_OFFSET) & \ + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the watchdog timer. This macro will read the watchdog load register +* and write the same value to load register to update the counter register. +* An application needs to call this function periodically to keep the watchdog +* from asserting the WDRESETREQ reset request output pin. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_RestartWdt(InstancePtr) \ + XScuWdt_LoadWdt((InstancePtr), \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET))) + +/****************************************************************************/ +/** +* +* Write to the watchdog timer load register. This will also update the +* watchdog counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param Value is the value to be written to the Watchdog Load register. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuWdt_LoadWdt(InstancePtr, Value) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the +* Watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetWdMode(InstancePtr) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) | \ + (XSCUWDT_CONTROL_WD_MODE_MASK))) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 +* successively to the Watchdog Disable Register. +* The software must write 0x12345678 and 0x87654321 successively to the +* Watchdog Disable Register so that the watchdog mode bit in the Watchdog +* Control Register is set to zero. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetTimerMode(InstancePtr) \ +{ \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ +} + +/****************************************************************************/ +/** +* +* Get the contents of the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return Contents of the watchdog control register. +* +* @note C-style signature: + u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_GetControlReg(InstancePtr) \ + XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param ControlReg is the value to be written to the watchdog control +* register. +* +* @return None. +* +* @note C-style signature: + void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) +* +******************************************************************************/ +#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, (ControlReg)) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_EnableAutoReload(InstancePtr) \ + XScuWdt_SetControlReg((InstancePtr), \ + (XScuWdt_GetControlReg(InstancePtr) | \ + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscuwdt_sinit.c. + */ +XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscuwdt_selftest.c + */ +s32 XScuWdt_SelfTest(XScuWdt *InstancePtr); + +/* + * Interface functions in xscuwdt.c + */ +s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, + XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); + +void XScuWdt_Start(XScuWdt *InstancePtr); + +void XScuWdt_Stop(XScuWdt *InstancePtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h new file mode 100644 index 0000000..2067d3a --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt_hw.h +* @addtogroup scuwdt_v2_1 +* @{ +* +* This file contains the hardware interface to the Xilinx SCU private Watch Dog +* Timer (XSCUWDT). +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ +#ifndef XSCUWDT_HW_H /* prevent circular inclusions */ +#define XSCUWDT_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device. The WDT registers start at + * an offset 0x20 + * @{ + */ + +#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */ +#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */ +#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */ +#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */ +#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */ +#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */ +/* @} */ + +/** @name Watchdog Control register + * This register bits control the prescaler, WD/Timer mode, Intr enable, + * auto-reload, watchdog enable. + * @{ + */ + +#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U +#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */ +#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in + timer mode) */ +#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in + timer mode) */ +#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Counter register has reached zero in Counter + * mode. + * @{ + */ + +#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/** @name Reset Status register + * This register indicates the Counter register has reached zero in Watchdog + * mode and a reset request is sent. + * @{ + */ + +#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */ +/*@}*/ + +/** @name Disable register + * This register is used to switch from watchdog mode to timer mode. + * The software must write 0x12345678 and 0x87654321 successively to the + * Watchdog Disable Register so that the watchdog mode bit in the Watchdog + * Control Register is set to zero. + * @{ + */ +#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable + value 1 */ +#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable + value 2 */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + ((u32)RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps.h new file mode 100644 index 0000000..f413a86 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps.h @@ -0,0 +1,280 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps.h +* @addtogroup sdps_v3_3 +* @{ +* @details +* +* This file contains the implementation of XSdPs driver. +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Intialization: +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer: +* The SD card is put in tranfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use: +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesytem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support: +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
+*                       information.
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*
+*
    +* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_printf.h" +#include "xil_cache.h" +#include "xstatus.h" +#include "xsdps_hw.h" +#include "xplatform_info.h" +#include + +/************************** Constant Definitions *****************************/ + +#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */ +#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */ + +/**************************** Type Definitions *******************************/ + +typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u32 CardDetect; /**< Card Detect */ + u32 WriteProtect; /**< Write Protect */ + u32 BusWidth; /**< Bus Width */ + u32 BankNumber; /**< MIO Bank selection for SD */ + u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ +} XSdPs_Config; + +/* ADMA2 descriptor table */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else + u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 +} XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif + +/** + * The XSdPs driver instance data. The user is required to allocate a + * variable of this type for every SD device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSdPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Host_Caps; /**< Capabilities of host controller */ + u32 Host_CapsExt; /**< Extended Capabilities */ + u32 HCS; /**< High capacity support in card */ + u8 CardType; /**< Type of card - SD/MMC/eMMC */ + u8 Card_Version; /**< Card version */ + u8 HC_Version; /**< Host controller version */ + u8 BusWidth; /**< Current operating bus width */ + u32 BusSpeed; /**< Current operating bus speed */ + u8 Switch1v8; /**< 1.8V Switch support */ + u32 CardID[4]; /**< Card ID Register */ + u32 RelCardAddr; /**< Relative Card Address */ + u32 CardSpecData[4]; /**< Card Specific Data Register */ + u32 SectorCount; /**< Sector Count */ + u32 SdCardConfig; /**< Sd Card Configuration Register */ + u32 Mode; /**< Bus Speed Mode */ + XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */ + /**< ADMA Descriptors */ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + XSdPs_Adma2Descriptor Adma2_DescrTbl[32]; +#pragma data_alignment = 4 +#else + XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif +} XSdPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr); +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +s32 XSdPs_Select_Card (XSdPs *InstancePtr); +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr); +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Pullup(XSdPs *InstancePtr); +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_CardInitialize(XSdPs *InstancePtr); +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SD_H_ */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps_hw.h new file mode 100644 index 0000000..5656d7d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xsdps_hw.h @@ -0,0 +1,1297 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* @addtogroup sdps_v3_3 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Added support for ARMCC toolchain
+*
    +* +******************************************************************************/ + +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address + Register */ +#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET + /**< SDMA System Address + Low Register */ +#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ +#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address + High Register */ +#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */ + +#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ +#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET + /**< Argument1 Register */ +#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ + +#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */ +#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control + register */ + +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version + Register */ + +/* @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */ +#define XSDPS_HC_BUS_WIDTH_4 0x00000002U +#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */ +#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */ + +/* @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U +#define XSDPS_CC_MAX_DIV_CNT 256U +#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U +#define XSDPS_CC_EXT_DIV_SHIFT 6U + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU + +#define XSDPS_SWRST_ALL_MASK 0x00000001U +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U + +#define XSDPS_CC_MAX_NUM_OF_DIV 9U +#define XSDPS_CC_DIV_SHIFT 8U + +/* @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */ +/* @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_SIZE_1024 0x400U +#define XSDPS_BLK_SIZE_2048 0x800U +#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for + Current Transfer */ + +/* @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/* @} */ + +/** @name Auto CMD Error Status Register + * + * This register is read only register which contains + * information about the error status of Auto CMD 12 and 23. + * Read Only + * @{ + */ +#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + +/** @name Host Control2 Register + * + * This register contains extended configuration bits. + * Read Write + * @{ + */ +#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */ +#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */ +#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */ +#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength + Selection */ +#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */ +#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */ +#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */ +#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */ +#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */ +#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock + Selection */ +#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt + Enable */ +#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */ + +/* @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */ +#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */ +#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */ +#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */ + +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */ + +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus + support */ +/* Spec 2.0 */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */ + + +/* Spec 3.0 */ +#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt + support */ +#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */ +#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */ +#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */ +#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */ + +#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */ +#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */ +#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */ +#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */ +#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */ +#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */ +#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for + Re-tuning */ +#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs + tuning */ +#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes + support */ +#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */ +#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */ +#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */ +#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value + for Programmable clock + mode */ +#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */ +#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */ + +/* @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */ +#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch + pin level */ +#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */ +#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */ +#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */ + +/* @} */ + +/** @name Maximum Current Capablities Register + * + * This register is read only register which contains + * information about current capabilities at each voltage levels. + * Read Only + * @{ + */ +#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current + Capability at 1.8V */ +#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current + Capability at 3.0V */ +#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current + Capability at 3.3V */ +/* @} */ + + +/** @name Force Event for Auto CMD Error Status Register + * + * This register is write only register which contains + * control bits to generate events for Auto CMD error status. + * Write Only + * @{ + */ +#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + + + +/** @name Force Event for Error Interrupt Status Register + * + * This register is write only register which contains + * control bits to generate events of error interrupt status register. + * Write Only + * @{ + */ +#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout + Error */ +#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */ +#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit + Error */ +#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */ +#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */ +#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */ +#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */ +#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */ +#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */ +#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */ +#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */ +#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific + Error */ + +/* @} */ + +/** @name ADMA Error Status Register + * + * This register is read only register which contains + * status information about ADMA errors. + * Read Only + * @{ + */ +#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch + Error */ +#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */ +#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State + STOP */ +#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State + FDS */ +#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State + TFR */ +/* @} */ + +/** @name Preset Values Register + * + * This register is read only register which contains + * preset values for each of speed modes. + * Read Only + * @{ + */ +#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency + Select Value */ +#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator + Mode Select */ +#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength + Select Value */ + +/* @} */ + +/** @name Slot Interrupt Status Register + * + * This register is read only register which contains + * interrupt slot signal for each slot. + * Read Only + * @{ + */ +#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal + mask */ + +/* @} */ + +/** @name Host Controller Version Register + * + * This register is read only register which contains + * Host Controller and Vendor Specific version. + * Read Only + * @{ + */ +#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor + Specification + version mask */ +#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host + Specification + version mask */ +#define XSDPS_HC_SPEC_V3 0x0002U +#define XSDPS_HC_SPEC_V2 0x0001U +#define XSDPS_HC_SPEC_V1 0x0000U + +/** @name Block size mask for 512 bytes + * + * Block size mask for 512 bytes - This is the default block size. + * @{ + */ + +#define XSDPS_BLK_SIZE_512_MASK 0x200U + +/* @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000U +#define CMD0 0x0000U +#define CMD1 0x0100U +#define CMD2 0x0200U +#define CMD3 0x0300U +#define CMD4 0x0400U +#define CMD5 0x0500U +#define CMD6 0x0600U +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U) +#define CMD7 0x0700U +#define CMD8 0x0800U +#define CMD9 0x0900U +#define CMD10 0x0A00U +#define CMD11 0x0B00U +#define CMD12 0x0C00U +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U) +#define CMD16 0x1000U +#define CMD17 0x1100U +#define CMD18 0x1200U +#define CMD19 0x1300U +#define CMD21 0x1500U +#define CMD23 0x1700U +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U) +#define CMD24 0x1800U +#define CMD25 0x1900U +#define CMD41 0x2900U +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U) +#define CMD52 0x3400U +#define CMD55 0x3700U +#define CMD58 0x3A00U + +#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +/* @} */ + +/* Card Interface Conditions Definitions */ +#define XSDPS_CIC_CHK_PATTERN 0xAAU +#define XSDPS_CIC_VOLT_MASK (0xFU<<8) +#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8) +#define XSDPS_CIC_VOLT_LOW (1U<<9) + +/* Operation Conditions Register Definitions */ +#define XSDPS_OCR_PWRUP_STS (1U<<31) +#define XSDPS_OCR_CC_STS (1U<<30) +#define XSDPS_OCR_S18 (1U<<24) +#define XSDPS_OCR_3V5_3V6 (1U<<23) +#define XSDPS_OCR_3V4_3V5 (1U<<22) +#define XSDPS_OCR_3V3_3V4 (1U<<21) +#define XSDPS_OCR_3V2_3V3 (1U<<20) +#define XSDPS_OCR_3V1_3V2 (1U<<19) +#define XSDPS_OCR_3V0_3V1 (1U<<18) +#define XSDPS_OCR_2V9_3V0 (1U<<17) +#define XSDPS_OCR_2V8_2V9 (1U<<16) +#define XSDPS_OCR_2V7_2V8 (1U<<15) +#define XSDPS_OCR_1V7_1V95 (1U<<7) +#define XSDPS_OCR_HIGH_VOL 0x00FF8000U +#define XSDPS_OCR_LOW_VOL 0x00000080U + +/* SD Card Configuration Register Definitions */ +#define XSDPS_SCR_REG_LEN 8U +#define XSDPS_SCR_STRUCT_MASK (0xFU<<28) +#define XSDPS_SCR_SPEC_MASK (0xFU<<24) +#define XSDPS_SCR_SPEC_1V0 0U +#define XSDPS_SCR_SPEC_1V1 (1U<<24) +#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24) +#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23) +#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20) +#define XSDPS_SCR_SEC_SUPP_NONE 0U +#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20) +#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20) +#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20) +#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16) +#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16) +#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16) +#define XSDPS_SCR_SPEC3_MASK (1U<<12) +#define XSDPS_SCR_SPEC3_2V0 0U +#define XSDPS_SCR_SPEC3_3V0 (1U<<12) +#define XSDPS_SCR_CMD_SUPP_MASK 0x3U +#define XSDPS_SCR_CMD23_SUPP (1U<<1) +#define XSDPS_SCR_CMD20_SUPP (1U<<0) + +/* Card Status Register Definitions */ +#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31) +#define XSDPS_CD_STS_ADDR_ERR (1U<<30) +#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29) +#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28) +#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27) +#define XSDPS_CD_STS_WP_VIO (1U<<26) +#define XSDPS_CD_STS_IS_LOCKED (1U<<25) +#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24) +#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23) +#define XSDPS_CD_STS_ILGL_CMD (1U<<22) +#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21) +#define XSDPS_CD_STS_CC_ERR (1U<<20) +#define XSDPS_CD_STS_ERR (1U<<19) +#define XSDPS_CD_STS_CSD_OVRWR (1U<<16) +#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15) +#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14) +#define XSDPS_CD_STS_ER_RST (1U<<13) +#define XSDPS_CD_STS_CUR_STATE (0xFU<<9) +#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8) +#define XSDPS_CD_STS_APP_CMD (1U<<5) +#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2) + +/* Switch Function Definitions CMD6 */ +#define XSDPS_SWITCH_SD_RESP_LEN 64U + +#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31) +#define XSDPS_SWITCH_FUNC_CHECK 0U + +#define XSDPS_MODE_FUNC_GRP1 1U +#define XSDPS_MODE_FUNC_GRP2 2U +#define XSDPS_MODE_FUNC_GRP3 3U +#define XSDPS_MODE_FUNC_GRP4 4U +#define XSDPS_MODE_FUNC_GRP5 5U +#define XSDPS_MODE_FUNC_GRP6 6U + +#define XSDPS_FUNC_GRP_DEF_VAL 0xFU +#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU + +#define XSDPS_ACC_MODE_DEF_SDR12 0U +#define XSDPS_ACC_MODE_HS_SDR25 1U +#define XSDPS_ACC_MODE_SDR50 2U +#define XSDPS_ACC_MODE_SDR104 3U +#define XSDPS_ACC_MODE_DDR50 4U + +#define XSDPS_CMD_SYS_ARG_SHIFT 4U +#define XSDPS_CMD_SYS_DEF 0U +#define XSDPS_CMD_SYS_eC 1U +#define XSDPS_CMD_SYS_OTP 3U +#define XSDPS_CMD_SYS_ASSD 4U +#define XSDPS_CMD_SYS_VEND 5U + +#define XSDPS_DRV_TYPE_ARG_SHIFT 8U +#define XSDPS_DRV_TYPE_B 0U +#define XSDPS_DRV_TYPE_A 1U +#define XSDPS_DRV_TYPE_C 2U +#define XSDPS_DRV_TYPE_D 3U + +#define XSDPS_CUR_LIM_ARG_SHIFT 12U +#define XSDPS_CUR_LIM_200 0U +#define XSDPS_CUR_LIM_400 1U +#define XSDPS_CUR_LIM_600 2U +#define XSDPS_CUR_LIM_800 3U + +#define CSD_SPEC_VER_MASK 0x3C0000U +#define READ_BLK_LEN_MASK 0x00000F00U +#define C_SIZE_MULT_MASK 0x00000380U +#define C_SIZE_LOWER_MASK 0xFFC00000U +#define C_SIZE_UPPER_MASK 0x00000003U +#define CSD_STRUCT_MASK 0x00C00000U +#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U + +/* EXT_CSD field definitions */ +#define XSDPS_EXT_CSD_SIZE 512U + +#define EXT_CSD_WR_REL_PARAM_EN (1U<<2) + +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U) + +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) + +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) + +#define EXT_CSD_CMD_SET_NORMAL (1U<<0) +#define EXT_CSD_CMD_SET_SECURE (1U<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1U<<2) + +#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ + /* DDR mode @1.8V or 3V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ + /* DDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) +#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_BUS_WIDTH_BYTE 183U +#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */ + +#define EXT_CSD_HS_TIMING_BYTE 185U +#define EXT_CSD_HS_TIMING_DEF 0U +#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ +#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ + +#define EXT_CSD_RST_N_FUN_BYTE 162U +#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */ +#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */ +#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */ + +#define XSDPS_EXT_CSD_CMD_SET 0U +#define XSDPS_EXT_CSD_SET_BITS 1U +#define XSDPS_EXT_CSD_CLR_BITS 2U +#define XSDPS_EXT_CSD_WRITE_BYTE 3U + +#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + +#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + +#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + +#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8)) + +#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + +#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + +#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + +#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + +#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + +#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U + +/* @} */ + +/* @400KHz, in usec */ +#define XSDPS_74CLK_DELAY 2960U +#define XSDPS_100CLK_DELAY 4000U +#define XSDPS_INIT_DELAY 10000U + +#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK +#define XSDPS_CARD_DEF_ADDR 0x1234U + +#define XSDPS_CARD_SD 1U +#define XSDPS_CARD_MMC 2U +#define XSDPS_CARD_SDIO 3U +#define XSDPS_CARD_SDCOMBO 4U +#define XSDPS_CHIP_EMMC 5U + + +/** @name ADMA2 Descriptor related definitions + * + * ADMA2 Descriptor related definitions + * @{ + */ + +#define XSDPS_DESC_MAX_LENGTH 65536U + +#define XSDPS_DESC_VALID (0x1U << 0) +#define XSDPS_DESC_END (0x1U << 1) +#define XSDPS_DESC_INT (0x1U << 2) +#define XSDPS_DESC_TRAN (0x2U << 4) + +/* @} */ + +/* For changing clock frequencies */ +#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */ +#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */ +#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */ +#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */ +#define XSDPS_SCR_BLKCNT 1U +#define XSDPS_SCR_BLKSIZE 8U +#define XSDPS_1_BIT_WIDTH 0x1U +#define XSDPS_4_BIT_WIDTH 0x2U +#define XSDPS_8_BIT_WIDTH 0x3U +#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U +#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U +#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U +#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U +#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U +#define XSDPS_HIGH_SPEED_MODE 0x5U +#define XSDPS_DEFAULT_SPEED_MODE 0x6U +#define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U +#define XSDPS_SWITCH_CMD_BLKCNT 1U +#define XSDPS_SWITCH_CMD_BLKSIZE 64U +#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U +#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U +#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U +#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U +#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U +#define XSDPS_EXT_CSD_CMD_BLKCNT 1U +#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U +#define XSDPS_TUNING_CMD_BLKCNT 1U +#define XSDPS_TUNING_CMD_BLKSIZE 64U + +#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U +#define XSDPS_UHS_SDR104_MAX_CLK 208000000U +#define XSDPS_UHS_SDR50_MAX_CLK 100000000U +#define XSDPS_UHS_DDR50_MAX_CLK 50000000U +#define XSDPS_UHS_SDR25_MAX_CLK 50000000U +#define XSDPS_UHS_SDR12_MAX_CLK 25000000U + +#define SD_DRIVER_TYPE_B 0x01U +#define SD_DRIVER_TYPE_A 0x02U +#define SD_DRIVER_TYPE_C 0x04U +#define SD_DRIVER_TYPE_D 0x08U +#define SD_SET_CURRENT_LIMIT_200 0U +#define SD_SET_CURRENT_LIMIT_400 1U +#define SD_SET_CURRENT_LIMIT_600 2U +#define SD_SET_CURRENT_LIMIT_800 3U + +#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) + +#define XSDPS_SD_SDR12_MAX_CLK 25000000U +#define XSDPS_SD_SDR25_MAX_CLK 50000000U +#define XSDPS_SD_SDR50_MAX_CLK 100000000U +#define XSDPS_SD_DDR50_MAX_CLK 50000000U +#define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_MMC_HS200_MAX_CLK is set to 150000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_MMC_HS200_MAX_CLK 150000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U + +#define XSDPS_CARD_STATE_IDLE 0U +#define XSDPS_CARD_STATE_RDY 1U +#define XSDPS_CARD_STATE_IDEN 2U +#define XSDPS_CARD_STATE_STBY 3U +#define XSDPS_CARD_STATE_TRAN 4U +#define XSDPS_CARD_STATE_DATA 5U +#define XSDPS_CARD_STATE_RCV 6U +#define XSDPS_CARD_STATE_PROG 7U +#define XSDPS_CARD_STATE_DIS 8U +#define XSDPS_CARD_STATE_BTST 9U +#define XSDPS_CARD_STATE_SLP 10U + +#define XSDPS_SLOT_REM 0U +#define XSDPS_SLOT_EMB 1U + +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U +#define SD_DLL_CTRL 0x00000358U +#define SD_ITAPDLY 0x00000314U +#define SD_OTAPDLY 0x00000318U +#define SD0_DLL_RST 0x00000004U +#define SD1_DLL_RST 0x00040000U +#define SD0_ITAPCHGWIN 0x00000200U +#define SD0_ITAPDLYENA 0x00000100U +#define SD0_OTAPDLYENA 0x00000040U +#define SD1_ITAPCHGWIN 0x02000000U +#define SD1_ITAPDLYENA 0x01000000U +#define SD1_OTAPDLYENA 0x00400000U + +#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U +#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD0_ITAPDLYSEL_SD50 0x00000014U +#define SD0_OTAPDLYSEL_SD50 0x00000003U +#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU +#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U +#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U +#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U +#define SD0_ITAPDLYSEL_HSD 0x00000015U +#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U +#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U + +#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U +#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U +#define SD1_ITAPDLYSEL_SD50 0x00140000U +#define SD1_OTAPDLYSEL_SD50 0x00030000U +#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U +#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U +#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U +#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U +#define SD1_ITAPDLYSEL_HSD 0x00150000U +#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U +#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U + +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define XSdPs_In64 Xil_In64 +#define XSdPs_Out64 Xil_Out64 + +#define XSdPs_In32 Xil_In32 +#define XSdPs_Out32 Xil_Out32 + +#define XSdPs_In16 Xil_In16 +#define XSdPs_Out16 Xil_Out16 + +#define XSdPs_In8 Xil_In8 +#define XSdPs_Out8 Xil_Out8 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg64(InstancePtr, RegOffset) \ + XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ + XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ + (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h new file mode 100644 index 0000000..9937475 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xstatus.h @@ -0,0 +1,535 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xtime_l.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xtime_l.h new file mode 100644 index 0000000..f939d84 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xtime_l.h @@ -0,0 +1,96 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+*
    +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ \ No newline at end of file diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h new file mode 100644 index 0000000..a41404d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps.h @@ -0,0 +1,518 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartps.h +* @addtogroup uartps_v3_4 +* @{ +* @details +* +* This driver supports the following features: +* +* - Dynamic data format (baud rate, data bits, stop bits, parity) +* - Polled mode +* - Interrupt driven mode +* - Transmit and receive FIFOs (32 byte FIFO depth) +* - Access to the external modem control lines +* +* Initialization & Configuration +* +* The XUartPs_Config structure is used by the driver to configure itself. +* Fields inside this structure are properties of XUartPs based on its hardware +* build. +* +* To support multiple runtime loading and initialization strategies employed +* by various operating systems, the driver instance can be initialized in the +* following way: +* +* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the parameter EffectiveAddr should be the +* virtual address. +* +* Baud Rate +* +* The UART has an internal baud rate generator, which furnishes the baud rate +* clock for both the receiver and the transmitter. Ther input clock frequency +* can be either the master clock or the master clock divided by 8, configured +* through the mode register. +* +* Accompanied with the baud rate divider register, the baud rate is determined +* by: +* 
    +*	baud_rate = input_clock / (bgen * (bdiv + 1)
+*
    +* where bgen is the value of the baud rate generator, and bdiv is the value of +* baud rate divider. +* +* Interrupts +* +* The FIFOs are not flushed when the driver is initialized, but a function is +* provided to allow the user to reset the FIFOs if desired. +* +* The driver defaults to no interrupts at initialization such that interrupts +* must be enabled if desired. An interrupt is generated for one of the +* following conditions. +* +* - A change in the modem signals +* - Data in the receive FIFO for a configuable time without receiver activity +* - A parity error +* - A framing error +* - An overrun error +* - Transmit FIFO is full +* - Transmit FIFO is empty +* - Receive FIFO is full +* - Receive FIFO is empty +* - Data in the receive FIFO equal to the receive threshold +* +* The application can control which interrupts are enabled using the +* XUartPs_SetInterruptMask() function. +* +* In order to use interrupts, it is necessary for the user to connect the +* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt +* system of the application. A separate handler should be provided by the +* application to communicate with the interrupt system, and conduct +* application specific interrupt handling. An application registers its own +* handler through the XUartPs_SetHandler() function. +* +* Data Transfer +* +* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the +* driver to allow data to be sent and received. They can be used in either +* polled or interrupt mode. +* +* @note +* +* The default configuration for the UART after initialization is: +* +* - 9,600 bps or XPAR_DFT_BAUDRATE if defined +* - 8 data bits +* - 1 stop bit +* - no parity +* - FIFO's are enabled with a receive threshold of 8 bytes +* - The RX timeout is enabled with a timeout of 1 (4 char times) +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+*
    +* +*****************************************************************************/ + +#ifndef XUARTPS_H /* prevent circular inclusions */ +#define XUARTPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xuartps_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 921600U +#define XUARTPS_MIN_RATE 110U + +#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */ + +/** @name Configuration options + * @{ + */ +/** + * These constants specify the options that may be set or retrieved + * with the driver, each is a unique bit mask such that multiple options + * may be specified. These constants indicate the available options + * in active state. + * + */ + +#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */ +#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */ +#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */ +#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */ +#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */ +#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */ +#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */ +#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */ +/*@}*/ + + +/** @name Channel Operational Mode + * + * The UART can operate in one of four modes: Normal, Local Loopback, Remote + * Loopback, or automatic echo. + * + * @{ + */ + +#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */ +#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */ +#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */ +#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */ + +/* @} */ + +/** @name Data format values + * + * These constants specify the data format that the driver supports. + * The data format includes the number of data bits, the number of stop + * bits and parity. + * + * @{ + */ +#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */ +#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */ +#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */ + +#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */ +#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */ +#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */ +#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */ +#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */ + +#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */ +#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */ +#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that an application can handle + * using its specific handler function. Note that these constants are not bit + * mask, so only one event can be passed to an application at a time. + * + * @{ + */ +#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */ +#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break + * error detected */ +#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ +/*@}*/ + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ + u32 InputClockHz;/**< Input clock frequency */ + s32 ModemPinsConnected; /** Specifies whether modem pins are connected + * to MIO or FMIO */ +} XUartPs_Config; + +/* Keep track of state information about a data buffer in the interrupt mode. */ +typedef struct { + u8 *NextBytePtr; + u32 RequestedBytes; + u32 RemainingBytes; +} XUartPsBuffer; + +/** + * Keep track of data format setting of a device. + */ +typedef struct { + u32 BaudRate; /**< In bps, ie 1200 */ + u32 DataBits; /**< Number of data bits */ + u32 Parity; /**< Parity */ + u8 StopBits; /**< Number of stop bits */ +} XUartPsFormat; + +/******************************************************************************/ +/** + * This data type defines a handler that an application defines to communicate + * with interrupt system to retrieve state information about an application. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the handler, and is passed back to the upper layer + * when the handler is called. It is used to find the device driver + * instance. + * @param Event contains one of the event constants indicating events that + * have occurred. + * @param EventData contains the number of bytes sent or received at the + * time of the call for send and receive events and contains the + * modem status for modem events. + * + ******************************************************************************/ +typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, + u32 EventData); + +/** + * The XUartPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XUartPs_Config Config; /* Configuration data structure */ + u32 InputClockHz; /* Input clock frequency */ + u32 IsReady; /* Device is initialized and ready */ + u32 BaudRate; /* Current baud rate */ + + XUartPsBuffer SendBuffer; + XUartPsBuffer ReceiveBuffer; + + XUartPs_Handler Handler; + void *CallBackRef; /* Callback reference for event handler */ + u32 Platform; + u8 is_rxbs_error; +} XUartPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Get the UART Channel Status Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetChannelStatus(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) + +/****************************************************************************/ +/** +* Get the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_GetControl(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetModeControl(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET) + +/****************************************************************************/ +/** +* Set the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \ + (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Enable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_EnableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_EnableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN))) + +/****************************************************************************/ +/** +* Disable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_DisableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_DisableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS))) + +/****************************************************************************/ +/** +* Determine if the transmitter FIFO is empty. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return +* - TRUE if a byte can be sent +* - FALSE if the Transmitter Fifo is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(InstancePtr) \ + ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + + +/************************** Function Prototypes *****************************/ + +/* Static lookup function implemented in xuartps_sinit.c */ +XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); + +/* Interface functions implemented in xuartps.c */ +s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, + XUartPs_Config * Config, u32 EffectiveAddr); + +u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); + +/* Options functions in xuartps_options.c */ +void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); + +u16 XUartPs_GetOptions(XUartPs *InstancePtr); + +void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); + +u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); + +u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); + +u32 XUartPs_IsSending(XUartPs *InstancePtr); + +u8 XUartPs_GetOperMode(XUartPs *InstancePtr); + +void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); + +u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); + +void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); + +u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); + +void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); + +s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +/* interrupt functions in xuartps_intr.c */ +u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); + +void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); + +void XUartPs_InterruptHandler(XUartPs *InstancePtr); + +void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, + void *CallBackRef); + +/* self-test functions in xuartps_selftest.c */ +s32 XUartPs_SelfTest(XUartPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h new file mode 100644 index 0000000..0eb6936 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/include/xuartps_hw.h @@ -0,0 +1,449 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xuartps_hw.h +* @addtogroup uartps_v3_4 +* @{ +* +* This header file contains the hardware interface of an XUartPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+*
    +* +******************************************************************************/ +#ifndef XUARTPS_HW_H /* prevent circular inclusions */ +#define XUARTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */ +#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */ +/* @}*/ + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */ +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */ +#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */ +/* @} */ + + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ +#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + +/** @name Receiver FIFO Byte Status Register + * + * The Receiver FIFO Status register is used to have a continuous + * monitoring of the raw unmasked byte status information. The register + * contains frame, parity and break status information for the top + * four bytes in the RX FIFO. + * + * Receiver FIFO Byte Status Register Bit Definition + * @{ + */ +#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */ +#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */ +#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */ +#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */ +#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */ +#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */ +#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */ +#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */ +#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */ +#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */ +#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */ +#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */ +#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */ +/* @} */ + + +/* + * Defines for backwards compatabilty, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* Read a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) +* +******************************************************************************/ +#define XUartPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* u32 XUartPs_IsReceiveData(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsReceiveData(BaseAddress) \ + !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitFull(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitFull(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) + +/************************** Function Prototypes ******************************/ + +void XUartPs_SendByte(u32 BaseAddress, u8 Data); + +u8 XUartPs_RecvByte(u32 BaseAddress); + +void XUartPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/lib/libxil.a b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/lib/libxil.a new file mode 100644 index 0000000..cc4faf4 Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/lib/libxil.a differ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile new file mode 100644 index 0000000..007162d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner coresightps_dcc_comp_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling coresightps_dcc" + +coresightps_dcc_comp_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: coresightps_dcc_includes + +coresightps_dcc_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c new file mode 100644 index 0000000..cfa356c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c @@ -0,0 +1,188 @@ +/****************************************************************************** +* +* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.c +* @addtogroup coresightps_dcc_v1_1 +* @{ +* +* Functions in this file are the minimum required functions for the +* XCoreSightPs driver. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifdef __MICROBLAZE__ +#warning "The driver is supported only for ARM architecture" +#else + +#include +#include + +#ifdef __ICCARM__ +#define INLINE +#else +#define INLINE __inline +#endif + +/* DCC Status Bits */ +#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30) +#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29) + +static INLINE u32 XCoresightPs_DccGetStatus(void); + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the DCC. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) +{ + (void) BaseAddress; + while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX) + dsb(); +#ifdef __aarch64__ + asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mcr p14, 0, %0, c0, c5, 0" + : : "r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Reg = Data; + } +#endif + isb(); + +} + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the DCC. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XCoresightPs_DccRecvByte(u32 BaseAddress) +{ + u8 Data = 0U; + (void) BaseAddress; + + while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) + dsb(); + +#ifdef __aarch64__ + asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c5, 0" + : "=r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Data = Reg; + } +#endif + isb(); + + return Data; +} + + +/****************************************************************************/ +/**INLINE +* +* This functions read the status register of the DCC. +* +* @param BaseAddress is the base address of the device +* +* @return The contents of the Status Register. +* +* @note None. +* +******************************************************************************/ +static INLINE u32 XCoresightPs_DccGetStatus(void) +{ + u32 Status = 0U; + +#ifdef __aarch64__ + asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c1, 0" + : "=r" (Status) : : "cc"); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c1:0"); + Status = Reg; + } +#endif + return Status; +#endif +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h new file mode 100644 index 0000000..a732b23 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.h +* @addtogroup coresightps_dcc_v1_1 +* @{ +* @details +* +* CoreSight driver component. +* +* The coresight is a part of debug communication channel (DCC) group. Jtag UART +* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an +* ARM target in XSDB console before running the jtag terminal command. Using the +* coresight driver component, the output stream can be directed to a log file. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifndef __MICROBLAZE__ +#include + +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); + +u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +#endif +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/Makefile new file mode 100644 index 0000000..7ea505c --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/Makefile @@ -0,0 +1,25 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I${INCLUDEDIR} + +OUTS = *.o +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +LIBSOURCES=*.c +INCLUDEFILES=*.h + +libs: + echo "Compiling cpu_cortexa9" + +.PHONY: include +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OBJECTS} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/xcpu_cortexa9.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/xcpu_cortexa9.h new file mode 100644 index 0000000..eff6cd8 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_5/src/xcpu_cortexa9.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9_v2_1 +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +******************************************************************************/ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile new file mode 100644 index 0000000..7b191dd --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xddrps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling ddrps" + +xddrps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xddrps_includes + +xddrps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h new file mode 100644 index 0000000..fe7adb0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps_v1_0 + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile new file mode 100644 index 0000000..25ff740 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xdevcfg_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling devcfg" + +xdevcfg_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xdevcfg_includes + +xdevcfg_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c new file mode 100644 index 0000000..dcb8030 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c @@ -0,0 +1,945 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.c +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the implementation of the interface functions for XDcfg +* driver. Refer to the header file xdevcfg.h for more detailed information. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Updated the XDcfg_Transfer function to use the
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  08/27/12 Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Initialize the Device Config Interface driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* - XST_DEVICE_IS_STARTED if the device has already been started. +* +* @note The very first APB access to the Device Configuration Interface +* block needs to be a write to the UNLOCK register with the value +* of 0x757BDF0D. This step is to be done once after reset, any +* other APB access has to come after this. The APB access is +* considered illegal if the step is not done or if it is done +* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, +* the following additional actions would be carried out. +* In other words, if all bits are low, the following steps are not +* done. +* 1. AES is disabled +* 2. All APB writes disabled +* 3. SoC debug fully enabled +* +******************************************************************************/ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * If the device is started, disallow the initialize and return a + * status indicating it is started. This allows the user to stop the + * device and reinitialize, but prevents a user from inadvertently + * initializing. + */ + if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Copy configuration into instance. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + + /* + * Save the base address pointer such that the registers of the block + * can be accessed and indicate it has not been started yet. + */ + InstancePtr->Config.BaseAddr = EffectiveAddress; + InstancePtr->IsStarted = 0; + + + /* Unlock the Device Configuration Interface */ + XDcfg_Unlock(InstancePtr); + + /* + * Indicate the instance is ready to use, successfully initialized. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* The functions enables the PCAP interface by setting the PCAP mode bit in the +* control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note Enable FPGA programming from PCAP interface. Enabling this bit +* disables all the external interfaces from programming of FPGA +* except for ICAP. The user needs to ensure that the FPGA is +* programmed through either PCAP or ICAP. +* +*****************************************************************************/ +void XDcfg_EnablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); + +} + +/****************************************************************************/ +/** +* +* The functions disables the PCAP interface by clearing the PCAP mode bit in +* the control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_DisablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit mask data to be written to the Register. +* The mask definitions are defined in the xdevcfg_hw.h file. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | Mask)); + +} + +/****************************************************************************/ +/** +* +* The function Clears the specified bit positions of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit value which holds the bit positions to be cleared. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ~Mask)); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Control +* Register. +* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Lock Register. These bits +* can only be set to a 1. They will be cleared after a Power On Reset. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Lock Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Lock +* Register. +* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Lock Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Config +* Register. +* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Status +* Register. +* Use the XDCFG_STATUS_*_MASK constants defined in +* xdevcfg_hw.h to interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Status Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the ROM Shadow Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note This register is can only be written and is used to control the +* RAM shadow of 32 bit 4K page ROM pages in user mode +* +*****************************************************************************/ +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, + Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Software ID Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API for reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Software ID Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the bit mask for the feature in Miscellaneous Control +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the feature to be set. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegData; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, + (RegData | Mask)); +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API to reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Miscellaneous Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); +} + +/******************************************************************************/ +/** +* +* This function checks if DMA command queue is full. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return XST_SUCCESS is the DMA is busy +* XST_FAILURE if the DMA is idle +* +* @note The DMA queue has a depth of two. +* +****************************************************************************/ +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) +{ + + u32 RegData; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Read the PCAP status register for DMA status */ + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + + if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK){ + return XST_SUCCESS; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function initiates the DMA transfer. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return None. +* +* @note It is the responsibility of the caller function to ensure that +* correct values are passed to this function. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +****************************************************************************/ +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength) +{ + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_ADDR_OFFSET, + SourcePtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_ADDR_OFFSET, + DestPtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_LEN_OFFSET, + SrcWordLength); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_LEN_OFFSET, + DestWordLength); +} + +/******************************************************************************/ +/** +* +* This function Implements the DMA Read Command. This command is used to +* transfer the image data from FPGA to the external memory. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return - XST_INVALID_PARAM if source address/length is invalid. +* - XST_SUCCESS if DMA transfer initiated properly. +* +* @note None. +* +****************************************************************************/ +static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, + u32 SrcWordLength, u32 DestPtr, + u32 DestWordLength) +{ + u32 IntrReg; + + /* + * Send READ Frame command to FPGA + */ + XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, + SrcWordLength, 0); + + /* + * Store the enabled interrupts to enable before the actual read + * transfer is initiated and Disable all the interrupts temporarily. + */ + IntrReg = XDcfg_IntrGetEnabled(InstancePtr); + XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK); + + /* + * Wait till you get the DMA done for the read command sent + */ + while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET) & + XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK); + /* + * Enable the previously stored Interrupts . + */ + XDcfg_IntrEnable(InstancePtr, IntrReg); + + /* + * Initiate the DMA write command. + */ + XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, + 0, DestWordLength); + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* This function starts the DMA transfer. This function only starts the +* operation and returns before the operation may be completed. +* If the interrupt is enabled, an interrupt will be generated when the +* operation is completed, otherwise it is necessary to poll the Status register +* to determine when it is completed. It is the responsibility of the caller to +* determine when the operation is completed by handling the generated interrupt +* or polling the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* @param TransferType contains the type of PCAP transfer being requested. +* The definitions can be found in the xdevcfg.h file. +* @return +* - XST_SUCCESS.if DMA transfer initiated successfully +* - XST_DEVICE_BUSY if DMA is busy +* - XST_INVALID_PARAM if invalid Source / Destination address +* is sent or an invalid Source / Destination length is +* sent +* +* @note It is the responsibility of the caller to ensure that the cache +* is flushed and invalidated both before the DMA operation is +* started and after the DMA operation completes if the memory +* pointed to is cached. The caller must also ensure that the +* pointers contain physical address rather than a virtual address +* if address translation is being used. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +*****************************************************************************/ +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType) +{ + + u32 CtrlReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) { + return XST_DEVICE_BUSY; + } + + /* + * Check whether the fabric is in initialized state + */ + if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) + & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { + /* + * We don't need to check PCFG_INIT to be high for + * non-encrypted loopback transfers. + */ + if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + return XST_FAILURE; + } + } + + if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || + (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { + + /* Check for valid source pointer and length */ + if ((!SourcePtr) || (SrcWordLength == 0)) { + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_SECURE_PCAP_WRITE) { + /* + * AES engine handles only 8 bit data every clock cycle. + * Hence, Encrypted PCAP data which is 32 bit data can + * only be sent in every 4 clock cycles. Set the control + * register QUARTER_PCAP_RATE_EN bit to achieve this + * operation. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + + } + + if (TransferType == XDCFG_PCAP_READBACK) { + + if ((!DestPtr) || (DestWordLength == 0)) { + + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * For PCAP readback of FPGA configuration register or memory, + * the read command is first sent (written) to the FPGA fabric + * which responds by returning the required read data. Read data + * from the FPGA is captured if pcap_radata_v is active.A DMA + * read transfer is required to obtain the readback command, + * which is then sent to the FPGA, followed by a DMA write + * transfer to support this mode of operation. + */ + return XDcfg_PcapReadback(InstancePtr, + (u32)SourcePtr, SrcWordLength, + (u32)DestPtr, DestWordLength); + } + + + if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || + (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { + + if ((!SourcePtr) || (SrcWordLength == 0) || + (!DestPtr) || (DestWordLength == 0)) { + return XST_INVALID_PARAM; + } + + if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + /* Enable internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg | + XDCFG_MCTRL_PCAP_LPBK_MASK)); + + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * Set the QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every 4 clock + * cycles, this is required for encrypted data. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + } + + return XST_SUCCESS; +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h new file mode 100644 index 0000000..52f99a0 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* @addtogroup devcfg_v3_3 +* @{ +* @details +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/10/17 Modified filename tag in interrupt and polled examples
+*                    to include them in doxygen examples.
+* 3.5   ms  04/18/17 Modified tcl file to add suffix U for all macros
+*                    definitions of devcfg in xparameters.h
+*       ms  08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
    +* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c new file mode 100644 index 0000000..320af47 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/* +* The configuration table for devices +*/ + +XDcfg_Config XDcfg_ConfigTable[] = +{ + { + XPAR_PS7_DEV_CFG_0_DEVICE_ID, + XPAR_PS7_DEV_CFG_0_BASEADDR + } +}; + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c new file mode 100644 index 0000000..8a3095d --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.c +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the implementation of the interface reset functionality +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given devcfg interface by +* configuring the appropriate control bits in the devcfg specifc registers +* the devcfg reset squence involves the following steps +* Disable all the interuupts +* Clear the status +* Update relevant config registers with reset values +* Disbale the looopback mode and pcap rate enable +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* devcfg controller +******************************************************************************/ +void XDcfg_ResetHw(u32 BaseAddr) +{ + u32 Regval = 0; + + /* Mask the interrupts */ + XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, + XDCFG_IXR_ALL_MASK); + /* Clear the interuupt status */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); + XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); + /* Clear the source address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0); + /* Clear the destination address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0); + /* Clear the source length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0); + /* Clear the destination length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0); + /* Clear the loopback enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET); + Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); + /*Reset the configuration register to reset value */ + XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, + XDCFG_CONFIG_RESET_VALUE); + /*Disable the PCAP rate enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); + Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval); + +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h new file mode 100644 index 0000000..c506ca5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h @@ -0,0 +1,395 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
    +* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c new file mode 100644 index 0000000..55bbde2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c @@ -0,0 +1,310 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_intr.c +* @addtogroup devcfg_v3_3 +* @{ +* +* Contains the implementation of interrupt related functions of the XDcfg +* driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* This function enables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be enabled. +* Bit positions of 1 will be enabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Enable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} + + +/****************************************************************************/ +/** +* +* This function disables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be disabled. +* Bit positions of 1 will be disabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Disable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue |= (Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} +/****************************************************************************/ +/** +* +* This function returns the enabled interrupts read from the Interrupt Mask +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the IMR. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Mask Register. + */ + return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET)); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt status read from Interrupt Status +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Interrupt +* Status register. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Status register. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears the specified interrupts in the Interrupt Status +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be cleared. +* Bit positions of 1 will be cleared. Bit positions of 0 will not +* change the previous interrupt status. This mask is formed by +* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, + Mask); + +} + +/*****************************************************************************/ +/** +* The interrupt handler for the Device Config Interface. +* +* Events are signaled to upper layer for proper handling. +* +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XDcfg_InterruptHandler(XDcfg *InstancePtr) +{ + u32 IntrStatusReg; + + /* + * Assert validates the input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Interrupt status register. + */ + IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); + + /* + * Write the status back to clear the interrupts so that no + * subsequent interrupts are missed while processing this interrupt. + * This also does the DMA acknowledgment automatically. + */ + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, IntrStatusReg); + + /* + * Signal application that there are events to handle. + */ + InstancePtr->StatusHandler(InstancePtr->CallBackRef, + IntrStatusReg); + +} + +/****************************************************************************/ +/** +* +* This function sets the handler that will be called when an event (interrupt) +* occurs that needs application's attention. +* +* @param InstancePtr is a pointer to the XDcfg instance +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return None. +* +* @note None. +* +* +*****************************************************************************/ +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef) +{ + /* + * Asserts validate the input arguments + * CallBackRef not checked, no way to know what is valid + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallBackFunc != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc; + InstancePtr->CallBackRef = CallBackRef; +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c new file mode 100644 index 0000000..7159782 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c @@ -0,0 +1,114 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_selftest.c +* @addtogroup devcfg_v3_3 +* @{ +* +* Contains diagnostic self-test functions for the XDcfg driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm  02/27/13 Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Run a self-test on the Device Configuration Interface. This test does a +* control register write and reads back the same value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return +* - XST_SUCCESS if self-test was successful. +* - XST_FAILURE if fails. +* +* @note None. +* +******************************************************************************/ +int XDcfg_SelfTest(XDcfg *InstancePtr) +{ + u32 OldCfgReg; + u32 CfgReg; + int Status = XST_SUCCESS; + + /* + * Assert to ensure the inputs are valid and the instance has been + * initialized. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + OldCfgReg = XDcfg_GetControlRegister(InstancePtr); + + XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK); + + CfgReg = XDcfg_GetControlRegister(InstancePtr); + + if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) { + + Status = XST_FAILURE; + } + + /* + * Restore the original values of the register + */ + XDcfg_SetControlRegister(InstancePtr, OldCfgReg); + + return Status; +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c new file mode 100644 index 0000000..2ffa7f2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdevcfg_sinit.c +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5   ms  08/07/17 Fixed compilation warnings.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) +{ + extern XDcfg_Config XDcfg_ConfigTable[]; + XDcfg_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { + if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDcfg_ConfigTable[Index]; + break; + } + } + + return (CfgPtr); +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile new file mode 100644 index 0000000..d1240c5 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile @@ -0,0 +1,41 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xdmaps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dmaps" + +xdmaps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xdmaps_includes + +xdmaps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c new file mode 100644 index 0000000..9db7692 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c @@ -0,0 +1,1982 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the implementation of the interface functions for XDmaPs +* driver. Refer to the header file xdmaps.h for more detailed information. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/2010 First Release
+* 1.00  nm     05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg     05/16/2012 Made changes for doxygen and moved some function
+*			  header from the xdmaps.h file to xdmaps.c file
+*			  Other cleanup for coding guidelines and CR 657109
+*			  and CR 657898
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.01 kpc    08/23/14   Fixed the IAR compiler reported errors
+* 2.2  mus    12/08/16   Remove definition of INLINE macro to avoid re-definition,
+*                         since it is being defined in xil_io.h
+* 2.3 kpc     14/10/16   Fixed the compiler error when optimization O0 is used.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include + +#include "xstatus.h" +#include "xdmaps.h" +#include "xil_io.h" +#include "xil_cache.h" + +#include "xil_printf.h" + + +/************************** Constant Definitions ****************************/ + +/* The following constant defines the amount of error that is allowed for + * a specified baud rate. This error is the difference between the actual + * baud rate that will be generated using the specified clock and the + * desired baud rate. + */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Function Prototypes *****************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread); + +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf); + +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg); + +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel); +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool); +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength); + +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); + + + +/************************** Variable Definitions ****************************/ + +/****************************************************************************/ +/** +* +* Initializes a specific XDmaPs instance such that it is ready to be used. +* The data format of the device is setup for 8 data bits, 1 stop bit, and no +* parity by default. The baud rate is set to a default value specified by +* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The +* receive FIFO threshold is set for 8 bytes. The default operating mode of the +* driver is polled mode. +* +* @param InstPtr is a pointer to the XDmaPs instance. +* @param Config is a reference to a structure containing information +* about a specific XDmaPs driver. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical base +* address unchanged once this function is invoked. Unexpected +* errors may occur if the address mapping changes after this +* function is called. If address translation is not used, pass in +* the physical address instead. +* +* @return +* +* - XST_SUCCESS on initialization completion +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr) +{ + int Status = XST_SUCCESS; + unsigned int CacheLength = 0; + u32 CfgReg; + unsigned Channel; + XDmaPs_ChannelData *ChanData; + + /* + * Assert validates the input arguments + */ + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Config != NULL); + + /* + * Setup the driver instance using passed in parameters + */ + InstPtr->Config.DeviceId = Config->DeviceId; + InstPtr->Config.BaseAddress = EffectiveAddr; + + CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET); + CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK; + if (CacheLength < 2 || CacheLength > 5) + CacheLength = 0; + else + CacheLength = 1 << CacheLength; + + InstPtr->CacheLength = CacheLength; + + memset(InstPtr->Chans, 0, + sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV])); + + for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) { + ChanData = InstPtr->Chans + Channel; + ChanData->ChanId = Channel; + ChanData->DevId = Config->DeviceId; + } + + InstPtr->IsReady = 1; + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the DMA Manager. +* +* @param InstPtr is the DMA instance. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetManager(XDmaPs *InstPtr) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + 0, 0); + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the specified DMA Channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel to be reset. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + Channel, 1); + + return Status; + +} + +/*****************************************************************************/ +/** +* +* Driver fault interrupt service routine +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_FaultISR(XDmaPs *InstPtr) +{ + + void *DmaProgBuf; + u32 Fsm; /* Fault status DMA manager register value */ + u32 Fsc; /* Fault status DMA channel register value */ + u32 FaultType; /* Fault type DMA manager register value */ + + u32 BaseAddr = InstPtr->Config.BaseAddress; + + u32 Pc; /* DMA Pc or channel Pc */ + XDmaPs_ChannelData *ChanData; + + unsigned Chan; + unsigned DevId; + + XDmaPs_Cmd *DmaCmd; + + Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01; + Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF; + + + DevId = InstPtr->Config.DeviceId; + + if (Fsm) { + /* + * if DMA manager is fault + */ + FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET); + Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET); + + xil_printf("PL330 device %d fault with type: %x at Pc %x\n", + DevId, + FaultType, Pc); + + /* kill the DMA manager thread */ + /* Should we disable interrupt?*/ + XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0); + } + + /* + * check which channel faults and kill the channel thread + */ + for (Chan = 0; + Chan < XDMAPS_CHANNELS_PER_DEV; + Chan++) { + if (Fsc & (0x01 << Chan)) { + FaultType = + XDmaPs_ReadReg(BaseAddr, + XDmaPs_FTCn_OFFSET(Chan)); + Pc = XDmaPs_ReadReg(BaseAddr, + XDmaPs_CPCn_OFFSET(Chan)); + + /* kill the channel thread */ + /* Should we disable interrupt? */ + XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1); + + /* + * get the fault type and fault Pc and invoke the + * fault callback. + */ + ChanData = InstPtr->Chans + Chan; + + DmaCmd = ChanData->DmaCmdToHw; + + /* Should we check DmaCmd is not null */ + DmaCmd->DmaStatus = -1; + DmaCmd->ChanFaultType = FaultType; + DmaCmd->ChanFaultPCAddr = Pc; + ChanData->DmaCmdFromHw = DmaCmd; + ChanData->DmaCmdToHw = NULL; + + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + if (InstPtr->FaultHandler) + InstPtr->FaultHandler(Chan, + DmaCmd, + InstPtr->FaultRef); + + } + } + +} + +/*****************************************************************************/ +/** +* +* Set the done handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel number. +* @param DoneHandler is the done interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef) +{ + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + + if (Channel >= XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + + ChanData = InstPtr->Chans + Channel; + + ChanData->DoneHandler = DoneHandler; + ChanData->DoneRef = CallbackRef; + + return 0; +} + +/*****************************************************************************/ +/** +* +* Set the fault handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param FaultHandler is the fault interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + InstPtr->FaultHandler = FaultHandler; + InstPtr->FaultRef = CallbackRef; + + return XST_SUCCESS; +} + + + +/****************************************************************************/ +/** +* Construction function for DMAEND instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for +* the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg) +{ + /* + * DMAEND encoding: + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 0 0 0 + */ + *DmaProg = 0x0; + + return 1; +} + +static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) +{ + *Dst = *Src; + *(Dst + 1) = *(Src + 1); + *(Dst + 2) = *(Src + 2); + *(Dst + 3) = *(Src + 3); +} + +/****************************************************************************/ +/** +* +* Construction function for DMAGO instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Cn is the Channel number, 0 - 7 +* @param Imm is 32-bit immediate number written to the Channel Program +* Counter. +* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in +* the Non-secure state. If Ns is 0, the execution depends on the +* security state of the DMA manager: +* DMA manager is in the Secure state, DMA channel operates in the +* Secure state. +* DMA manager is in the Non-secure state, DMAC aborts. +* +* @return The number of bytes for this instruction which is 6. +* +* @note None +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns) +{ + /* + * DMAGO encoding: + * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0 + * + * 47 ... 16 + * imm[32:0] + */ + *DmaProg = 0xA0 | ((Ns << 1) & 0x02); + + *(DmaProg + 1) = (u8)(Cn & 0x07); + + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + /* success */ + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALD instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for the +* instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALD(char *DmaProg) +{ + /* + * DMALD encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 1 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x04; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALP instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Lc is the Loop counter register, can either be 0 or 1. +* @param LoopIterations: the number of interations, LoopInterations - 1 +* will be encoded in the DMALP instruction. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations) +{ + /* + * DMALP encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | iter[7:0] |0 0 1 0 0 0 lc 0 + */ + *DmaProg = (u8)(0x20 | ((Lc & 1) << 1)); + *(DmaProg + 1) = (u8)(LoopIterations - 1); + return 2; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALPEND instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param BodyStart is the starting address of the loop body. It is used +* to calculate the bytes of backward jump. +* @param Lc is the Loop counter register, can either be 0 or 1. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) +{ + /* + * DMALPEND encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | backward_jump[7:0] |0 0 1 nf 1 lc bs x + * + * lc: loop counter + * nf is for loop forever. The driver does not support loop forever, + * so nf is 1. + * The driver does not support conditional LPEND, so bs is 0, x is 0. + */ + *DmaProg = 0x38 | ((Lc & 1) << 2); + *(DmaProg + 1) = (u8)(DmaProg - BodyStart); + + return 2; +} + +/* + * Register number for the DMAMOV instruction + */ +#define XDMAPS_MOV_SAR 0x0 +#define XDMAPS_MOV_CCR 0x1 +#define XDMAPS_MOV_DAR 0x2 + +/****************************************************************************/ +/** +* +* Construction function for DMAMOV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR +* @param Imm is the 32-bit immediate number +* +* @return The number of bytes for this instruction which is 6. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) +{ + /* + * DMAMOV encoding + * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0 + * + * 47 ... 16 + * imm[32:0] + * + * rd: b000 for SAR, b001 CCR, b010 DAR + */ + *DmaProg = 0xBC; + *(DmaProg + 1) = Rd & 0x7; + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMANOP instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg) +{ + /* + * DMANOP encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 1 0 0 0 + */ + *DmaProg = 0x18; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMARMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg) +{ + /* + * DMARMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x12; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMASEV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param EventNumber is the Event number to signal. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) +{ + /* + * DMASEV encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0 + */ + *DmaProg = 0x34; + *(DmaProg + 1) = (u8)(EventNumber << 3); + + return 2; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAST instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAST(char *DmaProg) +{ + /* + * DMAST encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 1 0 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x08; + return 1; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAWMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg) +{ + /* + * DMAWMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x13; + return 1; +} + +/****************************************************************************/ +/** +* +* Conversion function from the endian swap size to the bit encoding of the CCR +* +* @param EndianSwapSize is the endian swap size, in terms of bits, it +* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax) +* +* @return The endian swap size bit encoding for the CCR. +* +* @note None. +* +*****************************************************************************/ +static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) +{ + switch (EndianSwapSize) { + case 0: + case 8: + return 0; + case 16: + return 1; + case 32: + return 2; + case 64: + return 3; + case 128: + return 4; + default: + return 0; + } + +} + +/****************************************************************************/ +/** +* +* Conversion function from the burst size to the bit encoding of the CCR +* +* @param BurstSize is the burst size. It's the data width. +* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128. +* It must be no larger than the bus width. +* (We are using DMA assembly syntax.) +* +* @note None. +* +*****************************************************************************/ +static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) +{ + switch (BurstSize) { + case 1: + return 0; + case 2: + return 1; + case 4: + return 2; + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + default: + return 0; + } +} + + +/****************************************************************************/ +/** +* +* Conversion function from PL330 bus transfer descriptors to CCR value. All the +* values passed to the functions are in terms of assembly languages, not in +* terms of the register bit encoding. +* +* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl. +* +* @return The 32-bit CCR value. +* +* @note None. +* +*****************************************************************************/ +u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) +{ + /* + * Channel Control Register encoding + * [31:28] - endian_swap_size + * [27:25] - dst_cache_ctrl + * [24:22] - dst_prot_ctrl + * [21:18] - dst_burst_len + * [17:15] - dst_burst_size + * [14] - dst_inc + * [13:11] - src_cache_ctrl + * [10:8] - src_prot_ctrl + * [7:4] - src_burst_len + * [3:1] - src_burst_size + * [0] - src_inc + */ + + unsigned es = + XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize); + + unsigned dst_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize); + unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F; + unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03) + | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); + unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07; + unsigned dst_inc_bit = ChanCtrl->DstInc & 1; + + unsigned src_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize); + unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F; + unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03) + | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); + unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07; + unsigned src_inc_bit = ChanCtrl->SrcInc & 1; + + u32 ccr_value = (es << 28) + | (dst_cache_ctrl << 25) + | (dst_prot_ctrl << 22) + | (dst_burst_len << 18) + | (dst_burst_size << 15) + | (dst_inc_bit << 14) + | (src_cache_ctrl << 11) + | (src_prot_ctrl << 8) + | (src_burst_len << 4) + | (src_burst_size << 1) + | (src_inc_bit); + + return ccr_value; +} + +/****************************************************************************/ +/** +* Construct a loop with only DMALD and DMAST as the body using loop counter 0. +* The function also makes sure the loop body and the lpend is in the same +* cache line. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCount The inner loop count. Loop count - 1 will be used to +* initialize the loop counter. +* +* @return The number of bytes the loop has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructSingleLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + int LoopCount) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount); + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 3; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + + return DmaProgBuf - DmaProgLoopStart; +} + +/****************************************************************************/ +/** +* Construct a nested loop with only DMALD and DMAST in the inner loop body. +* It uses loop counter 1 for the outer loop and loop counter 0 for the +* inner loop. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCountOuter The outer loop count. Loop count - 1 will be +* used to initialize the loop counter. +* @param LoopCountInner The inner loop count. Loop count - 1 will be +* used to initialize the loop counter. +* +* @return The number byes the nested loop program has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructNestedLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + unsigned int LoopCountOuter, + unsigned int LoopCountInner) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *InnerLoopStart; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter); + InnerLoopStart = DmaProgBuf; + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + if (CacheLength < 8) { + /* + * if the cache line is too small to fit both loops + * just align the inner loop + */ + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCountInner); + /* outer loop end */ + DmaProgBuf += + XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, + 1); + + /* + * the nested loop is constructed for + * smaller cache line + */ + return DmaProgBuf - DmaProgLoopStart; + } + + /* + * Now let's handle the case where a cache line can + * fit the nested loops. + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 7; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + /* insert the inner DMALP */ + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner); + + /* DMALD and DMAST instructions */ + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + + /* inner DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + /* outer DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, 1); + + /* return the number of bytes */ + return DmaProgBuf - DmaProgLoopStart; +} + +/* + * [31:28] endian_swap_size b0000 + * [27:25] dst_cache_ctrl b000 + * [24:22] dst_prot_ctrl b000 + * [21:18] dst_burst_len b0000 + * [17:15] dst_burst_size b000 + * [14] dst_inc b0 + * [27:25] src_cache_ctrl b000 + * [24:22] src_prot_ctrl b000 + * [21:18] src_burst_len b0000 + * [17:15] src_burst_size b000 + * [14] src_inc b0 + */ +#define XDMAPS_CCR_SINGLE_BYTE (0x0) +#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1) + + +/****************************************************************************/ +/** +* +* Construct the DMA program based on the descriptions of the DMA transfer. +* The function handles memory to memory DMA transfers. +* It also handles unalgined head and small amount of residue tail. +* +* @param Channel DMA channel number +* @param Cmd is the DMA command. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* +* @returns The number of bytes for the program. +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength) +{ + /* + * unpack arguments + */ + char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg; + unsigned DevChan = Channel; + unsigned long DmaLength = Cmd->BD.Length; + u32 SrcAddr = Cmd->BD.SrcAddr; + + unsigned SrcInc = Cmd->ChanCtrl.SrcInc; + u32 DstAddr = Cmd->BD.DstAddr; + unsigned DstInc = Cmd->ChanCtrl.DstInc; + + char *DmaProgStart = DmaProgBuf; + + unsigned int BurstBytes; + unsigned int LoopCount; + unsigned int LoopCount1 = 0; + unsigned int LoopResidue = 0; + unsigned int TailBytes; + unsigned int TailWords; + int DmaProgBytes; + u32 CCRValue; + unsigned int Unaligned; + unsigned int UnalignedCount; + unsigned int MemBurstSize = 1; + u32 MemAddr = 0; + unsigned int Index; + unsigned int SrcUnaligned = 0; + unsigned int DstUnaligned = 0; + + XDmaPs_ChanCtrl *ChanCtrl; + XDmaPs_ChanCtrl WordChanCtrl; + static XDmaPs_ChanCtrl Mem2MemByteCC; + + Mem2MemByteCC.EndianSwapSize = 0; + Mem2MemByteCC.DstCacheCtrl = 0; + Mem2MemByteCC.DstProtCtrl = 0; + Mem2MemByteCC.DstBurstLen = 1; + Mem2MemByteCC.DstBurstSize = 1; + Mem2MemByteCC.DstInc = 1; + Mem2MemByteCC.SrcCacheCtrl = 0; + Mem2MemByteCC.SrcProtCtrl = 0; + Mem2MemByteCC.SrcBurstLen = 1; + Mem2MemByteCC.SrcBurstSize = 1; + Mem2MemByteCC.SrcInc = 1; + + ChanCtrl = &Cmd->ChanCtrl; + + /* insert DMAMOV for SAR and DAR */ + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_SAR, + SrcAddr); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_DAR, + DstAddr); + + + if (ChanCtrl->SrcInc) + SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize; + + if (ChanCtrl->DstInc) + DstUnaligned = DstAddr % ChanCtrl->DstBurstSize; + + if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) { + ChanCtrl = &Mem2MemByteCC; + } + + if (ChanCtrl->SrcInc) { + MemBurstSize = ChanCtrl->SrcBurstSize; + MemAddr = SrcAddr; + + } else if (ChanCtrl->DstInc) { + MemBurstSize = ChanCtrl->DstBurstSize; + MemAddr = DstAddr; + } + + /* check whether the head is aligned or not */ + Unaligned = MemAddr % MemBurstSize; + + if (Unaligned) { + /* if head is unaligned, transfer head in bytes */ + UnalignedCount = MemBurstSize - Unaligned; + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + for (Index = 0; Index < UnalignedCount; Index++) { + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + } + + DmaLength -= UnalignedCount; + } + + /* now the burst transfer part */ + CCRValue = XDmaPs_ToCCRValue(ChanCtrl); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen; + + LoopCount = DmaLength / BurstBytes; + TailBytes = DmaLength % BurstBytes; + + /* + * the loop count register is 8-bit wide, so if we need + * a larger loop, we need to have nested loops + */ + if (LoopCount > 256) { + LoopCount1 = LoopCount / 256; + if (LoopCount1 > 256) { + xil_printf("DMA operation cannot fit in a 2-level " + "loop for channel %d, please reduce the " + "DMA length or increase the burst size or " + "length", + Channel); + return 0; + } + LoopResidue = LoopCount % 256; + + if (LoopCount1 > 1) + DmaProgBuf += + XDmaPs_ConstructNestedLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount1, + 256); + else + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + 256); + + /* there will be some that cannot be covered by + * nested loops + */ + LoopCount = LoopResidue; + } + + if (LoopCount > 0) { + DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount); + } + + if (TailBytes) { + /* handle the tail */ + TailWords = TailBytes / MemBurstSize; + TailBytes = TailBytes % MemBurstSize; + + if (TailWords) { + WordChanCtrl = *ChanCtrl; + /* + * if we can transfer the tail in words, we will + * transfer words as much as possible + */ + WordChanCtrl.SrcBurstSize = MemBurstSize; + WordChanCtrl.SrcBurstLen = 1; + WordChanCtrl.DstBurstSize = MemBurstSize; + WordChanCtrl.DstBurstLen = 1; + + + /* + * the burst length is 1 + */ + CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailWords); + + } + + if (TailBytes) { + /* + * for the rest, we'll tranfer in bytes + */ + /* + * So far just to be safe, the tail bytes + * are transfered in a loop. We can optimize a little + * to perform a burst. + */ + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailBytes); + + } + } + + DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan); + DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf); + + DmaProgBytes = DmaProgBuf - DmaProgStart; + + Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes); + + return DmaProgBytes; + +} + + +/****************************************************************************/ +/** +* +* Generate a DMA program based for the DMA command, the buffer will be pointed +* by the GeneratedDmaProg field of the command. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* +* @return - XST_SUCCESS on success. +* - XST_FAILURE if it fails +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + void *Buf; + int ProgLen; + XDmaPs_ChannelData *ChanData; + XDmaPs_ChanCtrl *ChanCtrl; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + ChanData = InstPtr->Chans + Channel; + ChanCtrl = &Cmd->ChanCtrl; + + if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen + != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) { + return XST_FAILURE; + } + + + /* + * unaligned fixed address is not supported + */ + if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) { + return XST_FAILURE; + } + + if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) { + return XST_FAILURE; + } + + Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool); + if (Buf == NULL) { + return XST_FAILURE; + } + + Cmd->GeneratedDmaProg = Buf; + ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd, + InstPtr->CacheLength); + Cmd->GeneratedDmaProgLength = ProgLen; + + +#ifdef XDMAPS_DEBUG + XDmaPs_Print_DmaProg(Cmd); +#endif + + if (ProgLen <= 0) { + /* something wrong, release the buffer */ + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProgLength = 0; + Cmd->GeneratedDmaProg = NULL; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** + * Free the DMA program buffer that is pointed by the GeneratedDmaProg field + * of the command. + * + * @param InstPtr is then DMA instance. + * @param Channel is the DMA channel number. + * @param Cmd is the DMA command. + * + * @return XST_SUCCESS on success. + * XST_FAILURE if there is any error. + * + * @note None. + * + ****************************************************************************/ +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + + void *Buf; + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + Buf = (void *)Cmd->GeneratedDmaProg; + ChanData = InstPtr->Chans + Channel; + + if (Buf) { + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProg = 0; + Cmd->GeneratedDmaProgLength = 0; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* Start a DMA command. The command can only be invoked when the channel +* is idle. The driver takes the command, generates DMA program if needed, +* then pass the program to DMAC to execute. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* @param HoldDmaProg is tag indicating whether the driver can release +* the allocated DMA buffer or not. If a user wants to examine the +* generated DMA program, the flag should be set to 1. After the +* DMA program is finished, a user needs to explicity free the +* buffer. +* +* @return +* - XST_SUCCESS on success +* - XST_DEVICE_BUSY if DMA is busy +* - XST_FAILURE on other failures +* +* @note None. +* +****************************************************************************/ +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg) +{ + int Status; + u32 DmaProg = 0; + u32 Inten; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + Cmd->DmaStatus = XST_FAILURE; + + if (XDmaPs_IsActive(InstPtr, Channel)) + return XST_DEVICE_BUSY; + + if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) { + Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd); + if (Status) + return XST_FAILURE; + } + + InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg; + + if (Cmd->UserDmaProg) + DmaProg = (u32)Cmd->UserDmaProg; + else if (Cmd->GeneratedDmaProg) + DmaProg = (u32)Cmd->GeneratedDmaProg; + + if (DmaProg) { + /* enable the interrupt */ + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + Inten |= 0x01 << Channel; /* set the correpsonding bit */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET, + Inten); + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + + InstPtr->Chans[Channel].DmaCmdToHw = Cmd; + + if (Cmd->ChanCtrl.SrcInc) { + Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length); + } + if (Cmd->ChanCtrl.DstInc) { + Xil_DCacheInvalidateRange(Cmd->BD.DstAddr, + Cmd->BD.Length); + } + + Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress, + Channel, DmaProg); + } + else { + InstPtr->Chans[Channel].DmaCmdToHw = NULL; + Status = XST_FAILURE; + } + + return Status; +} + +/****************************************************************************/ +/** +* +* Checks whether the DMA channel is active or idle. +* +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel number. +* +* @return 0: if the channel is idle +* 1: otherwise +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + /* Need to assert Channel is in range */ + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return 0; + + return InstPtr->Chans[Channel].DmaCmdToHw != NULL; +} + + + +/****************************************************************************/ +/** +* +* Allocate a buffer of the DMA program buffer from the pool. +* +* @param Pool the DMA program pool. +* +* @return The allocated buffer, NULL if there is any error. +* +* @note None. +* +*****************************************************************************/ +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool) +{ + int Index; + + Xil_AssertNonvoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (!Pool[Index].Allocated) { + Pool[Index].Allocated = 1; + return Pool[Index].Buf; + } + } + + return NULL; + +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 0. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 0); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 1. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_1(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 1); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 2. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_2(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 2); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 3. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_3(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 3); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 4. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_4(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 4); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 5. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_5(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 5); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 6. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_6(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 6); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 7. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_7(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 7); +} + +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif + +/****************************************************************************/ +/** +* Use the debug registers to kill the DMA thread. +* +* @param BaseAddr is DMA device base address. +* @param Channel is the DMA channel number. +* @param Thread is Debug thread encoding. +* 0: DMA manager thread, 1: DMA channel. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread) +{ + u32 DbgInst0; + int WaitCount; + + DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread); + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + if (WaitCount >= XDMAPS_MAX_WAIT) { + /* wait time out */ + xil_printf("PL330 device at %x debug status busy time out\n", + BaseAddr); + + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0); + + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + +/****************************************************************************/ +/** +* +* +* Free a buffer of the DMA program buffer. +* @param Pool the DMA program pool. +* @param Buf the DMA program buffer to be release. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf) +{ + int Index; + Xil_AssertVoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (Pool[Index].Buf == Buf) { + if (Pool[Index].Allocated) { + Pool[Index].Allocated = 0; + } + } + } +} + +/*****************************************************************************/ +/** +* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel. +* +* @param BaseAddr PL330 device base address +* @param Channel Channel number for the device +* @param DmaProg DMA program starting address, this should be DMA address +* +* @return 0 on success, -1 on time out +* +* @note None. +* +****************************************************************************/ +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) +{ + char DmaGoProg[8]; + u32 DbgInst0; + u32 DbgInst1; + + int WaitCount; + + XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0); + + DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0); + DbgInst1 = (u32)DmaProg; + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) { + + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + /* write debug instruction 1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1); + + + /* wait while the DMA Manager is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, + XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) + != XDMAPS_DS_DMA_STATUS_STOPPED + && WaitCount <= XDMAPS_MAX_WAIT) { + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + + +/****************************************************************************/ +/** +* +* It's the generic Done ISR. +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel numer. +* +* @return None.* +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) +{ + + void *DmaProgBuf; + XDmaPs_ChannelData *ChanData; + XDmaPs_Cmd *DmaCmd; + //u32 Value; + + ChanData = InstPtr->Chans + Channel; + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + /* clear the interrupt status */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTCLR_OFFSET, + 1 << ChanData->ChanId); + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + + DmaCmd = ChanData->DmaCmdToHw; + if (DmaCmd) { + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + DmaCmd->DmaStatus = 0; + ChanData->DmaCmdToHw = NULL; + ChanData->DmaCmdFromHw = DmaCmd; + + if (ChanData->DoneHandler) + ChanData->DoneHandler(Channel, DmaCmd, + ChanData->DoneRef); + } + +} + + +/****************************************************************************/ +/** +* Prints the content of the buffer in bytes +* @param Buf is the buffer. +* @param Length is the length of the DMA program. +* +* @return None. +* +* @note None. +****************************************************************************/ +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) +{ + int Index; + for (Index = 0; Index < Length; Index++) + xil_printf("[%x] %x\r\n", Index, Buf[Index]); + +} +/****************************************************************************/ +/** +* Print the Dma Prog Contents. +* +* @param Cmd is the command buffer. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ + void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) +{ + if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) { + xil_printf("Generated DMA program (%d):\r\n", + Cmd->GeneratedDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg, + Cmd->GeneratedDmaProgLength); + } + + if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) { + xil_printf("User defined DMA program (%d):\r\n", + Cmd->UserDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg, + Cmd->UserDmaProgLength); + } +} + + +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h new file mode 100644 index 0000000..5a0c1a2 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h @@ -0,0 +1,352 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* @addtogroup dmaps_v2_3 +* @{ +* @details +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * To avoid linking error,Declare all inline functions as extern for + * IAR compiler + */ +#ifdef __ICCARM__ +extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg); +extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c new file mode 100644 index 0000000..3bfe837 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c @@ -0,0 +1,59 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdmaps.h" + +/* +* The configuration table for devices +*/ + +XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_DMA_NS_DEVICE_ID, + XPAR_PS7_DMA_NS_BASEADDR + }, + { + XPAR_PS7_DMA_S_DEVICE_ID, + XPAR_PS7_DMA_S_BASEADDR + } +}; + + diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c new file mode 100644 index 0000000..4c0cfbf --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c @@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_hw.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the implementation of the interface reset functionality +* for XDmaPs driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif +/************************** Function Prototypes *****************************/ + +/************************** Variable Definitions ****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given dmaps interface by +* configuring the appropriate control bits in the dmaps specifc registers +* the dmaps reset squence involves the following steps +* Disable all the interuupts +* Clear the pending interrupts +* Kill all the active channel threads +* Kill the manager thread +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* dmaps controller +******************************************************************************/ +void XDmaPs_ResetHw(u32 BaseAddress) +{ + u32 DbgInst; + u32 WaitCount = 0; + u32 ChanIndex; + + /* Disable all the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00); + /* Clear the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK); + /* Kill the dma channel threads */ + for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) { + while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); + } + /* Kill the manager thread */ + DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); +} + + + +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h new file mode 100644 index 0000000..628f1ec --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h @@ -0,0 +1,293 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* @addtogroup dmaps_v2_3 +* @{ +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
    +* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c new file mode 100644 index 0000000..daebd99 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_selftest.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the self-test functions for the XDmaPs driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	hbm 	03/29/2010 First Release
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xdmaps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. This self +* test performs a local loopback and verifies data can be sent and received. +* +* The time for this test is proportional to the baud rate that has been set +* prior to calling this function. +* +* The mode and control registers are restored before return. +* +* @param InstPtr is a pointer to the XDmaPs instance +* +* @return +* +* - XST_SUCCESS if the test was successful +* - XST_FAILURE if the test failed +* +* @note +* +* This function can hang if the hardware is not functioning properly. +* +******************************************************************************/ +int XDmaPs_SelfTest(XDmaPs *InstPtr) +{ + u32 BaseAddr = InstPtr->Config.BaseAddress; + int i; + + if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + return XST_FAILURE; + + for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) { + if (XDmaPs_ReadReg(BaseAddr, + XDmaPs_CSn_OFFSET(i))) + return XST_FAILURE; + } + return XST_SUCCESS; +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c new file mode 100644 index 0000000..b92ee53 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_sinit.c +* @addtogroup dmaps_v2_3 +* @{ +* +* The implementation of the XDmaPs driver's static initialzation +* functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00  hbm  08/13/10 First Release
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xparameters.h" +#include "xdmaps.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ +extern XDmaPs_Config XDmaPs_ConfigTable[]; + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* Looks up the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device +* +* @return +* +* A pointer to the configuration structure or NULL if the specified device +* is not in the system. +* +* @note +* +* None. +* +******************************************************************************/ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId) +{ + XDmaPs_Config *CfgPtr = NULL; + + int i; + + for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) { + if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) { + CfgPtr = &XDmaPs_ConfigTable[i]; + break; + } + } + + return CfgPtr; +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/Makefile new file mode 100644 index 0000000..7002e62 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xemacps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling emacps" + +xemacps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xemacps_includes + +xemacps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.c new file mode 100644 index 0000000..c3e8d39 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.c @@ -0,0 +1,492 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps.c +* @addtogroup emacps_v3_4 +* @{ +* +* The XEmacPs driver. Functions in this file are the minimum required functions +* for this driver. See xemacps.h for a detailed description of the driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5  hk   08/14/17 Update cache coherency information of the interface in
+*                    its config structure.
+*
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xemacps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void XEmacPs_StubHandler(void); /* Default handler routine */ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* Initialize a specific XEmacPs instance/driver. The initialization entails: +* - Initialize fields of the XEmacPs instance structure +* - Reset hardware and apply default options +* - Configure the DMA channels +* +* The PHY is setup independently from the device. Use the MII or whatever other +* interface may be present for setup. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param CfgPtr is the device configuration structure containing required +* hardware build data. +* @param EffectiveAddress is the base address of the device. If address +* translation is not utilized, this parameter can be passed in using +* CfgPtr->Config.BaseAddress to specify the physical base address. +* +* @return +* - XST_SUCCESS if initialization was successful +* +******************************************************************************/ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, + UINTPTR EffectiveAddress) +{ + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + + /* Set device base address and ID */ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; + + /* Set callbacks to an initial stub routine */ + InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler)); + InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler); + InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler); + + /* Reset the hardware and set default options */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + XEmacPs_Reset(InstancePtr); + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** +* Start the Ethernet controller as follows: +* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set +* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set +* - Start the SG DMA send and receive channels and enable the device +* interrupt +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return N/A +* +* @note +* Hardware is configured with scatter-gather DMA, the driver expects to start +* the scatter-gather channels and expects that the user has previously set up +* the buffer descriptor lists. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and Set/ClearOptions functions. So if one task might be setting +* device options while another is trying to start the device, the user is +* required to provide protection of this shared data (typically using a +* semaphore). +* +* This function must not be preempted by an interrupt that may service the +* device. +* +******************************************************************************/ +void XEmacPs_Start(XEmacPs *InstancePtr) +{ + u32 Reg; + + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Start DMA */ + /* When starting the DMA channels, both transmit and receive sides + * need an initialized BD list. + */ + if (InstancePtr->Version == 2) { + Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); + Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + InstancePtr->RxBdRing.BaseBdAddr); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + InstancePtr->TxBdRing.BaseBdAddr); + } + + /* clear any existed int status */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Enable transmitter if not already enabled */ + if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK); + } + } + + /* Enable receiver if not already enabled */ + if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK); + } + } + + /* Enable TX and RX interrupts */ + XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | + XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK | + (u32)XEMACPS_IXR_TXCOMPL_MASK)); + + /* Enable TX Q1 Interrupts */ + if (InstancePtr->Version > 2) + XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); + + /* Mark as started */ + InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; + + return; +} + + +/*****************************************************************************/ +/** +* Gracefully stop the Ethernet MAC as follows: +* - Disable all interrupts from this device +* - Stop DMA channels +* - Disable the tansmitter and receiver +* +* Device options currently in effect are not changed. +* +* This function will disable all interrupts. Default interrupts settings that +* had been enabled will be restored when XEmacPs_Start() is called. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @note +* This function makes use of internal resources that are shared between the +* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be +* setting device options while another is trying to start the device, the user +* is required to provide protection of this shared data (typically using a +* semaphore). +* +* Stopping the DMA channels causes this function to block until the DMA +* operation is complete. +* +******************************************************************************/ +void XEmacPs_Stop(XEmacPs *InstancePtr) +{ + u32 Reg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Disable all interrupts */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Disable the receiver & transmitter */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Mark as stopped */ + InstancePtr->IsStarted = 0U; +} + + +/*****************************************************************************/ +/** +* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the +* transmitter, and the receiver. +* +* Steps to reset +* - Stops transmit and receive channels +* - Stops DMA +* - Configure transmit and receive buffer size to default +* - Clear transmit and receive status register and counters +* - Clear all interrupt sources +* - Clear phy (if there is any previously detected) address +* - Clear MAC addresses (1-4) as well as Type IDs and hash value +* +* All options are placed in their default state. Any frames in the +* descriptor lists will remain in the lists. The side effect of doing +* this is that after a reset and following a restart of the device, frames +* were in the list before the reset may be transmitted or received. +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required, the driver notifies the upper layer software of +* this need through the ErrorHandler callback and specific status codes. +* The upper layer software is responsible for calling this Reset function +* and then re-configuring the device. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +******************************************************************************/ +void XEmacPs_Reset(XEmacPs *InstancePtr) +{ + u32 Reg; + u8 i; + s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Stop the device and reset hardware */ + XEmacPs_Stop(InstancePtr); + InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; + + InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC); + + InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF; + + InstancePtr->MaxMtuSize = XEMACPS_MTU; + InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE + + XEMACPS_TRL_SIZE; + InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize + + XEMACPS_HDR_VLAN_SIZE; + InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK; + + /* Setup hardware with default values */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEMACPS_NWCTRL_STATCLR_MASK | + XEMACPS_NWCTRL_MDEN_MASK) & + (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK)); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET); + Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK; + + Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK | + (u32)XEMACPS_NWCFG_FDEN_MASK | + (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK; + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET, Reg); + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | + XEMACPS_NWCFG_DWIDTH_64_MASK)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_DMACR_OFFSET, + (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) + + (((((u32)XEMACPS_RX_BUF_SIZE % + (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) << + (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) & + (u32)(XEMACPS_DMACR_RXBUF_MASK)) | + (u32)XEMACPS_DMACR_RXSIZE_MASK | + (u32)XEMACPS_DMACR_TXSIZE_MASK); + + + /* Single bursts */ + /* FIXME: Why Single bursts? */ + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | +#ifdef __aarch64__ + (u32)XEMACPS_DMACR_ADDR_WIDTH_64 | +#endif + (u32)XEMACPS_DMACR_INCR16_AHB_BURST)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXSR_OFFSET, 0x0U); + + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); + if (InstancePtr->Version > 2) + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXSR_OFFSET, 0x0U); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_ISR_OFFSET); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + Reg); + + XEmacPs_ClearHash(InstancePtr); + + for (i = 1U; i < 5U; i++) { + (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); + (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i); + } + + /* clear all counters */ + for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U); + i++) { + (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4))); + } + + /* Disable the receiver */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Sync default options with hardware but leave receiver and + * transmitter disabled. They get enabled with XEmacPs_Start() if + * XEMACPS_TRANSMITTER_ENABLE_OPTION and + * XEMACPS_RECEIVER_ENABLE_OPTION are set. + */ + (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & + ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | + (u32)XEMACPS_RECEIVER_ENABLE_OPTION)); + + (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); +} + + +/******************************************************************************/ +/** + * This is a stub for the asynchronous callbacks. The stub is here in case the + * upper layer forgot to set the handler(s). On initialization, all handlers are + * set to this callback. It is considered an error for this handler to be + * invoked. + * + ******************************************************************************/ +void XEmacPs_StubHandler(void) +{ + Xil_AssertVoidAlways(); +} + +/*****************************************************************************/ +/** +* This function sets the start address of the transmit/receive buffer queue. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @QPtr Address of the Queue to be written +* @QueueNum Buffer Queue Index +* @Direction Transmit/Recive +* +* @note +* The buffer queue addresses has to be set before starting the transfer, so +* this function has to be called in prior to XEmacPs_Start() +* +******************************************************************************/ +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction) +{ + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* If already started, then there is nothing to do */ + if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) { + return; + } + + if (QueueNum == 0x00U) { + if (Direction == XEMACPS_SEND) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } + } + else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQ1BASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } +#ifdef __aarch64__ + if (Direction == XEMACPS_SEND) { + /* Set the MSB of TX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_TXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } else { + /* Set the MSB of RX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_RXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } +#endif +} +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.h new file mode 100644 index 0000000..a19b7a1 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps.h @@ -0,0 +1,806 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps_v3_4 +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ *
+ *
    + * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bd.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bd.h new file mode 100644 index 0000000..11f4a75 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bd.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps_v3_4 +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ *
    + * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#define XEMACPS_BD_NUM_WORDS 4U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#define XEMACPS_BD_NUM_WORDS 2U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.c new file mode 100644 index 0000000..e53db02 --- /dev/null +++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.c @@ -0,0 +1,1075 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.c +* @addtogroup emacps_v3_4 +* @{ +* +* This file implements buffer descriptor ring related functions. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_cache.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************************************************************** + * Compute the virtual address of a descriptor from its physical address + * + * @param BdPtr is the physical address of the BD + * + * @returns Virtual address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ + ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Compute the physical address of a descriptor from its virtual address + * + * @param BdPtr is the physical address of the BD + * + * @returns Physical address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ + ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around + * to the beginning of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is greater than + * the high address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr += ((RingPtr)->Separation * (NumBd)); \ + if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \ + { \ + Addr -= (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \ + } + +/**************************************************************************** + * Move the BdPtr argument backwards an arbitrary number of BDs wrapping + * around to the end of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is less than + * the base address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr -= ((RingPtr)->Separation * (NumBd)); \ + if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \ + { \ + Addr += (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \ + } + + +/************************** Function Prototypes ******************************/ + +static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr); +static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr); + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** + * Using a memory segment allocated by the caller, create and setup the BD list + * for the given DMA channel. + * + * @param RingPtr is the instance to be worked on. + * @param PhysAddr is the physical base address of user memory region. + * @param VirtAddr is the virtual base address of the user memory region. If + * address translation is not being utilized, then VirtAddr should be + * equivalent to PhysAddr. + * @param Alignment governs the byte alignment of individual BDs. This function + * will enforce a minimum alignment of 4 bytes with no maximum as long + * as it is specified as a power of 2. + * @param BdCount is the number of BDs to setup in the user memory region. It + * is assumed the region is large enough to contain the BDs. + * + * @return + * + * - XST_SUCCESS if initialization was successful + * - XST_NO_FEATURE if the provided instance is a non DMA type + * channel. + * - XST_INVALID_PARAM under any of the following conditions: + * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment + * parameter. + * 2) Alignment parameter does not meet minimum requirements or is not a + * power of 2 value. + * 3) BdCount is 0. + * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans + * over address 0x00000000 in virtual address space. + * + * @note + * Make sure to pass in the right alignment value. + *****************************************************************************/ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount) +{ + u32 i; + UINTPTR BdVirtAddr; + UINTPTR BdPhyAddr; + UINTPTR VirtAddrLoc = VirtAddr; + + /* In case there is a failure prior to creating list, make sure the + * following attributes are 0 to prevent calls to other functions + * from doing anything. + */ + RingPtr->AllCnt = 0U; + RingPtr->FreeCnt = 0U; + RingPtr->HwCnt = 0U; + RingPtr->PreCnt = 0U; + RingPtr->PostCnt = 0U; + + /* Make sure Alignment parameter meets minimum requirements */ + if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure Alignment is a power of 2 */ + if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure PhysAddr and VirtAddr are on same Alignment */ + if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Is BdCount reasonable? */ + if (BdCount == 0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Figure out how many bytes will be between the start of adjacent BDs */ + RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd)); + + /* Must make sure the ring doesn't span address 0x00000000. If it does, + * then the next/prev BD traversal macros will fail. + */ + if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + /* Initial ring setup: + * - Clear the entire space + * - Setup each BD's BDA field with the physical address of the next BD + */ + (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount)); + + BdVirtAddr = VirtAddrLoc; + BdPhyAddr = PhysAddr + RingPtr->Separation; + for (i = 1U; i < BdCount; i++) { + BdVirtAddr += RingPtr->Separation; + BdPhyAddr += RingPtr->Separation; + } + + /* Setup and initialize pointers and counters */ + RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED); + RingPtr->BaseBdAddr = VirtAddrLoc; + RingPtr->PhysBaseAddr = PhysAddr; + RingPtr->HighBdAddr = BdVirtAddr; + RingPtr->Length = + ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation); + RingPtr->AllCnt = (u32)BdCount; + RingPtr->FreeCnt = (u32)BdCount; + RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc; + RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr; + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Clone the given BD into every BD in the list. + * every field of the source BD is replicated in every BD of the list. + * + * This function can be called only when all BDs are in the free group such as + * they are immediately after initialization with XEmacPs_BdRingCreate(). + * This prevents modification of BDs while they are in use by hardware or the + * user. + * + * @param RingPtr is the pointer of BD ring instance to be worked on. + * @param SrcBdPtr is the source BD template to be cloned into the list. This + * BD will be modified. + * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates + * which direction. + * + * @return + * - XST_SUCCESS if the list was modified. + * - XST_DMA_SG_NO_LIST if a list has not been created. + * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under + * hardware or user control. + * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. + * + *****************************************************************************/ +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction) +{ + u32 i; + UINTPTR CurBd; + + /* Can't do this function if there isn't a ring */ + if (RingPtr->AllCnt == 0x00000000U) { + return (LONG)(XST_DMA_SG_NO_LIST); + } + + /* Can't do this function with the channel running */ + if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) { + return (LONG)(XST_DEVICE_IS_STARTED); + } + + /* Can't do this function with some of the BDs in use */ + if (RingPtr->FreeCnt != RingPtr->AllCnt) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Starting from the top of the ring, save BD.Next, overwrite the entire + * BD with the template, then restore BD.Next + */ + CurBd = RingPtr->BaseBdAddr; + for (i = 0U; i < RingPtr->AllCnt; i++) { + memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); + CurBd += RingPtr->Separation; + } + + CurBd -= RingPtr->Separation; + + if (Direction == XEMACPS_RECV) { + XEmacPs_BdSetRxWrap(CurBd); + } + else { + XEmacPs_BdSetTxWrap(CurBd); + } + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Reserve locations in the BD list. The set of returned BDs may be modified + * in preparation for future DMA transaction(s). Once the BDs are ready to be + * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same + * order which they were allocated here. Example: + * + * 
    + *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * 
    + *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * 
    
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * 
    + *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * 
    
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void) BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
    + *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
    + *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.h
new file mode 100644
index 0000000..5a30ce3
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_bdring.h
@@ -0,0 +1,238 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_4
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_control.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_control.c
new file mode 100644
index 0000000..088a834
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_4
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 
    
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * 
    + * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * 
    
+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK);
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK));
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * 
    + *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * 
    
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * 
    + * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * 
    
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_g.c
new file mode 100644
index 0000000..0987122
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_ETHERNET_0_DEVICE_ID,
+		XPAR_PS7_ETHERNET_0_BASEADDR,
+		XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.c
new file mode 100644
index 0000000..738cd7d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_4
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.h
new file mode 100644
index 0000000..bf35234
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_4
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_intr.c
new file mode 100644
index 0000000..6cc9397
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_4
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+*                     there is no error. CR# 869403
+* 
    
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+
+		if(RegSR != 0) {
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+						XEMACPS_RECV, RegSR);
+		}
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_sinit.c
new file mode 100644
index 0000000..29b2bf6
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/emacps_v3_6/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_4
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
new file mode 100644
index 0000000..8601ce4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
new file mode 100644
index 0000000..7b6fe2e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
@@ -0,0 +1,628 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_SUCCESS;
+	u8 i;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	/* Initialize the Bank data based on platform */
+	if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 *	Max pins in the ZynqMP GPIO device
+		 *	0 - 25,  Bank 0
+		 *	26 - 51, Bank 1
+		 *	52 - 77, Bank 2
+		 *	78 - 109, Bank 3
+		 *	110 - 141, Bank 4
+		 *	142 - 173, Bank 5
+		 */
+		InstancePtr->MaxPinNum = (u32)174;
+		InstancePtr->MaxBanks = (u8)6;
+	} else {
+		/*
+		 *	Max pins in the GPIO device
+		 *	0 - 31,  Bank 0
+		 *	32 - 53, Bank 1
+		 *	54 - 85, Bank 2
+		 *	86 - 117, Bank 3
+		 */
+		InstancePtr->MaxPinNum = (u32)118;
+		InstancePtr->MaxBanks = (u8)4;
+	}
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	for (i=0;iMaxBanks;i++) {
+		XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+	}
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+	u32 DataVar = Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15U) {
+		/* There are only 16 data bits in bit maskable register. */
+		PinNumber -= (u8)16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	DataVar &= (u32)0x01;
+	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(Direction <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction!=(u32)0) { /*  Output Direction */
+		DirModeReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(OpEnable <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable != (u32)0) { /*  Enable Output Enable */
+		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+	u32 XGpioPsPinTable[6] = {0};
+	u32 Platform = XGetPlatform_Info();
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 * This structure defines the mapping of the pin numbers to the banks when
+		 * the driver APIs are used for working on the individual pins.
+		 */
+
+		XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+		XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+		XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+		XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+		XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+		XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 6U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	} else {
+		XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+		XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+		XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+		XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 4U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	}
+	if (*BankNumber == (u8)0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = (u8)((u32)PinNumber %
+					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+	}
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
new file mode 100644
index 0000000..e778f9c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
@@ -0,0 +1,276 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_3
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* 

    
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*       ms   04/05/17 Added tabspace for return statements in functions of
+*                     gpiops examples for proper documentation while
+*                     generating doxygen.
+* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
+*                     for zcu102 and zc702 boards in polled and interrupt
+*                     example, configured Interrupt pin to input pin for
+*                     proper functioning of interrupt example.
+* 
    
+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
+										*	Zynq Ultrascale+ MP GPIO device
+										*/
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
+						  *	Zynq Ultrascale+ MP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+	u32 Platform;			/**< Platform data */
+	u32 MaxPinNum;			/**< Max pins in the GPIO device */
+	u8 MaxBanks;			/**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
new file mode 100644
index 0000000..25b9b1f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_GPIO_0_DEVICE_ID,
+		XPAR_PS7_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
new file mode 100644
index 0000000..8961c42
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains low level GPIO functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+	u32 Platform,MaxBanks;
+
+	Platform = XGetPlatform_Info();
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		MaxBanks = (u32)6;
+	} else {
+		MaxBanks = (u32)4;
+	}
+	/* Write reset values to all mask data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+	}
+	/* Write reset values to all output data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0U);
+	}
+
+	/* Reset all registers of all GPIO banks */
+	for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0U);
+	}
+
+	/* Bank 0 Int type */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/* Bank 1 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/* Bank 2 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/* Bank 3 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/* Bank 4 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK4_RESET);
+		/* Bank 5 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK5_RESET);
+	}
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
new file mode 100644
index 0000000..ff01906
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 
    
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
new file mode 100644
index 0000000..a8b0a56
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg =  ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	/* Clear the currently pending interrupts. */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	/* Clear the specified pending interrupts. */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= ((u32)1 << PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		default:
+			/**< Default statement is added for MISRA C compliance. */
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+	if (IntrType == ((u32)1 << PinNumber)) {
+
+		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+		if (IntrOnAny == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+		if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPointer;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != (u32)0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+							(IntrStatus & IntrEnabled));
+			InstancePtr->Handler(InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+	(void) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
new file mode 100644
index 0000000..378524c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the Interrupts for Bank 0 . */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
new file mode 100644
index 0000000..4cc0c39
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
new file mode 100644
index 0000000..3600928
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspips_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspips"
+
+xqspips_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspips_includes
+
+xqspips_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
new file mode 100644
index 0000000..c33322c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
@@ -0,0 +1,1571 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added logic to XQspiPs_GetReadData to handle data
+*		     shift for normal data reads and instruction/status
+*		     reads differently based on the ShiftReadData flag.
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+*		     This version of the driver fixes CRs 670197/663787.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk  05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+*			 function
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk  09/05/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+	u8 OpCode;	/**< Operational code of the instruction */
+	u8 InstSize;	/**< Size of the instruction including address bytes */
+	u8 TxOffset;	/**< Register address where instruction has to be
+			     written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array)		(sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+	{ XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+	/* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Master mode
+*   - Active high clock polarity
+*   - Clock phase 0
+*   - Baud rate divisor 2
+*   - Transfer width 32
+*   - Master reference clock = pclk
+*   - No chip select active
+*   - Manual CS and Manual Start disabled
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPI device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->StatusHandler = StubStatusHandler;
+
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+	/*
+	 * Reset the QSPI device to get it into its initial state. It is
+	 * expected that device configuration will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress
+	 */
+	XQspiPs_Abort(InstancePtr);
+
+	/*
+	 * Write default value to configuration register.
+	 * Do not modify reserved bits.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+	u32 IsLock;
+
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * QSPI Software Reset
+	 */
+	IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+				SLCR_UNLOCK_MASK);
+	}
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+			LQSPI_RST_CTRL_MASK);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+				SLCR_LOCK_MASK);
+	}
+
+	/*
+	 * Set the RX and TX FIFO threshold to reset value (one)
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
    +*   XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+* 
    
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+*
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+			u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	unsigned int Index;
+	u8 TransCount = 0;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+
+	CurrInst = &NewInst[0];
+
+	/*
+	 * The RecvBufPtr argument can be null
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared in the ISR when the
+	 * transfer is entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	/*
+	 * Clear all the interrrupts.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used
+		 * The InstSize mentioned in case of instructions greater than
+		 * 4 bytes is not the actual size, but is indicative of
+		 * the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 CurrInst->TxOffset, Data);
+	TransCount++;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Fill the Tx FIFO with as many bytes as it takes (or as many as
+	 * we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_TXD_00_OFFSET,
+				  *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		TransCount++;
+	}
+
+	/*
+	 * Enable QSPI interrupts (connecting to the interrupt controller and
+	 * enabling interrupts should have been done by the caller).
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+			  XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+			  XQSPIPS_IXR_TXUF_MASK);
+
+	/*
+	 * If, in Manual Start mode, Start the transfer.
+	 */
+	if (XQspiPs_IsManualStart(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
    +*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+*
+* 
    
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	u8 TransCount;
+	unsigned int Index;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+	u8 IsManualStart = FALSE;
+	u32 RxCount = 0;
+
+	CurrInst = &NewInst[0];
+	/*
+	 * The RecvBufPtr argument can be NULL.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used.
+		 * The InstSize mentioned in case of instructions greater than 4 bytes
+		 * is not the actual size, but is indicative of the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+	TransCount = 0;
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					CurrInst->TxOffset, Data);
+	++TransCount;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Check if manual start is selected and store it in a
+	 * local varibale for reference. This is to avoid reading
+	 * the config register everytime.
+	 */
+	IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+	/*
+	 * Fill the DTR/FIFO with as many bytes as it will take (or as
+	 * many as we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_TXD_00_OFFSET,
+				 *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		++TransCount;
+	}
+
+	while((InstancePtr->RemainingBytes > 0) ||
+	      (InstancePtr->RequestedBytes > 0)) {
+
+		/*
+		 * Fill the TX FIFO with RX threshold no. of entries (or as
+		 * many as we have to send, in case that's less).
+		 */
+		while ((InstancePtr->RemainingBytes > 0) &&
+			(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_TXD_00_OFFSET,
+					 *((u32 *)InstancePtr->SendBufferPtr));
+			InstancePtr->SendBufferPtr += 4;
+			InstancePtr->RemainingBytes -= 4;
+			if (InstancePtr->RemainingBytes < 0) {
+				InstancePtr->RemainingBytes = 0;
+			}
+			++TransCount;
+		}
+
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (IsManualStart == TRUE) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Reset TransCount - this is only used to fill TX FIFO
+		 * in the above loop;
+		 * RxCount is used to keep track of data received
+		 */
+		TransCount = 0;
+
+		/*
+		 * Wait for RX FIFO to reach threshold (or)
+		 * TX FIFO to become empty.
+		 * The latter check is required for
+		 * small transfers (<32 words) and
+		 * when the last chunk in a large data transfer is < 32 words.
+		 */
+
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+			((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
+
+		/*
+		 * A transmit has just completed. Process received data
+		 * and check for more data to transmit.
+		 * First get the data received as a result of the
+		 * transmit that just completed. Receive data based on the
+		 * count obtained while filling tx fifo. Always get
+		 * the received data, but only fill the receive
+		 * buffer if it points to something (the upper layer
+		 * software may not care to receive data).
+		 */
+		while ((InstancePtr->RequestedBytes > 0) &&
+			(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
+			u32 Data;
+
+			RxCount++;
+
+			if (InstancePtr->RecvBufferPtr != NULL) {
+				if (InstancePtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(InstancePtr, Data,
+						InstancePtr->RequestedBytes);
+				} else {
+					(*(u32 *)InstancePtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					InstancePtr->RecvBufferPtr += 4;
+					InstancePtr->RequestedBytes -= 4;
+					if (InstancePtr->RequestedBytes < 0) {
+						InstancePtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				InstancePtr->RequestedBytes -= 4;
+			}
+		}
+		RxCount = 0;
+	}
+
+	/*
+	 * If the Slave select lines are being manually controlled, disable
+	 * them because the transfer is complete.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	/*
+	 * Clear the busy flag.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	/*
+	 * Disable the device.
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * Reset the RX FIFO threshold to one
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+* @param	Address is the starting address within the flash from
+*		from where data needs to be read.
+* @param	ByteCount contains the number of bytes to receive.
+*
+* @return
+*		- XST_SUCCESS if read is performed
+*		- XST_FAILURE if Linear mode is not set
+*
+* @note		None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RecvBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define	XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+	/*
+	 * Enable the controller
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+		XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+		memcpy((void*)RecvBufPtr,
+		      (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+		       Address),
+		      (size_t)ByteCount);
+		return XST_SUCCESS;
+	} else {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Disable the controller
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- XST_SUCCESS if the slave is selected or deselected
+*		  successfully.
+*		- XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+*		  changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Select the slave
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+	ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET, ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
    +*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPI device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* 
    
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+*   transmit register or FIFO is empty. The driver uses this interrupt during a
+*   transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+*   the QSPI device, when configured as a slave, attempts to read an empty
+*   DTR/FIFO.  An empty DTR/FIFO usually means that software is not giving the
+*   device data in a timely manner. No action is taken by the driver other than
+*   to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+*   QSPI device attempts to write a received byte to an already full DRR/FIFO.
+*   A full DRR/FIFO usually means software is not emptying the data in a timely
+*   manner.  No action is taken by the driver other than to inform the upper
+*   layer software of the error.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+	XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+	u32 IntrStatus;
+	u32 ConfigReg;
+	u32 Data;
+	u32 TransCount;
+	u32 Count = 0;
+	unsigned BytesDone; /* Number of bytes done so far. */
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Immediately clear the interrupts in case the ISR causes another
+	 * interrupt to be generated. If we clear at the end of the ISR,
+	 * we may miss newly generated interrupts. This occurs because we
+	 * transmit from within the ISR, which could potentially cause another
+	 * TX_EMPTY interrupt.
+	 */
+	IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+				      XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			  (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+			XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+			XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+	if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+		(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+		/*
+		 * Rx FIFO has just reached threshold no. of entries.
+		 * Read threshold no. of entries from RX FIFO
+		 * Another possiblity of entering this loop is when
+		 * the last byte has been transmitted and TX FIFO is empty,
+		 * in which case, read all the data from RX FIFO.
+		 * Always get the received data, but only fill the
+		 * receive buffer if it is not null (it can be null when
+		 * the device does not care to receive data).
+		 */
+		TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		if (TransCount % 4) {
+			TransCount = TransCount/4 + 1;
+		} else {
+			TransCount = TransCount/4;
+		}
+
+		while ((Count < TransCount) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+			if (QspiPtr->RecvBufferPtr != NULL) {
+				if (QspiPtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(QspiPtr, Data,
+						QspiPtr->RequestedBytes);
+				} else {
+					(*(u32 *)QspiPtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					QspiPtr->RecvBufferPtr += 4;
+					QspiPtr->RequestedBytes -= 4;
+					if (QspiPtr->RequestedBytes < 0) {
+						QspiPtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				QspiPtr->RequestedBytes -= 4;
+				if (QspiPtr->RequestedBytes < 0) {
+					QspiPtr->RequestedBytes = 0;
+				}
+
+			}
+			Count++;
+		}
+		Count = 0;
+		/*
+		 * Interrupt asserted as TX_OW got asserted
+		 * See if there is more data to send.
+		 * Fill TX FIFO with RX threshold no. of entries or
+		 * remaining entries (in case that is less than threshold)
+		 */
+		while ((QspiPtr->RemainingBytes > 0) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			/*
+			 * Send more data.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_TXD_00_OFFSET,
+				*((u32 *)QspiPtr->SendBufferPtr));
+			QspiPtr->SendBufferPtr += 4;
+			QspiPtr->RemainingBytes -= 4;
+			if (QspiPtr->RemainingBytes < 0) {
+				QspiPtr->RemainingBytes = 0;
+			}
+
+			Count++;
+		}
+
+		if ((QspiPtr->RemainingBytes == 0) &&
+			(QspiPtr->RequestedBytes == 0)) {
+			/*
+			 * No more data to send.  Disable the interrupt
+			 * and inform the upper layer software that the
+			 * transfer is done. The interrupt will be re-enabled
+			 * when another transfer is initiated.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_IDR_OFFSET,
+					  XQSPIPS_IXR_RXNEMPTY_MASK |
+					  XQSPIPS_IXR_TXOW_MASK |
+					  XQSPIPS_IXR_RXOVR_MASK |
+					  XQSPIPS_IXR_TXUF_MASK);
+
+			/*
+			 * If the Slave select is being manually controlled,
+			 * disable it because the transfer is complete.
+			 */
+			if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+						QspiPtr->Config.BaseAddress,
+						XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+				XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+						  XQSPIPS_CR_OFFSET,
+						   ConfigReg);
+			}
+
+			/*
+			 * Clear the busy flag.
+			 */
+			QspiPtr->IsBusy = FALSE;
+
+			/*
+			 * Disable the device.
+			 */
+			XQspiPs_Disable(QspiPtr);
+
+			/*
+			 * Reset the RX FIFO threshold to one
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+			QspiPtr->StatusHandler(QspiPtr->StatusRef,
+						XST_SPI_TRANSFER_DONE,
+						QspiPtr->RequestedBytes);
+		} else {
+			/*
+			 * Enable the TXOW interrupt.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					 XQSPIPS_IER_OFFSET,
+					 XQSPIPS_IXR_RXNEMPTY_MASK |
+					 XQSPIPS_IXR_TXOW_MASK |
+					 XQSPIPS_IXR_RXOVR_MASK |
+					 XQSPIPS_IXR_TXUF_MASK);
+			/*
+			 * If, in Manual Start mode, start the transfer.
+			 */
+			if (XQspiPs_IsManualStart(QspiPtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+				XQspiPs_WriteReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+			}
+		}
+	}
+
+	/*
+	 * Check for overflow and underflow errors.
+	 */
+	if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		QspiPtr->IsBusy = FALSE;
+
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+			XST_SPI_RECEIVE_OVERRUN, BytesDone);
+	}
+
+	if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+		QspiPtr->IsBusy = FALSE;
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+				      XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Data is the data which needs to be copied to the Rx buffer.
+* @param	Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+	u8 DataByte3;
+
+	if (InstancePtr->RecvBufferPtr) {
+		switch (Size) {
+		case 1:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFF000000) >> 24);
+			} else {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFF);
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		case 2:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFFFF0000) >> 16);
+			} else 	{
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+			}
+			InstancePtr->RecvBufferPtr += 2;
+			break;
+		case 3:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0x00FFFF00) >> 8);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0xFF000000) >> 24);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			} else {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0x00FF0000) >> 16);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		default:
+			/* This will never execute */
+			break;
+		}
+	}
+	InstancePtr->ShiftReadData  = 0;
+	InstancePtr->RequestedBytes -= Size;
+	if (InstancePtr->RequestedBytes < 0) {
+		InstancePtr->RequestedBytes = 0;
+	}
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
new file mode 100644
index 0000000..139ce4d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
@@ -0,0 +1,799 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_4
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+*  Linear Mode 
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device.  The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+*	  static configuration structure defined in xqspips_g.c. This is setup
+*	  by the tools. For some operating systems the config structure will be
+*	  initialized by the software and this call is not needed.
+*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	  configuration structure provided by the caller. If running in a system
+*	  with address translation, the provided virtual memory base address
+*	  replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/05/17 Modified Comment lines in functions of qspips
+*                    examples to recognize it as documentation block
+*                    and modified filename tag in
+*                    xqspips_dual_flash_stack_lqspi_example.c to include it in
+*                    doxygen examples.
+* 3.4   nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XQSPIPS_H		/* prevent circular inclusions */
+#define XQSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
+#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
+#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
+#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
+#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
+#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
+#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
+#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
+#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
+#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
+#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
+#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 	1
+#define XQSPIPS_SIZE_TWO 	2
+#define XQSPIPS_SIZE_THREE 	3
+#define XQSPIPS_SIZE_FOUR 	4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE		0
+#define XQSPIPS_CONNECTION_MODE_STACKED		1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
+	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	XQspiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
+				   *   read from the Rx FIFO needs to be shifted
+				   *   in cases where the data is less than 4
+				   *   bytes
+				   */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+			XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	An 8-bit value representing Slave Idle Count.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr)				\
+	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Tx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Rx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+			XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written to the Linear QSPI
+*		configuration register.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+*					u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 32-bit value representing the contents of the LQSPI Config
+*		register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+			   u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+		      u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
new file mode 100644
index 0000000..a7ced17
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_QSPI_0_DEVICE_ID,
+		XPAR_PS7_QSPI_0_BASEADDR,
+		XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PS7_QSPI_0_QSPI_MODE
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
new file mode 100644
index 0000000..1817b07
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk  09/17/13 First release
+* 3.1   hk  06/19/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4	0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+	u32 ConfigReg;
+
+	/*
+	 * Disable interrupts
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+				XQSPIPS_IXR_DISABLE_ALL);
+
+	/*
+	 * Disable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				0);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write default value to RX and TX threshold registers
+	 * RX threshold should be set to 1 here because the corresponding
+	 * status bit is used next to clear the RXFIFO
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+			(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+			(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+	/*
+	 * Clear RXFIFO
+	 */
+	while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+		XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+		XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+	}
+
+	/*
+	 * Clear status register by reading register and
+	 * writing 1 to clear the write to clear bits
+	 */
+	XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+				XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	/*
+	 * Write default value to configuration register
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * De-select linear mode
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+	u32 BaudRateDiv;
+	u32 LinearCfg;
+	u32 ConfigReg;
+
+	/*
+	 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+	 * should be set to 0x001; hence shift the value and use the mask.
+	 */
+	BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+			XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+	/*
+	 * Write configuration register with default values, slave selected &
+	 * pre-scaler value for divide by 4
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+	ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write linear configuration register with default value -
+	 * enable linear mode and use fast read.
+	 */
+
+	if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_STACKED){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+				XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+	}
+
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				LinearCfg);
+
+	/*
+	 * Enable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
new file mode 100644
index 0000000..96c867a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_4
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
+#define XQSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+						   Enable */
+#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
+						   transferred */
+#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
+				   XQSPIPS_CR_SSCTRL_MASK | \
+				   XQSPIPS_CR_DATA_SZ_MASK | \
+				   XQSPIPS_CR_MSTREN_MASK | \
+				   XQSPIPS_CR_SSFORCE_MASK | \
+				   XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
+				   XQSPIPS_CR_CPHA_MASK | \
+				   XQSPIPS_CR_PRESC_MASK | \
+				   XQSPIPS_CR_MANSTRTEN_MASK | \
+				   XQSPIPS_CR_MANSTRT_MASK | \
+				   XQSPIPS_CR_ENDIAN_MASK | \
+				   XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register.  Write only.
+ *
+ * QSPI Interrupt Disable Register 
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
+						    mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
+						    need write to clear */
+#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
+						between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
+						between two words shift */
+#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
+						mask */
+#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+							 or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
+							 between addr and return
+							 read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
+							  received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
+							  received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+	XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
new file mode 100644
index 0000000..1cd43f4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode. The driver doesnot support
+*		     Slave mode or the legacy mode.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+* 2.01a sg  02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk  26/03/13 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+	{XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+	{XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+	{XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+	{XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained in
+*		the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+*		the file xqspips.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+	Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it on */
+			ConfigReg |= OptionsTable[Index].Mask;
+		} else {
+			/* Turn it off */
+			ConfigReg &= ~(OptionsTable[Index].Mask);
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			 ConfigReg);
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+
+	if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET,
+				  XQSPIPS_LQSPI_CR_RST_STATE);
+		XQspiPs_SetSlaveSelect(InstancePtr);
+	} else {
+		ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPI configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to grab options
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+	if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+		OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Prescaler is the value that determine how much the clock should
+*		be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+*		in xqspips.h for this setting.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Read the configuration register, mask out the interesting bits, and set
+	 * them with the shifted value passed into the function. Write the
+	 * results back to the configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+	ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+			    XQSPIPS_CR_PRESC_SHIFT;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+	return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is the delay to de-assert slave select between
+*		two word transfers.
+* @param	DelayBtwn is the delay between one Slave Select being
+*		de-activated and the activation of another slave. The delay is
+*		the number of master clock periods given by DelayBtwn + 2.
+* @param	DelayAfter define the delay between the last bit of the current
+*		byte transfer and the first bit of the next byte transfer.
+*		The delay in number of master clock periods is given as:
+*		CHPA=0:DelayInit+DelayAfter+3
+*		CHPA=1:DelayAfter+1
+* @param	DelayInit is the delay between asserting the slave select signal
+*		and the first bit transfer. The delay int number of master clock
+*		periods is DelayInit+1.
+*
+* @return
+*		- XST_SUCCESS if delays are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the delays to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/* Shift, Mask and OR the values to build the register settings */
+	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+	DelayRegister |= (u32) DelayInit;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_DR_OFFSET, DelayRegister);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is a pointer to the Delay to de-assert slave select
+*		between two word transfers.
+* @param	DelayBtwn is a pointer to the Delay Between transfers value.
+*		This is a return parameter.
+* @param	DelayAfter is a pointer to the Delay After transfer value.
+*		This is a return parameter.
+* @param	DelayInit is a pointer to the Delay Initially value. This is
+*		a return parameter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_DR_OFFSET);
+
+	*DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+	*DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+			   XQSPIPS_DR_AFTER_SHIFT);
+
+	*DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+			  XQSPIPS_DR_BTWN_SHIFT);
+
+	*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+			  XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
new file mode 100644
index 0000000..4c44cdf
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.01a sg  02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1   hk  06/19/14 Remove checks for CR and ISR register values as they are
+*                    reset in the previous step.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+	int Status;
+	u8 DelayTestNss;
+	u8 DelayTestBtwn;
+	u8 DelayTestAfter;
+	u8 DelayTestInit;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	DelayTestNss = 0x5A;
+	DelayTestBtwn = 0xA5;
+	DelayTestAfter = 0xAA;
+	DelayTestInit = 0x55;
+
+	/*
+	 * Write and read the delay register, just to be sure there is some
+	 * hardware out there.
+	 */
+	Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+				DelayTestAfter, DelayTestInit);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+				&DelayTestAfter, &DelayTestInit);
+	if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+		(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+		return XST_REGISTER_ERROR;
+	}
+
+	Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
new file mode 100644
index 0000000..929ecd8
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+	XQspiPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+		if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/Makefile
new file mode 100644
index 0000000..04867a4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic.c
new file mode 100644
index 0000000..5d8da98
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic.c
@@ -0,0 +1,946 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      		  "Config" entry is now made as pointer in the XScuGic
+*		      		  structure, necessary changes are made.
+*		      		  The HandlerTable can now be populated through the low
+*		      		  level routine XScuGic_RegisterHandler added in this
+*		      		  release. Hence necessary checks are added not to
+*		      		  overwrite the HandlerTable entriesin function
+*		      		  XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*					  - XScuGic_SetPriTrigTypeByDistAddr()
+*					  - XScuGic_GetPriTrigTypeByDistAddr()
+* 		    		  Removed Offset calculation macros, defined in _hw.h
+*		      		  (CR 702687)
+*			  		  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  		  interrupts were directed to CPU1 (hard coded). Now depending
+*			  		  upon the CPU selected by the user (xparameters.h), interrupts
+*			  		  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  		  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  		  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             		  XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  		  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  		  in function XScuGic_CfgInitialize is removed as it was
+*		      		  a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+*			  		  target CPU mapping
+* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
+*					  the current cpu to interrupt processor targets registers
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  		  distributor is left uninitialized for Zynq AMP. It is assumed
+*             		  that the distributor will be initialized by Linux master. However
+*             		  for CortexR5 case, the earlier code is left unchanged where the
+*             		  the interrupt processor target registers in the distributor is
+*             		  initialized with the corresponding CPU ID on which the application
+*             		  built over the scugic driver runs.
+*             		  These changes fix CR#937243.
+* 3.3	pkp  05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+*					  to interrupt target register to fix CR#951848
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*                     the flow and avoid code duplication. Changes are made for
+*                     USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*                     one R5 is operating with A53 in open amp config and other
+*                     R5 running baremetal app, the existing code
+*                     had the potential to stop the whole AMP solution to work (if
+*                     for some reason the R5 running the baremetal app tasked to
+*                     initialize the Distributor hangs or crashes before initializing).
+*                     Changes are made so that the R5 under AMP first checks if
+*                     the distributor is enabled or not and if not, it does the
+*                     standard Distributor initialization.
+*                     This fixes the CR#952962.
+* 3.4   mus  09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+*                     for single core zynq-7000s
+* 3.5   mus  10/05/16 Modified DistributorInit function to avoid re-initialization of
+*                     distributor,If it is already initialized by other CPU.
+* 3.5	pkp	 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+*					  and properly mask interrupt target processor value to modify
+*					  interrupt target processor register for a given interrupt ID
+*					  and cpu ID
+* 3.6	pkp	 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+*					  interrupts in case they are being used only by current cpu.
+*					  It also removes current cpu from interrupt target registers
+*					  for all interrupts.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0U);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdBaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = CpuId + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	/*
+     * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+     * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+	 */
+#ifdef ARMA9
+	if ( XPAR_CPU_ID == 0x01 )
+	{
+		Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+		 & EFUSE_STATUS_CPU_MASK ) == 0);
+	}
+#endif
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0U;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_IdConfig->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+		XScuGic_Stop(InstancePtr);
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue, Offset;
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	Offset = (Int_Id & 0x3U);
+	Cpu_Id = (0x1U << Cpu_Id);
+
+	RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+	RegValue |= ((Cpu_Id) << (Offset*8U));
+
+	XScuGic_DistWriteReg(InstancePtr,
+						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+						 RegValue);
+}
+/****************************************************************************/
+/**
+* It checks if the interrupt target register contains all interrupts to be
+* targeted for current CPU. If they are programmed to be forwarded to current
+* cpu, this API disable all interrupts and disable GIC distributor.
+* This API also removes current CPU from interrupt target registers for all
+* interrupt.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_Stop(XScuGic *InstancePtr)
+{
+	u32 Int_Id;
+	u32 RegValue;
+	u32 Target_Cpu;
+	u32 DistDisable = 1; /* To track if distributor need to be disabled or not */
+	u32 LocalCpuID = ((u32)0x1 << CpuId);
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* If distributor is already disabled, no need to do anything */
+	RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+	if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+		return;
+	}
+
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+
+	/*
+	 * Check if the interrupt are targeted to current cpu only or not.
+	 * Also remove current cpu from interrupt target register for all
+	 * interrupts.
+	 */
+	for (Int_Id = 32U; Int_IdInterrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
+*                     definitions of scugic in xparameters.h
+* 3.8   mus  07/05/17 Updated scugic.tcl to add support for intrrupts connected
+*                     through util_reduced_vector IP(OR gate)
+*       mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+*                     the HandlerTable in XScuGic_ConfigTable to 0, it removes
+*                     the compilation warning in xscugic_g.c. Fix for CR#978736.
+*       mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
+*                     definitions for pl to ps interrupts.Fix for CR#980534
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_g.c
new file mode 100644
index 0000000..faad4ae
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUGIC_0_DEVICE_ID,
+		XPAR_PS7_SCUGIC_0_BASEADDR,
+		XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+		{{0}}		/**< Initialize the HandlerTable to 0 */
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.c
new file mode 100644
index 0000000..5b63c07
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.c
@@ -0,0 +1,574 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*
+* 
    
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+extern u32 CpuId;
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.h
new file mode 100644
index 0000000..8d1b04c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_hw.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_8
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 
    
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_intr.c
new file mode 100644
index 0000000..d82a60b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_selftest.c
new file mode 100644
index 0000000..7b1028f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_sinit.c
new file mode 100644
index 0000000..842f318
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scugic_v3_8/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
new file mode 100644
index 0000000..7c673d4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scutimer_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scutimer"
+
+scutimer_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scutimer_includes
+
+scutimer_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000..9d477d9
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function  must be called
+* before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	ConfigPtr points to the XScuTimer configuration structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			 XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+		/*
+		 * Copy configuration into the instance structure.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+		InstancePtr->IsStarted = (u32)0;
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status =(s32)XST_SUCCESS;
+	}
+	else {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'timer enable' bit in the register.
+	 */
+	Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'timer enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+					XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register.
+	 */
+	ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+	/*
+	 * Set the prescaler value.
+	 */
+	ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			  XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				    XSCUTIMER_CONTROL_OFFSET);
+	ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+	return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000..ea4ba79
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* 		has to register it's own handler)
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+*  Interrupts 
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 

    
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H		/* prevent circular inclusions */
+#define XSCUTIMER_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID of device */
+	u32 BaseAddr;	/**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuTimer_Config Config; /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- TRUE if the timer has expired.
+*		- FALSE if the timer has not expired.
+*
+* @note		C-style signature:
+*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_ISR_OFFSET) & \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr)				\
+	XScuTimer_LoadTimer((InstancePtr),				\
+		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr)				\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+				XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) |		 \
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_CONTROL_OFFSET) |	\
+					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr)			\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000..34b0686
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+		XPAR_PS7_SCUTIMER_0_BASEADDR
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000..ac7b429
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
+#define XSCUTIMER_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET		0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET	0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET	0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET		0x0CU /**< Timer Interrupt
+						  Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000..6e37fef
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE	0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+	s32 Status;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Save the contents of the Control Register and stop the timer.
+	 */
+	CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+	Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Save the contents of the Load Register.
+	 * Load a new test value in the Load Register, read it back and
+	 * compare it with the written value.
+	 */
+	LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+	XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+	Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+
+	/*
+	 * Restore the contents of the Load Register and Control Register.
+	 */
+	XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+	/*
+	 * Return a Failure if the contents of the Load Register do not
+	 * match with the value written to it.
+	 */
+	if (Register != XSCUTIMER_SELFTEST_VALUE) {
+		Status = (s32)XST_FAILURE;
+	}
+	else {
+		Status = (s32)XST_SUCCESS;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000..3bcc57e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+	XScuTimer_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+		if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuTimer_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
new file mode 100644
index 0000000..493ad9a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scuwdt_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scuwdt"
+
+scuwdt_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scuwdt_includes
+
+scuwdt_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000..8e97885
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,218 @@
+/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			 XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 CfgStatus;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+	}
+	else {
+		/*
+		 * Copy configuration into instance.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+		InstancePtr->IsStarted = 0U;
+
+		/*
+		 * Put the watchdog timer in Watchdog mode.
+		 */
+		XScuWdt_SetWdMode(InstancePtr);
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		CfgStatus =(s32)XST_SUCCESS;
+	}
+	return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		User needs to select the appropriate mode (watchdog/timer)
+*		before using this API.
+*		See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+*		xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'watchdog enable' bit in the register.
+	 */
+	Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'watchdog enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000..372bbc3
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 

    
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUWDT_H		/* prevent circular inclusions */
+#define XSCUWDT_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuWdt_Config Config;/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_RST_STS_OFFSET) &			\
+	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_ISR_OFFSET) &				\
+	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr)					 \
+	XScuWdt_LoadWdt((InstancePtr),					 \
+			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+					 XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	Value is the value to be written to the Watchdog Load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value)				\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr)					  \
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
+			 XSCUWDT_CONTROL_OFFSET,			  \
+			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+			  XSCUWDT_CONTROL_OFFSET) |			  \
+			  (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr)				\
+{									\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE1);			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE2);			\
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	Contents of the watchdog control register.
+*
+* @note		C-style signature:
+		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr)				\
+	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
+			XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ControlReg is the value to be written to the watchdog control
+*		register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			 XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr)				\
+	XScuWdt_SetControlReg((InstancePtr),				\
+			      (XScuWdt_GetControlReg(InstancePtr) |	\
+			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000..ae52c19
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUWDT_0_DEVICE_ID,
+		XPAR_PS7_SCUWDT_0_BASEADDR
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000..2067d3a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
+#define XSCUWDT_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET	0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET	0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET	0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET	0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET	0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET	0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004U /**< Intr enable (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1		0x12345678U /**< Watchdog mode disable
+							value 1 */
+#define XSCUWDT_DISABLE_VALUE2		0x87654321U /**< Watchdog mode disable
+							value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000..95d5065
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if the WDT is not decrementing.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+	s32 SelfTestStatus;
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Stop the watchdog timer.
+	 */
+	CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+	LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_LOAD_OFFSET);
+	XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+	/*
+	 * Start the watchdog timer and check if the watchdog counter is
+	 * decrementing.
+	 */
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_COUNTER_OFFSET);
+
+	XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+	XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+	if (Register == 0xFFFFFFFFU) {
+		SelfTestStatus = (s32)XST_FAILURE;
+	}
+	else {
+		SelfTestStatus = (s32)XST_SUCCESS;
+	}
+
+	return SelfTestStatus;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000..c63eb9a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+	XScuWdt_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+		if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuWdt_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/Makefile
new file mode 100644
index 0000000..f57081a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.c
new file mode 100644
index 0000000..6a0f532
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.c
@@ -0,0 +1,1736 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v3_3
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+*       mn     07/17/17 Add support for running SD at 200MHz
+*       mn     07/26/17 Fixed compilation warnings
+*       mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*       mn     09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
+#define XSDPS_RESPOCR_READY	0x80000000U
+#define XSDPS_ACMD41_HCS	0x40000000U
+#define XSDPS_ACMD41_3V3	0x00300000U
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
+#define HIGH_SPEED_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define WIDTH_4_BIT_SUPPORT	0x4U
+#define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_19_MHZ		19000000U
+#define SD_CLK_26_MHZ		26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_SEC_COUNT_BYTE1		212U
+#define EXT_CSD_SEC_COUNT_BYTE2		213U
+#define EXT_CSD_SEC_COUNT_BYTE3		214U
+#define EXT_CSD_SEC_COUNT_BYTE4		215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
+#define CSD_SPEC_VER_3		0x3U
+#define SCR_SPEC_VER_3		0x80U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+u16 TransferMode;
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u8 PowerLevel;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+#ifdef UHS_MODE_ENABLE
+	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+#else
+	InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+	InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+	InstancePtr->SectorCount = 0;
+	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+	InstancePtr->Config_TapDelay = NULL;
+
+	/* Disable bus power and issue emmc hw reset */
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+			XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+	/* Delay to poweroff card */
+    (void)usleep(1000U);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	}
+	/* Host Controller version is read. */
+	 InstancePtr->HC_Version =
+			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/* Select voltage and enable bus power. */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+				~XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Delay before issuing the command after emmc reset */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+				XSDPS_CAPS_EMB_SLOT)
+			usleep(200);
+
+	/* Change the clock frequency to 400 KHz */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+	} else {
+		PowerLevel = 0U;
+	}
+
+	/* Select voltage based on capability and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+#ifdef __aarch64__
+	/* Enable ADMA2 in 64bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_64_MASK);
+#else
+	/* Enable ADMA2 in 32bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+#endif
+
+	/* Enable all interrupt status except card interrupt initially */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* Disable all interrupt signals by default. */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK;
+
+	/* Set block size to 512 by default */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 Arg;
+	u8 ReadReg;
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0U);
+	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (Status == XSDPS_CT_ERROR) {
+		 /* "Software reset for all" is initiated */
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+				XSDPS_SWRST_CMD_LINE_MASK);
+
+		/* Proceed with initialization only after reset is complete */
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		}
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+	}
+	else {
+		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+	}
+
+	RespOCR = 0U;
+	/* Send ACMD41 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+		/*
+		 * There is no support to switch to 1.8V and use UHS mode on
+		 * 1.0 silicon
+		 */
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+			(XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+			(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+			Arg |= XSDPS_OCR_S18;
+		}
+
+		/* 0x40300000 - Host High Capacity support & 3.3V window */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+		InstancePtr->Switch1v8 = 1U;
+		Status = XSdPs_Switch_Voltage(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+	} while (InstancePtr->RelCardAddr == 0U);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+		BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+		Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+		DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+		DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+		DeviceSize = (DeviceSize + 1U) * Mult;
+		DeviceSize =  DeviceSize * BlkLen;
+		InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+	} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+		InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+										1U) * 1024U;
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+*			   initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	static u8 ExtCsd[512];
+	u8 SCR[8] = { 0U };
+#pragma data_alignment = 4
+#else
+	static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+	u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
+#endif
+	u8 ReadBuff[64] = { 0U };
+	s32 Status;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Default settings */
+	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+	InstancePtr->CardType = XSDPS_CARD_SD;
+	InstancePtr->Switch1v8 = 0U;
+	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+			== XSDPS_CAPS_EMB_SLOT)) {
+		InstancePtr->CardType = XSDPS_CHIP_EMMC;
+	} else {
+		Status = XSdPs_IdentifyCard(InstancePtr);
+		if (Status == XST_FAILURE) {
+			goto RETURN_PATH;
+		}
+	}
+
+	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
+		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		Status = XSdPs_SdCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Change clock to default clock 25MHz */
+		/*
+		 * SD default speed mode timing should be closed at 19 MHz.
+		 * The reason for this is SD requires a voltage level shifter.
+		 * This limitation applies to ZynqMPSoC.
+		 */
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+			InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+		else
+			InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+		Status = XSdPs_MmcCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		/* Change clock to default clock 26MHz */
+		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_Select_Card(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		/* Pull-up disconnected during data transfer */
+		Status = XSdPs_Pullup(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+			Status = XSdPs_Change_BusWidth(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		/* Get speed supported by device */
+		Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH;
+		}
+
+		if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+			(ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+			(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+			(XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+			(InstancePtr->Switch1v8 == 0U)) {
+			u16 CtrlReg, ClockReg;
+
+			/* Stop the clock */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+			CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+					CtrlReg);
+
+			/* Enabling 1.8V in controller */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL2_OFFSET);
+			CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+					CtrlReg);
+
+			/* Wait minimum 5mSec */
+			(void)usleep(5000U);
+
+			/* Check for 1.8V signal enable bit is cleared by Host */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_HOST_CTRL2_OFFSET);
+			if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			/* Wait for internal clock to stabilize */
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET,
+						ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+								XSDPS_CLK_CTRL_OFFSET);
+			while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+				ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+							XSDPS_CLK_CTRL_OFFSET);
+			}
+
+			/* Enable SD clock */
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET,
+					ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+			/* Wait for 1mSec */
+			(void)usleep(1000U);
+
+			InstancePtr->Switch1v8 = 1U;
+		}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		if (InstancePtr->Switch1v8 != 0U) {
+
+			/* Identify the UHS mode supported by card */
+			XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+			/* Set UHS-I SDR104 mode */
+			Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+			if (Status != XST_SUCCESS) {
+				goto RETURN_PATH;
+			}
+
+		} else {
+#endif
+			/*
+			 * card supports CMD6 when SD_SPEC field in SCR register
+			 * indicates that the Physical Layer Specification Version
+			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+			 */
+			if (SCR[0] != 0U) {
+				/* Check for high speed support */
+				if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+						(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+					InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+					InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+					Status = XSdPs_Change_BusSpeed(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		}
+#endif
+
+	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+		/* Change bus width to 8-bit */
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Get Extended CSD */
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		/* Check for card supported speed */
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+				EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+		} else
+			InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+
+		if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+			}
+
+			if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+					InstancePtr->Mode == XSDPS_DDR52_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+
+				if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+					Status = XSdPs_Change_BusWidth(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+		}
+
+		/* Enable Rst_n_Fun bit if it is disabled */
+		if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+			Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+			Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+	if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+			(InstancePtr->CardType == XSDPS_CARD_SD)) {
+		Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* 74 CLK delay after card is powered up, before the first command. */
+	usleep(XSDPS_INIT_DELAY);
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Host High Capacity support & High voltage window */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->CardType = XSDPS_CARD_SD;
+	} else {
+		InstancePtr->CardType = XSDPS_CARD_MMC;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_CMD_LINE_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 CtrlReg;
+	u32 ReadReg, ClockReg;
+
+	/* Send switch voltage command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+	}
+
+	/* Wait for CMD and DATA line to go low */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+	/* Stop the clock */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+			CtrlReg);
+
+	/* Enabling 1.8V in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+			CtrlReg);
+
+	/* Wait minimum 5mSec */
+	(void)usleep(5000U);
+
+	/* Check for 1.8V signal enable bit is cleared by Host */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET,
+				ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	/* Wait for 1mSec */
+	(void)usleep(1000U);
+
+	/* Wait for CMD and DATA line to go high */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Write block count register */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+	/* Write argument register */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/* Command register is set to trigger transfer of command */
+	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFFU;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines.
+	 * For Tuning Commands DAT lines check can be ignored.
+	 */
+	if ((Cmd != CMD21) && (Cmd != CMD19)) {
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			(CommandReg << 16) | TransferMode);
+
+	/* Polling for response for now */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((Cmd == CMD21) || (Cmd == CMD19)) {
+			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+				break;
+			}
+		}
+
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+									XSDPS_ERR_INTR_STS_OFFSET);
+			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+				Status = XSDPS_CT_ERROR;
+			}
+			 /* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+		case CMD6:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			} else {
+				RetVal |= RESP_R1B;
+			}
+			break;
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+		case CMD8:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1;
+			} else {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			}
+			break;
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD11:
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+		case CMD19:
+		case CMD21:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		default :
+			RetVal |= Cmd;
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)Buff,
+			BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+	}
+
+	/* Send block read command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Check for transfer complete */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)Buff,
+			BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+	}
+
+	TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	s32 Status = 0;
+
+	/* Send CMD7 - Select card */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0U;
+	u32 DescNum = 0U;
+	u32 BlkSize = 0U;
+
+	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1U;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+			TotalDescLines += 1U;
+		}
+
+	}
+
+	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+#ifdef __aarch64__
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/* This will write '0' to length field which indicates 65536 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+#ifdef __aarch64__
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+#ifdef __aarch64__
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+			(u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
+#endif
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32U);
+	}
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0U;
+	/* Send CMD1 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+		/* Host High Capacity support & High volage window */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	/* Set relative card address */
+	InstancePtr->RelCardAddr = 0x12340000U;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+	/* Calculating the memory capacity */
+	BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+	Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+	DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+	DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+	DeviceSize = (DeviceSize + 1U) * Mult;
+	DeviceSize =  DeviceSize * BlkLen;
+
+	InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.h
new file mode 100644
index 0000000..f413a86
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps.h
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_3
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
+*                       information.
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*
+* 
    
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
+	u8 IsCacheCoherent; 		/**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+#ifdef __aarch64__
+	u64 Address;		/**< Address of current dma transfer */
+#else
+	u32 Address;		/**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+}  __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_g.c
new file mode 100644
index 0000000..e4456f8
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_g.c
@@ -0,0 +1,62 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SD_0_DEVICE_ID,
+		XPAR_PS7_SD_0_BASEADDR,
+		XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+		XPAR_PS7_SD_0_HAS_CD,
+		XPAR_PS7_SD_0_HAS_WP,
+		XPAR_PS7_SD_0_BUS_WIDTH,
+		XPAR_PS7_SD_0_MIO_BANK,
+		XPAR_PS7_SD_0_HAS_EMIO,
+		XPAR_PS7_SD_0_IS_CACHE_COHERENT
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_hw.h
new file mode 100644
index 0000000..5656d7d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_hw.h
@@ -0,0 +1,1297 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_3
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Added support for ARMCC toolchain
+* 
    
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ *  Normal and Error Interrupt Status Register 
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ *  Normal and Error Interrupt Status Enable Register 
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ *  Normal and Error Interrupt Signal Enable Register 
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
+#define XSDPS_DDR52_MODE			0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+/*
+ * XSDPS_MMC_HS200_MAX_CLK is set to 150000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_MMC_HS200_MAX_CLK	150000000U
+#define XSDPS_MMC_HSD_MAX_CLK	52000000U
+#define XSDPS_MMC_DDR_MAX_CLK	52000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#define XSDPS_WIDTH_8		8U
+#define XSDPS_WIDTH_4		4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK		0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK		0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK		0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK		0x003F0000U
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg >>= ((RegOffset & 0x3)*8);
+	return (u16)Reg;
+#else
+	return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+	Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+	XSdPs_Out32(BaseAddress, Reg);
+#else
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg >>= ((RegOffset & 0x3)*8);
+	return (u8)Reg;
+#else
+	return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+	Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+	XSdPs_Out32(BaseAddress, Reg);
+#else
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_options.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_options.c
new file mode 100644
index 0000000..b3c47f9
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_options.c
@@ -0,0 +1,1759 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v3_3
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       vns    03/13/17 Fixed MISRAC mandatory violation
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+*       mn     08/07/17	Properly set OTAPDLY value by clearing previous bit
+* 			settings
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT	0x1U
+#define UHS_SDR25_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define UHS_SDR104_SUPPORT	0x8U
+#define UHS_DDR50_SUPPORT	0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+extern u16 TransferMode;
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	s32 Status;
+	u32 PresentStateReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/* Set block size to the value passed */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize & XSDPS_BLK_SIZE_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	s32 Status;
+	u32 StatusReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0U;
+	}
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/* Set block size to the value passed */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * check for bus width for 3.0 controller and return if
+	 * bus width is <4
+	 */
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			(InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+		Status = XST_SUCCESS;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+				0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+		Arg = ((u32)InstancePtr->BusWidth);
+
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+				(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+			/* in case of eMMC data width 8-bit */
+			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+		} else {
+			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+		}
+
+		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+		} else {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Check for transfer complete */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+
+	/* Width setting in controller */
+	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+	} else {
+		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			(u8)StatusReg);
+
+	if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL2_OFFSET);
+		StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+		StatusReg |= InstancePtr->Mode;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, StatusReg);
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+		BlkSize &= XSDPS_BLK_SIZE_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+		if (InstancePtr->Config.IsCacheCoherent == 0) {
+			Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+		}
+
+		TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+		Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 * Polling for response for now
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 50 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+
+	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 52 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Arg = XSDPS_MMC_HS200_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+		} else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+		} else {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Status = XSdPs_Execute_Tuning(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	u16 DivCnt;
+	u16 Divisor = 0U;
+	u16 ExtDivisor;
+	s32 Status;
+	u16 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+			(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
+		/* Calculate divisor */
+		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt >> 1;
+				break;
+			}
+		}
+
+		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		/* Calculate divisor */
+		DivCnt = 0x1U;
+		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt / 2U;
+				break;
+			}
+			DivCnt = DivCnt << 1U;
+		}
+
+		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Set clock divisor */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+		ExtDivisor = Divisor >> 8;
+		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	} else {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	}
+
+	/* Wait for internal clock to stabilize */
+	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);;
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg = 0U;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+	}
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	/* Send SEND_EXT_CSD command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Arg is the argument to be sent along with the command
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+	s32 Status;
+	u32 StatusReg;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff contains the response for CMD6
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+		InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+		InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+		InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+		InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+	}
+	else
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Mode UHS-I mode
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+	s32 Status;
+	u16 StatusReg;
+	u16 CtrlReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Drive strength */
+
+	/* Bus speed mode selection */
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+	}
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	switch (Mode) {
+	case 0U:
+		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+		break;
+	case 1U:
+		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+		break;
+	case 2U:
+		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+		break;
+	case 3U:
+		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+		break;
+	case 4U:
+		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+		break;
+	default:
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+		break;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+	/* Current limit */
+
+	/* Set UHS mode in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+	CtrlReg |= Mode;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/* Change the clock frequency */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+			(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+		/* Send tuning pattern */
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 BlkSize;
+	u16 CtrlReg;
+	u8 TuningCount;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+	{
+		BlkSize = BlkSize*2U;
+	}
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK;
+
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/*
+	 * workaround which can work for 1.0/2.0 silicon for auto tuning.
+	 * This can be revisited for 3.0 silicon if necessary.
+	 */
+	/* Wait for ~60 clock cycles to reset the tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+		if (InstancePtr->CardType == XSDPS_CARD_SD) {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+		} else {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+		}
+
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+			break;
+		}
+
+		if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			/* Issue DLL Reset to load new SDHC tuned tap values */
+			XSdPs_DllReset(InstancePtr);
+#endif
+		}
+	}
+
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for ~12 clock cycles to synchronize the new tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (Bank == 2)
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (Bank == 2)
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		TapDelay |= SD0_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		TapDelay |= SD1_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType== XSDPS_CARD_SD)
+			TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD0_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD1_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+	u32 DllCtrl, BankNum, DeviceId, CardType;
+
+	BankNum = InstancePtr->Config.BankNumber;
+	DeviceId = InstancePtr->Config.DeviceId ;
+	CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#endif
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+	u32 ClockReg, DllCtrl;
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/* Issue DLL Reset to load zero tap values */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for 2 micro seconds */
+	(void)usleep(2U);
+
+	/* Release the DLL out of reset */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_sinit.c
new file mode 100644
index 0000000..37ab20e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/sdps_v3_3/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_3
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/Makefile
new file mode 100644
index 0000000..0f23775
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/Makefile
@@ -0,0 +1,87 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+include config.make
+
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles\
+		  -march=armv7-a \
+		  -mfloat-abi=soft \
+		  -mfpu=neon
+endif
+
+ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+ASSEMBLY_OBJECTS  = $(addsuffix .o, $(basename $(wildcard *.S)))
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+profile_libs:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
+
+.PHONY: include
+include: standalone_includes profile_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
+
+clean:
+	rm -rf ${OBJECTS}
+	rm -rf ${ASSEMBLY_OBJECTS}
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_exit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_exit.c
new file mode 100644
index 0000000..cf59888
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1) {
+	;
+  }
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_exit.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_exit.o
new file mode 100644
index 0000000..81080b4
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_open.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_open.c
new file mode 100644
index 0000000..a108b77
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_open.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_open.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_open.o
new file mode 100644
index 0000000..1f5a264
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_sbrk.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_sbrk.c
new file mode 100644
index 0000000..2a069ec
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if (heap > HeapEndPtr){
+	  Status = (caddr_t) -1;
+  }
+  else if (prev_heap != NULL) {
+	  Status = (caddr_t) ((void *)prev_heap);
+  }
+  else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_sbrk.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/_sbrk.o
new file mode 100644
index 0000000..8e010e0
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/abort.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/abort.c
new file mode 100644
index 0000000..e8988c0
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/abort.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/abort.o
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index 0000000..71c736f
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/asm_vectors.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/asm_vectors.S
new file mode 100644
index 0000000..1752548
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/asm_vectors.S
@@ -0,0 +1,198 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A9 processor
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+*			 abort and prefetch abort into DataAbortAddr and
+*			 PrefetchAbortAddr for further use to fix CR#854523
+* 5.4	pkp	12/03/15 Added handler for undefined exception
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xil_errata.h"
+
+#define __ARM_NEON__ 1
+
+.org 0
+.text
+
+.globl _vector_table
+
+.section .vectors
+_vector_table:
+	B	_boot
+	B	Undefined
+	B	SVCHandler
+	B	PrefetchAbortHandler
+	B	DataAbortHandler
+	NOP	/* Placeholder for address exception vector*/
+	B	IRQHandler
+	B	FIQHandler
+
+
+IRQHandler:					/* IRQ vector handler */
+
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+#ifdef PROFILING
+	ldr	r2, =prof_pc
+	subs	r3, lr, #0
+	str	r3, [r2]
+#endif
+
+	bl	IRQInterrupt			/* IRQ vector */
+
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+
+	subs	pc, lr, #4			/* adjust return */
+
+
+FIQHandler:					/* FIQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+FIQLoop:
+	bl	FIQInterrupt			/* FIQ vector */
+
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+
+Undefined:					/* Undefined handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =UndefinedExceptionAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Store address of instruction causing undefined exception */
+
+	bl	UndefinedException		/* UndefinedException: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	movs	pc, lr
+
+SVCHandler:					/* SWI handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	tst	r0, #0x20			/* check the T bit */
+	ldrneh	r0, [lr,#-2]			/* Thumb mode */
+	bicne	r0, r0, #0xff00			/* Thumb mode */
+	ldreq	r0, [lr,#-4]			/* ARM mode */
+	biceq	r0, r0, #0xff000000		/* ARM mode */
+
+	bl	SWInterrupt			/* SWInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	movs	pc, lr		/*return to the next instruction after the SWI instruction */
+
+
+DataAbortHandler:				/* Data Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =DataAbortAddr
+	sub     r1, lr, #8
+	str     r1, [r0]            		/* Stores instruction causing data abort */
+
+	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #8			/* points to the instruction that caused the Data Abort exception */
+
+PrefetchAbortHandler:				/* Prefetch Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =PrefetchAbortAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Stores instruction causing prefetch abort */
+
+	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #4			/* points to the instruction that caused the Prefetch Abort exception */
+
+.end
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/asm_vectors.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/asm_vectors.o
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.S
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+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.S
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
+* @{
+* 
     boot.S 
    
+* The boot code performs minimum configuration which is required for an
+* application to run starting from processor's reset state. Below is a
+* sequence illustrating what all configuration is performed before control
+* reaches to main function.
+*
+* 1. Program vector table base for exception handling
+* 2. Invalidate instruction cache, data cache and TLBs
+* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
+*    abort, system)
+* 4. Configure MMU with short descriptor translation table format and program
+*    base address of translation table
+* 5. Enable data cache, instruction cache and MMU
+* 6. Enable Floating point unit
+* 7. Transfer control to _start which clears BSS sections, initializes
+*    global timer and runs global constructor before jumping to main
+*    application
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+* 5.0	pkp	16/15/14 Modified initialization code to enable scu after
+*			 MMU is enabled
+* 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+*			 caches and TLB, enable MMU and caches, then enable SMP
+*			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+*			 is done later.
+* 5.4   asa     12/6/15  Added code to initialize SPSR for all relevant modes.
+* 6.0   mus     08/04/16 Added code to detect zynq-7000 base silicon configuration and
+*                        attempt to enable dual core behavior on single cpu zynq-7000s
+*                        devices is prevented from corrupting system behavior.
+* 6.0   mus     08/24/16 Check CPU core before putting cpu1 to reset for single core
+*                        zynq-7000s devices
+*
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_errata.h"
+
+.globl MMUTable
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+.set PSS_L2CC_BASE_ADDR, 0xF8F02000
+.set PSS_SLCR_BASE_ADDR, 0xF8000000
+
+.set RESERVED,		0x0fffff00
+.set TblBase ,		MMUTable
+.set LRemap,		0xFE00000F		/* set the base address of the peripheral block as not shared */
+.set L2CCWay,		(PSS_L2CC_BASE_ADDR + 0x077C)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
+.set L2CCSync,		(PSS_L2CC_BASE_ADDR + 0x0730)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
+.set L2CCCrtl,		(PSS_L2CC_BASE_ADDR + 0x0100)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
+.set L2CCAuxCrtl,	(PSS_L2CC_BASE_ADDR + 0x0104)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
+.set L2CCTAGLatReg,	(PSS_L2CC_BASE_ADDR + 0x0108)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
+.set L2CCDataLatReg,	(PSS_L2CC_BASE_ADDR + 0x010C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
+.set L2CCIntClear,	(PSS_L2CC_BASE_ADDR + 0x0220)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
+.set L2CCIntRaw,	(PSS_L2CC_BASE_ADDR + 0x021C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
+
+.set SLCRlockReg,	    (PSS_SLCR_BASE_ADDR + 0x04)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
+.set SLCRUnlockReg,     (PSS_SLCR_BASE_ADDR + 0x08)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
+.set SLCRL2cRamReg,     (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
+.set SLCRCPURSTReg,     (0xF8000000 + 0x244)           /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
+.set EFUSEStaus,        (0xF800D000 + 0x10)            /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
+
+/* workaround for simulation not working when L1 D and I caches,MMU and  L2 cache enabled - DT568997 */
+.if SIM_MODE == 1
+.set CRValMmuCac,	0b00000000000000	/* Disable IDC, and MMU */
+.else
+.set CRValMmuCac,	0b01000000000101	/* Enable IDC, and MMU */
+.endif
+
+.set CRValHiVectorAddr,	0b10000000000000	/* Set the Vector address to high, 0xFFFF0000 */
+
+.set L2CCAuxControl,	0x72360000		/* Enable all prefetching, Cache replacement policy, Parity enable,
+                                        Event monitor bus enable and Way Size (64 KB) */
+.set L2CCControl,	0x01			/* Enable L2CC */
+.set L2CCTAGLatency,	0x0111			/* latency for TAG RAM */
+.set L2CCDataLatency,	0x0121			/* latency for DATA RAM */
+
+.set SLCRlockKey,	        0x767B			/* SLCR lock key */
+.set SLCRUnlockKey,	        0xDF0D			/* SLCR unlock key */
+.set SLCRL2cRamConfig,      0x00020202      /* SLCR L2C ram configuration */
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack,	__undef_stack
+.set FIQ_stack,		__fiq_stack
+.set Abort_stack,	__abort_stack
+.set SPV_stack,		__supervisor_stack
+.set IRQ_stack,		__irq_stack
+.set SYS_stack,		__stack
+
+.set vector_base,	_vector_table
+
+.set FPEXC_EN,		0x40000000		/* FPU enable bit, (1 << 30) */
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+#if XPAR_CPU_ID==0
+        /* only allow cpu0 through */
+	mrc	p15,0,r1,c0,c0,5
+	and	r1, r1, #0xf
+        cmp	r1, #0
+	beq	CheckEFUSE
+	EndlessLoop0:
+		wfe
+	b	EndlessLoop0
+
+CheckEFUSE:
+        ldr r0,=EFUSEStaus
+        ldr r1,[r0]                             /* Read eFuse setting */
+        ands r1,r1,#0x80                        /* Check whether device is having single core */
+	beq OKToRun
+
+ /* single core device, reset cpu1 */
+        ldr     r0,=SLCRUnlockReg               /* Load SLCR base address base + unlock register */
+        ldr     r1,=SLCRUnlockKey               /* set unlock key */
+        str     r1, [r0]                        /* Unlock SLCR */
+
+	ldr r0,=SLCRCPURSTReg
+	ldr r1,[r0]                             /* Read CPU Software Reset Control register */
+	orr r1,r1,#0x22
+        str r1,[r0]                             /* Reset CPU1 */
+
+        ldr	r0,=SLCRlockReg         	/* Load SLCR base address base + lock register */
+	ldr	r1,=SLCRlockKey	        	/* set lock key */
+	str	r1, [r0]	        	/* lock SLCR */
+
+#elif XPAR_CPU_ID==1
+	/* only allow cpu1 through */
+       mrc	p15,0,r1,c0,c0,5
+       and	r1, r1, #0xf
+       cmp	r1, #1
+       beq	CheckEFUSE1
+       b        EndlessLoop1
+
+CheckEFUSE1:
+        ldr r0,=EFUSEStaus
+        ldr r1,[r0]                             /* Read eFuse setting */
+        ands r1,r1,#0x80                        /* Check whether device is having single core */
+	beq OKToRun
+	EndlessLoop1:
+	        wfe
+	b	EndlessLoop1
+#endif
+
+OKToRun:
+	mrc     p15, 0, r0, c0, c0, 0		/* Get the revision */
+	and     r5, r0, #0x00f00000
+	and     r6, r0, #0x0000000f
+	orr     r6, r6, r5, lsr #20-4
+
+#ifdef CONFIG_ARM_ERRATA_742230
+        cmp     r6, #0x22                       /* only present up to r2p2 */
+        mrcle   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+        orrle   r10, r10, #1 << 4               /* set bit #4 */
+        mcrle   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+	teq     r5, #0x00200000                 /* only present in r2p* */
+	mrceq   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+	orreq   r10, r10, #1 << 6               /* set bit #6 */
+	mcreq   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+	/* set VBAR to the _vector_table address in linker script */
+	ldr	r0, =vector_base
+	mcr	p15, 0, r0, c12, c0, 0
+
+	/*invalidate scu*/
+	ldr	r7, =0xf8f0000c
+	ldr	r6, =0xffff
+	str	r6, [r7]
+
+	/* Invalidate caches and TLBs */
+	mov	r0,#0				/* r0 = 0  */
+	mcr	p15, 0, r0, c8, c7, 0		/* invalidate TLBs */
+	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
+	mcr	p15, 0, r0, c7, c5, 6		/* Invalidate branch predictor array */
+	bl	invalidate_dcache		/* invalidate dcache */
+
+	/* Disable MMU, if enabled */
+	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
+	bic	r0, r0, #0x1			/* clear bit 0 */
+	mcr	p15, 0, r0, c1, c0, 0		/* write value back */
+
+#ifdef SHAREABLE_DDR
+	/* Mark the entire DDR memory as shareable */
+	ldr	r3, =0x3ff			/* 1024 entries to cover 1G DDR */
+	ldr	r0, =TblBase			/* MMU Table address in memory */
+	ldr	r2, =0x15de6			/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+shareable_loop:
+	str	r2, [r0]			/* write the entry to MMU table */
+	add	r0, r0, #0x4			/* next entry in the table */
+	add	r2, r2, #0x100000		/* next section */
+	subs	r3, r3, #1
+	bge	shareable_loop			/* loop till 1G is covered */
+#endif
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the irq stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x12			/* IRQ mode */
+	msr	cpsr, r2
+	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
+	bic r2, r2, #(0x1 << 9)    		 /* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x13			/* supervisor mode */
+	msr	cpsr, r2
+	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x17			/* Abort mode */
+	msr	cpsr, r2
+	ldr	r13,=Abort_stack		/* Abort stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x11			/* FIQ mode */
+	msr	cpsr, r2
+	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
+	bic r2, r2, #(0x1 << 9)    		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1b			/* Undefine mode */
+	msr	cpsr, r2
+	ldr	r13,=Undef_stack		/* Undefine stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the system stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1F			/* SYS mode */
+	msr	cpsr, r2
+	ldr	r13,=SYS_stack			/* SYS stack pointer */
+
+	/*set scu enable bit in scu*/
+	ldr	r7, =0xf8f00000
+	ldr	r0, [r7]
+	orr	r0, r0, #0x1
+	str	r0, [r7]
+
+	/* enable MMU and cache */
+
+	ldr	r0,=TblBase			/* Load MMU translation table base */
+	orr	r0, r0, #0x5B			/* Outer-cacheable, WB */
+	mcr	15, 0, r0, c2, c0, 0		/* TTB0 */
+
+	mvn	r0,#0				/* Load MMU domains -- all ones=manager */
+	mcr	p15,0,r0,c3,c0,0
+
+	/* Enable mmu, icahce and dcache */
+	ldr	r0,=CRValMmuCac
+	mcr	p15,0,r0,c1,c0,0		/* Enable cache and MMU */
+	dsb					/* dsb	allow the MMU to start up */
+	isb					/* isb	flush prefetch buffer */
+
+	/* Write to ACTLR */
+	mrc	p15, 0, r0, c1, c0, 1		/* Read ACTLR*/
+	orr	r0, r0, #(0x01 << 6)		/* set SMP bit */
+	orr	r0, r0, #(0x01 )		/* Cache/TLB maintenance broadcast */
+	mcr	p15, 0, r0, c1, c0, 1		/* Write ACTLR*/
+
+/* Invalidate L2 Cache and enable L2 Cache*/
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	mov	r1, #0				/* force the disable bit */
+	str	r1, [r0]			/* disable the L2 Caches */
+
+	ldr	r0,=L2CCAuxCrtl			/* Load L2CC base address base + Aux control register */
+	ldr	r1,[r0]				/* read the register */
+	ldr	r2,=L2CCAuxControl		/* set the default bits */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* store the Aux Control Register */
+
+	ldr	r0,=L2CCTAGLatReg		/* Load L2CC base address base + TAG Latency address */
+	ldr	r1,=L2CCTAGLatency		/* set the latencies for the TAG*/
+	str	r1, [r0]			/* store the TAG Latency register Register */
+
+	ldr	r0,=L2CCDataLatReg		/* Load L2CC base address base + Data Latency address */
+	ldr	r1,=L2CCDataLatency		/* set the latencies for the Data*/
+	str	r1, [r0]			/* store the Data Latency register Register */
+
+	ldr	r0,=L2CCWay			/* Load L2CC base address base + way register*/
+	ldr	r2, =0xFFFF
+	str	r2, [r0]			/* force invalidate */
+
+	ldr	r0,=L2CCSync			/* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
+						/* Load L2CC base address base + sync register*/
+	/* poll for completion */
+Sync:	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	Sync
+
+	ldr	r0,=L2CCIntRaw			/* clear pending interrupts */
+	ldr	r1,[r0]
+	ldr	r0,=L2CCIntClear
+	str	r1,[r0]
+
+	ldr	r0,=SLCRUnlockReg		/* Load SLCR base address base + unlock register */
+	ldr	r1,=SLCRUnlockKey	    	/* set unlock key */
+	str	r1, [r0]		    	/* Unlock SLCR */
+
+	ldr	r0,=SLCRL2cRamReg		/* Load SLCR base address base + l2c Ram Control register */
+	ldr	r1,=SLCRL2cRamConfig        	/* set the configuration value */
+	str	r1, [r0]	        	/* store the L2c Ram Control Register */
+
+	ldr	r0,=SLCRlockReg         	/* Load SLCR base address base + lock register */
+	ldr	r1,=SLCRlockKey	        	/* set lock key */
+	str	r1, [r0]	        	/* lock SLCR */
+
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	ldr	r1,[r0]				/* read the register */
+	mov	r2, #L2CCControl		/* set the enable bit */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* enable the L2 Caches */
+#endif
+
+	mov	r0, r0
+	mrc	p15, 0, r1, c1, c0, 2		/* read cp access control register (CACR) into r1 */
+	orr	r1, r1, #(0xf << 20)		/* enable full access for p10 & p11 */
+	mcr	p15, 0, r1, c1, c0, 2		/* write back into CACR */
+
+	/* enable vfp */
+	fmrx	r1, FPEXC			/* read the exception register */
+	orr	r1,r1, #FPEXC_EN		/* set VFP enable bit, leave the others in orig state */
+	fmxr	FPEXC, r1			/* write back the exception register */
+
+	mrc	p15,0,r0,c1,c0,0		/* flow prediction enable */
+	orr	r0, r0, #(0x01 << 11)		/* #0x8000 */
+	mcr	p15,0,r0,c1,c0,0
+
+	mrc	p15,0,r0,c1,c0,1		/* read Auxiliary Control Register */
+	orr	r0, r0, #(0x1 << 2)		/* enable Dside prefetch */
+	orr	r0, r0, #(0x1 << 1)		/* enable L2 Prefetch hint */
+	mcr	p15,0,r0,c1,c0,1		/* write Auxiliary Control Register */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	bic	r0, r0, #0x100			/* enable asynchronous abort exception */
+	msr	cpsr_xsf, r0
+
+
+	b	_start				/* jump to C startup code */
+	and	r0, r0, r0			/* no op */
+
+.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
+
+
+/*
+ *************************************************************************
+ *
+ * invalidate_dcache - invalidate the entire d-cache by set/way
+ *
+ * Note: for Cortex-A9, there is no cp instruction for invalidating
+ * the whole D-cache. Need to invalidate each line.
+ *
+ *************************************************************************
+ */
+invalidate_dcache:
+	mrc	p15, 1, r0, c0, c0, 1		/* read CLIDR */
+	ands	r3, r0, #0x7000000
+	mov	r3, r3, lsr #23			/* cache level value (naturally aligned) */
+	beq	finished
+	mov	r10, #0				/* start with level 0 */
+loop1:
+	add	r2, r10, r10, lsr #1		/* work out 3xcachelevel */
+	mov	r1, r0, lsr r2			/* bottom 3 bits are the Cache type for this level */
+	and	r1, r1, #7			/* get those 3 bits alone */
+	cmp	r1, #2
+	blt	skip				/* no cache or only instruction cache at this level */
+	mcr	p15, 2, r10, c0, c0, 0		/* write the Cache Size selection register */
+	isb					/* isb to sync the change to the CacheSizeID reg */
+	mrc	p15, 1, r1, c0, c0, 0		/* reads current Cache Size ID register */
+	and	r2, r1, #7			/* extract the line length field */
+	add	r2, r2, #4			/* add 4 for the line length offset (log2 16 bytes) */
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		/* r4 is the max number on the way size (right aligned) */
+	clz	r5, r4				/* r5 is the bit position of the way size increment */
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		/* r7 is the max number of the index size (right aligned) */
+loop2:
+	mov	r9, r4				/* r9 working copy of the max way size (right aligned) */
+loop3:
+	orr	r11, r10, r9, lsl r5		/* factor in the way number and cache number into r11 */
+	orr	r11, r11, r7, lsl r2		/* factor in the index number */
+	mcr	p15, 0, r11, c7, c6, 2		/* invalidate by set/way */
+	subs	r9, r9, #1			/* decrement the way number */
+	bge	loop3
+	subs	r7, r7, #1			/* decrement the index */
+	bge	loop2
+skip:
+	add	r10, r10, #2			/* increment the cache number */
+	cmp	r3, r10
+	bgt	loop1
+
+finished:
+	mov	r10, #0				/* swith back to cache level 0 */
+	mcr	p15, 2, r10, c0, c0, 0		/* select current cache level in cssr */
+	dsb
+	isb
+
+	bx	lr
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.o
new file mode 100644
index 0000000..059dff0
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/boot.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/bspconfig.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/bspconfig.h
new file mode 100644
index 0000000..50464da
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/changelog.txt b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/changelog.txt
new file mode 100644
index 0000000..1d542b1
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/changelog.txt
@@ -0,0 +1,491 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ *		       of L2Cache is done later.
+ * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ *		       taking long time to fix CR#853097. L2CacheSync is added into
+ *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
+ * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
+ *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ *		       accordingly generate the	translation table
+ * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS to fix a bug introduced during new version creation
+ *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ *		       definition for dsb, isb and dmb to fix the compilation error when used
+ *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ *		       R5 deadlock for errata 780125
+ * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ *		       32 bit BSP in the initialization
+ * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
+ *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
+ *                     required for MISRA-C:2012 Compliance.
+ * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ *		       in cortexa9/xil_mmu.h
+ * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
+ *		       checking the current executing platform
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ *		       to initialize global constructor for C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ *		       C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ *		       translation_table.S to update the translation table according to proper
+ *		       address map
+ * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
+ *		       address map
+ * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ *		       equivalent to vector table base address
+ * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ *		       as per the toolchain update
+ * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
+ *		       for Cortex-A53 32bit mode
+ * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ *		       instead take it from xparameters.h to properly configure the timestamp
+ *		       clock frequency
+ * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
+ *		       new instructions for MB address extension feature
+ * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
+ *		       system monitor.
+ * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ *		       use set of assembly instructions to provide required delay to fix
+ *		       CR#913249.
+ * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ *		       _exit with exit. We should not be directly calling _exit and should
+ *		       always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
+ *		       registers, banked registers for various modes and enabled
+ *		       the cache ECC check before enabling the fault log for lock step mode
+ *		       Also modified the cortexr5/gcc/Makefile to support floating point
+ *		       registers initialization in boot code.
+ * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ *		       logic in case of lock-step mode when fault log is enabled to fix
+ *		       CR#938281
+ * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ *		       header file instrinsics.h which contains assembly instructions
+ *		       definitions which can be used by C
+ * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ *		       interrupts when sleep/usleep is being executed using assembly
+ *		       instructions to fix CR#913249.
+ * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ *		       value and compare it with previous value to detect the overflow
+ *		       to fix CR#940209.
+ * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ *		       the fault log to avoid intervention for lock-step mode and cortexr5/
+ *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ *		       to fix CR#947335
+ * 5.5 pkp   04/11/16  Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ *		       in lock-step to avoid resetting the debug logic which restricts the
+ *		       access for debugger and removed enabling back of debug modules in
+ *		       cortexr5/_exit.c
+ * 5.5 pkp   04/13/16  Modified cortexa9/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ *		       to return correct number of bytes when read buffer is filled and
+ *		       removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexr5/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ *		       instruction macros to disable certain optimizations which may move
+ *		       code out of loops if optimizers believe that the code will always
+ *		       return the same result or discard asm statements if optimizers
+ *		       determine there is no need for the output variables
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ *		       sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ *		       sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ *		       to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * 		       Xil_DCacheInvalidateRange functions description for proper
+ *		       explaination to fix CR#949801
+ * 5.5 asa   04/20/16  Added missing macros for hibernate and suspend in Microblaze BSP
+ *                     file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa   04/29/16  Fix for CR#951080. Updated cache APIs for HW designs where cache
+ *                     memory is not included for MicroBlaze.
+ * 5.5 pkp   05/06/16  Modified the cortexa9/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp   05/06/16  Modified the cortexr5/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn   05/31/16  Make Xil_AsserWait a global variable
+ * 6.0 pkp   06/27/16  Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ *		       section since it is part of boot process to fix CR#949555
+ *     hk    07/12/16  Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp   07/25/16  Program the counter frequency in boot code for CortexA53
+ * 6.0 asa   08/03/16  Updated sleep_common function in microblaze_sleep.c to improve the
+ *                     the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus   08/03/16  Restructured the BSP to avoid code duplication across all BSPs.
+ *                     Source code directories specific to ARM processor's are moved to src/arm
+ *                     directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ *                     src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ *                     print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ *                     consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ *                     xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ *                     into common file each and consolidated files are kept at src/arm/common directory.
+ *                     GCC source files related to file  operations are consolidated and kept
+ *                     at src/arm/common/gcc directory.
+ *                     All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ *                     are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ *                     xil_io.h must be included as a header file to access io interfacing functions.
+ *                     Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus   08/11/16  Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ *                     TTC counter value register is read only.
+ * 6.0 asa   08/15/16  Modified the signatures for functions sleep and usleep. This fixes
+ *                     the CR#956899.
+ * 6.0 mus   08/18/16  Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ *                     in cortexr5/xparameters_ps.h
+ * 6.0 mus   08/18/16  Added support for the the Zynq 7000s devices
+ * 6.0 mus   08/18/16  Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus   08/19/16  Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus   11/03/16  Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ *                     these APIs and modifications are done on top of it to handle stdout/stdin
+ *                     parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk   11/07/16  Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp   12/14/16  Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ *		       0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ *		       and rest of the memory in that 32GB region is marked as reserved to avoid
+ *		       any speculative access
+ * 6.2 pkp   12/23/16  Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ *		       asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ *		       access is enabled if there is any floating point operation, it is disabled by
+ *		       default. Also FPU is initally disabled for IRQ and none of the floating point
+ *		       registers are saved during normal context saving. If IRQ handler does not require
+ *		       floating point operation, the floating point registers are untouched and no need
+ *		       for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ *		       point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ *		       registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus   01/01/17  Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ *                     target.It fixes the CR#966900
+ * 6.2 pkp   01/22/17  Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ *		       64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ *		       for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ *		       as false i.e. default bsp is EL3.
+ * 6.2 pkp   01/24/17  Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ *		       contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ *		       when bss sections are not cleared, it may contain previously updated value which
+ *		       does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa   01/31/17  The existing Xil_DCacheDisable API first flushes the
+ *		       D caches and then disables it. The problem with that is,
+ *		       potentially there will be a small window after the cache
+ *		       flush operation and before the we disable D caches where
+ *		       we might have valid data in cache lines. In such a
+ *		       scenario disabling the D cache can lead to unknown behavior.
+ *		       The ideal solution to this is to use assembly code for
+ *		       the complete API and avoid any memory accesses. But with
+ *		       that we will end up having a huge amount on assembly code
+ *		       which is not maintainable. Changes are done to use a mix
+ *		       of assembly and C code. All local variables are put in
+ *		       registers. Also function calls are avoided in the API to
+ *		       avoid using stack memory.
+ * 6.2 mus   02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ *                    scenarios when an invalidated cache line can get pre fetched to cache.
+ *                    If that happens, the coherency between cache and memory is lost
+ *                    resulting in lost data. To avoid this kind of issue either
+ *                    user has to use dsb() or disable pre-fetching for L1 cache
+ *                    or else reduce maximum number of outstanding data prefetches allowed.
+ *                    Using dsb() while comparing data costing more performance compared to
+ *                    disabling pre-fetching/reducing maximum number of outstanding data
+ *                    prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ *                    to disable pre-fetching/configure maximum number of outstanding data
+ *                    prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp   02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ *		      used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn   03/03/17 Added support thumb mode
+ * 6.2 mus   03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ *                    It fixes CR#970543
+ * 6.2 asa   03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ *                    profiling we see a crash. That is because the the tcl uses invalid
+ *                    HSI command. This change fixes it.
+ * 6.2 mus   03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ *                    any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus   03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus   04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ *                    the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus   04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ *                    L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus   06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ *                    of ARM 32 bit processor's.
+ * 6.4 mus   06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in  IRQInterruptHandler code
+ *                    snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms    05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ *                    XGetPSVersion_Info function for PMUFW.
+ *     ms    06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ *                    function for PMUFW.
+ * 6.4 mus   07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus   07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ *                    operations.Now,VFP is being enabled in FPEXC register, through boot code
+ *                    and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk   08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * 		      if h/w design configured with HPC port.
+ * 6.4 mus   08/10/17 Updated a53 64 bit translation table to mark  memory as a outer shareable for
+ *                    EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus   08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ *                    CR#982209.
+ * 6.4 asa   08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ *                    make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus   08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ *                    version register through SMC call, over EL1 NS mode. This change has been done to
+ *                    support these APIs over EL1 NS mode.
+ * 6.5 mus   10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ *                    it fixes CR#987464.
+ *
+ *****************************************************************************************/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.c
new file mode 100644
index 0000000..dbbe0d4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.o
new file mode 100644
index 0000000..1f89337
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/close.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/config.make b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/config.make
new file mode 100644
index 0000000..2668199
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/config.make
@@ -0,0 +1,3 @@
+LIBSOURCES = *.c *.S
+PROFILE_ARCH_OBJS = profile_mcount_arm.o
+LIBS = standalone_libs
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.S
new file mode 100644
index 0000000..2b4048f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.S
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0   pkp	12/16/14 removed incorrect initialization of TLB lockdown
+*			 register to fix CR#830580
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.text
+	.global __cpu_init
+	.align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+	mov	r0, #0x0
+	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
+	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
+	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
+	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
+	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
+	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
+	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
+
+/* Reset and start Cycle Counter */
+	mov	r2, #0x80000000		/* clear overflow */
+	mcr	p15, 0, r2, c9, c12, 3
+	mov	r2, #0xd		/* D, C, E */
+	mcr	p15, 0, r2, c9, c12, 0
+	mov	r2, #0x80000000		/* enable cycle counter */
+	mcr	p15, 0, r2, c9, c12, 1
+
+	bx	lr
+
+.end
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.o
new file mode 100644
index 0000000..dd83df5
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/cpu_init.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.c
new file mode 100644
index 0000000..df0218e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.o
new file mode 100644
index 0000000..474c33e
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/errno.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.c
new file mode 100644
index 0000000..e58221a
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.o
new file mode 100644
index 0000000..8fc4013
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fcntl.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.c
new file mode 100644
index 0000000..c5a31f3
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.o
new file mode 100644
index 0000000..970cc06
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/fstat.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.c
new file mode 100644
index 0000000..d02df5c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.o
new file mode 100644
index 0000000..2af2a1d
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/getpid.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.c
new file mode 100644
index 0000000..0036459
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.o
new file mode 100644
index 0000000..b27e468
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/inbyte.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.c
new file mode 100644
index 0000000..f142515
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.o
new file mode 100644
index 0000000..8860149
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/isatty.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.c
new file mode 100644
index 0000000..fc2f89d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.o
new file mode 100644
index 0000000..bb0b896
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/kill.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.c
new file mode 100644
index 0000000..106c45c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.o
new file mode 100644
index 0000000..1619875
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/lseek.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.c
new file mode 100644
index 0000000..85e9ce4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.o
new file mode 100644
index 0000000..d1131f2
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/open.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.c
new file mode 100644
index 0000000..8b56036
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.o
new file mode 100644
index 0000000..eb7c346
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/outbyte.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.c
new file mode 100644
index 0000000..74d70ee
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.o
new file mode 100644
index 0000000..6f0a255
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/print.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/Makefile
new file mode 100644
index 0000000..891fdf6
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/Makefile
@@ -0,0 +1,78 @@
+###############################################################################
+#
+# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Makefile for profiler
+#
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include:
+	$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_clean.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_clean.c
new file mode 100644
index 0000000..1d8aada
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_clean.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+	Xil_ExceptionDisable();
+	disable_timer();
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_init.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_init.c
new file mode 100644
index 0000000..0ac51b1
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_init.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+*	Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ *  Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1;	/* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE;    			/* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ;	/* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ;	/* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* 	print("Gmon Init called....\r\n")  */
+/* 	putnum(n_gmon_sections) , print("\r\n")   */
+/* 	if( _gmonparam == 0xffffffff ) */
+/* 		printf("Gmonparam is NULL !!\r\n")  */
+/* 	for( i = 0, i < n_gmon_sections, i++ )[ */
+/* 		putnum( _gmonparam[i].lowpc) , print("\t")   */
+/* 		putnum( _gmonparam[i].highpc) , print("\r\n")  */
+/* 		putnum( _gmonparam[i].textsize ), print("\r\n")  */
+/* 		putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n")  */
+/* 	] */
+
+#ifdef PROC_MICROBLAZE
+	(void)microblaze_init();
+#elif defined PROC_PPC
+	powerpc405_init();
+#else
+	(void)cortexa9_init();
+#endif
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000..e85fb5c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.c
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+*  _program_timer_hw.c:
+*	Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif	/* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif	/* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif	/* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif	/* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+  * PowerPC Target - Timer related functions
+  *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+*	Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set PIT Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_PITSetInterval( timer_clk_ticks ) ;
+	XTime_PITEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+*	For PowerPC, PIT and opb_timer can be used for Profiling. This
+*	is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+	Xil_ExceptionInit() ;
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	  * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+	  * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	  * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+  * PowerPC440 Target - Timer related functions
+  * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ *	Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set DEC Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_DECSetInterval( timer_clk_ticks ) ;
+	XTime_DECEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ *	For PowerPC, DEC and opb_timer can be used for Profiling. This
+ *	is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+	Xil_ExceptionInit();
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	 * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+	 * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting */
+	XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+	/* reset the timers, and clear interrupts */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+				     (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+	/* start the timers */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+			     | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ *	For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ *	connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+	/* Register profile_intr_handler
+	 * 1. If timer is connected to Interrupt Controller, register the handler
+	 *    to Interrupt Controllers vector table.
+	 * 2. If timer is directly connected to MicroBlaze, register the handler
+	 *    as Interrupt handler */
+	Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)profile_intr_handler,
+				     NULL) ;
+#endif
+
+	/* Initialize the timer with Timer Ticks */
+	(void)opb_timer_init() ;
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+	XIntc_MasterEnable((u32)INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+	Xil_ExceptionEnable();
+
+	return 0;
+
+}
+
+#endif	/* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ *	The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting
+	 * scu timer runs at half the cpu clock */
+	XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+	/* clear any pending interrupts */
+	XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+	/* enable interrupts, auto-reload mode and start the timer */
+	XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+	Xil_ExceptionInit();
+
+	XScuGic_DeviceInitialize(0);
+
+	/*
+	 * Connect the interrupt controller interrupt handler to the hardware
+	 * interrupt handling logic in the processor.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+				(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+				NULL);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+				PROFILE_TIMER_INTR_ID,
+				(Xil_ExceptionHandler)profile_intr_handler,
+				NULL);
+
+	/*
+	 * Enable the interrupt for scu timer.
+	 */
+	XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+	/*
+	 * Enable interrupts in the Processor.
+	 */
+	Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+	/*
+	 * Initialize the timer with Timer Ticks
+	 */
+	(void)scu_timer_init() ;
+
+	Xil_ExceptionEnable();
+
+	return 0;
+}
+
+#endif	/* PROC_CORTEXA9 */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000..2cee66b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/_profile_timer_hw.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+*	Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/dummy.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/dummy.S
new file mode 100644
index 0000000..d28646d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/dummy.S
@@ -0,0 +1,64 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+	.text
+	.align 2
+	.ent dummy_f
+
+dummy_f:
+	nop
+
+	.end dummy_f
+#endif
+
+#ifdef PROC_PPC
+	.section .text
+	.align 2
+	.type dummy_f@function
+
+dummy_f:
+	b dummy_f
+
+#endif
+
+#ifdef PROC_CORTEXA9
+	.section .text
+	.align 2
+	.type dummy_f, %function
+
+dummy_f:
+	b dummy_f
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/mblaze_nt_types.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000..7096a92
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/mblaze_nt_types.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile.h
new file mode 100644
index 0000000..4cb07a7
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include 
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_cg.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_cg.c
new file mode 100644
index 0000000..2539ce6
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_cg.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include 
+#include 
+#include 
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+	s32 index = 0 ;
+
+	while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == cgtable_size ) {
+		return -1 ;
+	} else {
+		return index ;
+	}
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+	s32 index = 0 ;
+	s32 Status;
+
+	while( (index < fromssize) && (froms[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == fromssize ) {
+		Status = -1 ;
+	} else {
+		Status = index ;
+	}
+	return Status;
+}
+#endif		/* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+	register struct gmonparam *p = NULL;
+	register s32 toindex, fromindex;
+	s32 j;
+
+	disable_timer();
+
+	/*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+	 * check that frompcindex is a reasonable pc value.
+	 * for example:	signal catchers get called from the stack,
+	 *		not from text space.  too bad.
+	*/
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+			p = &_gmonparam[j];
+			break;
+		}
+	}
+	if( j == n_gmon_sections ) {
+		goto done;
+	}
+
+#ifdef PROFILE_NO_FUNCPTR
+	fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = p->cgtable_size ;
+		p->cgtable_size++ ;
+		p->cgtable[fromindex].frompc = frompc ;
+		p->cgtable[fromindex].selfpc = selfpc ;
+		p->cgtable[fromindex].count = 1 ;
+		goto done ;
+	}
+	p->cgtable[fromindex].count++ ;
+#else
+	fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = (s32)p->fromssize ;
+		p->fromssize++ ;
+		/*if( fromindex >= N_FROMS ) {
+		* print("Error : From PC table overflow\r\n")
+		* goto overflow
+		*}*/
+		p->froms[fromindex].frompc = frompc ;
+		p->froms[fromindex].link = -1 ;
+	}else {
+		toindex = ((s32)(p->froms[fromindex].link));
+		while(toindex != -1) {
+			toindex = (((s32)p->tossize) - toindex)-1 ;
+			if( p->tos[toindex].selfpc == selfpc ) {
+				p->tos[toindex].count++ ;
+				goto done ;
+			}
+			toindex = ((s32)(p->tos[toindex].link)) ;
+		}
+	}
+
+	/*if( toindex == -1 ) { */
+	p->tos-- ;
+	p->tossize++ ;
+	/* if( toindex >= N_TOS ) {
+	* print("Error : To PC table overflow\r\n")
+	* goto overflow
+	*} */
+	p->tos[0].selfpc = selfpc ;
+	p->tos[0].count = 1 ;
+	p->tos[0].link = p->froms[fromindex].link ;
+	p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+	p->state = GMON_PROF_ON;
+	goto enable_timer_label ;
+ /* overflow: */
+	/*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+	enable_timer();
+	return ;
+}
+
+
+#endif		/* PROFILE_NO_GRAPH */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_config.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_config.h
new file mode 100644
index 0000000..550c60b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_config.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_hist.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_hist.c
new file mode 100644
index 0000000..c8ee9ce
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_hist.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+	s32 j;
+
+#ifdef PROC_MICROBLAZE
+	asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+	prof_pc = mfspr(SPR_SRR0);
+#else
+	/* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+	/* print("PC: "), putnum(prof_pc), print("\r\n"), */
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+			_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+			break;
+		}
+	}
+	/* Ack the Timer Interrupt */
+	timer_ack();
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_arm.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_arm.S
new file mode 100644
index 0000000..e62cec0
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_arm.S
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+	push	{r0, r1, r2, r3, lr}
+	subs	r1, lr, #0			/* callee - current lr */
+	ldr	r0, [sp, #20]			/* caller - at the top of the stack */
+	bl	mcount				/* when __gnu_mcount_nc is called */
+	pop	{r0, r1, r2, r3, ip, lr}
+	bx	ip
+
+	.end __gnu_mcount_nc
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_mb.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_mb.S
new file mode 100644
index 0000000..bea2726
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_mb.S
@@ -0,0 +1,69 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl _mcount
+	.text
+	.align 2
+	.ent _mcount
+
+	#ifndef PROFILE_NO_GRAPH
+
+_mcount:
+	addi r1, r1, -48
+	swi r11, r1, 44
+	swi r12, r1, 40
+	swi r5, r1, 36
+	swi r6, r1, 32
+	swi r7, r1, 28
+	swi r8, r1, 24
+	swi r9, r1, 20
+	swi r10, r1, 16
+	swi r15, r1, 12
+	add r5, r0, r15
+	brlid r15, mcount
+	add r6, r0, r16
+
+	lwi r11, r1, 44
+	lwi r12, r1, 40
+	lwi r5, r1, 36
+	lwi r6, r1, 32
+	lwi r7, r1, 28
+	lwi r8, r1, 24
+	lwi r9, r1, 20
+	lwi r10, r1, 16
+	lwi r15, r1, 12
+	rtsd r15, 4
+	addi r1, r1, 48
+
+	#endif	/* PROFILE_NO_GRAPH */
+
+	.end _mcount
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_ppc.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_ppc.S
new file mode 100644
index 0000000..39bb92f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/profile/profile_mcount_ppc.S
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl _mcount
+
+	#define _MCOUNT_STACK_FRAME 48
+	.section .text
+	.align 2
+	.type _mcount@function
+
+
+_mcount:
+	stwu 1,	-_MCOUNT_STACK_FRAME(1)
+	stw 3, 8(1)
+	stw 4, 12(1)
+	stw 5, 16(1)
+	stw 6, 20(1)
+	stw 7, 24(1)
+	stw 8, 28(1)
+	stw 9, 32(1)
+	stw 10, 36(1)
+	stw 11, 40(1)
+	stw 12, 44(1)
+	mflr 4
+	stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+	lwz 3, (_MCOUNT_STACK_FRAME)(1)
+	lwz 3, 4(3)
+	bl mcount
+	lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+	mtlr 4
+	lwz 12, 44(1)
+	lwz 11, 40(1)
+	lwz 10, 36(1)
+	lwz 9, 32(1)
+	lwz 8, 28(1)
+	lwz 7, 24(1)
+	lwz 6, 20(1)
+	lwz 5, 16(1)
+	lwz 4, 12(1)
+	lwz 3, 8(1)
+	addi 1,1, _MCOUNT_STACK_FRAME
+	blr
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.c
new file mode 100644
index 0000000..aaf9ede
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  s32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
+    digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.o
new file mode 100644
index 0000000..7e0b749
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/putnum.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.c
new file mode 100644
index 0000000..7f7b7d2
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.o
new file mode 100644
index 0000000..466e306
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/read.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.c
new file mode 100644
index 0000000..64d5156
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.o
new file mode 100644
index 0000000..a9bf3db
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sbrk.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.c
new file mode 100644
index 0000000..039fa61
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 
    
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+unsigned sleep(unsigned int seconds)
+{
+  XTime tEnd, tCur;
+
+  XTime_GetTime(&tCur);
+  tEnd  = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+  do
+  {
+    XTime_GetTime(&tCur);
+  } while (tCur < tEnd);
+
+  return 0;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.h
new file mode 100644
index 0000000..27add66
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.o
new file mode 100644
index 0000000..f7c6e97
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/sleep.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/smc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/smc.h
new file mode 100644
index 0000000..5a4d336
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* 
    
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.S
new file mode 100644
index 0000000..ade44de
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.S
@@ -0,0 +1,223 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* @addtogroup a9_boot_code
+* @{
+* 
     translation_table.S 
    
+* translation_table.S contains a static page table required by MMU for
+* cortex-A9. This translation table is flat mapped (input address = output
+* address) with default memory attributes defined for zynq architecture. It
+* utilizes short descriptor translation table format with each section defining
+* 1MB of memory.
+*
+* The overview of translation table memory attributes is described below.
+*
+*|                       | Memory Range            | Definition in Translation Table   |
+*|-----------------------|-------------------------|-----------------------------------|
+*| DDR                   | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable       |
+*| PL                    | 0x40000000 - 0xBFFFFFFF | Strongly Ordered                  |
+*| Reserved              | 0xC0000000 - 0xDFFFFFFF | Unassigned                        |
+*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory                     |
+*| Reserved              | 0xE0300000 - 0xE0FFFFFF | Unassigned                        |
+*| NAND, NOR             | 0xE1000000 - 0xE3FFFFFF | Device memory                     |
+*| SRAM                  | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable       |
+*| Reserved              | 0xE6000000 - 0xF7FFFFFF | Unassigned                        |
+*| AMBA APB Peripherals  | 0xF8000000 - 0xF8FFFFFF | Device Memory                     |
+*| Reserved              | 0xF9000000 - 0xFBFFFFFF | Unassigned                        |
+*| Linear QSPI - XIP     | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable    |
+*| Reserved              | 0xFE000000 - 0xFFEFFFFF | Unassigned                        |
+*| OCM                   | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
+*
+* @note
+*
+* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
+* region after DDR and before PL is marked as undefined/reserved in translation
+* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
+* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved  but due to granual size
+* of 1MB, it is not possible to define separate regions for them. For region
+* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
+* granual size, it is not possible to define separate region for it
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2	pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*			and  0xe0000000 - 0xe1ffffff is broken down into
+*			0xe0000000 - 0xe02fffff (memory mapped devides)
+*			0xe0300000 - 0xe0ffffff (reserved) and
+*			0xe1000000 - 0xe1ffffff (NAND)
+* 5.2	pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+*			if DDR is present or not and accordingly generate the
+*			translation table
+* 6.1	pkp  07/11/2016 Corrected comments for memory attributes
+* 
    
+*
+*
+******************************************************************************/
+#include "xparameters.h"
+	.globl  MMUTable
+
+	.section .mmu_tbl,"a"
+
+MMUTable:
+	/* Each table entry occupies one 32-bit word and there are
+	 * 4096 entries, so the entire table takes up 16KB.
+	 * Each entry covers a 1MB section.
+	 */
+.set SECT, 0
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+.set DDR_SIZE, (DDR_END - DDR_START)+1
+.set DDR_REG, DDR_SIZE/0x100000
+#else
+.set DDR_REG, 0
+#endif
+
+.set UNDEF_REG, 0x3FF - DDR_REG
+
+				/*0x00000000 - 0x00100000 (cacheable )*/
+.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+
+.rept	DDR_REG			/*  (DDR Cacheable) */
+.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	UNDEF_REG			/*  (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+
+.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0200			/* 0xc0000000 - 0xdfffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x003			/* 0xe0000000 - 0xe02fffff (Memory mapped devices)
+				 * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0D			/* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0010			/* 0xe1000000 - 0xe1ffffff (NAND) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe2000000 - 0xe3ffffff (NOR) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe4000000 - 0xe5ffffff (SRAM) */
+.word	SECT + 0xc0e		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0120			/* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
+   0xf8f03000 to 0xf8ffffff are reserved  but due to granual size of
+   1MB, it is not possible to define separate regions for them */
+
+.rept	0x0010			/* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
+
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0030			/* 0xf9000000 - 0xfbffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
+.word	SECT + 0xc0a		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x001F			/* 0xfe000000 - 0xffefffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
+   1MB, it is not possible to define separate region for  it
+
+ 0xfff00000 - 0xffffffff
+   256K OCM when mapped to high address space
+   inner-cacheable */
+.word	SECT + 0x4c0e		/* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.o
new file mode 100644
index 0000000..d5cb78b
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/translation_table.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.c
new file mode 100644
index 0000000..d0cc680
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+  (void) path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.o
new file mode 100644
index 0000000..2ac1faa
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/unlink.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.c
new file mode 100644
index 0000000..9171d43
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.c
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 
    
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+int usleep(unsigned long useconds)
+{
+	XTime tEnd, tCur;
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	return 0;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.o
new file mode 100644
index 0000000..c1bd02c
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/usleep.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.c
new file mode 100644
index 0000000..0a36163
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.c
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.h
new file mode 100644
index 0000000..bb599b5
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.o
new file mode 100644
index 0000000..61baf48
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/vectors.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.c
new file mode 100644
index 0000000..aaa879e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.o
new file mode 100644
index 0000000..8b5272d
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/write.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xbasic_types.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xbasic_types.h
new file mode 100644
index 0000000..787212c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 
    
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include 
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xdebug.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xdebug.h
new file mode 100644
index 0000000..650946b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv.h
new file mode 100644
index 0000000..3d97beb
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv_standalone.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv_standalone.h
new file mode 100644
index 0000000..f186018
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 
    
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include 
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * 

    
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.S b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.S
new file mode 100644
index 0000000..64175fe
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.S
@@ -0,0 +1,150 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2	pkp  08/04/14 Removed PEEP board related code which contained
+*		      initialization of uart smc nor and sram
+* 5.3	pkp  10/07/15 Added support for OpenAMP by not initializing global
+*		      timer when USE_AMP flag is defined
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start
+
+.Lbss_end:
+	.long	__bss_end
+
+.Lstack:
+	.long	__stack
+
+
+	.globl	_start
+_start:
+	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+
+	mov	r0, #0
+
+	/* clear sbss */
+	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
+
+.Lloop_sbss:
+	cmp	r1,r2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	r2,.Lbss_end		/* calculate end of the BSS */
+
+.Lloop_bss:
+	cmp	r1,r2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	/* set stack pointer */
+	ldr	r13,.Lstack		/* stack address */
+
+    /* Reset and start Global Timer */
+	mov	r0, #0x0
+	mov	r1, #0x0
+
+#if USE_AMP != 1
+	bl XTime_SetTime
+#endif
+
+#ifdef PROFILING			/* defined in Makefile */
+	/* Setup profiling stuff */
+	bl	_profile_init
+#endif /* PROFILING */
+
+   /* run global constructors */
+   bl __libc_init_array
+
+	/* make sure argc and argv are valid */
+	mov	r0, #0
+	mov	r1, #0
+
+	/* Let her rip */
+	bl	main
+
+   /* Cleanup global constructors */
+   bl __libc_fini_array
+
+#ifdef PROFILING
+	/* Cleanup profiling stuff */
+	bl	_profile_clean
+#endif /* PROFILING */
+
+        /* All done */
+	bl	exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_start,.Lstart-_start
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.o
new file mode 100644
index 0000000..22a2f44
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil-crt0.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.c
new file mode 100644
index 0000000..59b3c1c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    Implement assert. Currently, it calls a user-defined callback
+*           function if one has been set.  Then, it potentially enters an
+*           infinite loop depending on the value of the Xil_AssertWait
+*           variable.
+*
+* @param    file: filename of the source
+* @param    line: linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Set up a callback function to be invoked when an assert occurs.
+*           If a callback is already installed, then it will be replaced.
+*
+* @param    routine: callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Null handler function. This follows the XInterruptHandler
+*           signature for interrupt handlers. It can be used to assign a null
+*           handler (a stub) to an interrupt controller vector table.
+*
+* @param    NullParameter: arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+	(void) NullParameter;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.h
new file mode 100644
index 0000000..add4124
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	        case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
+*
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	      case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_assert.o
new file mode 100644
index 0000000..eeee03b
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diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.c
new file mode 100644
index 0000000..83f6835
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.c
@@ -0,0 +1,1621 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+	extern s32  _stack_end;
+	extern s32  __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param	Value, value to be written to Debug Control Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+	(void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+#ifdef CONFIG_PL310_ERRATA_753970
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+#endif
+}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	Xil_L1DCacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1DCacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a Data cache line. If the byte specified by the address
+* 			(adr) is cached by the Data cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			modified contents are lost and are NOT written to the system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1DCacheInvalidateLine(adr);
+
+	mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+*			cache, the cachelines containing those bytes are invalidated. If
+*			the cachelines are modified (dirty), the modified contents are lost
+*			and NOT written to the system memory before the lines are
+*			invalidated.
+*
+* 			In this function, if start address or end address is not aligned to
+* 			cache-line, particular cache-line containing unaligned start or end
+* 			address is flush first and then invalidated the others as
+* 			invalidating the same unaligned cache line may result into loss of
+*			data. This issue raises few possibilities.
+*
+* 			If the address to be invalidated is not cache-line aligned, the
+* 			following choices are available:
+* 			1. Invalidate the cache line when required and do not bother much
+* 			for the side effects. Though it sounds good, it can result in
+* 			hard-to-debug issues. The problem is, if some other variable are
+* 			allocated in the same cache line and had been recently updated
+* 			(in cache), the invalidation would result in loss of data.
+* 			2. Flush the cache line first. This will ensure that if any other
+* 			variable present in the same cache line and updated recently are
+* 			flushed out to memory. Then it can safely be invalidated. Again it
+* 			sounds good, but this can result in issues. For example, when the
+* 			invalidation happens in a typical ISR (after a DMA transfer has
+* 			updated the memory), then flushing the cache line means, loosing
+* 			data that were updated recently before the ISR got invoked.
+*
+* 			Linux prefers the second one. To have uniform implementation
+* 			(across standalone and Linux), the second option is implemented.
+* 			This being the case, follwoing needs to be taken care of:
+* 			1. Whenever possible, the addresses must be cache line aligned.
+* 			Please nore that, not just start address, even the end address must
+* 			be cache line aligned. If that is taken care of, this will always
+*			work.
+* 			2. Avoid situations where invalidation has to be done after the
+* 			data is updated by peripheral/DMA directly into the memory. It is
+* 			not tough to achieve (may be a bit risky). The common use case to
+* 			do invalidation is when a DMA happens. Generally for such use
+*			cases, buffers can be allocated first and then start the DMA. The
+* 			practice that needs to be followed here is, immediately after
+* 			buffer allocation and before starting the DMA, do the invalidation.
+* 			With this approach, invalidation need not to be done after the DMA
+*			transfer is over.
+*
+* 			This is going to always work if done carefully.
+* 			However, the concern is, there is no guarantee that invalidate has
+* 			not needed to be done after DMA is complete. For example, because
+* 			of some reasons if the first cache line or last cache line
+* 			(assuming the buffer in question comprises of multiple cache lines)
+*			are brought into cache (between the time it is invalidated and DMA
+* 			completes) because of some speculative prefetching or reading data
+* 			for a variable present in the same cache line, then we will have to
+*			invalidate the cache after DMA is complete.
+*
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempadr);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+			tempadr += cacheline;
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempend);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+		}
+
+		while (tempadr < tempend) {
+#ifndef USE_AMP
+			/* Invalidate L2 cache line */
+			*L2CCOffset = tempadr;
+			Xil_L2CacheSync();
+#endif
+
+	/* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = tempadr; }
+#endif
+			tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlush();
+#ifndef USE_AMP
+	Xil_L2CacheFlush();
+#endif
+	mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Flush a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache, the cacheline containing that byte is
+* 			invalidated. If the cacheline is modified (dirty), the entire
+* 			contents of the cacheline are written to system memory before the
+* 			line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_L2CacheFlushLine(adr);
+
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+	Xil_L2CacheSync();
+#endif
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the
+* 			data cache, the cachelines containing those bytes are invalidated.
+* 			If the cachelines are modified (dirty), they are written to the
+* 			system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+
+	/* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+			/* Flush L2 cache line */
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief	Store a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache and the cacheline is modified (dirty),
+* 			the entire contents of the cacheline are written to system memory.
+* 			After the store completes, the cacheline is marked as unmodified
+* 			(not dirty).
+*
+* @param	adr: 32bit address of the data to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+	Xil_L2CacheStoreLine(adr);
+#endif
+	mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief	Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	Xil_L1ICacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1ICacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate an instruction cache line. If the instruction specified
+*			by the address is cached by the instruction cache, the cacheline
+*			containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1ICacheInvalidateLine(adr);
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the instruction cache for the given address range.
+* 			If the instructions specified by the address range are cached by
+* 			the instrunction cache, the cachelines containing those
+*			instructions are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+#ifndef USE_AMP
+		/* Invalidate L2 cache line */
+		*L2CCOffset = LocalAddr;
+		dsb();
+#endif
+
+		/* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 and L2 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+		return;
+	}
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheInvalidate();
+
+	/* enable the Data cache */
+	CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for invalidating
+*			the whole D-cache. This function invalidates each line by
+*			set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way, WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+#endif
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/*Flush stack memory to save return address*/
+	Xil_DCacheFlushRange(stack_end, stack_size);
+#endif
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+	/* Determine Cache Size */
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+
+		/* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+			/*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1 Data cache line. If the byte specified by the
+* 			address (Addr) is cached by the Data cache, the cacheline
+* 			containing that byte is invalidated. If the cacheline is modified
+* 			(dirty), the modified contents are lost and are NOT written to
+*			system memory before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cachelines containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			NOT written to the system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for flushing
+*			the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way;
+	u32 WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 1 Data cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 flush to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1  Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to system memory
+* 			before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 1  Data cache line. If the byte specified by the
+* 			address (adr) is cached by the Data cache and the cacheline is
+* 			modified (dirty), the entire contents of the cacheline are written
+* 			to system memory. After the store completes, the cacheline is
+*			marked as unmodified (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 store to complete */
+	dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+		return;
+	}
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* enable the instruction cache */
+	CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable level 1 the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* disable the instruction cache */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1  instruction cache line. If the instruction
+*			specified by the address is cached by the instruction cache, the
+*			cacheline containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 instruction cache for the given address
+* 			range. If the instrucions specified by the address range are cached
+*			by the instruction cache, the cacheline containing those bytes are
+*			invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief	Enable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+	register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+	/* only enable if L2CC is currently disabled */
+	if ((L2CCReg & 0x01U) == 0U) {
+		/* set up the way size and latencies */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_AUX_CNTRL_OFFSET);
+		L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+		L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+			  L2CCReg);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+		/* Clear the pending interrupts */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_ISR_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+		Xil_L2CacheInvalidate();
+		/* Enable the L2CC */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_CNTRL_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+			  (L2CCReg | (0x01U)));
+
+        Xil_L2CacheSync();
+        /* synchronize the processor */
+	    dsb();
+
+    }
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+    register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+    if((L2CCReg & 0x1U) != 0U) {
+
+        /* Clean and Invalidate L2 Cache */
+        Xil_L2CacheFlush();
+
+	    /* Disable the L2CC */
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+	    Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+		      (L2CCReg & (~0x01U)));
+		/* Wait for the cache operations to complete */
+
+		dsb();
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+	#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/*Flush stack memory to save return address*/
+	Xil_DCacheFlushRange(stack_end, stack_size);
+	#endif
+	u32 ResultDCache;
+	/* Invalidate the caches */
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	while(ResultDCache != (u32)0U) {
+		ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	}
+
+	/* Wait for the invalidate to complete */
+	Xil_L2CacheSync();
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a level 2 cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty),
+*			the modified contents are lost and are NOT written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			are NOT written to system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+	u32 ResultL2Cache;
+
+	/* Flush the caches */
+
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+							& 0x0000FFFFU;
+
+	while(ResultL2Cache != (u32)0U) {
+		ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+									& 0x0000FFFFU;
+	}
+
+	Xil_L2CacheSync();
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to the system
+* 			memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache and the cacheline is modified
+* 			(dirty), the entire contents of the cacheline are written to
+*			system memory. After the store completes, the cacheline is marked
+*			as unmodified (not dirty).
+*
+* @param	adr: 32bit address of the data/instruction to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	/* synchronize the processor */
+	dsb();
+}
+#endif
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.h
new file mode 100644
index 0000000..b6614d5
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.o
new file mode 100644
index 0000000..d547587
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_l.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_l.h
new file mode 100644
index 0000000..fa92c6b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_vxworks.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_vxworks.h
new file mode 100644
index 0000000..6e8cfa7
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 
    
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_errata.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_errata.h
new file mode 100644
index 0000000..800fcd5
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_errata.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ *  Errata No: 	 742230
+ *  Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ *  Errata No: 	 743622
+ *  Description: Faulty hazard checking in the Store Buffer may lead
+ *	         	 to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ *  Errata No: 	 775420
+ *  Description: A data cache maintenance operation which aborts,
+ *		 		 might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ *  Errata No: 	 794073
+ *  Description: Speculative instruction fetches with MMU disabled
+ *               might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ *  Errata No: 	 588369
+ *  Description: Clean & Invalidate maintenance operations do not
+ *	   	 		 invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ *  Errata No: 	 727915
+ *  Description: Background Clean and Invalidate by Way operation
+ *		 can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/**
+ *  Errata No: 	 753970
+ *  Description: Cache sync operation may be faulty
+ */
+#define CONFIG_PL310_ERRATA_753970 1
+/*@}*/
+#endif  /* ENABLE_ARM_ERRATA */
+
+#endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.c
new file mode 100644
index 0000000..4a2f2cf
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.c
@@ -0,0 +1,334 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_UndefinedExceptionHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_PrefetchAbortHandler, NULL},
+	{Xil_DataAbortHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr;       /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr;   /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
+							     exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief	The function is a common API used to initialize exception handlers
+*			across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+*			and Cortex-A9, the exception handlers are being initialized
+*			statically and this function does not do anything.
+* 			However, it is still present to take care of backward compatibility
+*			issues (in earlier versions of BSPs, this API was being used to
+*			initialize exception handlers).
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+* @brief	Register a handler for a specific exception. This handler is being
+*			called when the processor encounters the specified exception.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*			Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief	Removes the Handler for a specific exception Id. The stub Handler
+*			is then registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+        xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+	        mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+	    #else
+	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+	        FaultStatus = Reg; }
+	    #endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+    xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+			mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+	    #else
+			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+			FaultStatus = Reg; }
+		#endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
+	while(1) {
+		;
+	}
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.h
new file mode 100644
index 0000000..ad48222
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief	Enable Exceptions.
+*
+* @param	Mask: Value for enabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief	Disable Exceptions.
+*
+* @param	Mask: Value for disabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.o
new file mode 100644
index 0000000..c57008f
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_exception.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_hal.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_hal.h
new file mode 100644
index 0000000..d4434d0
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 
    
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.c
new file mode 100644
index 0000000..90bfc81
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
    
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 16-bit endian converion.
+*
+* @param	Data: 16 bit value to be converted
+*
+* @return	16 bit Data with converted endianess
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 32-bit endian converion.
+*
+* @param	Data: 32 bit value to be converted
+*
+* @return	32 bit data with converted endianess
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.h
new file mode 100644
index 0000000..9c5aa43
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* 
    
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
+*
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
+*
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains 64 bit Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u32 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.o
new file mode 100644
index 0000000..ad0ff0f
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_io.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_macroback.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_macroback.h
new file mode 100644
index 0000000..ebafde8
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.c
new file mode 100644
index 0000000..0929a68
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief       This  function copies memory from once location to other.
+*
+* @param       dst: pointer pointing to destination memory
+*
+* @param       src: pointer pointing to source memory
+*
+* @param       cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+	char *d = (char*)(void *)dst;
+	const char *s = src;
+
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int);
+		s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+	while ((cnt) > 0U){
+		*d = *s;
+		d += 1U;
+		s += 1U;
+		cnt -= 1U;
+	}
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.h
new file mode 100644
index 0000000..a2d5e66
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 
    
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.o
new file mode 100644
index 0000000..dd854ab
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mem.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000..e114d14
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.c
@@ -0,0 +1,524 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 5.4	pkp	  09/11/15 Change the description for XOcm_Remap function
+* 
    
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert and deassert the ddr softreset bit */
+     RegVal = 	Xil_In32(XDDRC_CTRL_BASEADDR);
+	 RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+	 RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Map the ocm region to postbootrom state */
+	RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+	RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+	Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Clear the interuupts */
+	RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+	RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+	Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+	/* Clear the idle counter registers */
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+	/* Update the ecc registers with reset values */
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+							XSMC_ECC_MEMCFG1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+							XSMC_ECC_MEMCMD1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+							XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+	u32 i;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Update all the MIO registers with reset values */
+    for (i=0U; i<=1U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+	for (; i<=8U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_02_RESET_VAL);
+	}
+	for (; i<=53U ;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+	/* update the pll control registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+	/* update the pll config registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+	/* update the clock control registers with reset values */
+	Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Disable the level shifters */
+	RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+	Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000..c228c98
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
+#define XIL_MISC_RESET_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR				0xF8006000U
+#define XSLCR_BASEADDR					0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET		0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET		0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET				0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET				0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET				0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE		0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 	0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 		0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL		0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK	0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK		0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL			0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL			0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL			0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL			0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL			0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL			0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL			0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL			0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.o
new file mode 100644
index 0000000..41cf917
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_misc_psreset_api.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.c
new file mode 100644
index 0000000..1f58d90
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.c
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief	This function sets the memory attributes for a section covering 1MB
+*			of memory in the translation table.
+*
+* @param	Addr: 32-bit address for which memory attributes need to be set.
+* @param	attrib: Attribute for the given memory region. xil_mmu.h contains
+*			definitions of commonly used memory attributes which can be
+*			utilized for this function.
+*
+*
+* @return	None.
+*
+* @note		The MMU or D-cache does not need to be disabled before changing a
+*			translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+	u32 *ptr;
+	u32 section;
+
+	section = Addr / 0x100000U;
+	ptr = &MMUTable;
+	ptr += section;
+	if(ptr != NULL) {
+		*ptr = (Addr & 0xFFF00000U) | attrib;
+	}
+
+	Xil_DCacheFlush();
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	/* Invalidate all branch predictors */
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief	Enable MMU for cortex A9 processor. This function invalidates the
+*			instruction and data caches, and then enables MMU.
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+	u32 Reg;
+	Xil_DCacheInvalidate();
+	Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg |= (u32)0x05U;
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+	dsb();
+	isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Disable MMU for Cortex A9 processors. This function invalidates
+*			the TLBs, Branch Predictor Array and flushed the D Caches before
+*			disabling the MMU.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		When the MMU is disabled, all the memory accesses are treated as
+*			strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+	u32 Reg;
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+	Xil_DCacheFlush();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+	/* Disable Branch Prediction */
+	Reg &= (u32)(~0x800U);
+#endif
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.h
new file mode 100644
index 0000000..dd14b63
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 
    
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 	/* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02	/* Strongly ordered */
+#define DEVICE_MEMORY 0xC06		/* Device memory */
+#define RESERVED 0x0			/* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE	(~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.o
new file mode 100644
index 0000000..34d03c9
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_mmu.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.c
new file mode 100644
index 0000000..8ec6c9e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.c
@@ -0,0 +1,438 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include 
+#include 
+#include 
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+    s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, struct params_s *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+        outbyte(*LocalPtr);
+#endif
+		LocalPtr += 1;
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = n;
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+	outbyte( outbuf[i] );
+#endif
+		i--;
+}
+    padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a 64-bit number to the output  */
+/* buffer as directed by the padding and positioning */
+/* flags. 											 */
+/*                                                   */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[64];
+    const char8 digits[] = "0123456789ABCDEF";
+    u64 num;
+    for(i = 0; i<64; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+#if defined (__aarch64__)
+    s32 long_flag;
+#endif
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+#endif
+			ctrl += 1;
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+#if defined (__aarch64__)
+		long_flag = 0;
+#endif
+        par.unsigned_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+            #if defined (__aarch64__)
+                long_flag = 1;
+            #endif
+                Check = 0;
+                break;
+
+            case 'u':
+                par.unsigned_flag = 1;
+                /* fall through */
+            case 'i':
+            case 'd':
+                #if defined (__aarch64__)
+                if (long_flag != 0){
+			        outnum1((s64)va_arg(argp, s64), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                #else
+                    outnum( va_arg(argp, s32), 10L, &par);
+                #endif
+				Check = 1;
+                break;
+            case 'p':
+                #if defined (__aarch64__)
+                par.unsigned_flag = 1;
+			    outnum1((s64)va_arg(argp, s64), 16L, &par);
+			    Check = 1;
+                break;
+                #endif
+            case 'X':
+            case 'x':
+                par.unsigned_flag = 1;
+                #if defined (__aarch64__)
+                if (long_flag != 0) {
+				    outnum1((s64)va_arg(argp, s64), 16L, &par);
+				}
+				else {
+				    outnum((s32)va_arg(argp, s32), 16L, &par);
+                }
+                #else
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                #endif
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, s32));
+#endif
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x07));
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x08));
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.h
new file mode 100644
index 0000000..2be5c57
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.o
new file mode 100644
index 0000000..3597306
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_printf.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.c
new file mode 100644
index 0000000..157ad08
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.c
@@ -0,0 +1,371 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 
    
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
+*           and Xil_DCacheInvalidateRange. This test function writes a constant
+*           value to the Data array, flushes the range, writes a new value, then
+*           invalidates the corresponding range.
+* @param	None
+*
+* @return
+*      - -1 is returned for a failure
+*      - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief    Perform DCache all related API test such as Xil_DCacheFlush and
+*           Xil_DCacheInvalidate. This test function writes a constant value
+*           to the Data array, flushes the DCache, writes a new value,
+*           then invalidates the DCache.
+*
+* @return
+*          - 0 is returned for a pass
+*          - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*     - 0 is returned for a pass
+* @note
+*     The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+*           - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.h
new file mode 100644
index 0000000..c35e9a4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* 
    Cache test 
    
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* 
    +* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.o
new file mode 100644
index 0000000..63d5794
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testcache.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.c
new file mode 100644
index 0000000..e6a3680
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.c
@@ -0,0 +1,299 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide register IO test where the
+*           register is accessed using Xil_Out8 and Xil_In8, and comparing
+*           the written values by reading them back.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief   Perform a destructive 16-bit wide register IO test. Each location
+*          is tested by sequentially writing a 16-bit wide register, reading
+*          the register, and comparing value. This function tests three kinds
+*          of register IO functions, normal register IO, little-endian register
+*          IO, and big-endian register IO. When testing little/big-endian IO,
+*          the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+*          Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+*          Compare In-Out values. Whether to swap the read-in value before
+*          comparing is controlled by the 5th argument.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: Type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide register IO test. Each location
+*           is tested by sequentially writing a 32-bit wide regsiter, reading
+*           the register, and comparing value. This function tests three kinds
+*           of register IO functions, normal register IO, little-endian register IO,
+*           and big-endian register IO. When testing little/big-endian IO,
+*           the function perform the following sequence, Xil_Out32LE/
+*           Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+*           Whether to swap the read-in value *before comparing is controlled
+*           by the 5th argument.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.h
new file mode 100644
index 0000000..ad68ead
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* 
    I/O test 
    
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.o
new file mode 100644
index 0000000..8744693
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testio.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.c
new file mode 100644
index 0000000..87426d1
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.c
@@ -0,0 +1,868 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief   Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*           The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief    Rotates the provided value to the right one bit position
+*
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
+*
+* @return
+*           The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.h
new file mode 100644
index 0000000..c204728
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* 
    Memory test
    
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
+*
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*@endcode
+*
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.o
new file mode 100644
index 0000000..c8fe6f9
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_testmem.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_types.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_types.h
new file mode 100644
index 0000000..8143aff
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include 
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief    Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief    Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include 
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc.h
new file mode 100644
index 0000000..735e26d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET		0x0000U
+#define XPS_L2CC_TYPE_OFFSET		0x0004U
+#define XPS_L2CC_CNTRL_OFFSET		0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210U
+
+#define XPS_L2CC_IER_OFFSET		0x0214U		/* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET		0x0218U		/* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET		0x021CU		/* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET		0x0220U		/* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730U		/* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740U		/* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770U		/* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077CU		/* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0U		/* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8U		/* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BCU		/* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0U		/* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8U		/* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FCU		/* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900U		/* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904U		/* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908U		/* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090CU		/* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910U		/* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914U		/* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918U		/* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091CU		/* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920U		/* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924U		/* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928U		/* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092CU		/* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930U		/* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934U		/* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938U		/* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093CU		/* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U		/* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954U		/* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00U		/* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04U		/* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40U		/* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK		0x00000001U	/* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000U	/* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK		0x20000000U	/* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK		0x10000000U	/* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK		0x08000000U	/* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK		0x04000000U	/* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK		0x02000000U	/* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK		0x01800000U	/* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK		0x00400000U	/* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK		0x00200000U	/* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK		0x00100000U	/* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000U	/* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000U	/* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK		0x00002000U	/* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000U	/* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800U	/* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400U	/* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK		0x00000001U	/* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000U	/* Enable all prefetching, */
+                                                    /* Cache replacement policy, Parity enable, */
+                                                    /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFFU	/* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111U	/* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121U	/* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK	0x00000100U	/* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080U	/* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040U	/* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020U	/* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010U	/* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008U	/* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK		0x00000004U	/* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK		0x00000002U	/* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001U	/* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000U	/* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U	/* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004U	/* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002U	/* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002U	/* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.c
new file mode 100644
index 0000000..d6b88cb
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include 
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function initializes the event counters in L2 Cache controller
+*			with a set of event codes specified by the user.
+*
+* @param	Event0: Event code for counter 0.
+* @param	Event1: Event code for counter 1.
+*
+* @return	None.
+*
+* @note		The definitions for event codes XL2CC_* can be found in
+*			xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+	/* Write event code into cnt1 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+	/* Write event code into cnt0 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+	/* Reset counters */
+	XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief	This function starts the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+	u32 *LocalPtr;
+	LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+	XL2cc_EventCtrReset();
+
+	/* Enable counter */
+	/* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+	*LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters in L2 Cache controller,
+*			saves the counter values and resets the counters.
+*
+* @param	EveCtr0: Output parameter which is used to return the value
+*			in event counter 0.
+*			EveCtr1: Output parameter which is used to return the value
+*			in event counter 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+	/* Disable counter */
+	*((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+	/* Save counter values */
+	*EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+	*EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+	XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.h
new file mode 100644
index 0000000..8d0a61f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
    
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO		0x1
+#define XL2CC_DRHIT		0x2
+#define XL2CC_DRREQ		0x3
+#define XL2CC_DWHIT		0x4
+#define XL2CC_DWREQ		0x5
+#define XL2CC_DWTREQ		0x6
+#define XL2CC_IRHIT		0x7
+#define XL2CC_IRREQ		0x8
+#define XL2CC_WA		0x9
+#define XL2CC_IPFALLOC		0xa
+#define XL2CC_EPFHIT		0xb
+#define XL2CC_EPFALLOC		0xc
+#define XL2CC_SRRCVD		0xd
+#define XL2CC_SRCONF		0xe
+#define XL2CC_EPFRCVD		0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.o
new file mode 100644
index 0000000..16ff8dd
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xl2cc_counter.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xparameters_ps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xparameters_ps.h
new file mode 100644
index 0000000..ea0d2bc
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xparameters_ps.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.c
new file mode 100644
index 0000000..2c08e5f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+#if EL1_NONSECURE
+	XSmc_OutVar reg;
+    /*
+	 * This SMC call will return,
+     *  idcode - upper 32 bits of reg.Arg0
+     *  version - lower 32 bits of reg.Arg1
+	 */
+	reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+	return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about PS Silicon version
+*
+* @param    None.
+*
+* @return   The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info()
+{
+#if EL1_NONSECURE
+        /*
+         * This SMC call will return,
+         *  idcode - upper 32 bits of reg.Arg0
+         *  version - lower 32 bits of reg.Arg1
+         */
+        XSmc_OutVar reg;
+        reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+        return (u32)(reg.Arg1 &  XPS_VERSION_INFO_MASK);
+#else
+	u32 reg;
+	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+			& XPS_VERSION_INFO_MASK);
+	return reg;
+#endif
+}
+#endif
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.h
new file mode 100644
index 0000000..0582222
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.h
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.o
new file mode 100644
index 0000000..88fd872
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xplatform_info.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.c
new file mode 100644
index 0000000..d0765b6
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.c
@@ -0,0 +1,297 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 4.2	pkp	 07/21/14 Corrected reset value of event counter in function
+*					  Xpm_ResetEventCounters to fix CR#796275
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function enables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1U << 1U); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief	This function configures the Cortex A9 event counters controller,
+*			with the event codes, in a configuration selected by the user and
+*			enables the counters.
+*
+* @param	PmcrCfg: Configuration value based on which the event counters
+*			are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+*			be utilized for setting configuration.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+	u32 Counter;
+	static PmcrEventCfg32 PmcrEvents[] = {
+	{
+		XPM_EVENT_SOFTINCR,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	{
+		XPM_EVENT_DATA_READS,
+		XPM_EVENT_DATA_WRITE,
+		XPM_EVENT_EXCEPTION,
+		XPM_EVENT_EXCEPRETURN,
+		XPM_EVENT_CHANGECONTEXT,
+		XPM_EVENT_SW_CHANGEPC
+	},
+	{
+		XPM_EVENT_IMMEDBRANCH,
+		XPM_EVENT_UNALIGNEDACCESS,
+		XPM_EVENT_BRANCHMISS,
+		XPM_EVENT_CLOCKCYCLES,
+		XPM_EVENT_BRANCHPREDICT,
+		XPM_EVENT_JAVABYTECODE
+	},
+	{
+		XPM_EVENT_SWJAVABYTECODE,
+		XPM_EVENT_JAVABACKBRANCH,
+		XPM_EVENT_COHERLINEMISS,
+		XPM_EVENT_COHERLINEHIT,
+		XPM_EVENT_INSTRSTALL,
+		XPM_EVENT_DATASTALL
+	},
+	{
+		XPM_EVENT_MAINTLBSTALL,
+		XPM_EVENT_STREXPASS,
+		XPM_EVENT_STREXFAIL,
+		XPM_EVENT_DATAEVICT,
+		XPM_EVENT_NODISPATCH,
+		XPM_EVENT_ISSUEEMPTY
+	},
+	{
+		XPM_EVENT_INSTRRENAME,
+		XPM_EVENT_PREDICTFUNCRET,
+		XPM_EVENT_MAINEXEC,
+		XPM_EVENT_SECEXEC,
+		XPM_EVENT_LDRSTR,
+		XPM_EVENT_FLOATRENAME
+	},
+	{
+		XPM_EVENT_NEONRENAME,
+		XPM_EVENT_PLDSTALL,
+		XPM_EVENT_WRITESTALL,
+		XPM_EVENT_INSTRTLBSTALL,
+		XPM_EVENT_DATATLBSTALL,
+		XPM_EVENT_INSTR_uTLBSTALL
+	},
+	{
+		XPM_EVENT_DATA_uTLBSTALL,
+		XPM_EVENT_DMB_STALL,
+		XPM_EVENT_INT_CLKEN,
+		XPM_EVENT_DE_CLKEN,
+		XPM_EVENT_INSTRISB,
+		XPM_EVENT_INSTRDSB
+	},
+	{
+		XPM_EVENT_INSTRDMB,
+		XPM_EVENT_EXTINT,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_PLE_OVFL,
+		XPM_EVENT_PLE_PROG,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_DATASTALL,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	};
+	const u32 *ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters and returns the counter
+*			values.
+*
+* @param	PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+*			It is an output parameter which is used to return the PM
+*			counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+		mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.h
new file mode 100644
index 0000000..45f0919
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include 
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.o
new file mode 100644
index 0000000..0aab20b
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpm_counter.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm.h
new file mode 100644
index 0000000..4ad9e5d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* 
    
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm_gcc.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..1b67263
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xpseudo_asm_gcc.h
@@ -0,0 +1,249 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#endif
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval = 0U;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval = 0U; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xreg_cortexa9.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xreg_cortexa9.h
new file mode 100644
index 0000000..dc9a4eb
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* 
    
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000
+#define XREG_CPSR_Z_BIT				0x40000000
+#define XREG_CPSR_C_BIT				0x20000000
+#define XREG_CPSR_V_BIT				0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
+#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
+#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
+
+#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(1<<23)
+#define XREG_FPSID_ARCH_BIT		(16)
+#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8)
+#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4)
+#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0)
+#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(1 << 31)
+#define XREG_FPSCR_Z_BIT		(1 << 30)
+#define XREG_FPSCR_C_BIT		(1 << 29)
+#define XREG_FPSCR_V_BIT		(1 << 28)
+#define XREG_FPSCR_QC			(1 << 27)
+#define XREG_FPSCR_AHP			(1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
+#define XREG_FPSCR_RMODE_BIT		(22)
+#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20)
+#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16)
+#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(1 << 7)
+#define XREG_FPSCR_IXC			(1 << 4)
+#define XREG_FPSCR_UFC			(1 << 3)
+#define XREG_FPSCR_OFC			(1 << 2)
+#define XREG_FPSCR_DZC			(1 << 1)
+#define XREG_FPSCR_IOC			(1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28)
+#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20)
+#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16)
+#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8)
+#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4)
+#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0)
+#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(1 << 31)
+#define XREG_FPEXC_EN			(1 << 30)
+#define XREG_FPEXC_DEX			(1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xstatus.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xstatus.h
new file mode 100644
index 0000000..9937475
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.c
new file mode 100644
index 0000000..e81643f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 
    
+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief	Set the time in the Global Timer Counter Register.
+*
+* @param	Xtime_Global: 64-bit Value to be written to the Global Timer
+*			Counter Register.
+*
+* @return	None.
+*
+* @note		When this function is called by any one processor in a multi-
+*			processor environment, reference time will reset/lost for all
+*			processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+	/* Disable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+	/* Updating Global Timer Counter Register */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+		(u32)((u32)(Xtime_Global>>32U)));
+
+	/* Enable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief	Get the time from the Global Timer Counter Register.
+*
+* @param	Xtime_Global: Pointer to the 64-bit location which will be
+*			updated with the current timer value.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	u32 low;
+	u32 high;
+
+	/* Reading Global Timer Counter Register */
+	do
+	{
+		high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+		low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+	} while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+	*Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.h
new file mode 100644
index 0000000..f939d84
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.h
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 
    
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET       0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET       0x04U
+#define GTIMER_CONTROL_OFFSET             0x08U
+
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.o b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.o
new file mode 100644
index 0000000..702814a
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/standalone_v6_5/src/xtime_l.o differ
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/Makefile
new file mode 100644
index 0000000..88b1e62
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.c
new file mode 100644
index 0000000..ec2987b
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.c
@@ -0,0 +1,645 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_4
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 3.5	NK     09/26/17 Fix the RX Buffer Overflow issue.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/* Setup the driver instance using passed in parameters */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/* Initialize other instance data to default values */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/* Initialize the platform data */
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	InstancePtr->is_rxbs_error = 0U;
+
+	/* Flag that the driver instance is ready to use */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/* Mask off what's already there */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/* Set the register value to the desired data format */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/* Write the mode register out */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/* Set the RX FIFO trigger at 8 data bytes. */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/* Set the RX timeout to 1, which will be 4 character time */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/* Disable all interrupts, polled mode is the default */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* 

    
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/* Setup the buffer parameters */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup the buffer parameters */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/* Receive the data from the device */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/* Restore the interrupt state */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/* Fill the FIFO from the buffer */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/* Increment the send count. */
+		SentCount++;
+	}
+
+	/* Update the buffer to reflect the bytes that were sent from it */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		if (InstancePtr->is_rxbs_error) {
+			ByteStatusValue = XUartPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XUARTPS_RXBS_OFFSET);
+			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+				EventData = ByteStatusValue;
+				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+				/*
+				 * Call the application handler to indicate that there is a receive
+				 * error or a break interrupt, if the application cares about the
+				 * error it call a function to get the last errors.
+				 */
+				InstancePtr->Handler(InstancePtr->CallBackRef,
+							Event, EventData);
+			}
+		}
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+	InstancePtr->is_rxbs_error = 0;
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/* Check whether the input clock is divided by 8 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/* Calculate the value for BRGR register */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/* Calculate the baud rate from the BRGR value */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/* Avoid unsigned integer underflow */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/* Find the calculated baud rate closest to requested baud rate. */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/* Make sure the best error is not too large. */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/* Disable TX and RX to avoid glitches when setting the baud rate. */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/* RX and TX SW reset */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/* Enable device */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.h
new file mode 100644
index 0000000..a41404d
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps.h
@@ -0,0 +1,518 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_4
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* 
    +*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* 
    
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+* 
    
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_g.c
new file mode 100644
index 0000000..8b80e68
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_UART_1_DEVICE_ID,
+		XPAR_PS7_UART_1_BASEADDR,
+		XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PS7_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.c
new file mode 100644
index 0000000..4a4eede
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_4
+* @{
+*
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/* Wait until there is space in TX FIFO */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/* Write the byte into the TX FIFO */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/* Wait until there is data */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/* Return the byte received */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/* Disable interrupts */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/* Disable receive and transmit */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/* Clear status flags - SW reset wont clear sticky flags. */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/* Rx and TX trigger register reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/* Rx timeout disabled by default */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/* Baud rate generator and dividor reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.h
new file mode 100644
index 0000000..0eb6936
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_hw.h
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_4
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_intr.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_intr.c
new file mode 100644
index 0000000..08e2690
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_4
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/* Assert validates the input argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Read the Interrupt Mask register */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/* Write the mask to the IER Register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/* Write the inverse of the Mask to the IDR register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/* Dispatch an appropriate handler. */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/* Clear the interrupt status. */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+	u32 EventData;
+	u32 Event;
+
+	InstancePtr->is_rxbs_error = 0;
+
+	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+					| (u32)XUARTPS_IXR_FRAMING))) {
+		InstancePtr->is_rxbs_error = 1;
+	}
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+
+	(void)XUartPs_ReceiveBuffer(InstancePtr);
+
+	if (!(InstancePtr->is_rxbs_error)) {
+		Event = XUARTPS_EVENT_RECV_ERROR;
+		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+			InstancePtr->ReceiveBuffer.RemainingBytes;
+
+		/*
+		 * Call the application handler to indicate that there is a receive
+		 * error or a break interrupt, if the application cares about the
+		 * error it call a function to get the last errors.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					Event,
+					EventData);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/* If TX FIFO is empty, send more. */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_options.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_options.c
new file mode 100644
index 0000000..2c0410c
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_options.c
@@ -0,0 +1,764 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_4
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+				Register &= ~XUARTPS_CR_STOPBRK;
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/* Return the constant */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/* Assert validates the input arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Set the correct value by masking the bits, then ORing the const. */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/* Return the contents of the flow delay register */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Receive Timeout register. */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/* Return the contents of the mode register shifted appropriately */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the correct value by masking the bits */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/* Configure CR to restart the receiver timeout counter */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* 

    
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Verify the inputs specified are valid */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/* Update the mode register */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Get the length of data (8,7,6,5) */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/* Get the number of stop bits */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/* Determine what parity is */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_selftest.c
new file mode 100644
index 0000000..2f82be8
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_4
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts in the interrupt disable register */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup for local loopback */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/* Send a number of bytes and receive them, one at a time. */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/* Receive the byte */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_sinit.c
new file mode 100644
index 0000000..cac8560
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/uartps_v3_5/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_4
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
new file mode 100644
index 0000000..837ca13
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
new file mode 100644
index 0000000..92a8656
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
@@ -0,0 +1,1831 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			to fix CR #693371
+* 2.1   bss    08/05/14	Modified Assert for XAdcPs_SetSingleChParams to fix
+*			CR #807563.
+* 2.2	bss	   04/27/14 Modified to use correct Device Config base address
+*						(CR#854437).
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ConfigPtr points to the XAdcPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAdcPs_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	u32 RegValue;
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Write Unlock value to Device Config Unlock register */
+	XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+				XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+	/* Enable the PS access of xadc and set FIFO thresholds */
+
+	RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+			XADCPS_CFG_OFFSET);
+
+	RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+			XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+					XADCPS_CFG_OFFSET, RegValue);
+
+	/* Release xadc from reset */
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+						XADCPS_MCTL_OFFSET, 0x00);
+
+	/*
+	 * Indicate the instance is now ready to use and
+	 * initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Config Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Miscellaneous
+*		Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+*		in xadcps_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Status Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the Miscellaneous control register Register.
+	 */
+	 XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous control register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param	InstancePtr is a pointer to the Xxadc instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Generate the reset by Control
+	 * register and release from reset
+	 */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x10);
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number. Use the XADCPS_CH_* defined in
+*		the file xadcps.h.
+*		The valid channels are
+*		- 0 to 6
+*		- 13 to 31
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The XADC Monitor/ADC device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		The channels 7,8,9 are used for calibration of the device and
+*		hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			 ((Channel >= XADCPS_CH_VCCPINT) &&
+			 (Channel <= XADCPS_CH_AUX_MAX)));
+
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+						(XADCPS_TEMP_OFFSET +
+						Channel));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+*		specify the calibration coefficient to be read.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+	/*
+	 * Read the selected calibration coefficient.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+					CoeffType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+*		specify the data to be read.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+			((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+			(MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+	/*
+	 * Read and return the specified Minimum/Maximum measurement.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_MAX_TEMP_OFFSET +
+					MeasurementType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+*		in xadcps.h file :
+*		- XADCPS_AVG_0_SAMPLES for no averaging
+*		- XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+	/*
+	 * Write the averaging value into the Configuration Register 0.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_AVG_VALID_MASK);
+
+	RegData |=  (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XADCPS_AVG_* bit definitions defined in
+*		xadcps.h file to interpret the returned value :
+*		- XADCPS_AVG_0_SAMPLES means no averaging
+*		- XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+	u32 Average;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging value from the Configuration Register 0.
+	 */
+	Average = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+	return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number for the singel channel mode.
+*		The valid channels are 0 to 6, 8, and 13 to 31.
+*		If the external Mux is used then this specifies the channel
+*		oonnected to the external Mux. Please read the Device Spec
+*		to know which channels are valid.
+* @param 	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param 	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XAdcPs_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			(Channel == XADCPS_CH_ADC_CALIB) ||
+			((Channel >= XADCPS_CH_VCCPINT) &&
+			(Channel <= XADCPS_CH_AUX_MAX)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			(IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			(IsDifferentialMode == FALSE));
+
+	/*
+	 * Check if the device is in single channel mode else return failure
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+		XADCPS_SEQ_MODE_SINGCHAN)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					XADCPS_CFR0_AVG_VALID_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_ACQ_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_DU_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Select the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	}
+
+	/*
+	 * Write the given values into the Configuration Register 0.
+	 */
+	RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+				RegValue);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+*		XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+	RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+	RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+*		XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+*		returned value.
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+	return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+*						correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+*					offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+*						gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Calibration is the Calibration to be applied.
+*		Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+*		Multiple calibrations can be enabled at a time by oring the
+*		XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+*		Calibration can be disabled by specifying
+		XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+			(Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+			(Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+	/*
+	 * Set the specified calibration in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+
+	RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+	RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The value of the calibration enables in the Configuration
+*		Register 1 :
+*		- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+*		- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+*				gain and offset correction
+*		- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the calibration enables from the Configuration Register 1.
+	 */
+	return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XADCPS_SEQ_MODE_SAFE)
+*		- One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+*		- Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+*		- Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time. Please
+*		read the Spec of the XADC for further information about the
+*		sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+			(SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+	/*
+	 * Set the specified sequencer mode in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+	RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+	RegValue |= ((SequencerMode  << XADCPS_CFR1_SEQ_SHIFT) &
+					XADCPS_CFR1_SEQ_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The channel sequencer mode :
+*		- XADCPS_SEQ_MODE_SAFE : Default safe mode
+*		- XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+*		- XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel sequencer mode from the Configuration Register 1.
+	 */
+	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+			XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+*		Refer to the device specification for more details
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		  divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the divisor value into the Configuration Register #2.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+			  Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+	u16 Divisor;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the divisor value from the Configuration Register 2.
+	 */
+	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_CFR2_OFFSET);
+
+	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET,
+				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET,
+				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ01_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValEnable;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Read the channel enable bits for all the channels from the ADC
+	 *  Channel Selection Register.
+	 */
+	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET) &
+				XADCPS_SEQ00_CH_VALID_MASK;
+	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET) &
+				XADCPS_SEQ01_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+	return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET,
+				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ03_OFFSET,
+				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ03_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValAvg;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+			XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+*		in xadcps_hw.h to specify the channel numbers. Differential
+*		input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET,
+				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET,
+				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ05_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The input mode for all the channels.
+*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+	u32 InputMode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET) &
+				XADCPS_SEQ04_CH_VALID_MASK;
+	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET) &
+				XADCPS_SEQ05_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+			XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET,
+				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET,
+				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ07_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+	u32 RegValAcq;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET) &
+				XADCPS_SEQ06_CH_VALID_MASK;
+	RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET) &
+				XADCPS_SEQ07_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+*
+* @return	None.
+*
+* @note		Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+*		threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Write the value into the specified Alarm Threshold Register.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+					AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XADCPS_ATR_* constants defined in 	xadcps_hw.h
+*		to specify the index.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+				(XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+	return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	/*
+	 * Preserve the powerdown value and write OT enable value the into the
+	 * OT Upper Alarm Threshold Register.
+	 */
+	OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT Upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_EC_MASK);
+
+	/*
+	 * Set the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	} else {
+		RegValue &= ~XADCPS_CFR0_EC_MASK;
+	}
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The sampling mode
+*		- 0 specifies continuous sampling
+*		- 1 specifies event driven sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+	u32 Mode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the sampling mode from the Configuration Register 0.
+	 */
+	Mode = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_CFR0_OFFSET) &
+				   XADCPS_CFR0_EC_MASK;
+	if (Mode) {
+
+		return 1;
+	}
+
+	return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	MuxMode specifies whether External Mux is used
+*		- FALSE specifies NO external MUX
+*		- TRUE specifies External Mux is used
+* @param	Channel specifies the channel to be used for the
+*		external Mux. Please read the Device Spec for which
+*		channels are valid for which mode.
+*
+* @return	None.
+*
+* @note		There is no Assert in this function for checking the channel
+*		number if the external Mux is used. The user should provide a
+*		valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_MUX_MASK);
+	/*
+	 * Select the Mux mode and the channel to be used.
+	 */
+	if (MuxMode == TRUE) {
+		RegValue |= XADCPS_CFR0_MUX_MASK;
+		RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+	}
+
+	/*
+	 * Write the mux mode into the Configuration Register 0.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+	/*
+	 * Read the Configuration Register 2.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Select the Power Down mode.
+	 */
+	RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+					RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Power Down Mode.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Return the Power Down mode.
+	 */
+	return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be written.
+* @param	Data is the data to be written.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+	u32 RegData;
+
+	/*
+	 * Write the Data into the FIFO Register.
+	 */
+	RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Read the Read FIFO after any write since for each write
+	 * one location of Read FIFO gets updated
+	 */
+	XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be read.
+*
+* @return	Data read from the FIFO
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+	u32 RegData;
+
+	RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+	/* Read cmd to FIFO*/
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do a Dummy read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	/* Do a Dummy write to get the actual read */
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do the Actual read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	return RegData;
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
new file mode 100644
index 0000000..549bfff
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+*  XADC Channel Sequencer Modes 
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   -  Default : This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   -  One pass through sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   -  Continuous cycling of sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   -  Single channel mode: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   -  Simultaneous Sampling Mode: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   -  Independent ADC mode: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+*  Building the driver 
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*  Limitations of the driver 
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* 

    
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of xadcps
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+*
+* 
    
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
new file mode 100644
index 0000000..ab17ec3
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_XADC_0_DEVICE_ID,
+		XPAR_PS7_XADC_0_BASEADDR
+	}
+};
+
+
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
new file mode 100644
index 0000000..55a47a4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* 
    
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the I.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Enable Register.
+	 */
+	return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the IPISR.
+*
+* @note		The device must be configured at hardware build time to include
+*		interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Status register.
+	 */
+	return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear the specified interrupts in the Interrupt Status register.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_STS_OFFSET);
+	RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+			  RegValue);
+
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
new file mode 100644
index 0000000..7f171b4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
@@ -0,0 +1,141 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note	None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 		0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+	int Status;
+	u32 RegValue;
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Reset the device to get it back to its default state
+	 */
+	XAdcPs_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+				  XADCPS_ATR_TEST_VALUE);
+	RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+	if (RegValue == XADCPS_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Reset the device again to its default state.
+	 */
+	XAdcPs_Reset(InstancePtr);
+	/*
+	 * Return the test result.
+	 */
+	return Status;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
new file mode 100644
index 0000000..5fb7cde
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note	None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI XADC driver
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+	XAdcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0; Index < 1; Index++) {
+		if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAdcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/system.mss b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/system.mss
new file mode 100644
index 0000000..f05bac4
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/Intr_Timer_bsp/system.mss
@@ -0,0 +1,213 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 6.5
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+ PARAMETER stdin = ps7_uart_1
+ PARAMETER stdout = ps7_uart_1
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa9
+ PARAMETER DRIVER_VER = 2.5
+ PARAMETER HW_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.4
+ PARAMETER HW_INSTANCE = ps7_coresight_comp_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrps
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = ps7_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = devcfg
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_dev_cfg_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_ns
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.6
+ PARAMETER HW_INSTANCE = ps7_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_globaltimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_gpv_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_intc_dist_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_l2cachec_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ocmc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspips
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.8
+ PARAMETER HW_INSTANCE = ps7_scugic_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scutimer
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scutimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scuwdt
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scuwdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_slcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = xadcps
+ PARAMETER DRIVER_VER = 2.2
+ PARAMETER HW_INSTANCE = ps7_xadc_0
+END
+
+
diff --git a/Miz_sys/Miz_sys.sdk/RemoteSystemsTempFiles/.project b/Miz_sys/Miz_sys.sdk/RemoteSystemsTempFiles/.project
new file mode 100644
index 0000000..5447a64
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/RemoteSystemsTempFiles/.project
@@ -0,0 +1,12 @@
+
+
+	RemoteSystemsTempFiles
+	
+	
+	
+	
+	
+	
+		org.eclipse.rse.ui.remoteSystemsTempNature
+	
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper.hdf b/Miz_sys/Miz_sys.sdk/system_wrapper.hdf
new file mode 100644
index 0000000..d0aa0ab
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/system_wrapper.hdf differ
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/.project b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/.project
new file mode 100644
index 0000000..3c2965e
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/.project
@@ -0,0 +1,41 @@
+
+
+	system_wrapper_hw_platform_0
+	Created by SDK v2018.2
+	
+	
+	
+	
+	
+		com.xilinx.sdk.hw.HwProject
+	
+	
+		
+			1559740658713
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.xml
+			
+		
+		
+			1559740658721
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.svd
+			
+		
+		
+			1559740658726
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.hwh
+			
+		
+	
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.c b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.c
new file mode 100644
index 0000000..3df7714
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.c
@@ -0,0 +1,12807 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
+* otherwise to promote the sale, use or other dealings in this Software without prior written
+* authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.h b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.h
new file mode 100644
index 0000000..1e0ef54
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.h
@@ -0,0 +1,137 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+* 
+* The above copyright notice and this permission notice shall be included in all copies or 
+* substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 
+* (b) that interact with a Xilinx device through a bus or interconnect.  
+* 
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+* 
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 
+* otherwise to promote the sale, use or other dealings in this Software without prior written 
+* authorization from Xilinx.
+* 
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.html b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.html
new file mode 100644
index 0000000..a0eee88
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.html
@@ -0,0 +1,137694 @@
+
+
+
+
+Zynq PS configuration detail
+
+
+
+
    
+
    
+
+
  • 
+
    Zynq PS Register Summary Viewer
+
    
+
    • 
+    
+
    
+
    
+
    
+
+
    Zynq PS7 Summary Report
+
    
+    
+
    User Configurations
+
    
+
    
+
+
    MIO Configurations
+
    
+    
+
    
+
+
    CLK Configurations
+
    
+    
+
    
+
+
    DDR Configurations
+
    
+    
+
    
+
+
    SMC Configurations
+
    
+    
+
    
+
    
+
    Select Version:
+
+
    
+
    
+
    Zynq Register View
+
    
+
    
+
+
    MIO Registers
+
    
+    
+
+
    PLL Registers
+
    
+    
+
+
    Clock Registers
+
    
+    
+
+
    DDR Registers
+
    
+    
+
+
    Peripherals Registers
+
    
+    
+
    
+
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1)
+
+
    
+
    Zynq Design Summary
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Device
+
+xc7z010
+
    
+SpeedGrade
+
+-1
+
    
+Part
+
+xc7z010clg400-1
+
    
+Description
+
+Zynq PS Configuration Report with register details
+
    
+Vendor
+
+Xilinx
+
    
+
    MIO Table View
    
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+MIO Pin
+
+Peripheral
+
+Signal
+
+IO Type
+
+Speed
+
+Pullup
+
+Direction
+
    
+MIO 0
+
+GPIO
+
+gpio[0]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 1
+
+Quad SPI Flash
+
+qspi0_ss_b
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+out
+
    
+MIO 2
+
+Quad SPI Flash
+
+qspi0_io[0]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 3
+
+Quad SPI Flash
+
+qspi0_io[1]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 4
+
+Quad SPI Flash
+
+qspi0_io[2]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 5
+
+Quad SPI Flash
+
+qspi0_io[3]/HOLD_B
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 6
+
+Quad SPI Flash
+
+qspi0_sclk
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 7
+
+GPIO
+
+gpio[7]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 8
+
+Quad SPI Flash
+
+qspi_fbclk
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 9
+
+GPIO
+
+gpio[9]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 10
+
+GPIO
+
+gpio[10]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 11
+
+GPIO
+
+gpio[11]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 12
+
+GPIO
+
+gpio[12]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 13
+
+GPIO
+
+gpio[13]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 14
+
+GPIO
+
+gpio[14]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 15
+
+GPIO
+
+gpio[15]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 16
+
+Enet 0
+
+tx_clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 17
+
+Enet 0
+
+txd[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 18
+
+Enet 0
+
+txd[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 19
+
+Enet 0
+
+txd[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 20
+
+Enet 0
+
+txd[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 21
+
+Enet 0
+
+tx_ctl
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 22
+
+Enet 0
+
+rx_clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 23
+
+Enet 0
+
+rxd[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 24
+
+Enet 0
+
+rxd[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 25
+
+Enet 0
+
+rxd[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 26
+
+Enet 0
+
+rxd[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 27
+
+Enet 0
+
+rx_ctl
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 28
+
+GPIO
+
+gpio[28]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 29
+
+GPIO
+
+gpio[29]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 30
+
+GPIO
+
+gpio[30]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 31
+
+GPIO
+
+gpio[31]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 32
+
+GPIO
+
+gpio[32]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 33
+
+GPIO
+
+gpio[33]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 34
+
+GPIO
+
+gpio[34]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 35
+
+GPIO
+
+gpio[35]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 36
+
+GPIO
+
+gpio[36]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 37
+
+GPIO
+
+gpio[37]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 38
+
+GPIO
+
+gpio[38]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 39
+
+GPIO
+
+gpio[39]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 40
+
+SD 0
+
+clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 41
+
+SD 0
+
+cmd
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 42
+
+SD 0
+
+data[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 43
+
+SD 0
+
+data[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 44
+
+SD 0
+
+data[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 45
+
+SD 0
+
+data[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 46
+
+GPIO
+
+gpio[46]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 47
+
+SD 0
+
+cd
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 48
+
+UART 1
+
+tx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 49
+
+UART 1
+
+rx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 50
+
+GPIO
+
+gpio[50]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 51
+
+GPIO
+
+gpio[51]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 52
+
+Enet 0
+
+mdc
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 53
+
+Enet 0
+
+mdio
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+
    DDR Memory information
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Parameter name
+
+Value
+
+Description
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Memory Part
+
+MT41K256M16 RE-125
+
+
+
    
+DRAM bus width
+
+32 Bit
+
+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
+
    
+ECC
+
+Disabled
+
+ECC is supported only for data width of 16-bit
+
    
+BURST Length (lppdr only)
+
+8
+
+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
+
    
+Internal Vref
+
+0
+
+
+
    
+Operating Frequency (MHz)
+
+533.333333
+
+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
+
    
+HIGH temperature
+
+Normal (0-85)
+
+Select the operating temparature
+
    
+DRAM IC bus width
+
+16 Bits
+
+Provide the width of the DRAM chip
+
    
+DRAM Device Capacity
+
+4096 MBits
+
+
+
    
+Speed Bin
+
+DDR3_1066F
+
+Provide the Speed Bin
+
    
+BANK Address Count
+
+3
+
+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
+
    
+ROW Address Count
+
+15
+
+Provide the Row address for ACTIVE commands
+
    
+COLUMN Address Count
+
+10
+
+Provide the Row address for READ/WRITE commands
+
    
+CAS Latency
+
+7
+
+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
+
    
+CAS Write Latency
+
+6
+
+Select the CAS Write Latency
+
    
+RAS to CAS Delay
+
+7
+
+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
+
    
+RECHARGE Time
+
+7
+
+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
+
    
+tRC (ns )
+
+48.75
+
+Provide the Row cycle time tRC (ns)
+
    
+tRASmin ( ns )
+
+35.0
+
+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
+
    
+tFAW
+
+40.0
+
+It restricts the number of activates that can be done within a certain window of time
+
    
+ADDITIVE Latency
+
+0
+
+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
+
    
+Write levelling
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+DQS to Clock delay [0] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [1] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [2] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [3] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+Board delay [0] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [1] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [2] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [3] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+
    PS Clocks information
    
+
    PS Reference Clock : 33.333333
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Peripheral
+
+PLL source
+
+Frequency (MHz)
+
    
+CPU 6x Freq (MHz)
+
+ARM PLL
+
+666.666687
+
    
+QSPI Flash Freq (MHz)
+
+IO PLL
+
+200.000000
+
    
+ENET0 Freq (MHz)
+
+IO PLL
+
+125.000000
+
    
+SDIO Freq (MHz)
+
+IO PLL
+
+100.000000
+
    
+UART Freq (MHz)
+
+IO PLL
+
+100.000000
+
    
+FPGA0 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+FPGA1 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+FPGA2 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+FPGA3 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Ref Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reserved_reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Reserved. Do not modify.
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+7ffff
+
+
+
+1081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_en_dfi_dram_clk_disable
+
+23:23
+
+800000
+
+0
+
+0
+
+Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+7fdffffc
+
+
+
+270872d0
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffc3
+
+
+
+0
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reserved_reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+Reserved. Do not modify.
+
    
+reserved_reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3f03f
+
+
+
+3c008
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+10000
+
+
+
+0
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum d'128)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+200
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_64@0XF8006190
+
+31:0
+
+6ffffefe
+
+
+
+40080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff5
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits
+
    
+reserved_VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+reserved_REFIO_TEST
+
+11:10
+
+c00
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+260
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+1
+
+
+
+1
+
+DDR IOB DCI Config
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialize flops in DCI system
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDR IOB DCI Config
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1
+
    
+reserved_VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT1
+
+15:14
+
+c000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update Mode. Use the values in the Calibration Table.
+
    
+reserved_INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7feffff
+
+
+
+823
+
+DDR IOB DCI Config
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables Pullup on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Divider Register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Generator Register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control Register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode Register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+Baud Rate Divider Register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud Rate Generator Register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter 1: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control Register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+3ff
+
+
+
+20
+
+UART Mode Register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_LVL_INP_EN_0
+
+3:3
+
+8
+
+1
+
+8
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_0
+
+2:2
+
+4
+
+1
+
+4
+
+Level shifter enable to drive signals from PS to PL
+
    
+USER_LVL_INP_EN_1
+
+1:1
+
+2
+
+1
+
+2
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_1
+
+0:0
+
+1
+
+1
+
+1
+
+Level shifter enable to drive signals from PS to PL
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    AFI2 SECURE REGISTER
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Ref Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ration: 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
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+
+
+
+
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+
+
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+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config0
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config1
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 1.
+
    
+
+PHY_Config2
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 2.
+
    
+
+PHY_Config3
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 3.
+
    
+
+phy_init_ratio0
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio1
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 1.
+
    
+
+phy_init_ratio2
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 2.
+
    
+
+phy_init_ratio3
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 3.
+
    
+
+phy_rd_dqs_cfg0
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg1
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 1.
+
    
+
+phy_rd_dqs_cfg2
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 2.
+
    
+
+phy_rd_dqs_cfg3
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 3.
+
    
+
+phy_wr_dqs_cfg0
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg1
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 1.
+
    
+
+phy_wr_dqs_cfg2
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 2.
+
    
+
+phy_wr_dqs_cfg3
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 3.
+
    
+
+phy_we_cfg0
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg1
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
+phy_we_cfg2
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
+phy_we_cfg3
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
+wr_data_slv0
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv1
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 1.
+
    
+
+wr_data_slv2
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 2.
+
    
+
+wr_data_slv3
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 3.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port0
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port1
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 1.
+
    
+
+axi_priority_wr_port2
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 2.
+
    
+
+axi_priority_wr_port3
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 3.
+
    
+
+axi_priority_rd_port0
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port1
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 1.
+
    
+
+axi_priority_rd_port2
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 2.
+
    
+
+axi_priority_rd_port3
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 3.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1: sdram device 0: non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+272872d0
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config0
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config0@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config1
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config1@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )PHY_Config2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config2
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config2@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )PHY_Config3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config3
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config3@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_init_ratio0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio0
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio0@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio1
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio1@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_init_ratio2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio2
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio2@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_init_ratio3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio3
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio3@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg0
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg0@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg1
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg1@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg2
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg2@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg3
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg3@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg0
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg0@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg1
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg1@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg2
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg2@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg3
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg3@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_we_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg0
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg0@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg1
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg1@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_we_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg2
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg2@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_we_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg3
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg3@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
    
+
    Register ( slcr )wr_data_slv0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv0
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv0@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv1
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv1@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 1.
+
    
+
    
+
    Register ( slcr )wr_data_slv2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv2
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv2@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 2.
+
    
+
    
+
    Register ( slcr )wr_data_slv3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv3
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv3@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 3.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port0
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port0@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port1
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port1@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port2
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port2@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port3
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port3@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 3.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port0
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port0@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port1
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port1@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port2
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port2@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port3
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port3@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 3.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 0
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 1
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Address
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Data
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Diff
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Clock
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 0
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 1
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDR IOB Slew for Address
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Data
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Diff
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Clock
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+REFIO_TEST
+
+11:10
+
+c00
+
+0
+
+0
+
+Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+260
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables pull-up on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud rate divider register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: start break transmission, 1: stop break transmission.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter, 0: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: disable, 1: enable
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CORTEX A9 Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CORTEX A9 Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Divisor value for the ddr_3xclk
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Linear Quad-SPI Reference Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Reference Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Reference Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP 2X Clock Contol
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+FPGA 0 Output Clock Control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+6:2:1 ratio clock, if set
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Linear Quad-SPI Reference Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Reference Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Reference Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active 0 - Clock is disabled 1 - Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP 2X Clock Contol
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+FPGA 0 Output Clock Control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+6:2:1 ratio clock, if set
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two rank configuration register
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control register
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control register
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control register
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM initialization parameters register
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access register
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access register
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM burst 8 read/write register
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ register
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM bank address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT register
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO register
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration register
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold register
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller register 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller register 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller register 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller register 4
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters register
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters register
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown register
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control register
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug register
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing register
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear register
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction register
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status register
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count register
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub register
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control register (2)
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control register (3)
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask register
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0 Register
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1 Register
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2 Register
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3 Register
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control Register
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two rank configuration register
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control register
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control register
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control register
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters register 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters register 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM RELATED.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters register 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1 = sdram device 0 = non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1 = disable the pad power down feature 0 = Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+272872d0
+
+DRAM Parameters register 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1 = DDRC will use 2T timing 0 = DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1 = Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 1 = read 0 = write
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters register 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM initialization parameters register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access register
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM burst 8 read/write register
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ register
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Selects the address bits used as DRAM bank address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Selects the address bits used as DRAM column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Selects the address bits used as DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT register
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1 = stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO register
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration register
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold register
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+When 1, disable Write Combine
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller register 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller register 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller register 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller register 4
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters register
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters register
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown register
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control register
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug register
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing register
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear register
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction register
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status register
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count register
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub register
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control register (2)
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control register (3)
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask register
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3 Register
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control Register
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 0 Configuartion Register
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 1 Configuration Register
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential Clock Configuration Register
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Address Register
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Data Register
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Clcok Register
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DDR Control Register
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 0
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 1
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 2
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 3
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 4
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 5
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 6
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 7
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 8
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 9
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 10
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 11
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 12
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 13
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 14
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 15
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 16
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 17
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 18
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 19
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 20
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 21
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 22
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 23
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 24
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 25
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 26
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 27
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 28
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 29
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 30
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 31
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 32
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 33
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 34
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 35
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 36
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 37
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 38
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 39
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 40
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 41
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 42
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 43
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 44
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 45
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 46
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 47
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 48
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 49
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 50
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 51
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 52
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 53
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 0 Configuartion Register
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Differential Clock Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDRIOB Drive Slew Address Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Data Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Clcok Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+73ff
+
+
+
+260
+
+DDRIOB DDR Control Register
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 0
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Control for Pin 1
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 2
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 3
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 4
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 5
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 6
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Control for Pin 7
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 8
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 9
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 10
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 11
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 12
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 13
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 14
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 15
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 16
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 17
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 18
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 19
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 20
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 21
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 22
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 23
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 24
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 25
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 26
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 27
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 28
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 29
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 30
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 31
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 32
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 33
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 34
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 35
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 36
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 37
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 38
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 39
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 40
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 41
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 42
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 43
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 44
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 45
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 46
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Control for Pin 47
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Control for Pin 48
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Control for Pin 49
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 50
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 51
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 52
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 53
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud rate divider register
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break. 1 = stop transmission of the break.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter 1 = receiver timeout counter is restarted
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable. 1, the transmitter is disabled
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable. 1= receiver is enabled
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.tcl b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.tcl
new file mode 100644
index 0000000..e735d59
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init.tcl
@@ -0,0 +1,832 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  666666666
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.c b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.c
new file mode 100644
index 0000000..0e45185
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.c
@@ -0,0 +1,12798 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see 
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.h b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.h
new file mode 100644
index 0000000..1e0ef54
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/ps7_init_gpl.h
@@ -0,0 +1,137 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+* 
+* The above copyright notice and this permission notice shall be included in all copies or 
+* substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 
+* (b) that interact with a Xilinx device through a bus or interconnect.  
+* 
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+* 
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 
+* otherwise to promote the sale, use or other dealings in this Software without prior written 
+* authorization from Xilinx.
+* 
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system.hdf b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system.hdf
new file mode 100644
index 0000000..d0aa0ab
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system.hdf differ
diff --git a/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system_wrapper.bit b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system_wrapper.bit
new file mode 100644
index 0000000..ca34eda
Binary files /dev/null and b/Miz_sys/Miz_sys.sdk/system_wrapper_hw_platform_0/system_wrapper.bit differ
diff --git a/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.tcl b/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.tcl
new file mode 100644
index 0000000..53ef103
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.tcl
@@ -0,0 +1,45 @@
+webtalk_init -webtalk_dir F:\\Code\\CH08_Intr_timer\\Miz_sys\\Miz_sys.sdk\\webtalk
+webtalk_register_client -client project
+webtalk_add_data -client project -key date_generated -value "2019-06-09 09:33:43" -context "software_version_and_target_device"
+webtalk_add_data -client project -key product_version -value "SDK v2018.2" -context "software_version_and_target_device"
+webtalk_add_data -client project -key build_version -value "2018.2" -context "software_version_and_target_device"
+webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device"
+webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
+webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device"
+webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device"
+webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device"
+webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device"
+webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device"
+webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device"
+webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device"
+webtalk_add_data -client project -key random_id -value "8f6jrb44fracouk0jh0uj181cg" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_id -value "2018.2_43" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_iteration -value "43" -context "software_version_and_target_device"
+webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
+webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
+webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz" -context "user_environment"
+webtalk_add_data -client project -key cpu_speed -value "2592 MHz" -context "user_environment"
+webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
+webtalk_add_data -client project -key system_ram -value "16.965 GB" -context "user_environment"
+webtalk_register_client -client sdk
+webtalk_add_data -client sdk -key uid -value "1559740662415" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key VivadoVersion -value "2017.4" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key Device -value "7z010" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1559740662415"
+webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key DebugCount -value "42" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1560044023795"
+webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1560044023795"
+webtalk_transmit -clientid 1870334959 -regid "" -xml F:\\Code\\CH08_Intr_timer\\Miz_sys\\Miz_sys.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html F:\\Code\\CH08_Intr_timer\\Miz_sys\\Miz_sys.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm F:\\Code\\CH08_Intr_timer\\Miz_sys\\Miz_sys.sdk\\webtalk\\sdk_webtalk.wdm -intro "
    SDK Usage Report

    "
+webtalk_terminate
diff --git a/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.wdm b/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.wdm
new file mode 100644
index 0000000..45bb613
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/webtalk/sdk_webtalk.wdm
@@ -0,0 +1,36 @@
+version = "1.0";
+clients =
+(
+	{ client_name = "project"; 
+		rules = (
+			{
+				context="software_version_and_target_device";
+				xml_map="software_version_and_target_device";
+				html_map="software_version_and_target_device";
+				html_format="UserEnvStyle";
+			},
+			{
+				context="user_environment";
+				xml_map="user_environment";
+				html_map="user_environment";
+				html_format="UserEnvStyle";
+			}
+		);
+     },
+	{ client_name = "sdk"; 
+		rules = (
+			{
+				context="sdk\\\\hardware/1559740662415";
+				xml_map="sdk\\\\hardware/1559740662415";
+				html_map="sdk\\\\hardware/1559740662415";
+				html_format="UnisimStatsStyle";
+			},
+			{
+				context="sdk\\\\bsp/1560044023795";
+				xml_map="sdk\\\\bsp/1560044023795";
+				html_map="sdk\\\\bsp/1560044023795";
+				html_format="UnisimStatsStyle";
+			}
+		);
+     }
+);
diff --git a/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.html b/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.html
new file mode 100644
index 0000000..ef36814
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.html
@@ -0,0 +1,66 @@
+Device Usage Statistics Report
+
    SDK Usage Report

    
+ 
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+  
+
+
    software_version_and_target_device
      betafalsebuild_version2018.2
      date_generated2019-06-05 21:17:09os_platformamd64
      product_versionSDK v2018.2project_id2018.2_42
      project_iteration42random_id4eae9eaofib00gfnguekj3pfpm
      registration_id4eae9eaofib00gfnguekj3pfpmroute_designNA
      target_deviceNAtarget_familyNA
      target_packageNAtarget_speedNA
      tool_flowSDK
     

    
+ 
+  
+
+  
+
+  
+
+  
+
    user_environment
      cpu_nameIntel(R) Core(TM) i7-6700HQ CPU @ 2.60GHzcpu_speed2592 MHz
      os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release  (build 9200)
      system_ram16.965 GBtotal_processors1
     

    
+ 
+  
+ 
    vivado_usage

    
+ 
+  
+   
+   
+  
    sdk
    
+   
+    
+
+    
+    
+    
+
+    
+    
+    
+
    bsp/1559740629035
        bootgencount=0crosstriggcount=0debugcount=0flashcount=0
        perfcount=0qemudebugcount=0recordtype=ToolUsageuid=NA
       
    
+   
    
+   
+    
+
+    
+    
+    
+
+    
+    
+    
+
+    
+    
+
    hardware/1559740599642
        apptemplate=NAarch=zynqdevice=7z010ishandoff=true
        iszynq=trueiszynqmp=falseos=NAprocessors=2
        recordtype=HWCreationuid=1559740599642vivadoversion=2017.4
       
    
+   

    
+
+
diff --git a/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.xml b/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.xml
new file mode 100644
index 0000000..50b2c5f
--- /dev/null
+++ b/Miz_sys/Miz_sys.sdk/webtalk/usage_statistics_ext_sdk.xml
@@ -0,0 +1,57 @@
+
+
+
    
+ 
    
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+ 
    
+ 
    
+  
+  
+  
+  
+  
+  
+ 
    
+ 
    
+  
    
+   
+   
+   
+   
+   
+   
+   
+   
+  
    
+  
    
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+  
    
+ 
    
+ 
    
+ 
    
+
    
+    
diff --git a/Miz_sys/Miz_sys.srcs/constrs_1/new/Miz_sys_pin.xdc b/Miz_sys/Miz_sys.srcs/constrs_1/new/Miz_sys_pin.xdc
new file mode 100644
index 0000000..d1fd9b4
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/constrs_1/new/Miz_sys_pin.xdc
@@ -0,0 +1,6 @@
+set_property PACKAGE_PIN T19 [get_ports {SW1[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW1[0]}]
+
+set_property PACKAGE_PIN R19 [get_ports {SW2[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW2[0]}]
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v
new file mode 100644
index 0000000..a888877
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hdl/system_wrapper.v
@@ -0,0 +1,100 @@
+//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
+//Date        : Sat May 25 13:08:00 2019
+//Host        : LB-201810041430 running 64-bit major release  (build 9200)
+//Command     : generate_target system_wrapper.bd
+//Design      : system_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module system_wrapper
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb);
+  inout [14:0]DDR_addr;
+  inout [2:0]DDR_ba;
+  inout DDR_cas_n;
+  inout DDR_ck_n;
+  inout DDR_ck_p;
+  inout DDR_cke;
+  inout DDR_cs_n;
+  inout [3:0]DDR_dm;
+  inout [31:0]DDR_dq;
+  inout [3:0]DDR_dqs_n;
+  inout [3:0]DDR_dqs_p;
+  inout DDR_odt;
+  inout DDR_ras_n;
+  inout DDR_reset_n;
+  inout DDR_we_n;
+  inout FIXED_IO_ddr_vrn;
+  inout FIXED_IO_ddr_vrp;
+  inout [53:0]FIXED_IO_mio;
+  inout FIXED_IO_ps_clk;
+  inout FIXED_IO_ps_porb;
+  inout FIXED_IO_ps_srstb;
+
+  wire [14:0]DDR_addr;
+  wire [2:0]DDR_ba;
+  wire DDR_cas_n;
+  wire DDR_ck_n;
+  wire DDR_ck_p;
+  wire DDR_cke;
+  wire DDR_cs_n;
+  wire [3:0]DDR_dm;
+  wire [31:0]DDR_dq;
+  wire [3:0]DDR_dqs_n;
+  wire [3:0]DDR_dqs_p;
+  wire DDR_odt;
+  wire DDR_ras_n;
+  wire DDR_reset_n;
+  wire DDR_we_n;
+  wire FIXED_IO_ddr_vrn;
+  wire FIXED_IO_ddr_vrp;
+  wire [53:0]FIXED_IO_mio;
+  wire FIXED_IO_ps_clk;
+  wire FIXED_IO_ps_porb;
+  wire FIXED_IO_ps_srstb;
+
+  system system_i
+       (.DDR_addr(DDR_addr),
+        .DDR_ba(DDR_ba),
+        .DDR_cas_n(DDR_cas_n),
+        .DDR_ck_n(DDR_ck_n),
+        .DDR_ck_p(DDR_ck_p),
+        .DDR_cke(DDR_cke),
+        .DDR_cs_n(DDR_cs_n),
+        .DDR_dm(DDR_dm),
+        .DDR_dq(DDR_dq),
+        .DDR_dqs_n(DDR_dqs_n),
+        .DDR_dqs_p(DDR_dqs_p),
+        .DDR_odt(DDR_odt),
+        .DDR_ras_n(DDR_ras_n),
+        .DDR_reset_n(DDR_reset_n),
+        .DDR_we_n(DDR_we_n),
+        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
+        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
+        .FIXED_IO_mio(FIXED_IO_mio),
+        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
+        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
+        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system.hwh b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system.hwh
new file mode 100644
index 0000000..61d71aa
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system.hwh
@@ -0,0 +1,1214 @@
+
+
+
+  
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+      
+        
+        
+        
+        
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+        
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+        
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+        
+        
+        
+        
+        
+      
+    
+    
+      
+      
+        
+        
+        
+        
+        
+        
+      
+    
+  
+
+  
+    
+      
+        
+      
+      
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+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
new file mode 100644
index 0000000..030dd0a
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
@@ -0,0 +1,989 @@
+
+################################################################
+# This is a generated script based on design: system
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2017.4
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source system_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z010clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name system
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable  to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of  from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable  to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable  to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable  is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+  # Create ports
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+   CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+   CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
+   CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
+   CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+   CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+   CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_CLK0_FREQ {50000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CORE0_FIQ_INTR {0} \
+   CONFIG.PCW_CORE0_IRQ_INTR {0} \
+   CONFIG.PCW_CORE1_FIQ_INTR {0} \
+   CONFIG.PCW_CORE1_IRQ_INTR {0} \
+   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
+   CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+   CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+   CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+   CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+   CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
+   CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DM_WIDTH {4} \
+   CONFIG.PCW_DQS_WIDTH {4} \
+   CONFIG.PCW_DQ_WIDTH {32} \
+   CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
+   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
+   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_EN_4K_TIMER {0} \
+   CONFIG.PCW_EN_CAN0 {0} \
+   CONFIG.PCW_EN_CAN1 {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_CLK1_PORT {0} \
+   CONFIG.PCW_EN_CLK2_PORT {0} \
+   CONFIG.PCW_EN_CLK3_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+   CONFIG.PCW_EN_DDR {1} \
+   CONFIG.PCW_EN_EMIO_CAN0 {0} \
+   CONFIG.PCW_EN_EMIO_CAN1 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_ENET1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {0} \
+   CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {0} \
+   CONFIG.PCW_EN_EMIO_SPI1 {0} \
+   CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+   CONFIG.PCW_EN_EMIO_TRACE {0} \
+   CONFIG.PCW_EN_EMIO_TTC0 {0} \
+   CONFIG.PCW_EN_EMIO_TTC1 {0} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_WDT {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_ENET1 {0} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {0} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_PTP_ENET0 {0} \
+   CONFIG.PCW_EN_PTP_ENET1 {0} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SDIO1 {0} \
+   CONFIG.PCW_EN_SMC {0} \
+   CONFIG.PCW_EN_SPI0 {0} \
+   CONFIG.PCW_EN_SPI1 {0} \
+   CONFIG.PCW_EN_TRACE {0} \
+   CONFIG.PCW_EN_TTC0 {0} \
+   CONFIG.PCW_EN_TTC1 {0} \
+   CONFIG.PCW_EN_UART0 {0} \
+   CONFIG.PCW_EN_UART1 {1} \
+   CONFIG.PCW_EN_USB0 {0} \
+   CONFIG.PCW_EN_USB1 {0} \
+   CONFIG.PCW_EN_WDT {0} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_FTM_CTI_IN0 {} \
+   CONFIG.PCW_FTM_CTI_IN2 {} \
+   CONFIG.PCW_FTM_CTI_OUT0 {} \
+   CONFIG.PCW_FTM_CTI_OUT2 {} \
+   CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0} \
+   CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
+   CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
+   CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {0} \
+   CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
+   CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
+   CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_I2C_RESET_ENABLE {1} \
+   CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+   CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+   CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {1} \
+   CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {inout} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {inout} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {inout} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {slow} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {slow} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {slow} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {slow} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {slow} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {slow} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {slow} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {slow} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {slow} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {slow} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {slow} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {slow} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {inout} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {inout} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {inout} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {inout} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {inout} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {in} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {out} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {in} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {inout} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_PRIMITIVE {54} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+   CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+   CONFIG.PCW_P2F_CAN0_INTR {0} \
+   CONFIG.PCW_P2F_CAN1_INTR {0} \
+   CONFIG.PCW_P2F_CTI_INTR {0} \
+   CONFIG.PCW_P2F_DMAC0_INTR {0} \
+   CONFIG.PCW_P2F_DMAC1_INTR {0} \
+   CONFIG.PCW_P2F_DMAC2_INTR {0} \
+   CONFIG.PCW_P2F_DMAC3_INTR {0} \
+   CONFIG.PCW_P2F_DMAC4_INTR {0} \
+   CONFIG.PCW_P2F_DMAC5_INTR {0} \
+   CONFIG.PCW_P2F_DMAC6_INTR {0} \
+   CONFIG.PCW_P2F_DMAC7_INTR {0} \
+   CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
+   CONFIG.PCW_P2F_ENET0_INTR {0} \
+   CONFIG.PCW_P2F_ENET1_INTR {0} \
+   CONFIG.PCW_P2F_GPIO_INTR {0} \
+   CONFIG.PCW_P2F_I2C0_INTR {0} \
+   CONFIG.PCW_P2F_I2C1_INTR {0} \
+   CONFIG.PCW_P2F_QSPI_INTR {0} \
+   CONFIG.PCW_P2F_SDIO0_INTR {0} \
+   CONFIG.PCW_P2F_SDIO1_INTR {0} \
+   CONFIG.PCW_P2F_SMC_INTR {0} \
+   CONFIG.PCW_P2F_SPI0_INTR {0} \
+   CONFIG.PCW_P2F_SPI1_INTR {0} \
+   CONFIG.PCW_P2F_UART0_INTR {0} \
+   CONFIG.PCW_P2F_UART1_INTR {0} \
+   CONFIG.PCW_P2F_USB0_INTR {0} \
+   CONFIG.PCW_P2F_USB1_INTR {0} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \
+   CONFIG.PCW_PACKAGE_NAME {clg400} \
+   CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+   CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+   CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+   CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+   CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+   CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+   CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+   CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
+   CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
+   CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
+   CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
+   CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+   CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+   CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
+   CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+   CONFIG.PCW_UART0_BAUD_RATE {115200} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+   CONFIG.PCW_UART1_BAUD_RATE {115200} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+   CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+   CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+   CONFIG.PCW_UIPARAM_DDR_AL {0} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BL {8} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
+   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+   CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+   CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+   CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {0} \
+   CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
+   CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
+   CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+   CONFIG.PCW_USE_AXI_NONSECURE {0} \
+   CONFIG.PCW_USE_CORESIGHT {0} \
+   CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+   CONFIG.PCW_USE_CR_FABRIC {1} \
+   CONFIG.PCW_USE_DDR_BYPASS {0} \
+   CONFIG.PCW_USE_DEBUG {0} \
+   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
+   CONFIG.PCW_USE_DMA0 {0} \
+   CONFIG.PCW_USE_DMA1 {0} \
+   CONFIG.PCW_USE_DMA2 {0} \
+   CONFIG.PCW_USE_DMA3 {0} \
+   CONFIG.PCW_USE_EXPANDED_IOP {0} \
+   CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_HIGH_OCM {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_S_AXI_ACP {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP2 {0} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+   CONFIG.PCW_USE_TRACE {0} \
+   CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
+   CONFIG.PCW_VALUE_SILVERSION {3} \
+   CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
+ ] $processing_system7_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+
+  # Create port connections
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+
+  # Create address segments
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
new file mode 100644
index 0000000..dea2baf
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
@@ -0,0 +1,3934 @@
+ 
+//-----------------------------------------------------------------------------
+// processing_system7
+// processor sub system wrapper
+//-----------------------------------------------------------------------------
+//
+// ************************************************************************
+// ** DISCLAIMER OF LIABILITY                                            **
+// **                                                                    **
+// ** This file contains proprietary and confidential information of     **
+// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license       **
+// ** from Xilinx, and may be used, copied and/or diSCLosed only         **
+// ** pursuant to the terms of a valid license agreement with Xilinx.    **
+// **                                                                    **
+// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION              **
+// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER         **
+// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT                **
+// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,          **
+// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx      **
+// ** does not warrant that functions included in the Materials will     **
+// ** meet the requirements of Licensee, or that the operation of the    **
+// ** Materials will be uninterrupted or error-free, or that defects     **
+// ** in the Materials will be corrected. Furthermore, Xilinx does       **
+// ** not warrant or make any representations regarding use, or the      **
+// ** results of the use, of the Materials in terms of correctness,      **
+// ** accuracy, reliability or otherwise.                                **
+// **                                                                    **
+// ** Xilinx products are not designed or intended to be fail-safe,      **
+// ** or for use in any application requiring fail-safe performance,     **
+// ** such as life-support or safety devices or systems, Class III       **
+// ** medical devices, nuclear facilities, applications related to       **
+// ** the deployment of airbags, or any other applications that could    **
+// ** lead to death, personal injury or severe property or               **
+// ** environmental damage (individually and collectively, "critical     **
+// ** applications"). Customer assumes the sole risk and liability       **
+// ** of any use of Xilinx products in critical applications,            **
+// ** subject only to applicable laws and regulations governing          **
+// ** limitations on product liability.                                  **
+// **                                                                    **
+// ** Copyright 2010 Xilinx, Inc.                                        **
+// ** All rights reserved.                                               **
+// **                                                                    **
+// ** This disclaimer and copyright notice must be retained as part      **
+// ** of this file at all times.                                         **
+// ************************************************************************
+//
+//-----------------------------------------------------------------------------
+// Filename:      processing_system7_v5_5_processing_system7.v
+// Version:       v1.00.a
+// Description:   This is the wrapper file for PSS. 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7_v5_5_processing_system7.v
+//                    --PS7.v - Unisim component
+//-----------------------------------------------------------------------------
+// Author:      SD
+//
+// History:
+//
+//  SD      09/20/11      -- First version
+// ~~~~~~
+// Created the first version v2.00.a
+// ^^^^^^
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  SR     11/25/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+// 1. Changed all clock, reset and clktrig ports to be individual
+// signals instead of vectors. This is required for modeling of tools.
+// 2. Interrupts are now defined as individual signals as well.
+// 3. Added Clk buffer logic for FCLK_CLK
+// 4. Includes the ACP related changes done
+//
+// TODO:
+// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
+//    number of interrupt ports connected for IRQ_F2P.
+// 
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  KP     12/07/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+//  C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     12/09/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+//  C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated 
+//  to STRING and fix for CR 640523
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     12/13/11       -- v3.00.a version
+// ~~~~~~~
+// Key changes are
+// Updated IRQ_F2P logic to address CR 641523.
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     02/01/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// Updated SDIO logic to address CR 636210.
+//         |
+//         Added C_PS7_SI_REV parameter to track SI Rev
+// Removed compress/decompress logic to address CR 642527.
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     02/27/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual 
+// ports as fix for CR 646379
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     03/05/12       -- v3.01.a version
+// ~~~~~~~
+// Key changes are
+// Added/updated compress/decompress logic to address 648393
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     03/14/12       -- v4.00.a version
+// ~~~~~~~
+// Unused parameters deleted CR 651120
+// Addressed CR 651751
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  NR     04/17/12       -- v4.01.a version
+// ~~~~~~~
+// Added FTM trace buffer functionality
+// Added support for ACP AxUSER ports local update
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     05/18/12       -- v4.01.a version
+// ~~~~~~~
+// Fixed CR#659157
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     07/25/12       -- v4.01.a version
+// ~~~~~~~
+// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
+// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
+//------------------------------------------------------------------------------
+// ^^^^^^
+//  VR     11/06/12       -- v5.00 version
+// ~~~~~~~
+// CR #682573
+// Added BIBUF to fixed IO ports and IBUF to fixed input ports
+//------------------------------------------------------------------------------
+(*POWER= "/>" *)
+(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
+, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=50\
+, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\
+, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0\
+, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low\
+, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)  
+(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)  
+
+module processing_system7_v5_5_processing_system7
+
+#(
+  parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
+  parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
+  parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
+  parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, 
+  parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
+  parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, 
+  parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
+  parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
+  parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
+  parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
+  parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
+  parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
+  parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
+  parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
+  parameter integer C_NUM_F2P_INTR_INPUTS = 1,
+  parameter         C_FCLK_CLK0_BUF = "TRUE",
+  parameter         C_FCLK_CLK1_BUF = "TRUE",
+  parameter         C_FCLK_CLK2_BUF = "TRUE",
+  parameter         C_FCLK_CLK3_BUF = "TRUE",
+  parameter integer C_EMIO_GPIO_WIDTH = 64,
+  parameter integer C_INCLUDE_TRACE_BUFFER = 0,
+  parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
+  parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
+  parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+  parameter integer C_TRACE_PIPELINE_WIDTH = 8,
+  parameter         C_PS7_SI_REV = "PRODUCTION",
+  parameter integer C_EN_EMIO_ENET0 = 0,
+  parameter integer C_EN_EMIO_ENET1 = 0,
+  parameter integer C_EN_EMIO_TRACE = 0,
+  parameter integer C_DQ_WIDTH = 32,
+  parameter integer C_DQS_WIDTH = 4,
+  parameter integer C_DM_WIDTH = 4,
+  parameter integer C_MIO_PRIMITIVE = 54,
+  parameter	    C_PACKAGE_NAME = "clg484",
+  parameter C_IRQ_F2P_MODE = "DIRECT",
+  parameter C_TRACE_INTERNAL_WIDTH = 32,
+  parameter integer C_EN_EMIO_PJTAG = 0,
+  
+  // Enable and disable AFI Secure transaction 
+  parameter C_USE_AXI_NONSECURE = 0,
+  
+  //parameters for HP enable ports 
+  parameter C_USE_S_AXI_HP0 = 0,
+  parameter C_USE_S_AXI_HP1 = 0,
+  parameter C_USE_S_AXI_HP2 = 0,
+  parameter C_USE_S_AXI_HP3 = 0,
+  
+  //parameters for GP and ACP enable ports */
+  parameter C_USE_M_AXI_GP0 = 0,
+  parameter C_USE_M_AXI_GP1 = 0,
+  parameter C_USE_S_AXI_GP0 = 0,
+  parameter C_USE_S_AXI_GP1 = 0,
+  parameter C_USE_S_AXI_ACP = 0,
+  parameter C_GP0_EN_MODIFIABLE_TXN=0,
+  parameter C_GP1_EN_MODIFIABLE_TXN=0
+   
+)
+(
+  //FMIO =========================================
+  
+  //FMIO CAN0
+  output          CAN0_PHY_TX,
+  input           CAN0_PHY_RX,
+
+  //FMIO CAN1
+  output          CAN1_PHY_TX,  
+  input           CAN1_PHY_RX,
+  
+  //FMIO ENET0
+  output  reg     ENET0_GMII_TX_EN = 'b0,
+  output  reg     ENET0_GMII_TX_ER = 'b0,
+  output          ENET0_MDIO_MDC,
+  output          ENET0_MDIO_O,
+  output          ENET0_MDIO_T,
+  output          ENET0_PTP_DELAY_REQ_RX,
+  output          ENET0_PTP_DELAY_REQ_TX,
+  output          ENET0_PTP_PDELAY_REQ_RX,
+  output          ENET0_PTP_PDELAY_REQ_TX,
+  output          ENET0_PTP_PDELAY_RESP_RX,
+  output          ENET0_PTP_PDELAY_RESP_TX,
+  output          ENET0_PTP_SYNC_FRAME_RX,
+  output          ENET0_PTP_SYNC_FRAME_TX,
+  output          ENET0_SOF_RX,
+  output          ENET0_SOF_TX,
+  
+  
+  output  reg [7:0]    ENET0_GMII_TXD,  
+
+  
+  input           ENET0_GMII_COL,
+  input           ENET0_GMII_CRS,
+  input           ENET0_GMII_RX_CLK,
+  input           ENET0_GMII_RX_DV,
+  input           ENET0_GMII_RX_ER,
+  input           ENET0_GMII_TX_CLK,
+  input           ENET0_MDIO_I,
+  input           ENET0_EXT_INTIN,
+  input [7:0]     ENET0_GMII_RXD,  
+
+  //FMIO ENET1
+  output   reg    ENET1_GMII_TX_EN = 'b0,
+  output   reg    ENET1_GMII_TX_ER = 'b0,
+  output          ENET1_MDIO_MDC,
+  output          ENET1_MDIO_O,
+  output          ENET1_MDIO_T,
+  output          ENET1_PTP_DELAY_REQ_RX,
+  output          ENET1_PTP_DELAY_REQ_TX,
+  output          ENET1_PTP_PDELAY_REQ_RX,
+  output          ENET1_PTP_PDELAY_REQ_TX,
+  output          ENET1_PTP_PDELAY_RESP_RX,
+  output          ENET1_PTP_PDELAY_RESP_TX,
+  output          ENET1_PTP_SYNC_FRAME_RX,
+  output          ENET1_PTP_SYNC_FRAME_TX,
+  output          ENET1_SOF_RX,
+  output          ENET1_SOF_TX,
+  output reg [7:0]    ENET1_GMII_TXD,  
+
+  input          ENET1_GMII_COL,
+  input          ENET1_GMII_CRS,
+  input          ENET1_GMII_RX_CLK,
+  input          ENET1_GMII_RX_DV,
+  input          ENET1_GMII_RX_ER,
+  input          ENET1_GMII_TX_CLK,
+  input          ENET1_MDIO_I,
+  input          ENET1_EXT_INTIN,  
+  input [7:0]    ENET1_GMII_RXD,
+  
+  //FMIO GPIO
+  input    [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
+  output   [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
+  output   [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,  
+  
+  //FMIO I2C0
+  input           I2C0_SDA_I,
+  output          I2C0_SDA_O,
+  output          I2C0_SDA_T,
+  input           I2C0_SCL_I,
+  output          I2C0_SCL_O,
+  output          I2C0_SCL_T,
+
+  //FMIO I2C1
+  input           I2C1_SDA_I,
+  output          I2C1_SDA_O,
+  output          I2C1_SDA_T,
+  input           I2C1_SCL_I,
+  output          I2C1_SCL_O,
+  output          I2C1_SCL_T,
+  
+  //FMIO PJTAG
+  input           PJTAG_TCK,
+  input           PJTAG_TMS,
+  input           PJTAG_TDI,
+  output          PJTAG_TDO,
+
+  
+  //FMIO SDIO0
+  output          SDIO0_CLK,
+  input           SDIO0_CLK_FB,
+  output          SDIO0_CMD_O,
+  input           SDIO0_CMD_I,
+  output          SDIO0_CMD_T,
+  input     [3:0] SDIO0_DATA_I,
+  output    [3:0] SDIO0_DATA_O,
+  output    [3:0] SDIO0_DATA_T,
+  output          SDIO0_LED,
+  input           SDIO0_CDN,
+  input           SDIO0_WP,  
+  output          SDIO0_BUSPOW,
+  output    [2:0] SDIO0_BUSVOLT,
+
+  //FMIO SDIO1
+  output          SDIO1_CLK,
+  input           SDIO1_CLK_FB,
+  output          SDIO1_CMD_O,
+  input           SDIO1_CMD_I,
+  output          SDIO1_CMD_T,
+  input     [3:0] SDIO1_DATA_I,
+  output    [3:0] SDIO1_DATA_O,
+  output    [3:0] SDIO1_DATA_T,  
+  output          SDIO1_LED,
+  input           SDIO1_CDN,  
+  input           SDIO1_WP,
+  output          SDIO1_BUSPOW,  
+  output    [2:0] SDIO1_BUSVOLT,
+
+  //FMIO SPI0
+  input           SPI0_SCLK_I,
+  output          SPI0_SCLK_O,
+  output          SPI0_SCLK_T,
+  input           SPI0_MOSI_I,
+  output          SPI0_MOSI_O,
+  output          SPI0_MOSI_T,
+  input           SPI0_MISO_I,
+  output          SPI0_MISO_O,
+  output          SPI0_MISO_T,
+  input           SPI0_SS_I,
+  output          SPI0_SS_O,
+  output          SPI0_SS1_O,
+  output          SPI0_SS2_O,
+  output          SPI0_SS_T,
+
+  //FMIO SPI1
+  input           SPI1_SCLK_I,
+  output          SPI1_SCLK_O,
+  output          SPI1_SCLK_T,
+  input           SPI1_MOSI_I,
+  output          SPI1_MOSI_O,
+  output          SPI1_MOSI_T,
+  input           SPI1_MISO_I,
+  output          SPI1_MISO_O,
+  output          SPI1_MISO_T,
+  input           SPI1_SS_I,
+  output          SPI1_SS_O,
+  output          SPI1_SS1_O,
+  output          SPI1_SS2_O,  
+  output          SPI1_SS_T,
+
+  //FMIO UART0
+  output          UART0_DTRN,
+  output          UART0_RTSN,  
+  output          UART0_TX,
+  input           UART0_CTSN,
+  input           UART0_DCDN,
+  input           UART0_DSRN,
+  input           UART0_RIN,  
+  input           UART0_RX,
+
+  //FMIO UART1
+  output          UART1_DTRN,
+  output          UART1_RTSN,  
+  output          UART1_TX,
+  input           UART1_CTSN,
+  input           UART1_DCDN,
+  input           UART1_DSRN,
+  input           UART1_RIN,  
+  input           UART1_RX,
+
+  //FMIO TTC0
+  output    		TTC0_WAVE0_OUT,
+  output    		TTC0_WAVE1_OUT,
+  output    		TTC0_WAVE2_OUT,
+  input     		TTC0_CLK0_IN,
+  input     		TTC0_CLK1_IN,
+  input     		TTC0_CLK2_IN,
+
+  //FMIO TTC1
+  output    		TTC1_WAVE0_OUT,
+  output    		TTC1_WAVE1_OUT,
+  output    		TTC1_WAVE2_OUT,
+  input     		TTC1_CLK0_IN,
+  input     		TTC1_CLK1_IN,
+  input     		TTC1_CLK2_IN,
+
+  //WDT
+  input           WDT_CLK_IN,
+  output          WDT_RST_OUT,
+
+  //FTPORT
+  input           TRACE_CLK,
+  output          TRACE_CTL,
+  output   [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
+  output   reg		  TRACE_CLK_OUT,
+  
+  // USB
+  output   [1:0]  USB0_PORT_INDCTL,
+  output          USB0_VBUS_PWRSELECT,
+  input           USB0_VBUS_PWRFAULT,
+
+  output   [1:0]  USB1_PORT_INDCTL,
+  output          USB1_VBUS_PWRSELECT,
+  input           USB1_VBUS_PWRFAULT,
+  
+  input           SRAM_INTIN,
+
+  //AIO ===================================================
+
+  //M_AXI_GP0
+  
+  // -- Output
+  
+  output M_AXI_GP0_ARESETN,
+  output M_AXI_GP0_ARVALID,
+  output M_AXI_GP0_AWVALID,
+  output M_AXI_GP0_BREADY,
+  output M_AXI_GP0_RREADY,
+  output M_AXI_GP0_WLAST,
+  output M_AXI_GP0_WVALID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
+  output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
+  output [1:0] M_AXI_GP0_ARBURST,
+  output [1:0] M_AXI_GP0_ARLOCK,
+  output [2:0] M_AXI_GP0_ARSIZE,
+  output [1:0] M_AXI_GP0_AWBURST,
+  output [1:0] M_AXI_GP0_AWLOCK,
+  output [2:0] M_AXI_GP0_AWSIZE,
+  output [2:0] M_AXI_GP0_ARPROT,
+  output [2:0] M_AXI_GP0_AWPROT,
+  output [31:0] M_AXI_GP0_ARADDR,
+  output [31:0] M_AXI_GP0_AWADDR,
+  output [31:0] M_AXI_GP0_WDATA,
+  output [3:0] M_AXI_GP0_ARCACHE,
+  output [3:0] M_AXI_GP0_ARLEN,
+  output [3:0] M_AXI_GP0_ARQOS,
+  output [3:0] M_AXI_GP0_AWCACHE,
+  output [3:0] M_AXI_GP0_AWLEN,
+  output [3:0] M_AXI_GP0_AWQOS,
+  output [3:0] M_AXI_GP0_WSTRB, 
+  
+  // -- Input  
+  
+  input M_AXI_GP0_ACLK,
+  input M_AXI_GP0_ARREADY,
+  input M_AXI_GP0_AWREADY,
+  input M_AXI_GP0_BVALID,
+  input M_AXI_GP0_RLAST,
+  input M_AXI_GP0_RVALID,
+  input M_AXI_GP0_WREADY,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
+  input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
+  input [1:0] M_AXI_GP0_BRESP,
+  input [1:0] M_AXI_GP0_RRESP,
+  input [31:0] M_AXI_GP0_RDATA,  
+
+
+  //M_AXI_GP1
+  
+  // -- Output
+
+  output M_AXI_GP1_ARESETN,
+  output M_AXI_GP1_ARVALID,
+  output M_AXI_GP1_AWVALID,
+  output M_AXI_GP1_BREADY,
+  output M_AXI_GP1_RREADY,
+  output M_AXI_GP1_WLAST,
+  output M_AXI_GP1_WVALID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
+  output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
+  output [1:0] M_AXI_GP1_ARBURST,
+  output [1:0] M_AXI_GP1_ARLOCK,
+  output [2:0] M_AXI_GP1_ARSIZE,
+  output [1:0] M_AXI_GP1_AWBURST,
+  output [1:0] M_AXI_GP1_AWLOCK,
+  output [2:0] M_AXI_GP1_AWSIZE,
+  output [2:0] M_AXI_GP1_ARPROT,
+  output [2:0] M_AXI_GP1_AWPROT,
+  output [31:0] M_AXI_GP1_ARADDR,
+  output [31:0] M_AXI_GP1_AWADDR,
+  output [31:0] M_AXI_GP1_WDATA,
+  output [3:0] M_AXI_GP1_ARCACHE,
+  output [3:0] M_AXI_GP1_ARLEN,
+  output [3:0] M_AXI_GP1_ARQOS,
+  output [3:0] M_AXI_GP1_AWCACHE,
+  output [3:0] M_AXI_GP1_AWLEN,
+  output [3:0] M_AXI_GP1_AWQOS,
+  output [3:0] M_AXI_GP1_WSTRB,
+  
+  // -- Input
+  
+  input M_AXI_GP1_ACLK,
+  input M_AXI_GP1_ARREADY,
+  input M_AXI_GP1_AWREADY,
+  input M_AXI_GP1_BVALID,
+  input M_AXI_GP1_RLAST,
+  input M_AXI_GP1_RVALID,
+  input M_AXI_GP1_WREADY,  
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
+  input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
+  input [1:0] M_AXI_GP1_BRESP,
+  input [1:0] M_AXI_GP1_RRESP,
+  input [31:0] M_AXI_GP1_RDATA,  
+  
+
+  // S_AXI_GP0
+  
+  // -- Output
+  
+  output S_AXI_GP0_ARESETN,
+  output S_AXI_GP0_ARREADY,
+  output S_AXI_GP0_AWREADY,
+  output S_AXI_GP0_BVALID,
+  output S_AXI_GP0_RLAST,
+  output S_AXI_GP0_RVALID,
+  output S_AXI_GP0_WREADY,  
+  output [1:0] S_AXI_GP0_BRESP,
+  output [1:0] S_AXI_GP0_RRESP,
+  output [31:0] S_AXI_GP0_RDATA,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
+  output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
+  
+  // -- Input
+  input S_AXI_GP0_ACLK,
+  input S_AXI_GP0_ARVALID,
+  input S_AXI_GP0_AWVALID,
+  input S_AXI_GP0_BREADY,
+  input S_AXI_GP0_RREADY,
+  input S_AXI_GP0_WLAST,
+  input S_AXI_GP0_WVALID,
+  input [1:0] S_AXI_GP0_ARBURST,
+  input [1:0] S_AXI_GP0_ARLOCK,
+  input [2:0] S_AXI_GP0_ARSIZE,
+  input [1:0] S_AXI_GP0_AWBURST,
+  input [1:0] S_AXI_GP0_AWLOCK,
+  input [2:0] S_AXI_GP0_AWSIZE,
+  input [2:0] S_AXI_GP0_ARPROT,
+  input [2:0] S_AXI_GP0_AWPROT,
+  input [31:0] S_AXI_GP0_ARADDR,
+  input [31:0] S_AXI_GP0_AWADDR,
+  input [31:0] S_AXI_GP0_WDATA,
+  input [3:0] S_AXI_GP0_ARCACHE,
+  input [3:0] S_AXI_GP0_ARLEN,
+  input [3:0] S_AXI_GP0_ARQOS,
+  input [3:0] S_AXI_GP0_AWCACHE,
+  input [3:0] S_AXI_GP0_AWLEN,
+  input [3:0] S_AXI_GP0_AWQOS,
+  input [3:0] S_AXI_GP0_WSTRB,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
+  input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,  
+
+  // S_AXI_GP1
+  
+  // -- Output  
+  output S_AXI_GP1_ARESETN,
+  output S_AXI_GP1_ARREADY,
+  output S_AXI_GP1_AWREADY,
+  output S_AXI_GP1_BVALID,
+  output S_AXI_GP1_RLAST,
+  output S_AXI_GP1_RVALID,
+  output S_AXI_GP1_WREADY,  
+  output [1:0] S_AXI_GP1_BRESP,
+  output [1:0] S_AXI_GP1_RRESP,
+  output [31:0] S_AXI_GP1_RDATA,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
+  output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
+  
+  // -- Input
+  input S_AXI_GP1_ACLK,
+  input S_AXI_GP1_ARVALID,
+  input S_AXI_GP1_AWVALID,
+  input S_AXI_GP1_BREADY,
+  input S_AXI_GP1_RREADY,
+  input S_AXI_GP1_WLAST,
+  input S_AXI_GP1_WVALID,
+  input [1:0] S_AXI_GP1_ARBURST,
+  input [1:0] S_AXI_GP1_ARLOCK,
+  input [2:0] S_AXI_GP1_ARSIZE,
+  input [1:0] S_AXI_GP1_AWBURST,
+  input [1:0] S_AXI_GP1_AWLOCK,
+  input [2:0] S_AXI_GP1_AWSIZE,
+  input [2:0] S_AXI_GP1_ARPROT,
+  input [2:0] S_AXI_GP1_AWPROT,
+  input [31:0] S_AXI_GP1_ARADDR,
+  input [31:0] S_AXI_GP1_AWADDR,
+  input [31:0] S_AXI_GP1_WDATA,
+  input [3:0] S_AXI_GP1_ARCACHE,
+  input [3:0] S_AXI_GP1_ARLEN,
+  input [3:0] S_AXI_GP1_ARQOS,
+  input [3:0] S_AXI_GP1_AWCACHE,
+  input [3:0] S_AXI_GP1_AWLEN,
+  input [3:0] S_AXI_GP1_AWQOS,
+  input [3:0] S_AXI_GP1_WSTRB,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
+  input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,  
+
+  //S_AXI_ACP
+  
+  // -- Output  
+  
+  output S_AXI_ACP_ARESETN,
+  output S_AXI_ACP_ARREADY,
+  output S_AXI_ACP_AWREADY,
+  output S_AXI_ACP_BVALID,
+  output S_AXI_ACP_RLAST,
+  output S_AXI_ACP_RVALID,
+  output S_AXI_ACP_WREADY,  
+  output [1:0] S_AXI_ACP_BRESP,
+  output [1:0] S_AXI_ACP_RRESP,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
+  output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
+  output [63:0] S_AXI_ACP_RDATA,
+  
+  // -- Input
+  
+  input S_AXI_ACP_ACLK,
+  input S_AXI_ACP_ARVALID,
+  input S_AXI_ACP_AWVALID,
+  input S_AXI_ACP_BREADY,
+  input S_AXI_ACP_RREADY,
+  input S_AXI_ACP_WLAST,
+  input S_AXI_ACP_WVALID,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
+  input [2:0] S_AXI_ACP_ARPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
+  input [2:0] S_AXI_ACP_AWPROT,
+  input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
+  input [31:0] S_AXI_ACP_ARADDR,
+  input [31:0] S_AXI_ACP_AWADDR,
+  input [3:0] S_AXI_ACP_ARCACHE,
+  input [3:0] S_AXI_ACP_ARLEN,
+  input [3:0] S_AXI_ACP_ARQOS,
+  input [3:0] S_AXI_ACP_AWCACHE,
+  input [3:0] S_AXI_ACP_AWLEN,
+  input [3:0] S_AXI_ACP_AWQOS,  
+  input [1:0] S_AXI_ACP_ARBURST,
+  input [1:0] S_AXI_ACP_ARLOCK,
+  input [2:0] S_AXI_ACP_ARSIZE,
+  input [1:0] S_AXI_ACP_AWBURST,
+  input [1:0] S_AXI_ACP_AWLOCK,
+  input [2:0] S_AXI_ACP_AWSIZE,
+  input [4:0] S_AXI_ACP_ARUSER,
+  input [4:0] S_AXI_ACP_AWUSER,
+  input [63:0] S_AXI_ACP_WDATA,
+  input [7:0] S_AXI_ACP_WSTRB,  
+  
+  // S_AXI_HP_0
+  
+  // -- Output
+  output S_AXI_HP0_ARESETN,
+  output S_AXI_HP0_ARREADY,
+  output S_AXI_HP0_AWREADY,
+  output S_AXI_HP0_BVALID,
+  output S_AXI_HP0_RLAST,
+  output S_AXI_HP0_RVALID,
+  output S_AXI_HP0_WREADY,  
+  output [1:0] S_AXI_HP0_BRESP,
+  output [1:0] S_AXI_HP0_RRESP,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
+  output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
+  output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
+  output [7:0] S_AXI_HP0_RCOUNT,
+  output [7:0] S_AXI_HP0_WCOUNT,
+  output [2:0] S_AXI_HP0_RACOUNT,
+  output [5:0] S_AXI_HP0_WACOUNT,
+  
+  // -- Input  
+  input S_AXI_HP0_ACLK,
+  input S_AXI_HP0_ARVALID,
+  input S_AXI_HP0_AWVALID,
+  input S_AXI_HP0_BREADY,
+  input S_AXI_HP0_RDISSUECAP1_EN,
+  input S_AXI_HP0_RREADY,
+  input S_AXI_HP0_WLAST,
+  input S_AXI_HP0_WRISSUECAP1_EN,
+  input S_AXI_HP0_WVALID,
+  input [1:0] S_AXI_HP0_ARBURST,
+  input [1:0] S_AXI_HP0_ARLOCK,
+  input [2:0] S_AXI_HP0_ARSIZE,
+  input [1:0] S_AXI_HP0_AWBURST,
+  input [1:0] S_AXI_HP0_AWLOCK,
+  input [2:0] S_AXI_HP0_AWSIZE,
+  input [2:0] S_AXI_HP0_ARPROT,
+  input [2:0] S_AXI_HP0_AWPROT,
+  input [31:0] S_AXI_HP0_ARADDR,
+  input [31:0] S_AXI_HP0_AWADDR,
+  input [3:0] S_AXI_HP0_ARCACHE,
+  input [3:0] S_AXI_HP0_ARLEN,
+  input [3:0] S_AXI_HP0_ARQOS,
+  input [3:0] S_AXI_HP0_AWCACHE,
+  input [3:0] S_AXI_HP0_AWLEN,
+  input [3:0] S_AXI_HP0_AWQOS,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
+  input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
+  input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
+  input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,  
+
+  // S_AXI_HP1
+  // -- Output
+  output S_AXI_HP1_ARESETN,
+  output S_AXI_HP1_ARREADY,
+  output S_AXI_HP1_AWREADY,
+  output S_AXI_HP1_BVALID,
+  output S_AXI_HP1_RLAST,
+  output S_AXI_HP1_RVALID,
+  output S_AXI_HP1_WREADY,  
+  output [1:0] S_AXI_HP1_BRESP,
+  output [1:0] S_AXI_HP1_RRESP,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
+  output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
+  output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
+  output [7:0] S_AXI_HP1_RCOUNT,
+  output [7:0] S_AXI_HP1_WCOUNT,
+  output [2:0] S_AXI_HP1_RACOUNT,
+  output [5:0] S_AXI_HP1_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP1_ACLK,
+  input S_AXI_HP1_ARVALID,
+  input S_AXI_HP1_AWVALID,
+  input S_AXI_HP1_BREADY,
+  input S_AXI_HP1_RDISSUECAP1_EN,
+  input S_AXI_HP1_RREADY,
+  input S_AXI_HP1_WLAST,
+  input S_AXI_HP1_WRISSUECAP1_EN,
+  input S_AXI_HP1_WVALID,
+  input [1:0] S_AXI_HP1_ARBURST,
+  input [1:0] S_AXI_HP1_ARLOCK,
+  input [2:0] S_AXI_HP1_ARSIZE,
+  input [1:0] S_AXI_HP1_AWBURST,
+  input [1:0] S_AXI_HP1_AWLOCK,
+  input [2:0] S_AXI_HP1_AWSIZE,
+  input [2:0] S_AXI_HP1_ARPROT,
+  input [2:0] S_AXI_HP1_AWPROT,
+  input [31:0] S_AXI_HP1_ARADDR,
+  input [31:0] S_AXI_HP1_AWADDR,
+  input [3:0] S_AXI_HP1_ARCACHE,
+  input [3:0] S_AXI_HP1_ARLEN,
+  input [3:0] S_AXI_HP1_ARQOS,
+  input [3:0] S_AXI_HP1_AWCACHE,
+  input [3:0] S_AXI_HP1_AWLEN,
+  input [3:0] S_AXI_HP1_AWQOS,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
+  input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
+  input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
+  input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,  
+
+  // S_AXI_HP2
+  // -- Output
+  output S_AXI_HP2_ARESETN,
+  output S_AXI_HP2_ARREADY,
+  output S_AXI_HP2_AWREADY,
+  output S_AXI_HP2_BVALID,
+  output S_AXI_HP2_RLAST,
+  output S_AXI_HP2_RVALID,
+  output S_AXI_HP2_WREADY,  
+  output [1:0] S_AXI_HP2_BRESP,
+  output [1:0] S_AXI_HP2_RRESP,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
+  output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
+  output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
+  output [7:0] S_AXI_HP2_RCOUNT,
+  output [7:0] S_AXI_HP2_WCOUNT,
+  output [2:0] S_AXI_HP2_RACOUNT,
+  output [5:0] S_AXI_HP2_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP2_ACLK,
+  input S_AXI_HP2_ARVALID,
+  input S_AXI_HP2_AWVALID,
+  input S_AXI_HP2_BREADY,
+  input S_AXI_HP2_RDISSUECAP1_EN,
+  input S_AXI_HP2_RREADY,
+  input S_AXI_HP2_WLAST,
+  input S_AXI_HP2_WRISSUECAP1_EN,
+  input S_AXI_HP2_WVALID,
+  input [1:0] S_AXI_HP2_ARBURST,
+  input [1:0] S_AXI_HP2_ARLOCK,
+  input [2:0] S_AXI_HP2_ARSIZE,
+  input [1:0] S_AXI_HP2_AWBURST,
+  input [1:0] S_AXI_HP2_AWLOCK,
+  input [2:0] S_AXI_HP2_AWSIZE,
+  input [2:0] S_AXI_HP2_ARPROT,
+  input [2:0] S_AXI_HP2_AWPROT,
+  input [31:0] S_AXI_HP2_ARADDR,
+  input [31:0] S_AXI_HP2_AWADDR,
+  input [3:0] S_AXI_HP2_ARCACHE,
+  input [3:0] S_AXI_HP2_ARLEN,
+  input [3:0] S_AXI_HP2_ARQOS,
+  input [3:0] S_AXI_HP2_AWCACHE,
+  input [3:0] S_AXI_HP2_AWLEN,
+  input [3:0] S_AXI_HP2_AWQOS,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
+  input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
+  input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
+  input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,  
+
+  // S_AXI_HP_3
+  
+  // -- Output
+  output S_AXI_HP3_ARESETN,
+  output S_AXI_HP3_ARREADY,
+  output S_AXI_HP3_AWREADY,
+  output S_AXI_HP3_BVALID,
+  output S_AXI_HP3_RLAST,
+  output S_AXI_HP3_RVALID,
+  output S_AXI_HP3_WREADY,  
+  output [1:0] S_AXI_HP3_BRESP,
+  output [1:0] S_AXI_HP3_RRESP,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
+  output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
+  output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
+  output [7:0] S_AXI_HP3_RCOUNT,
+  output [7:0] S_AXI_HP3_WCOUNT,
+  output [2:0] S_AXI_HP3_RACOUNT,
+  output [5:0] S_AXI_HP3_WACOUNT,
+  
+  
+  // -- Input  
+  input S_AXI_HP3_ACLK,
+  input S_AXI_HP3_ARVALID,
+  input S_AXI_HP3_AWVALID,
+  input S_AXI_HP3_BREADY,
+  input S_AXI_HP3_RDISSUECAP1_EN,
+  input S_AXI_HP3_RREADY,
+  input S_AXI_HP3_WLAST,
+  input S_AXI_HP3_WRISSUECAP1_EN,
+  input S_AXI_HP3_WVALID,
+  input [1:0] S_AXI_HP3_ARBURST,
+  input [1:0] S_AXI_HP3_ARLOCK,
+  input [2:0] S_AXI_HP3_ARSIZE,
+  input [1:0] S_AXI_HP3_AWBURST,
+  input [1:0] S_AXI_HP3_AWLOCK,
+  input [2:0] S_AXI_HP3_AWSIZE,
+  input [2:0] S_AXI_HP3_ARPROT,
+  input [2:0] S_AXI_HP3_AWPROT,
+  input [31:0] S_AXI_HP3_ARADDR,
+  input [31:0] S_AXI_HP3_AWADDR,
+  input [3:0] S_AXI_HP3_ARCACHE,
+  input [3:0] S_AXI_HP3_ARLEN,
+  input [3:0] S_AXI_HP3_ARQOS,
+  input [3:0] S_AXI_HP3_AWCACHE,
+  input [3:0] S_AXI_HP3_AWLEN,
+  input [3:0] S_AXI_HP3_AWQOS,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
+  input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
+  input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
+  input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,  
+  
+  //FIO ========================================
+
+  //IRQ
+  //output [28:0] IRQ_P2F,
+  output IRQ_P2F_DMAC_ABORT ,
+  output IRQ_P2F_DMAC0,
+  output IRQ_P2F_DMAC1,
+  output IRQ_P2F_DMAC2,
+  output IRQ_P2F_DMAC3,
+  output IRQ_P2F_DMAC4,
+  output IRQ_P2F_DMAC5,
+  output IRQ_P2F_DMAC6,
+  output IRQ_P2F_DMAC7,
+  output IRQ_P2F_SMC,
+  output IRQ_P2F_QSPI,
+  output IRQ_P2F_CTI,
+  output IRQ_P2F_GPIO,
+  output IRQ_P2F_USB0,
+  output IRQ_P2F_ENET0,
+  output IRQ_P2F_ENET_WAKE0,
+  output IRQ_P2F_SDIO0,
+  output IRQ_P2F_I2C0,
+  output IRQ_P2F_SPI0,
+  output IRQ_P2F_UART0,
+  output IRQ_P2F_CAN0,
+  output IRQ_P2F_USB1,
+  output IRQ_P2F_ENET1,
+  output IRQ_P2F_ENET_WAKE1,
+  output IRQ_P2F_SDIO1,
+  output IRQ_P2F_I2C1,
+  output IRQ_P2F_SPI1,
+  output IRQ_P2F_UART1,
+  output IRQ_P2F_CAN1,
+  input  [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
+  input         Core0_nFIQ,
+  input         Core0_nIRQ,
+  input         Core1_nFIQ,
+  input         Core1_nIRQ,
+
+  //DMA
+
+  output [1:0] DMA0_DATYPE,  
+  output DMA0_DAVALID,
+  output DMA0_DRREADY,
+  output DMA0_RSTN,  
+  output [1:0] DMA1_DATYPE,  
+  output DMA1_DAVALID,
+  output DMA1_DRREADY,
+  output DMA1_RSTN,  
+  output [1:0] DMA2_DATYPE,  
+  output DMA2_DAVALID,
+  output DMA2_DRREADY,
+  output DMA2_RSTN,  
+  output [1:0] DMA3_DATYPE,    
+  output DMA3_DAVALID,
+  output DMA3_DRREADY,
+  output DMA3_RSTN,  
+  input DMA0_ACLK,
+  input DMA0_DAREADY,
+  input DMA0_DRLAST,
+  input DMA0_DRVALID,
+  input DMA1_ACLK,
+  input DMA1_DAREADY,
+  input DMA1_DRLAST,
+  input DMA1_DRVALID,
+  input DMA2_ACLK,
+  input DMA2_DAREADY,
+  input DMA2_DRLAST,
+  input DMA2_DRVALID,
+  input DMA3_ACLK,
+  input DMA3_DAREADY,
+  input DMA3_DRLAST,
+  input DMA3_DRVALID,  
+  input [1:0] DMA0_DRTYPE,
+  input [1:0] DMA1_DRTYPE,
+  input [1:0] DMA2_DRTYPE,
+  input [1:0] DMA3_DRTYPE,
+  
+  //FCLK
+  output    FCLK_CLK3,
+  output    FCLK_CLK2,
+  output    FCLK_CLK1,
+  output    FCLK_CLK0,
+ 
+  input     FCLK_CLKTRIG3_N,
+  input     FCLK_CLKTRIG2_N,
+  input     FCLK_CLKTRIG1_N,
+  input     FCLK_CLKTRIG0_N,
+ 
+  output    FCLK_RESET3_N,
+  output    FCLK_RESET2_N,
+  output    FCLK_RESET1_N,
+  output    FCLK_RESET0_N,
+
+  //FTMD
+  input    [31:0] FTMD_TRACEIN_DATA,
+  input           FTMD_TRACEIN_VALID,
+  input           FTMD_TRACEIN_CLK,
+  input    [3:0]  FTMD_TRACEIN_ATID,
+
+  //FTMT
+  input     FTMT_F2P_TRIG_0,
+  output    FTMT_F2P_TRIGACK_0,
+  input     FTMT_F2P_TRIG_1,
+  output    FTMT_F2P_TRIGACK_1,
+  input     FTMT_F2P_TRIG_2,
+  output    FTMT_F2P_TRIGACK_2,
+  input     FTMT_F2P_TRIG_3,
+  output    FTMT_F2P_TRIGACK_3,
+  input     [31:0] FTMT_F2P_DEBUG,  
+  input     FTMT_P2F_TRIGACK_0,
+  output    FTMT_P2F_TRIG_0,
+  input     FTMT_P2F_TRIGACK_1,
+  output    FTMT_P2F_TRIG_1,
+  input     FTMT_P2F_TRIGACK_2,
+  output    FTMT_P2F_TRIG_2,
+  input     FTMT_P2F_TRIGACK_3,
+  output    FTMT_P2F_TRIG_3,
+  output    [31:0] FTMT_P2F_DEBUG,
+
+  //FIDLE
+  input           FPGA_IDLE_N,
+  
+  //EVENT
+
+  output EVENT_EVENTO,
+  output [1:0] EVENT_STANDBYWFE,
+  output [1:0] EVENT_STANDBYWFI,  
+  input EVENT_EVENTI,   
+  
+
+  //DARB
+  input     [3:0] DDR_ARB,
+  inout     [C_MIO_PRIMITIVE - 1:0] MIO,  
+  
+  //DDR
+  inout         DDR_CAS_n,       // CASB
+  inout         DDR_CKE,         // CKE
+  inout         DDR_Clk_n,       // CKN
+  inout         DDR_Clk,         // CKP
+  inout         DDR_CS_n,        // CSB 
+  inout         DDR_DRSTB,       // DDR_DRSTB  
+  inout         DDR_ODT,         // ODT
+  inout         DDR_RAS_n,       // RASB
+  inout         DDR_WEB,
+  inout  [2:0]  DDR_BankAddr,    // BA  
+  inout  [14:0] DDR_Addr,        // A
+  
+  inout          DDR_VRN,
+  inout          DDR_VRP,
+  inout   [C_DM_WIDTH - 1:0]  DDR_DM,          // DM  
+  inout   [C_DQ_WIDTH - 1:0] DDR_DQ,          // DQ
+  inout   [C_DQS_WIDTH -1:0]  DDR_DQS_n,       // DQSN
+  inout   [C_DQS_WIDTH - 1:0]  DDR_DQS,         // DQSP
+  
+  inout          PS_SRSTB,        // SRSTB    
+  inout          PS_CLK,          // CLK
+  inout          PS_PORB         // PORB 
+
+
+);
+
+wire [11:0]  M_AXI_GP0_AWID_FULL;
+wire [11:0]  M_AXI_GP0_WID_FULL;
+wire [11:0]  M_AXI_GP0_ARID_FULL;
+
+wire [11:0]  M_AXI_GP0_BID_FULL;
+wire [11:0]  M_AXI_GP0_RID_FULL;
+
+wire [11:0]  M_AXI_GP1_AWID_FULL;
+wire [11:0]  M_AXI_GP1_WID_FULL;
+wire [11:0]  M_AXI_GP1_ARID_FULL;
+
+wire [11:0]  M_AXI_GP1_BID_FULL;
+wire [11:0]  M_AXI_GP1_RID_FULL;
+
+wire [3:0] M_AXI_GP0_ARCACHE_t;
+wire [3:0] M_AXI_GP1_ARCACHE_t;
+wire [3:0] M_AXI_GP0_AWCACHE_t;
+wire [3:0] M_AXI_GP1_AWCACHE_t;
+
+
+// Wires for connecting to the PS7
+wire    ENET0_GMII_TX_EN_i;
+wire    ENET0_GMII_TX_ER_i;
+reg          ENET0_GMII_COL_i;
+reg          ENET0_GMII_CRS_i;
+reg          ENET0_GMII_RX_DV_i;
+reg          ENET0_GMII_RX_ER_i;
+reg [7:0]    ENET0_GMII_RXD_i;
+wire [7:0]   ENET0_GMII_TXD_i;
+
+wire         ENET1_GMII_TX_EN_i;
+wire         ENET1_GMII_TX_ER_i;
+reg          ENET1_GMII_COL_i;
+reg          ENET1_GMII_CRS_i;
+reg          ENET1_GMII_RX_DV_i;
+reg          ENET1_GMII_RX_ER_i;
+reg [7:0]   ENET1_GMII_RXD_i;
+wire [7:0]   ENET1_GMII_TXD_i;
+
+reg    [31:0] FTMD_TRACEIN_DATA_notracebuf;
+reg           FTMD_TRACEIN_VALID_notracebuf;
+reg    [3:0]  FTMD_TRACEIN_ATID_notracebuf;
+
+wire    [31:0] FTMD_TRACEIN_DATA_i;
+wire           FTMD_TRACEIN_VALID_i;
+wire    [3:0]  FTMD_TRACEIN_ATID_i;
+
+wire    [31:0] FTMD_TRACEIN_DATA_tracebuf;
+wire           FTMD_TRACEIN_VALID_tracebuf;
+wire    [3:0]  FTMD_TRACEIN_ATID_tracebuf;
+
+wire [5:0]    S_AXI_GP0_BID_out;
+wire [5:0]    S_AXI_GP0_RID_out;
+wire [5:0]    S_AXI_GP0_ARID_in;
+wire [5:0]    S_AXI_GP0_AWID_in;
+wire [5:0]    S_AXI_GP0_WID_in;
+
+wire [5:0]    S_AXI_GP1_BID_out;
+wire [5:0]    S_AXI_GP1_RID_out;
+wire [5:0]    S_AXI_GP1_ARID_in;
+wire [5:0]    S_AXI_GP1_AWID_in;
+wire [5:0]    S_AXI_GP1_WID_in;
+
+wire [5:0]    S_AXI_HP0_BID_out;
+wire [5:0]    S_AXI_HP0_RID_out;
+wire [5:0]    S_AXI_HP0_ARID_in;
+wire [5:0]    S_AXI_HP0_AWID_in;
+wire [5:0]    S_AXI_HP0_WID_in;
+
+wire [5:0]    S_AXI_HP1_BID_out;
+wire [5:0]    S_AXI_HP1_RID_out;
+wire [5:0]    S_AXI_HP1_ARID_in;
+wire [5:0]    S_AXI_HP1_AWID_in;
+wire [5:0]    S_AXI_HP1_WID_in;
+
+wire [5:0]    S_AXI_HP2_BID_out;
+wire [5:0]    S_AXI_HP2_RID_out;
+wire [5:0]    S_AXI_HP2_ARID_in;
+wire [5:0]    S_AXI_HP2_AWID_in;
+wire [5:0]    S_AXI_HP2_WID_in;
+
+wire [5:0]    S_AXI_HP3_BID_out;
+wire [5:0]    S_AXI_HP3_RID_out;
+wire [5:0]    S_AXI_HP3_ARID_in;
+wire [5:0]    S_AXI_HP3_AWID_in;
+wire [5:0]    S_AXI_HP3_WID_in;
+
+wire [2:0]    S_AXI_ACP_BID_out;
+wire [2:0]    S_AXI_ACP_RID_out;
+wire [2:0]    S_AXI_ACP_ARID_in;
+wire [2:0]    S_AXI_ACP_AWID_in;
+wire [2:0]    S_AXI_ACP_WID_in;  
+
+wire [63:0]   S_AXI_HP0_WDATA_in;
+wire [7:0]    S_AXI_HP0_WSTRB_in;
+wire [63:0]   S_AXI_HP0_RDATA_out;
+
+wire [63:0]   S_AXI_HP1_WDATA_in;
+wire [7:0]    S_AXI_HP1_WSTRB_in;
+wire [63:0]   S_AXI_HP1_RDATA_out;
+
+wire [63:0]   S_AXI_HP2_WDATA_in;
+wire [7:0]    S_AXI_HP2_WSTRB_in;
+wire [63:0]   S_AXI_HP2_RDATA_out;
+
+wire [63:0]   S_AXI_HP3_WDATA_in;
+wire [7:0]    S_AXI_HP3_WSTRB_in;
+wire [63:0]   S_AXI_HP3_RDATA_out;
+ 
+wire [1:0]    M_AXI_GP0_ARSIZE_i;
+wire [1:0]    M_AXI_GP0_AWSIZE_i;
+
+wire [1:0]    M_AXI_GP1_ARSIZE_i;
+wire [1:0]    M_AXI_GP1_AWSIZE_i;
+
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPBID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPRID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPARID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPAWID_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0]    SAXIACPWID_W;  
+
+
+wire SAXIACPARREADY_W;
+wire SAXIACPAWREADY_W;
+wire SAXIACPBVALID_W;
+wire SAXIACPRLAST_W;
+wire SAXIACPRVALID_W;
+wire SAXIACPWREADY_W;  
+wire [1:0] SAXIACPBRESP_W;
+wire [1:0] SAXIACPRRESP_W;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
+wire [63:0] SAXIACPRDATA_W;
+  
+wire S_AXI_ATC_ARVALID;
+wire S_AXI_ATC_AWVALID;
+wire S_AXI_ATC_BREADY;
+wire S_AXI_ATC_RREADY;
+wire S_AXI_ATC_WLAST;
+wire S_AXI_ATC_WVALID;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
+wire [2:0] S_AXI_ATC_ARPROT;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
+wire [2:0] S_AXI_ATC_AWPROT;
+wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
+wire [31:0] S_AXI_ATC_ARADDR;
+wire [31:0] S_AXI_ATC_AWADDR;
+wire [3:0] S_AXI_ATC_ARCACHE;
+wire [3:0] S_AXI_ATC_ARLEN;
+wire [3:0] S_AXI_ATC_ARQOS;
+wire [3:0] S_AXI_ATC_AWCACHE;
+wire [3:0] S_AXI_ATC_AWLEN;
+wire [3:0] S_AXI_ATC_AWQOS;  
+wire [1:0] S_AXI_ATC_ARBURST;
+wire [1:0] S_AXI_ATC_ARLOCK;
+wire [2:0] S_AXI_ATC_ARSIZE;
+wire [1:0] S_AXI_ATC_AWBURST;
+wire [1:0] S_AXI_ATC_AWLOCK;
+wire [2:0] S_AXI_ATC_AWSIZE;
+wire [4:0] S_AXI_ATC_ARUSER;
+wire [4:0] S_AXI_ATC_AWUSER;
+wire [63:0] S_AXI_ATC_WDATA;
+wire [7:0] S_AXI_ATC_WSTRB;  
+
+
+wire SAXIACPARVALID_W;
+wire SAXIACPAWVALID_W;
+wire SAXIACPBREADY_W;
+wire SAXIACPRREADY_W;
+wire SAXIACPWLAST_W;
+wire SAXIACPWVALID_W;
+wire [2:0] SAXIACPARPROT_W;
+wire [2:0] SAXIACPAWPROT_W;
+wire [31:0] SAXIACPARADDR_W;
+wire [31:0] SAXIACPAWADDR_W;
+wire [3:0] SAXIACPARCACHE_W;
+wire [3:0] SAXIACPARLEN_W;
+wire [3:0] SAXIACPARQOS_W;
+wire [3:0] SAXIACPAWCACHE_W;
+wire [3:0] SAXIACPAWLEN_W;
+wire [3:0] SAXIACPAWQOS_W;  
+wire [1:0] SAXIACPARBURST_W;
+wire [1:0] SAXIACPARLOCK_W;
+wire [2:0] SAXIACPARSIZE_W;
+wire [1:0] SAXIACPAWBURST_W;
+wire [1:0] SAXIACPAWLOCK_W;
+wire [2:0] SAXIACPAWSIZE_W;
+wire [4:0] SAXIACPARUSER_W;
+wire [4:0] SAXIACPAWUSER_W;
+wire [63:0] SAXIACPWDATA_W;
+wire [7:0] SAXIACPWSTRB_W;
+
+// AxUSER signal update
+wire [4:0] param_aruser;
+wire [4:0] param_awuser;
+
+// Added to address CR 651751
+wire [3:0]   fclk_clktrig_gnd = 4'h0;
+
+
+wire [19:0]   irq_f2p_i;
+wire [15:0]   irq_f2p_null = 16'h0000;
+
+// EMIO I2C0
+wire          I2C0_SDA_T_n;
+wire          I2C0_SCL_T_n;
+// EMIO I2C1
+wire          I2C1_SDA_T_n;
+wire          I2C1_SCL_T_n;
+// EMIO SPI0
+wire          SPI0_SCLK_T_n;
+wire          SPI0_MOSI_T_n;
+wire          SPI0_MISO_T_n;
+wire          SPI0_SS_T_n;
+// EMIO SPI1
+wire          SPI1_SCLK_T_n;
+wire          SPI1_MOSI_T_n;
+wire          SPI1_MISO_T_n;
+wire          SPI1_SS_T_n;
+
+// EMIO GEM0
+wire          ENET0_MDIO_T_n;
+
+// EMIO GEM1
+wire          ENET1_MDIO_T_n;
+
+// EMIO GPIO
+wire  [(C_EMIO_GPIO_WIDTH-1):0]        GPIO_T_n;
+
+wire [63:0]   gpio_out_t_n;
+wire [63:0]   gpio_out;
+wire [63:0]   gpio_in63_0;
+
+//For Clock buffering
+wire    [3:0] FCLK_CLK_unbuffered;
+wire    [3:0] FCLK_CLK_buffered;
+wire   		  FCLK_CLK0_temp;
+
+// EMIO PJTAG
+wire          PJTAG_TDO_O;
+wire          PJTAG_TDO_T;
+wire          PJTAG_TDO_T_n;
+
+// EMIO SDIO0
+wire          SDIO0_CMD_T_n;
+wire [3:0]    SDIO0_DATA_T_n;
+
+// EMIO SDIO1
+wire          SDIO1_CMD_T_n;
+wire [3:0]    SDIO1_DATA_T_n;
+
+// buffered IO
+wire  [C_MIO_PRIMITIVE - 1:0]  buffered_MIO;
+wire  buffered_DDR_WEB;
+wire  buffered_DDR_CAS_n;
+wire  buffered_DDR_CKE;
+wire  buffered_DDR_Clk_n;
+wire  buffered_DDR_Clk;
+wire  buffered_DDR_CS_n; 
+wire  buffered_DDR_DRSTB;  
+wire  buffered_DDR_ODT;
+wire  buffered_DDR_RAS_n;
+wire  [2:0]  buffered_DDR_BankAddr; 
+wire  [14:0]  buffered_DDR_Addr;
+  
+wire  buffered_DDR_VRN;
+wire  buffered_DDR_VRP;
+wire  [C_DM_WIDTH - 1:0]  buffered_DDR_DM;  
+wire  [C_DQ_WIDTH - 1:0]  buffered_DDR_DQ;
+wire  [C_DQS_WIDTH -1:0]  buffered_DDR_DQS_n;
+wire  [C_DQS_WIDTH - 1:0]  buffered_DDR_DQS;
+  
+wire  buffered_PS_SRSTB; 
+wire  buffered_PS_CLK;
+wire  buffered_PS_PORB;
+
+wire S_AXI_HP0_ACLK_temp;
+wire S_AXI_HP1_ACLK_temp;
+wire S_AXI_HP2_ACLK_temp;
+wire S_AXI_HP3_ACLK_temp;
+wire M_AXI_GP0_ACLK_temp;
+wire M_AXI_GP1_ACLK_temp;
+wire S_AXI_GP0_ACLK_temp;
+wire S_AXI_GP1_ACLK_temp;
+wire S_AXI_ACP_ACLK_temp;
+
+wire [31:0] TRACE_DATA_i;
+wire TRACE_CTL_i;
+(* keep = "true" *) reg   TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
+(* keep = "true" *) reg   [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
+
+// fixed CR #665394
+integer j;
+generate
+  if (C_EN_EMIO_TRACE == 1) begin 
+    always @(posedge TRACE_CLK) 
+    begin
+	  TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
+	  TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
+	  for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
+		TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
+		TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
+      end
+	  TRACE_CLK_OUT  <= ~TRACE_CLK_OUT;
+	end
+  end	
+else
+begin
+always @*
+begin
+TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
+  TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; 
+  for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
+  TRACE_CTL_PIPE[j-1] <= 1'b0;
+		TRACE_DATA_PIPE[j-1] <= 1'b0;
+		end
+  TRACE_CLK_OUT  <= 1'b0; 
+  end
+end
+endgenerate
+
+assign TRACE_CTL = TRACE_CTL_PIPE[0];
+
+assign TRACE_DATA = TRACE_DATA_PIPE[0];
+
+//irq_p2f
+
+// Updated IRQ_F2P logic to address CR 641523
+generate 
+  if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
+  end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
+  end else begin : irq_f2p_select
+	if (C_IRQ_F2P_MODE == "DIRECT") begin
+    assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
+				irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
+				IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
+	end else begin
+	assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
+				IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
+				irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
+	end
+  end
+endgenerate
+
+assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
+assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
+assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
+assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
+
+
+
+// Compress Function
+
+   
+// Modified as per CR 631955   
+//function [11:0] uncompress_id; 
+//   input [5:0] id; 
+//      begin 
+//         case (id[5:0]) 
+//            // dmac0 
+//            6'd1 : uncompress_id = 12'b010000_1000_00 ; 
+//            6'd2 : uncompress_id = 12'b010000_0000_00 ; 
+//            6'd3 : uncompress_id = 12'b010000_0001_00 ; 
+//            6'd4 : uncompress_id = 12'b010000_0010_00 ; 
+//            6'd5 : uncompress_id = 12'b010000_0011_00 ; 
+//            6'd6 : uncompress_id = 12'b010000_0100_00 ; 
+//            6'd7 : uncompress_id = 12'b010000_0101_00 ; 
+//            6'd8 : uncompress_id = 12'b010000_0110_00 ; 
+//            6'd9 : uncompress_id = 12'b010000_0111_00 ; 
+//            // ioum 
+//            6'd10 : uncompress_id = 12'b0100000_000_01 ; 
+//            6'd11 : uncompress_id = 12'b0100000_001_01 ; 
+//            6'd12 : uncompress_id = 12'b0100000_010_01 ; 
+//            6'd13 : uncompress_id = 12'b0100000_011_01 ; 
+//            6'd14 : uncompress_id = 12'b0100000_100_01 ; 
+//            6'd15 : uncompress_id = 12'b0100000_101_01 ; 
+//            // devci 
+//            6'd16 : uncompress_id = 12'b1000_0000_0000 ; 
+//            // dap 
+//            6'd17 : uncompress_id = 12'b1000_0000_0001 ; 
+//            // l2m1 (CPU000) 
+//            6'd18 : uncompress_id = 12'b11_000_000_00_00 ; 
+//            6'd19 : uncompress_id = 12'b11_010_000_00_00 ; 
+//            6'd20 : uncompress_id = 12'b11_011_000_00_00 ; 
+//            6'd21 : uncompress_id = 12'b11_100_000_00_00 ; 
+//            6'd22 : uncompress_id = 12'b11_101_000_00_00 ; 
+//            6'd23 : uncompress_id = 12'b11_110_000_00_00 ; 
+//            6'd24 : uncompress_id = 12'b11_111_000_00_00 ; 
+//            // l2m1 (CPU001) 
+//            6'd25 : uncompress_id = 12'b11_000_001_00_00 ; 
+//            6'd26 : uncompress_id = 12'b11_010_001_00_00 ; 
+//            6'd27 : uncompress_id = 12'b11_011_001_00_00 ; 
+//            6'd28 : uncompress_id = 12'b11_100_001_00_00 ; 
+//            6'd29 : uncompress_id = 12'b11_101_001_00_00 ; 
+//            6'd30 : uncompress_id = 12'b11_110_001_00_00 ; 
+//            6'd31 : uncompress_id = 12'b11_111_001_00_00 ; 
+//            // l2m1 (L2CC) 
+//            6'd32 : uncompress_id = 12'b11_000_00101_00 ; 
+//            6'd33 : uncompress_id = 12'b11_000_01001_00 ; 
+//            6'd34 : uncompress_id = 12'b11_000_01101_00 ; 
+//            6'd35 : uncompress_id = 12'b11_000_10011_00 ; 
+//            6'd36 : uncompress_id = 12'b11_000_10111_00 ; 
+//            6'd37 : uncompress_id = 12'b11_000_11011_00 ; 
+//            6'd38 : uncompress_id = 12'b11_000_11111_00 ; 
+//            6'd39 : uncompress_id = 12'b11_000_00011_00 ; 
+//            6'd40 : uncompress_id = 12'b11_000_00111_00 ; 
+//            6'd41 : uncompress_id = 12'b11_000_01011_00 ; 
+//            6'd42 : uncompress_id = 12'b11_000_01111_00 ; 
+//            6'd43 : uncompress_id = 12'b11_000_00001_00 ; 
+//            // l2m1 (ACP) 
+//            6'd44 : uncompress_id = 12'b11_000_10000_00 ; 
+//            6'd45 : uncompress_id = 12'b11_001_10000_00 ; 
+//            6'd46 : uncompress_id = 12'b11_010_10000_00 ; 
+//            6'd47 : uncompress_id = 12'b11_011_10000_00 ; 
+//            6'd48 : uncompress_id = 12'b11_100_10000_00 ; 
+//            6'd49 : uncompress_id = 12'b11_101_10000_00 ; 
+//            6'd50 : uncompress_id = 12'b11_110_10000_00 ; 
+//            6'd51 : uncompress_id = 12'b11_111_10000_00 ; 
+//         default : uncompress_id = ~0; 
+//      endcase 
+//   end 
+//endfunction 
+// 
+//function [5:0] compress_id; 
+//   input [11:0] id; 
+//      begin 
+//         case (id[11:0]) 
+//         // dmac0 
+//            12'b010000_1000_00 : compress_id = 'd1 ; 
+//            12'b010000_0000_00 : compress_id = 'd2 ; 
+//            12'b010000_0001_00 : compress_id = 'd3 ; 
+//            12'b010000_0010_00 : compress_id = 'd4 ; 
+//            12'b010000_0011_00 : compress_id = 'd5 ; 
+//            12'b010000_0100_00 : compress_id = 'd6 ; 
+//            12'b010000_0101_00 : compress_id = 'd7 ; 
+//            12'b010000_0110_00 : compress_id = 'd8 ; 
+//            12'b010000_0111_00 : compress_id = 'd9 ; 
+//            // ioum 
+//            12'b0100000_000_01 : compress_id = 'd10 ; 
+//            12'b0100000_001_01 : compress_id = 'd11 ; 
+//            12'b0100000_010_01 : compress_id = 'd12 ; 
+//            12'b0100000_011_01 : compress_id = 'd13 ; 
+//            12'b0100000_100_01 : compress_id = 'd14 ; 
+//            12'b0100000_101_01 : compress_id = 'd15 ; 
+//            // devci 
+//            12'b1000_0000_0000 : compress_id = 'd16 ; 
+//            // dap 
+//            12'b1000_0000_0001 : compress_id = 'd17 ; 
+//            // l2m1 (CPU000) 
+//            12'b11_000_000_00_00 : compress_id = 'd18 ; 
+//            12'b11_010_000_00_00 : compress_id = 'd19 ; 
+//            12'b11_011_000_00_00 : compress_id = 'd20 ; 
+//            12'b11_100_000_00_00 : compress_id = 'd21 ; 
+//            12'b11_101_000_00_00 : compress_id = 'd22 ; 
+//            12'b11_110_000_00_00 : compress_id = 'd23 ; 
+//            12'b11_111_000_00_00 : compress_id = 'd24 ; 
+//            // l2m1 (CPU001) 
+//            12'b11_000_001_00_00 : compress_id = 'd25 ; 
+//            12'b11_010_001_00_00 : compress_id = 'd26 ; 
+//            12'b11_011_001_00_00 : compress_id = 'd27 ; 
+//            12'b11_100_001_00_00 : compress_id = 'd28 ; 
+//            12'b11_101_001_00_00 : compress_id = 'd29 ; 
+//            12'b11_110_001_00_00 : compress_id = 'd30 ; 
+//            12'b11_111_001_00_00 : compress_id = 'd31 ; 
+//            // l2m1 (L2CC) 
+//            12'b11_000_00101_00 : compress_id = 'd32 ; 
+//            12'b11_000_01001_00 : compress_id = 'd33 ; 
+//            12'b11_000_01101_00 : compress_id = 'd34 ; 
+//            12'b11_000_10011_00 : compress_id = 'd35 ; 
+//            12'b11_000_10111_00 : compress_id = 'd36 ; 
+//            12'b11_000_11011_00 : compress_id = 'd37 ; 
+//            12'b11_000_11111_00 : compress_id = 'd38 ; 
+//            12'b11_000_00011_00 : compress_id = 'd39 ; 
+//            12'b11_000_00111_00 : compress_id = 'd40 ; 
+//            12'b11_000_01011_00 : compress_id = 'd41 ; 
+//            12'b11_000_01111_00 : compress_id = 'd42 ; 
+//            12'b11_000_00001_00 : compress_id = 'd43 ; 
+//            // l2m1 (ACP) 
+//            12'b11_000_10000_00 : compress_id = 'd44 ; 
+//            12'b11_001_10000_00 : compress_id = 'd45 ; 
+//            12'b11_010_10000_00 : compress_id = 'd46 ; 
+//            12'b11_011_10000_00 : compress_id = 'd47 ; 
+//            12'b11_100_10000_00 : compress_id = 'd48 ; 
+//            12'b11_101_10000_00 : compress_id = 'd49 ; 
+//            12'b11_110_10000_00 : compress_id = 'd50 ; 
+//            12'b11_111_10000_00 : compress_id = 'd51 ; 
+//         default: compress_id = ~0; 
+//      endcase 
+//   end 
+//endfunction 
+
+// Modified as per CR 648393
+
+	function [5:0] compress_id; 
+		input [11:0] id; 
+			begin 
+				compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]); 
+				compress_id[1] = id[8] | id[5] | (~id[11] & id[3]); 
+				compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]); 
+				compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]); 
+				compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]); 
+				compress_id[5] = id[11] & id[10] & ~id[3]; 
+			end 
+	endfunction 
+
+	function [11:0] uncompress_id; 
+		input [5:0] id; 
+			begin 
+				case (id[5:0]) 
+					// dmac0 
+					6'b000_010 : uncompress_id = 12'b010000_1000_00 ; 
+					6'b001_000 : uncompress_id = 12'b010000_0000_00 ; 
+					6'b001_001 : uncompress_id = 12'b010000_0001_00 ; 
+					6'b001_010 : uncompress_id = 12'b010000_0010_00 ; 
+					6'b001_011 : uncompress_id = 12'b010000_0011_00 ; 
+					6'b001_100 : uncompress_id = 12'b010000_0100_00 ; 
+					6'b001_101 : uncompress_id = 12'b010000_0101_00 ; 
+					6'b001_110 : uncompress_id = 12'b010000_0110_00 ; 
+					6'b001_111 : uncompress_id = 12'b010000_0111_00 ; 
+					// ioum 
+					6'b010_000 : uncompress_id = 12'b0100000_000_01 ; 
+					6'b010_001 : uncompress_id = 12'b0100000_001_01 ; 
+					6'b010_010 : uncompress_id = 12'b0100000_010_01 ; 
+					6'b010_011 : uncompress_id = 12'b0100000_011_01 ; 
+					6'b010_100 : uncompress_id = 12'b0100000_100_01 ; 
+					6'b010_101 : uncompress_id = 12'b0100000_101_01 ; 
+					// devci 
+					6'b000_000 : uncompress_id = 12'b1000_0000_0000 ; 
+					// dap 
+					6'b000_001 : uncompress_id = 12'b1000_0000_0001 ; 
+					// l2m1 (CPU000) 
+					6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ; 
+					6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ; 
+					6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ; 
+					6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ; 
+					6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ; 
+					6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ; 
+					6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ; 
+					// l2m1 (CPU001) 
+					6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ; 
+					6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ; 
+					6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ; 
+					6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ; 
+					6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ; 
+					6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ; 
+					6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ; 
+					// l2m1 (L2CC) 
+					6'b101_001 : uncompress_id = 12'b11_000_00101_00 ; 
+					6'b101_010 : uncompress_id = 12'b11_000_01001_00 ; 
+					6'b101_011 : uncompress_id = 12'b11_000_01101_00 ; 
+					6'b011_100 : uncompress_id = 12'b11_000_10011_00 ; 
+					6'b011_101 : uncompress_id = 12'b11_000_10111_00 ; 
+					6'b011_110 : uncompress_id = 12'b11_000_11011_00 ; 
+					6'b011_111 : uncompress_id = 12'b11_000_11111_00 ; 
+					6'b011_000 : uncompress_id = 12'b11_000_00011_00 ; 
+					6'b011_001 : uncompress_id = 12'b11_000_00111_00 ; 
+					6'b011_010 : uncompress_id = 12'b11_000_01011_00 ; 
+					6'b011_011 : uncompress_id = 12'b11_000_01111_00 ; 
+					6'b101_000 : uncompress_id = 12'b11_000_00001_00 ; 
+					// l2m1 (ACP) 
+					6'b100_000 : uncompress_id = 12'b11_000_10000_00 ; 
+					6'b100_001 : uncompress_id = 12'b11_001_10000_00 ; 
+					6'b100_010 : uncompress_id = 12'b11_010_10000_00 ; 
+					6'b100_011 : uncompress_id = 12'b11_011_10000_00 ; 
+					6'b100_100 : uncompress_id = 12'b11_100_10000_00 ; 
+					6'b100_101 : uncompress_id = 12'b11_101_10000_00 ; 
+					6'b100_110 : uncompress_id = 12'b11_110_10000_00 ; 
+					6'b100_111 : uncompress_id = 12'b11_111_10000_00 ; 
+					default : uncompress_id = 12'hx ; 
+				endcase 
+			end 
+	endfunction
+
+   
+// Static Remap logic Enablement and Disablement for C_M_AXI0 port
+        
+        assign M_AXI_GP0_AWID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
+        assign M_AXI_GP0_WID         = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL)  : M_AXI_GP0_WID_FULL;   
+        assign M_AXI_GP0_ARID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;      
+        assign M_AXI_GP0_BID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID)     : M_AXI_GP0_BID;
+        assign M_AXI_GP0_RID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID)     : M_AXI_GP0_RID;      
+
+  // Static Remap logic Enablement and Disablement for C_M_AXI1 port   
+
+        assign M_AXI_GP1_AWID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
+        assign M_AXI_GP1_WID         = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL)  : M_AXI_GP1_WID_FULL;   
+        assign M_AXI_GP1_ARID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;      
+        assign M_AXI_GP1_BID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID)     : M_AXI_GP1_BID;
+        assign M_AXI_GP1_RID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID)     : M_AXI_GP1_RID;      
+
+
+//// Compress_id and uncompress_id has been removed to address CR 642527
+//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
+//        assign M_AXI_GP0_AWID        =  M_AXI_GP0_AWID_FULL;
+//        assign M_AXI_GP0_WID         =  M_AXI_GP0_WID_FULL;   
+//        assign M_AXI_GP0_ARID        =  M_AXI_GP0_ARID_FULL;      
+//        assign M_AXI_GP0_BID_FULL    =  M_AXI_GP0_BID;
+//        assign M_AXI_GP0_RID_FULL    =  M_AXI_GP0_RID;      
+//
+//        assign M_AXI_GP1_AWID        =  M_AXI_GP1_AWID_FULL;
+//        assign M_AXI_GP1_WID         =  M_AXI_GP1_WID_FULL;   
+//        assign M_AXI_GP1_ARID        =  M_AXI_GP1_ARID_FULL;      
+//        assign M_AXI_GP1_BID_FULL    =  M_AXI_GP1_BID;
+//        assign M_AXI_GP1_RID_FULL    =  M_AXI_GP1_RID;      
+						  
+  
+// Pipeline Stage for ENET0
+	
+generate
+  if (C_EN_EMIO_ENET0 == 1) begin
+  always @(posedge ENET0_GMII_TX_CLK)
+  begin
+      ENET0_GMII_TXD    <= ENET0_GMII_TXD_i;
+      ENET0_GMII_TX_EN  <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
+	  ENET0_GMII_TX_ER  <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
+      ENET0_GMII_COL_i  <= ENET0_GMII_COL;
+      ENET0_GMII_CRS_i  <= ENET0_GMII_CRS;
+    end
+	end
+	else
+	always@*
+	 begin
+	  ENET0_GMII_TXD    <= 'b0;//ENET0_GMII_TXD_i;
+      ENET0_GMII_TX_EN  <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
+	  ENET0_GMII_TX_ER  <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
+	  ENET0_GMII_COL_i <= 'b0;
+	  ENET0_GMII_CRS_i <= 'b0;
+	 end  
+endgenerate
+  
+generate
+  if (C_EN_EMIO_ENET0 == 1) begin 
+    always @(posedge ENET0_GMII_RX_CLK) 
+    begin
+      ENET0_GMII_RXD_i    <= ENET0_GMII_RXD;
+      ENET0_GMII_RX_DV_i  <= ENET0_GMII_RX_DV;
+      ENET0_GMII_RX_ER_i  <= ENET0_GMII_RX_ER;
+    end
+  end
+	else
+	begin
+	always @*
+	begin
+	ENET0_GMII_RXD_i    <= 0;
+   ENET0_GMII_RX_DV_i  <= 0;
+    ENET0_GMII_RX_ER_i  <= 0;
+	end
+	end
+endgenerate
+
+// Pipeline Stage for ENET1
+	
+generate
+  if (C_EN_EMIO_ENET1 == 1) begin 
+    always @(posedge ENET1_GMII_TX_CLK) 
+    begin
+      ENET1_GMII_TXD    <= ENET1_GMII_TXD_i;
+      ENET1_GMII_TX_EN  <= ENET1_GMII_TX_EN_i;
+      ENET1_GMII_TX_ER  <= ENET1_GMII_TX_ER_i;
+      ENET1_GMII_COL_i  <= ENET1_GMII_COL;
+      ENET1_GMII_CRS_i  <= ENET1_GMII_CRS;
+    end
+  end
+  else
+  begin
+  always@*
+	 begin
+	  ENET1_GMII_TXD    <= 'b0;//ENET0_GMII_TXD_i;
+      ENET1_GMII_TX_EN  <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
+	  ENET1_GMII_TX_ER  <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
+	  ENET1_GMII_COL_i <= 0;
+	  ENET1_GMII_CRS_i <= 0;
+	 end  
+  end
+endgenerate
+   
+generate	
+  if (C_EN_EMIO_ENET1 == 1) begin 
+    always @(posedge ENET1_GMII_RX_CLK) 
+    begin
+      ENET1_GMII_RXD_i    <= ENET1_GMII_RXD;
+      ENET1_GMII_RX_DV_i  <= ENET1_GMII_RX_DV;
+      ENET1_GMII_RX_ER_i  <= ENET1_GMII_RX_ER;
+    end
+  end	
+else
+	begin
+	always @*
+	begin
+	ENET1_GMII_RXD_i    <= 'b0;
+   ENET1_GMII_RX_DV_i  <= 'b0;
+  ENET1_GMII_RX_ER_i  <= 'b0;
+	end
+	end  
+endgenerate   
+   
+// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
+
+generate
+  if (C_EN_EMIO_TRACE == 1)  begin
+    if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
+        
+      // Pipeline Stage for Traceport ATID
+      always @(posedge FTMD_TRACEIN_CLK) 
+      begin
+       	FTMD_TRACEIN_DATA_notracebuf    <= FTMD_TRACEIN_DATA;
+        FTMD_TRACEIN_VALID_notracebuf   <= FTMD_TRACEIN_VALID;
+	FTMD_TRACEIN_ATID_notracebuf    <= FTMD_TRACEIN_ATID;
+      end
+
+      assign FTMD_TRACEIN_DATA_i   = FTMD_TRACEIN_DATA_notracebuf;
+      assign FTMD_TRACEIN_VALID_i  = FTMD_TRACEIN_VALID_notracebuf;
+      assign FTMD_TRACEIN_ATID_i   = FTMD_TRACEIN_ATID_notracebuf;
+
+    end else begin : gen_trace_buffer
+    
+      processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
+      .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
+      .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
+       )
+      trace_buffer_i (
+        .TRACE_CLK(FTMD_TRACEIN_CLK), 
+        .RST(~FCLK_RESET0_N), 
+        .TRACE_VALID_IN(FTMD_TRACEIN_VALID), 
+        .TRACE_DATA_IN(FTMD_TRACEIN_DATA), 
+        .TRACE_ATID_IN(FTMD_TRACEIN_ATID), 
+        .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf), 
+        .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf), 
+        .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
+      );
+
+      assign FTMD_TRACEIN_DATA_i   = FTMD_TRACEIN_DATA_tracebuf;
+      assign FTMD_TRACEIN_VALID_i  = FTMD_TRACEIN_VALID_tracebuf;
+      assign FTMD_TRACEIN_ATID_i   = FTMD_TRACEIN_ATID_tracebuf;
+ 
+    end
+  end
+  else
+  begin
+  assign FTMD_TRACEIN_DATA_i   = 1'b0;
+      assign FTMD_TRACEIN_VALID_i  = 1'b0;
+      assign FTMD_TRACEIN_ATID_i   = 1'b0;
+	  end
+endgenerate
+  
+   
+   // ID Width Control on AXI Slave ports
+   // S_AXI_GP0
+   
+     function [5:0] id_in_gp0;
+       input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
+     begin
+        case (C_S_AXI_GP0_ID_WIDTH)
+              1:  id_in_gp0  = {5'b0, axi_id_gp0_in};
+              2:  id_in_gp0  = {4'b0, axi_id_gp0_in};
+              3:  id_in_gp0  = {3'b0, axi_id_gp0_in};
+              4:  id_in_gp0  = {2'b0, axi_id_gp0_in};
+              5:  id_in_gp0  = {1'b0, axi_id_gp0_in};
+              6:  id_in_gp0  = axi_id_gp0_in;    
+              default : id_in_gp0 =  axi_id_gp0_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
+    assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
+    assign S_AXI_GP0_WID_in  = id_in_gp0(S_AXI_GP0_WID);
+
+     function [5:0] id_out_gp0;
+       input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
+     begin
+        case (C_S_AXI_GP0_ID_WIDTH)
+              1:  id_out_gp0  = axi_id_gp0_out[0];
+              2:  id_out_gp0  = axi_id_gp0_out[1:0];
+              3:  id_out_gp0  = axi_id_gp0_out[2:0];
+              4:  id_out_gp0  = axi_id_gp0_out[3:0];
+              5:  id_out_gp0  = axi_id_gp0_out[4:0];
+              6:  id_out_gp0  = axi_id_gp0_out;    
+              default : id_out_gp0 =  axi_id_gp0_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_GP0_BID     = id_out_gp0(S_AXI_GP0_BID_out);
+    assign S_AXI_GP0_RID     = id_out_gp0(S_AXI_GP0_RID_out);    
+   
+   // S_AXI_GP1
+   
+     function [5:0] id_in_gp1;
+       input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
+     begin
+        case (C_S_AXI_GP1_ID_WIDTH)
+              1:  id_in_gp1  = {5'b0, axi_id_gp1_in};
+              2:  id_in_gp1  = {4'b0, axi_id_gp1_in};
+              3:  id_in_gp1  = {3'b0, axi_id_gp1_in};
+              4:  id_in_gp1  = {2'b0, axi_id_gp1_in};
+              5:  id_in_gp1  = {1'b0, axi_id_gp1_in};
+              6:  id_in_gp1  = axi_id_gp1_in;    
+              default : id_in_gp1 =  axi_id_gp1_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
+    assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
+    assign S_AXI_GP1_WID_in  = id_in_gp1(S_AXI_GP1_WID);
+
+     function [5:0] id_out_gp1;
+       input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
+     begin
+        case (C_S_AXI_GP1_ID_WIDTH)
+              1:  id_out_gp1  = axi_id_gp1_out[0];
+              2:  id_out_gp1  = axi_id_gp1_out[1:0];
+              3:  id_out_gp1  = axi_id_gp1_out[2:0];
+              4:  id_out_gp1  = axi_id_gp1_out[3:0];
+              5:  id_out_gp1  = axi_id_gp1_out[4:0];
+              6:  id_out_gp1  = axi_id_gp1_out;    
+              default : id_out_gp1 =  axi_id_gp1_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_GP1_BID     = id_out_gp1(S_AXI_GP1_BID_out);
+    assign S_AXI_GP1_RID     = id_out_gp1(S_AXI_GP1_RID_out);    
+    
+// S_AXI_HP0    
+    
+     function [5:0] id_in_hp0;
+       input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
+     begin
+        case (C_S_AXI_HP0_ID_WIDTH)
+              1:  id_in_hp0  = {5'b0, axi_id_hp0_in};
+              2:  id_in_hp0  = {4'b0, axi_id_hp0_in};
+              3:  id_in_hp0  = {3'b0, axi_id_hp0_in};
+              4:  id_in_hp0  = {2'b0, axi_id_hp0_in};
+              5:  id_in_hp0  = {1'b0, axi_id_hp0_in};
+              6:  id_in_hp0  = axi_id_hp0_in;    
+              default : id_in_hp0 =  axi_id_hp0_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
+    assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
+    assign S_AXI_HP0_WID_in  = id_in_hp0(S_AXI_HP0_WID);
+
+     function [5:0] id_out_hp0;
+       input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
+     begin
+        case (C_S_AXI_HP0_ID_WIDTH)
+              1:  id_out_hp0  = axi_id_hp0_out[0];
+              2:  id_out_hp0  = axi_id_hp0_out[1:0];
+              3:  id_out_hp0  = axi_id_hp0_out[2:0];
+              4:  id_out_hp0  = axi_id_hp0_out[3:0];
+              5:  id_out_hp0  = axi_id_hp0_out[4:0];
+              6:  id_out_hp0  = axi_id_hp0_out;    
+              default : id_out_hp0 =  axi_id_hp0_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP0_BID     = id_out_hp0(S_AXI_HP0_BID_out);
+    assign S_AXI_HP0_RID     = id_out_hp0(S_AXI_HP0_RID_out);  
+    
+    assign S_AXI_HP0_WDATA_in        = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
+    assign S_AXI_HP0_WSTRB_in        = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};       
+    assign S_AXI_HP0_RDATA           = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
+    
+// S_AXI_HP1    
+
+     function [5:0] id_in_hp1;
+       input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
+     begin
+        case (C_S_AXI_HP1_ID_WIDTH)
+              1:  id_in_hp1  = {5'b0, axi_id_hp1_in};
+              2:  id_in_hp1  = {4'b0, axi_id_hp1_in};
+              3:  id_in_hp1  = {3'b0, axi_id_hp1_in};
+              4:  id_in_hp1  = {2'b0, axi_id_hp1_in};
+              5:  id_in_hp1  = {1'b0, axi_id_hp1_in};
+              6:  id_in_hp1  = axi_id_hp1_in;    
+              default : id_in_hp1 =  axi_id_hp1_in;
+        endcase
+     end
+     endfunction
+     
+     
+
+    assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
+    assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
+    assign S_AXI_HP1_WID_in  = id_in_hp1(S_AXI_HP1_WID);
+
+     function [5:0] id_out_hp1;
+       input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
+     begin
+        case (C_S_AXI_HP1_ID_WIDTH)
+              1:  id_out_hp1  = axi_id_hp1_out[0];
+              2:  id_out_hp1  = axi_id_hp1_out[1:0];
+              3:  id_out_hp1  = axi_id_hp1_out[2:0];
+              4:  id_out_hp1  = axi_id_hp1_out[3:0];
+              5:  id_out_hp1  = axi_id_hp1_out[4:0];
+              6:  id_out_hp1  = axi_id_hp1_out;    
+              default : id_out_hp1 =  axi_id_hp1_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP1_BID     = id_out_hp1(S_AXI_HP1_BID_out);
+    assign S_AXI_HP1_RID     = id_out_hp1(S_AXI_HP1_RID_out); 
+    
+    assign S_AXI_HP1_WDATA_in        = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
+    assign S_AXI_HP1_WSTRB_in        = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};       
+    assign S_AXI_HP1_RDATA           = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
+    
+    
+// S_AXI_HP2    
+
+     function [5:0] id_in_hp2;
+       input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
+     begin
+        case (C_S_AXI_HP2_ID_WIDTH)
+              1:  id_in_hp2  = {5'b0, axi_id_hp2_in};
+              2:  id_in_hp2  = {4'b0, axi_id_hp2_in};
+              3:  id_in_hp2  = {3'b0, axi_id_hp2_in};
+              4:  id_in_hp2  = {2'b0, axi_id_hp2_in};
+              5:  id_in_hp2  = {1'b0, axi_id_hp2_in};
+              6:  id_in_hp2  = axi_id_hp2_in;    
+              default : id_in_hp2 =  axi_id_hp2_in;
+        endcase
+     end
+     endfunction
+     
+    assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
+    assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
+    assign S_AXI_HP2_WID_in  = id_in_hp2(S_AXI_HP2_WID);
+ 
+
+     function [5:0] id_out_hp2;
+       input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
+     begin
+        case (C_S_AXI_HP2_ID_WIDTH)
+              1:  id_out_hp2  = axi_id_hp2_out[0];
+              2:  id_out_hp2  = axi_id_hp2_out[1:0];
+              3:  id_out_hp2  = axi_id_hp2_out[2:0];
+              4:  id_out_hp2  = axi_id_hp2_out[3:0];
+              5:  id_out_hp2  = axi_id_hp2_out[4:0];
+              6:  id_out_hp2  = axi_id_hp2_out;    
+              default : id_out_hp2 =  axi_id_hp2_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP2_BID     = id_out_hp2(S_AXI_HP2_BID_out);
+    assign S_AXI_HP2_RID     = id_out_hp2(S_AXI_HP2_RID_out);  
+    
+    assign S_AXI_HP2_WDATA_in        = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
+    assign S_AXI_HP2_WSTRB_in        = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};       
+    assign S_AXI_HP2_RDATA           = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
+    
+    
+// S_AXI_HP3    
+
+     function [5:0] id_in_hp3;
+       input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
+     begin
+        case (C_S_AXI_HP3_ID_WIDTH)
+              1:  id_in_hp3  = {5'b0, axi_id_hp3_in};
+              2:  id_in_hp3  = {4'b0, axi_id_hp3_in};
+              3:  id_in_hp3  = {3'b0, axi_id_hp3_in};
+              4:  id_in_hp3  = {2'b0, axi_id_hp3_in};
+              5:  id_in_hp3  = {1'b0, axi_id_hp3_in};
+              6:  id_in_hp3  = axi_id_hp3_in;    
+              default : id_in_hp3 =  axi_id_hp3_in;
+        endcase
+     end
+     endfunction
+     
+    assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
+    assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
+    assign S_AXI_HP3_WID_in  = id_in_hp3(S_AXI_HP3_WID);
+     
+
+
+     function [5:0] id_out_hp3;
+       input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
+     begin
+        case (C_S_AXI_HP3_ID_WIDTH)
+              1:  id_out_hp3  = axi_id_hp3_out[0];
+              2:  id_out_hp3  = axi_id_hp3_out[1:0];
+              3:  id_out_hp3  = axi_id_hp3_out[2:0];
+              4:  id_out_hp3  = axi_id_hp3_out[3:0];
+              5:  id_out_hp3  = axi_id_hp3_out[4:0];
+              6:  id_out_hp3  = axi_id_hp3_out;    
+              default : id_out_hp3 =  axi_id_hp3_out;              
+        endcase
+     end
+     endfunction
+    
+    assign S_AXI_HP3_BID     = id_out_hp3(S_AXI_HP3_BID_out);
+    assign S_AXI_HP3_RID     = id_out_hp3(S_AXI_HP3_RID_out); 
+    
+    assign S_AXI_HP3_WDATA_in        = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
+    assign S_AXI_HP3_WSTRB_in        = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};       
+    assign S_AXI_HP3_RDATA           = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
+    
+    
+// S_AXI_ACP    
+
+     function [2:0] id_in_acp;
+       input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
+     begin
+        case (C_S_AXI_ACP_ID_WIDTH)
+              1:  id_in_acp  = {2'b0, axi_id_acp_in};
+              2:  id_in_acp  = {1'b0, axi_id_acp_in};
+              3:  id_in_acp  = axi_id_acp_in;
+              default : id_in_acp =  axi_id_acp_in;
+        endcase
+     end
+     endfunction
+
+    assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
+    assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
+    assign S_AXI_ACP_WID_in  = id_in_acp(SAXIACPWID_W);
+
+     function [2:0] id_out_acp;
+       input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
+     begin
+        case (C_S_AXI_ACP_ID_WIDTH)
+              1:  id_out_acp  = axi_id_acp_out[0];
+              2:  id_out_acp  = axi_id_acp_out[1:0];
+              3:  id_out_acp  = axi_id_acp_out;
+              default : id_out_acp =  axi_id_acp_out;              
+        endcase
+     end
+     endfunction
+    
+    assign SAXIACPBID_W     = id_out_acp(S_AXI_ACP_BID_out);
+    assign SAXIACPRID_W     = id_out_acp(S_AXI_ACP_RID_out);  
+    
+// FMIO Tristate Inversion logic 
+
+//FMIO I2C0
+assign        I2C0_SDA_T  = ~ I2C0_SDA_T_n;
+assign        I2C0_SCL_T  = ~ I2C0_SCL_T_n;
+//FMIO I2C1                     
+assign        I2C1_SDA_T  = ~ I2C1_SDA_T_n;
+assign        I2C1_SCL_T  = ~ I2C1_SCL_T_n;
+//FMIO SPI0             
+assign        SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
+assign        SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
+assign        SPI0_MISO_T = ~ SPI0_MISO_T_n;
+assign        SPI0_SS_T   = ~ SPI0_SS_T_n;
+//FMIO SPI1             
+assign        SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
+assign        SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
+assign        SPI1_MISO_T = ~ SPI1_MISO_T_n;
+assign        SPI1_SS_T   = ~ SPI1_SS_T_n;
+
+
+
+// EMIO GEM0 MDIO
+assign        ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
+    
+// EMIO GEM1 MDIO
+assign        ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
+
+// EMIO GPIO
+assign        GPIO_T = ~ GPIO_T_n;
+
+// EMIO GPIO Width Control 
+
+  function [63:0] gpio_width_adjust_in;
+    input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
+  begin
+     case (C_EMIO_GPIO_WIDTH)
+           1:  gpio_width_adjust_in   = {63'b0, gpio_in};
+           2:  gpio_width_adjust_in   = {62'b0, gpio_in};
+           3:  gpio_width_adjust_in   = {61'b0, gpio_in};
+           4:  gpio_width_adjust_in   = {60'b0, gpio_in};
+           5:  gpio_width_adjust_in   = {59'b0, gpio_in};
+           6:  gpio_width_adjust_in   = {58'b0, gpio_in};
+           7:  gpio_width_adjust_in   = {57'b0, gpio_in};
+           8:  gpio_width_adjust_in   = {56'b0, gpio_in};
+           9:  gpio_width_adjust_in   = {55'b0, gpio_in};
+           10:  gpio_width_adjust_in  = {54'b0, gpio_in};
+           11:  gpio_width_adjust_in  = {53'b0, gpio_in};
+           12:  gpio_width_adjust_in  = {52'b0, gpio_in};
+           13:  gpio_width_adjust_in  = {51'b0, gpio_in};
+           14:  gpio_width_adjust_in  = {50'b0, gpio_in};
+           15:  gpio_width_adjust_in  = {49'b0, gpio_in};
+           16:  gpio_width_adjust_in  = {48'b0, gpio_in};
+           17:  gpio_width_adjust_in  = {47'b0, gpio_in};
+           18:  gpio_width_adjust_in  = {46'b0, gpio_in};
+           19:  gpio_width_adjust_in  = {45'b0, gpio_in};
+           20:  gpio_width_adjust_in  = {44'b0, gpio_in};
+           21:  gpio_width_adjust_in  = {43'b0, gpio_in};
+           22:  gpio_width_adjust_in  = {42'b0, gpio_in};
+           23:  gpio_width_adjust_in  = {41'b0, gpio_in};
+           24:  gpio_width_adjust_in  = {40'b0, gpio_in};
+           25:  gpio_width_adjust_in  = {39'b0, gpio_in};
+           26:  gpio_width_adjust_in  = {38'b0, gpio_in};
+           27:  gpio_width_adjust_in  = {37'b0, gpio_in};
+           28:  gpio_width_adjust_in  = {36'b0, gpio_in};
+           29:  gpio_width_adjust_in  = {35'b0, gpio_in};
+           30:  gpio_width_adjust_in  = {34'b0, gpio_in};
+           31:  gpio_width_adjust_in  = {33'b0, gpio_in};
+           32:  gpio_width_adjust_in  = {32'b0, gpio_in};
+           33:  gpio_width_adjust_in  = {31'b0, gpio_in};
+           34:  gpio_width_adjust_in  = {30'b0, gpio_in};
+           35:  gpio_width_adjust_in  = {29'b0, gpio_in};
+           36:  gpio_width_adjust_in  = {28'b0, gpio_in};
+           37:  gpio_width_adjust_in  = {27'b0, gpio_in};
+           38:  gpio_width_adjust_in  = {26'b0, gpio_in};
+           39:  gpio_width_adjust_in  = {25'b0, gpio_in};
+           40:  gpio_width_adjust_in  = {24'b0, gpio_in};
+           41:  gpio_width_adjust_in  = {23'b0, gpio_in};
+           42:  gpio_width_adjust_in  = {22'b0, gpio_in};
+           43:  gpio_width_adjust_in  = {21'b0, gpio_in};
+           44:  gpio_width_adjust_in  = {20'b0, gpio_in};
+           45:  gpio_width_adjust_in  = {19'b0, gpio_in};
+           46:  gpio_width_adjust_in  = {18'b0, gpio_in};
+           47:  gpio_width_adjust_in  = {17'b0, gpio_in};
+           48:  gpio_width_adjust_in  = {16'b0, gpio_in};
+           49:  gpio_width_adjust_in  = {15'b0, gpio_in};
+           50:  gpio_width_adjust_in  = {14'b0, gpio_in};
+           51:  gpio_width_adjust_in  = {13'b0, gpio_in};
+           52:  gpio_width_adjust_in  = {12'b0, gpio_in};
+           53:  gpio_width_adjust_in  = {11'b0, gpio_in};
+           54:  gpio_width_adjust_in  = {10'b0, gpio_in};
+           55:  gpio_width_adjust_in  = {9'b0, gpio_in};
+           56:  gpio_width_adjust_in  = {8'b0, gpio_in};
+           57:  gpio_width_adjust_in  = {7'b0, gpio_in};
+           58:  gpio_width_adjust_in  = {6'b0, gpio_in};
+           59:  gpio_width_adjust_in  = {5'b0, gpio_in};
+           60:  gpio_width_adjust_in  = {4'b0, gpio_in};
+           61:  gpio_width_adjust_in  = {3'b0, gpio_in};
+           62:  gpio_width_adjust_in  = {2'b0, gpio_in};
+           63:  gpio_width_adjust_in  = {1'b0, gpio_in};
+           64:  gpio_width_adjust_in  = gpio_in;    
+           default : gpio_width_adjust_in =  gpio_in;
+     endcase
+  end
+  endfunction
+
+ assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
+
+
+  function [63:0] gpio_width_adjust_out;
+    input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
+  begin
+     case (C_EMIO_GPIO_WIDTH)
+           1:  gpio_width_adjust_out    = gpio_o[0];
+           2:  gpio_width_adjust_out    = gpio_o[1:0];
+           3:  gpio_width_adjust_out    = gpio_o[2:0];
+           4:  gpio_width_adjust_out    = gpio_o[3:0];
+           5:  gpio_width_adjust_out    = gpio_o[4:0];
+           6:  gpio_width_adjust_out    = gpio_o[5:0];
+           7:  gpio_width_adjust_out    = gpio_o[6:0];
+           8:  gpio_width_adjust_out    = gpio_o[7:0];
+           9:  gpio_width_adjust_out    = gpio_o[8:0];
+           10: gpio_width_adjust_out    = gpio_o[9:0];
+           11: gpio_width_adjust_out    = gpio_o[10:0];
+           12: gpio_width_adjust_out    = gpio_o[11:0];
+           13: gpio_width_adjust_out    = gpio_o[12:0];
+           14: gpio_width_adjust_out    = gpio_o[13:0];
+           15: gpio_width_adjust_out    = gpio_o[14:0];
+           16: gpio_width_adjust_out    = gpio_o[15:0];
+           17: gpio_width_adjust_out    = gpio_o[16:0];
+           18: gpio_width_adjust_out    = gpio_o[17:0];
+           19: gpio_width_adjust_out    = gpio_o[18:0];
+           20: gpio_width_adjust_out    = gpio_o[19:0];
+           21: gpio_width_adjust_out    = gpio_o[20:0];
+           22: gpio_width_adjust_out    = gpio_o[21:0];
+           23: gpio_width_adjust_out    = gpio_o[22:0];
+           24: gpio_width_adjust_out    = gpio_o[23:0];
+           25: gpio_width_adjust_out    = gpio_o[24:0];
+           26: gpio_width_adjust_out    = gpio_o[25:0];
+           27: gpio_width_adjust_out    = gpio_o[26:0];
+           28: gpio_width_adjust_out    = gpio_o[27:0];
+           29: gpio_width_adjust_out    = gpio_o[28:0];
+           30: gpio_width_adjust_out    = gpio_o[29:0];
+           31: gpio_width_adjust_out    = gpio_o[30:0];
+           32: gpio_width_adjust_out    = gpio_o[31:0];
+           33: gpio_width_adjust_out    = gpio_o[32:0];
+           34: gpio_width_adjust_out    = gpio_o[33:0];
+           35: gpio_width_adjust_out    = gpio_o[34:0];
+           36: gpio_width_adjust_out    = gpio_o[35:0];
+           37: gpio_width_adjust_out    = gpio_o[36:0];
+           38: gpio_width_adjust_out    = gpio_o[37:0];
+           39: gpio_width_adjust_out    = gpio_o[38:0];
+           40: gpio_width_adjust_out    = gpio_o[39:0];
+           41: gpio_width_adjust_out    = gpio_o[40:0];
+           42: gpio_width_adjust_out    = gpio_o[41:0];
+           43: gpio_width_adjust_out    = gpio_o[42:0];
+           44: gpio_width_adjust_out    = gpio_o[43:0];
+           45: gpio_width_adjust_out    = gpio_o[44:0];
+           46: gpio_width_adjust_out    = gpio_o[45:0];
+           47: gpio_width_adjust_out    = gpio_o[46:0];
+           48: gpio_width_adjust_out    = gpio_o[47:0];
+           49: gpio_width_adjust_out    = gpio_o[48:0];
+           50: gpio_width_adjust_out    = gpio_o[49:0];
+           51: gpio_width_adjust_out    = gpio_o[50:0];
+           52: gpio_width_adjust_out    = gpio_o[51:0];
+           53: gpio_width_adjust_out    = gpio_o[52:0];
+           54: gpio_width_adjust_out    = gpio_o[53:0];
+           55: gpio_width_adjust_out    = gpio_o[54:0];
+           56: gpio_width_adjust_out    = gpio_o[55:0];
+           57: gpio_width_adjust_out    = gpio_o[56:0];
+           58: gpio_width_adjust_out    = gpio_o[57:0];
+           59: gpio_width_adjust_out    = gpio_o[58:0];
+           60: gpio_width_adjust_out    = gpio_o[59:0];
+           61: gpio_width_adjust_out    = gpio_o[60:0];
+           62: gpio_width_adjust_out    = gpio_o[61:0];
+           63: gpio_width_adjust_out    = gpio_o[62:0];
+           64: gpio_width_adjust_out    = gpio_o;    
+           default : gpio_width_adjust_out =  gpio_o;
+     endcase
+  end
+  endfunction
+
+ assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0]   = gpio_width_adjust_out(gpio_out);
+ assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
+
+// Adding OBUFT to JTAG out port
+generate
+  if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
+	OBUFT jtag_obuft_inst (
+	.O(PJTAG_TDO),
+	.I(PJTAG_TDO_O),
+	.T(PJTAG_TDO_T)  
+	);
+  end
+  else
+  begin
+  assign PJTAG_TDO = 1'b0;
+  end
+endgenerate
+// -------
+// EMIO PJTAG
+assign        PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
+
+// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of  Silicon,
+// FOR Other SI REV, inversion is required
+ 
+assign        SDIO0_CMD_T       =   (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
+assign        SDIO0_DATA_T[3:0] =   (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
+
+// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of  Silicon,
+// FOR Other SI REV, inversion is required
+assign        SDIO1_CMD_T       =  (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
+assign        SDIO1_DATA_T[3:0] =  (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
+
+// FCLK_CLK optional clock buffers
+
+generate
+   if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
+     BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
+   end
+   if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
+     BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
+   end
+   if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
+     BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
+   end
+   if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
+     BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
+   end
+endgenerate 
+
+assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
+assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
+assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
+assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
+
+assign FCLK_CLK0 = FCLK_CLK0_temp;
+
+// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
+
+BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
+BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
+BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
+BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
+BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
+BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
+BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
+BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
+BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
+BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
+BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
+BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
+BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
+BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
+
+genvar i;
+generate
+	for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
+		BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < 3; i=i+1) begin
+		BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < 15; i=i+1) begin
+		BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < C_DM_WIDTH; i=i+1) begin
+		BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < C_DQ_WIDTH; i=i+1) begin
+		BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < C_DQS_WIDTH; i=i+1) begin
+		BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
+	end
+endgenerate
+
+generate
+	for (i=0; i < C_DQS_WIDTH; i=i+1) begin
+		BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
+	end
+endgenerate
+
+// Connect FCLK in case of disable the AXI port for non Secure Transaction
+//Start
+
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin 
+   assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+  assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin 
+	assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin 
+	assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin 
+	assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
+  end
+endgenerate
+
+//Start
+
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin 
+	assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;  
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin 
+	assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;    
+  end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin 
+	assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;    
+    end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin 
+	assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;      
+   end
+endgenerate
+
+generate
+  if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin 
+	assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
+  end
+  else begin
+	assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;        
+  end
+endgenerate
+
+assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
+assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
+assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
+assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
+
+
+//END
+//====================
+//PSS TOP             
+//====================
+generate 
+if (C_PACKAGE_NAME == "clg225" ) begin
+	wire [21:0] dummy;
+	PS7 PS7_i (
+	  .DMA0DATYPE		   (DMA0_DATYPE ),
+	  .DMA0DAVALID		   (DMA0_DAVALID),
+	  .DMA0DRREADY		   (DMA0_DRREADY),  
+	  .DMA0RSTN		   (DMA0_RSTN   ),  
+	  .DMA1DATYPE		   (DMA1_DATYPE ),
+	  .DMA1DAVALID		   (DMA1_DAVALID),
+	  .DMA1DRREADY		   (DMA1_DRREADY),
+	  .DMA1RSTN		   (DMA1_RSTN   ),
+	  .DMA2DATYPE		   (DMA2_DATYPE ),
+	  .DMA2DAVALID		   (DMA2_DAVALID),
+	  .DMA2DRREADY		   (DMA2_DRREADY),
+	  .DMA2RSTN		   (DMA2_RSTN   ),
+	  .DMA3DATYPE		   (DMA3_DATYPE ),
+	  .DMA3DAVALID		   (DMA3_DAVALID),
+	  .DMA3DRREADY		   (DMA3_DRREADY),
+	  .DMA3RSTN		   (DMA3_RSTN   ),  
+	  .EMIOCAN0PHYTX	   (CAN0_PHY_TX ),
+	  .EMIOCAN1PHYTX	   (CAN1_PHY_TX ),  
+	  .EMIOENET0GMIITXD	  (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
+	  .EMIOENET0GMIITXEN	(ENET0_GMII_TX_EN_i), //   (ENET0_GMII_TX_EN_i),
+	  .EMIOENET0GMIITXER	(ENET0_GMII_TX_ER_i), //   (ENET0_GMII_TX_ER_i),
+	  .EMIOENET0MDIOMDC	   (ENET0_MDIO_MDC),
+	  .EMIOENET0MDIOO	   (ENET0_MDIO_O  ),
+	  .EMIOENET0MDIOTN	   (ENET0_MDIO_T_n  ),
+	  .EMIOENET0PTPDELAYREQRX  (ENET0_PTP_DELAY_REQ_RX),
+	  .EMIOENET0PTPDELAYREQTX  (ENET0_PTP_DELAY_REQ_TX),
+	  .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
+	  .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
+	  .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+	  .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+	  .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
+	  .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
+	  .EMIOENET0SOFRX          (ENET0_SOF_RX),
+	  .EMIOENET0SOFTX          (ENET0_SOF_TX),   
+	  .EMIOENET1GMIITXD	   (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
+	  .EMIOENET1GMIITXEN	(ENET1_GMII_TX_EN_i), //  (ENET1_GMII_TX_EN_i),
+	  .EMIOENET1GMIITXER	(ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
+	  .EMIOENET1MDIOMDC	   (ENET1_MDIO_MDC),
+	  .EMIOENET1MDIOO	   (ENET1_MDIO_O),
+	  .EMIOENET1MDIOTN	   (ENET1_MDIO_T_n),
+	  .EMIOENET1PTPDELAYREQRX  (ENET1_PTP_DELAY_REQ_RX),
+	  .EMIOENET1PTPDELAYREQTX  (ENET1_PTP_DELAY_REQ_TX),
+	  .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
+	  .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
+	  .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+	  .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+	  .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
+	  .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
+	  .EMIOENET1SOFRX          (ENET1_SOF_RX),
+	  .EMIOENET1SOFTX          (ENET1_SOF_TX),  
+	  .EMIOGPIOO	           (gpio_out),
+	  .EMIOGPIOTN	           (gpio_out_t_n),
+	  .EMIOI2C0SCLO            (I2C0_SCL_O),
+	  .EMIOI2C0SCLTN           (I2C0_SCL_T_n),
+	  .EMIOI2C0SDAO	           (I2C0_SDA_O),
+	  .EMIOI2C0SDATN	   (I2C0_SDA_T_n),
+	  .EMIOI2C1SCLO	           (I2C1_SCL_O),
+	  .EMIOI2C1SCLTN           (I2C1_SCL_T_n),
+	  .EMIOI2C1SDAO	           (I2C1_SDA_O),
+	  .EMIOI2C1SDATN	   (I2C1_SDA_T_n),
+	  .EMIOPJTAGTDO  	   (PJTAG_TDO_O),
+	  .EMIOPJTAGTDTN	   (PJTAG_TDO_T_n),
+	  .EMIOSDIO0BUSPOW         (SDIO0_BUSPOW),
+	  .EMIOSDIO0CLK		   (SDIO0_CLK   ),
+	  .EMIOSDIO0CMDO	   (SDIO0_CMD_O ),
+	  .EMIOSDIO0CMDTN	   (SDIO0_CMD_T_n ),
+	  .EMIOSDIO0DATAO	   (SDIO0_DATA_O),
+	  .EMIOSDIO0DATATN	   (SDIO0_DATA_T_n),
+	  .EMIOSDIO0LED            (SDIO0_LED),
+	  .EMIOSDIO1BUSPOW         (SDIO1_BUSPOW),  
+	  .EMIOSDIO1CLK            (SDIO1_CLK   ),
+	  .EMIOSDIO1CMDO           (SDIO1_CMD_O ),
+	  .EMIOSDIO1CMDTN          (SDIO1_CMD_T_n ),
+	  .EMIOSDIO1DATAO          (SDIO1_DATA_O),
+	  .EMIOSDIO1DATATN         (SDIO1_DATA_T_n),
+	  .EMIOSDIO1LED            (SDIO1_LED),  
+	  .EMIOSPI0MO		   (SPI0_MOSI_O),
+	  .EMIOSPI0MOTN	           (SPI0_MOSI_T_n),
+	  .EMIOSPI0SCLKO	   (SPI0_SCLK_O),
+	  .EMIOSPI0SCLKTN	   (SPI0_SCLK_T_n),
+	  .EMIOSPI0SO		   (SPI0_MISO_O),
+	  .EMIOSPI0STN	           (SPI0_MISO_T_n),
+	  .EMIOSPI0SSON	           ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+	  .EMIOSPI0SSNTN	   (SPI0_SS_T_n),
+	  .EMIOSPI1MO		   (SPI1_MOSI_O),
+	  .EMIOSPI1MOTN	           (SPI1_MOSI_T_n),
+	  .EMIOSPI1SCLKO	   (SPI1_SCLK_O),
+	  .EMIOSPI1SCLKTN	   (SPI1_SCLK_T_n),
+	  .EMIOSPI1SO		   (SPI1_MISO_O),
+	  .EMIOSPI1STN	           (SPI1_MISO_T_n),
+	  .EMIOSPI1SSON	           ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+	  .EMIOSPI1SSNTN	   (SPI1_SS_T_n),
+	  .EMIOTRACECTL		   (TRACE_CTL_i),
+	  .EMIOTRACEDATA	   (TRACE_DATA_i),
+	  .EMIOTTC0WAVEO	   ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+	  .EMIOTTC1WAVEO	   ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+	  .EMIOUART0DTRN	   (UART0_DTRN),
+	  .EMIOUART0RTSN	   (UART0_RTSN),
+	  .EMIOUART0TX		   (UART0_TX  ),
+	  .EMIOUART1DTRN	   (UART1_DTRN),
+	  .EMIOUART1RTSN	   (UART1_RTSN),
+	  .EMIOUART1TX		   (UART1_TX  ),
+	  .EMIOUSB0PORTINDCTL      (USB0_PORT_INDCTL),  
+	  .EMIOUSB0VBUSPWRSELECT   (USB0_VBUS_PWRSELECT),
+	  .EMIOUSB1PORTINDCTL      (USB1_PORT_INDCTL),
+	  .EMIOUSB1VBUSPWRSELECT   (USB1_VBUS_PWRSELECT),  
+	  .EMIOWDTRSTO    	   (WDT_RST_OUT),
+	  .EVENTEVENTO             (EVENT_EVENTO),
+	  .EVENTSTANDBYWFE         (EVENT_STANDBYWFE),
+	  .EVENTSTANDBYWFI         (EVENT_STANDBYWFI),  
+	  .FCLKCLK		   (FCLK_CLK_unbuffered),
+	  .FCLKRESETN		   ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),  
+	  .EMIOSDIO0BUSVOLT        (SDIO0_BUSVOLT), 
+	  .EMIOSDIO1BUSVOLT        (SDIO1_BUSVOLT),  
+	  .FTMTF2PTRIGACK	   ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+	  .FTMTP2FDEBUG		   (FTMT_P2F_DEBUG  ),
+	  .FTMTP2FTRIG		   ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+	  .IRQP2F		   ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),    
+	  .MAXIGP0ARADDR	   (M_AXI_GP0_ARADDR),
+	  .MAXIGP0ARBURST	   (M_AXI_GP0_ARBURST),
+	  .MAXIGP0ARCACHE	   (M_AXI_GP0_ARCACHE_t),
+	  .MAXIGP0ARESETN	   (M_AXI_GP0_ARESETN),
+	  .MAXIGP0ARID	           (M_AXI_GP0_ARID_FULL   ),
+	  .MAXIGP0ARLEN	           (M_AXI_GP0_ARLEN  ),
+	  .MAXIGP0ARLOCK	   (M_AXI_GP0_ARLOCK ),
+	  .MAXIGP0ARPROT	   (M_AXI_GP0_ARPROT ),
+	  .MAXIGP0ARQOS	           (M_AXI_GP0_ARQOS  ),
+	  .MAXIGP0ARSIZE	   (M_AXI_GP0_ARSIZE_i ),
+	  .MAXIGP0ARVALID	   (M_AXI_GP0_ARVALID),
+	  .MAXIGP0AWADDR	   (M_AXI_GP0_AWADDR ),
+	  .MAXIGP0AWBURST	   (M_AXI_GP0_AWBURST),
+	  .MAXIGP0AWCACHE	   (M_AXI_GP0_AWCACHE_t),
+	  .MAXIGP0AWID	           (M_AXI_GP0_AWID_FULL   ),
+	  .MAXIGP0AWLEN	           (M_AXI_GP0_AWLEN  ),
+	  .MAXIGP0AWLOCK	   (M_AXI_GP0_AWLOCK ),
+	  .MAXIGP0AWPROT	   (M_AXI_GP0_AWPROT ),
+	  .MAXIGP0AWQOS	           (M_AXI_GP0_AWQOS  ),
+	  .MAXIGP0AWSIZE	   (M_AXI_GP0_AWSIZE_i ),
+	  .MAXIGP0AWVALID	   (M_AXI_GP0_AWVALID),
+	  .MAXIGP0BREADY	   (M_AXI_GP0_BREADY ),
+	  .MAXIGP0RREADY	   (M_AXI_GP0_RREADY ),
+	  .MAXIGP0WDATA	           (M_AXI_GP0_WDATA  ),
+	  .MAXIGP0WID	           (M_AXI_GP0_WID_FULL    ),
+	  .MAXIGP0WLAST	           (M_AXI_GP0_WLAST  ),
+	  .MAXIGP0WSTRB	           (M_AXI_GP0_WSTRB  ),
+	  .MAXIGP0WVALID	   (M_AXI_GP0_WVALID ),
+	  .MAXIGP1ARADDR	   (M_AXI_GP1_ARADDR ),
+	  .MAXIGP1ARBURST	   (M_AXI_GP1_ARBURST),
+	  .MAXIGP1ARCACHE	   (M_AXI_GP1_ARCACHE_t),
+	  .MAXIGP1ARESETN	   (M_AXI_GP1_ARESETN),
+	  .MAXIGP1ARID	           (M_AXI_GP1_ARID_FULL   ),
+	  .MAXIGP1ARLEN	           (M_AXI_GP1_ARLEN  ),
+	  .MAXIGP1ARLOCK	   (M_AXI_GP1_ARLOCK ),
+	  .MAXIGP1ARPROT	   (M_AXI_GP1_ARPROT ),
+	  .MAXIGP1ARQOS	           (M_AXI_GP1_ARQOS  ),
+	  .MAXIGP1ARSIZE	   (M_AXI_GP1_ARSIZE_i ),
+	  .MAXIGP1ARVALID	   (M_AXI_GP1_ARVALID),
+	  .MAXIGP1AWADDR	   (M_AXI_GP1_AWADDR ),
+	  .MAXIGP1AWBURST	   (M_AXI_GP1_AWBURST),
+	  .MAXIGP1AWCACHE	   (M_AXI_GP1_AWCACHE_t),
+	  .MAXIGP1AWID	           (M_AXI_GP1_AWID_FULL   ),
+	  .MAXIGP1AWLEN	           (M_AXI_GP1_AWLEN  ),
+	  .MAXIGP1AWLOCK	   (M_AXI_GP1_AWLOCK ),
+	  .MAXIGP1AWPROT	   (M_AXI_GP1_AWPROT ),
+	  .MAXIGP1AWQOS	           (M_AXI_GP1_AWQOS  ),
+	  .MAXIGP1AWSIZE	   (M_AXI_GP1_AWSIZE_i ),
+	  .MAXIGP1AWVALID	   (M_AXI_GP1_AWVALID),
+	  .MAXIGP1BREADY	   (M_AXI_GP1_BREADY ),
+	  .MAXIGP1RREADY	   (M_AXI_GP1_RREADY ),
+	  .MAXIGP1WDATA	           (M_AXI_GP1_WDATA  ),
+	  .MAXIGP1WID	           (M_AXI_GP1_WID_FULL    ),
+	  .MAXIGP1WLAST	           (M_AXI_GP1_WLAST  ),
+	  .MAXIGP1WSTRB	           (M_AXI_GP1_WSTRB  ),
+	  .MAXIGP1WVALID	   (M_AXI_GP1_WVALID ),
+	  .SAXIACPARESETN	   (S_AXI_ACP_ARESETN),
+	  .SAXIACPARREADY	   (SAXIACPARREADY_W),
+	  .SAXIACPAWREADY	   (SAXIACPAWREADY_W),
+	  .SAXIACPBID	           (S_AXI_ACP_BID_out    ),
+	  .SAXIACPBRESP	           (SAXIACPBRESP_W  ),
+	  .SAXIACPBVALID	   (SAXIACPBVALID_W ),
+	  .SAXIACPRDATA	           (SAXIACPRDATA_W  ),
+	  .SAXIACPRID	           (S_AXI_ACP_RID_out),
+	  .SAXIACPRLAST	           (SAXIACPRLAST_W  ),
+	  .SAXIACPRRESP	           (SAXIACPRRESP_W  ),
+	  .SAXIACPRVALID	   (SAXIACPRVALID_W ),
+	  .SAXIACPWREADY	   (SAXIACPWREADY_W ),
+	  .SAXIGP0ARESETN	   (S_AXI_GP0_ARESETN),
+	  .SAXIGP0ARREADY	   (S_AXI_GP0_ARREADY),
+	  .SAXIGP0AWREADY	   (S_AXI_GP0_AWREADY),
+	  .SAXIGP0BID	           (S_AXI_GP0_BID_out),
+	  .SAXIGP0BRESP	           (S_AXI_GP0_BRESP  ),
+	  .SAXIGP0BVALID	   (S_AXI_GP0_BVALID ),
+	  .SAXIGP0RDATA	           (S_AXI_GP0_RDATA  ),
+	  .SAXIGP0RID	           (S_AXI_GP0_RID_out ),
+	  .SAXIGP0RLAST	           (S_AXI_GP0_RLAST  ),
+	  .SAXIGP0RRESP	           (S_AXI_GP0_RRESP  ),
+	  .SAXIGP0RVALID	   (S_AXI_GP0_RVALID ),
+	  .SAXIGP0WREADY	   (S_AXI_GP0_WREADY ),
+	  .SAXIGP1ARESETN	   (S_AXI_GP1_ARESETN),
+	  .SAXIGP1ARREADY	   (S_AXI_GP1_ARREADY),
+	  .SAXIGP1AWREADY	   (S_AXI_GP1_AWREADY),
+	  .SAXIGP1BID	           (S_AXI_GP1_BID_out    ),
+	  .SAXIGP1BRESP	           (S_AXI_GP1_BRESP  ),
+	  .SAXIGP1BVALID	   (S_AXI_GP1_BVALID ),
+	  .SAXIGP1RDATA	           (S_AXI_GP1_RDATA  ),
+	  .SAXIGP1RID	           (S_AXI_GP1_RID_out    ),
+	  .SAXIGP1RLAST	           (S_AXI_GP1_RLAST  ),
+	  .SAXIGP1RRESP	           (S_AXI_GP1_RRESP  ),
+	  .SAXIGP1RVALID	   (S_AXI_GP1_RVALID ),
+	  .SAXIGP1WREADY	   (S_AXI_GP1_WREADY ),
+	  .SAXIHP0ARESETN	   (S_AXI_HP0_ARESETN),
+	  .SAXIHP0ARREADY	   (S_AXI_HP0_ARREADY),
+	  .SAXIHP0AWREADY	   (S_AXI_HP0_AWREADY),
+	  .SAXIHP0BID	           (S_AXI_HP0_BID_out    ),
+	  .SAXIHP0BRESP	           (S_AXI_HP0_BRESP  ),
+	  .SAXIHP0BVALID	   (S_AXI_HP0_BVALID ),
+	  .SAXIHP0RACOUNT          (S_AXI_HP0_RACOUNT),
+	  .SAXIHP0RCOUNT	   (S_AXI_HP0_RCOUNT),
+	  .SAXIHP0RDATA	           (S_AXI_HP0_RDATA_out),
+	  .SAXIHP0RID	           (S_AXI_HP0_RID_out ),
+	  .SAXIHP0RLAST	           (S_AXI_HP0_RLAST),
+	  .SAXIHP0RRESP	           (S_AXI_HP0_RRESP),
+	  .SAXIHP0RVALID	   (S_AXI_HP0_RVALID),
+	  .SAXIHP0WCOUNT	   (S_AXI_HP0_WCOUNT),
+	  .SAXIHP0WACOUNT          (S_AXI_HP0_WACOUNT),  
+	  .SAXIHP0WREADY	   (S_AXI_HP0_WREADY),
+	  .SAXIHP1ARESETN	   (S_AXI_HP1_ARESETN),
+	  .SAXIHP1ARREADY	   (S_AXI_HP1_ARREADY),
+	  .SAXIHP1AWREADY	   (S_AXI_HP1_AWREADY),
+	  .SAXIHP1BID	           (S_AXI_HP1_BID_out    ),
+	  .SAXIHP1BRESP	           (S_AXI_HP1_BRESP  ),
+	  .SAXIHP1BVALID	   (S_AXI_HP1_BVALID ),
+	  .SAXIHP1RACOUNT	   (S_AXI_HP1_RACOUNT ),  
+	  .SAXIHP1RCOUNT	   (S_AXI_HP1_RCOUNT ),
+	  .SAXIHP1RDATA	           (S_AXI_HP1_RDATA_out),
+	  .SAXIHP1RID	           (S_AXI_HP1_RID_out    ),
+	  .SAXIHP1RLAST	           (S_AXI_HP1_RLAST  ),
+	  .SAXIHP1RRESP	           (S_AXI_HP1_RRESP  ),
+	  .SAXIHP1RVALID	   (S_AXI_HP1_RVALID),
+	  .SAXIHP1WACOUNT	   (S_AXI_HP1_WACOUNT),  
+	  .SAXIHP1WCOUNT	   (S_AXI_HP1_WCOUNT),
+	  .SAXIHP1WREADY	   (S_AXI_HP1_WREADY),
+	  .SAXIHP2ARESETN	   (S_AXI_HP2_ARESETN),
+	  .SAXIHP2ARREADY	   (S_AXI_HP2_ARREADY),
+	  .SAXIHP2AWREADY	   (S_AXI_HP2_AWREADY),
+	  .SAXIHP2BID	           (S_AXI_HP2_BID_out ),
+	  .SAXIHP2BRESP	           (S_AXI_HP2_BRESP),
+	  .SAXIHP2BVALID	   (S_AXI_HP2_BVALID),
+	  .SAXIHP2RACOUNT	   (S_AXI_HP2_RACOUNT),  
+	  .SAXIHP2RCOUNT	   (S_AXI_HP2_RCOUNT),
+	  .SAXIHP2RDATA	           (S_AXI_HP2_RDATA_out),
+	  .SAXIHP2RID	           (S_AXI_HP2_RID_out ),
+	  .SAXIHP2RLAST	           (S_AXI_HP2_RLAST),
+	  .SAXIHP2RRESP	           (S_AXI_HP2_RRESP),
+	  .SAXIHP2RVALID	   (S_AXI_HP2_RVALID),
+	  .SAXIHP2WACOUNT	   (S_AXI_HP2_WACOUNT),  
+	  .SAXIHP2WCOUNT	   (S_AXI_HP2_WCOUNT),
+	  .SAXIHP2WREADY	   (S_AXI_HP2_WREADY),
+	  .SAXIHP3ARESETN	   (S_AXI_HP3_ARESETN),
+	  .SAXIHP3ARREADY	   (S_AXI_HP3_ARREADY),
+	  .SAXIHP3AWREADY	   (S_AXI_HP3_AWREADY),
+	  .SAXIHP3BID	           (S_AXI_HP3_BID_out),
+	  .SAXIHP3BRESP	           (S_AXI_HP3_BRESP),
+	  .SAXIHP3BVALID	   (S_AXI_HP3_BVALID),
+	  .SAXIHP3RACOUNT	   (S_AXI_HP3_RACOUNT),    
+	  .SAXIHP3RCOUNT	   (S_AXI_HP3_RCOUNT),
+	  .SAXIHP3RDATA	           (S_AXI_HP3_RDATA_out),
+	  .SAXIHP3RID	           (S_AXI_HP3_RID_out),
+	  .SAXIHP3RLAST	           (S_AXI_HP3_RLAST),
+	  .SAXIHP3RRESP	           (S_AXI_HP3_RRESP),
+	  .SAXIHP3RVALID	   (S_AXI_HP3_RVALID),
+	  .SAXIHP3WCOUNT	   (S_AXI_HP3_WCOUNT),
+	  .SAXIHP3WACOUNT	   (S_AXI_HP3_WACOUNT),    
+	  .SAXIHP3WREADY	   (S_AXI_HP3_WREADY), 
+	  .DDRARB                  (DDR_ARB), 
+	  .DMA0ACLK		   (DMA0_ACLK   ),
+	  .DMA0DAREADY		   (DMA0_DAREADY),
+	  .DMA0DRLAST		   (DMA0_DRLAST ),
+	  .DMA0DRTYPE              (DMA0_DRTYPE),
+	  .DMA0DRVALID		   (DMA0_DRVALID),
+	  .DMA1ACLK		   (DMA1_ACLK   ),
+	  .DMA1DAREADY		   (DMA1_DAREADY),
+	  .DMA1DRLAST		   (DMA1_DRLAST ),
+	  .DMA1DRTYPE              (DMA1_DRTYPE),  
+	  .DMA1DRVALID		   (DMA1_DRVALID),
+	  .DMA2ACLK		   (DMA2_ACLK   ),
+	  .DMA2DAREADY		   (DMA2_DAREADY),
+	  .DMA2DRLAST		   (DMA2_DRLAST ),
+	  .DMA2DRTYPE              (DMA2_DRTYPE),    
+	  .DMA2DRVALID		   (DMA2_DRVALID),
+	  .DMA3ACLK		   (DMA3_ACLK   ),
+	  .DMA3DAREADY		   (DMA3_DAREADY),
+	  .DMA3DRLAST		   (DMA3_DRLAST ),
+	  .DMA3DRTYPE              (DMA3_DRTYPE),      
+	  .DMA3DRVALID		   (DMA3_DRVALID),
+	  .EMIOCAN0PHYRX	   (CAN0_PHY_RX),  
+	  .EMIOCAN1PHYRX	   (CAN1_PHY_RX),
+	  .EMIOENET0EXTINTIN       (ENET0_EXT_INTIN),  
+	  .EMIOENET0GMIICOL        (ENET0_GMII_COL_i),
+	  .EMIOENET0GMIICRS        (ENET0_GMII_CRS_i),
+	  .EMIOENET0GMIIRXCLK      (ENET0_GMII_RX_CLK),
+	  .EMIOENET0GMIIRXD        (ENET0_GMII_RXD_i),
+	  .EMIOENET0GMIIRXDV       (ENET0_GMII_RX_DV_i),
+	  .EMIOENET0GMIIRXER       (ENET0_GMII_RX_ER_i),
+	  .EMIOENET0GMIITXCLK      (ENET0_GMII_TX_CLK),
+	  .EMIOENET0MDIOI          (ENET0_MDIO_I),
+	  .EMIOENET1EXTINTIN       (ENET1_EXT_INTIN),    
+	  .EMIOENET1GMIICOL        (ENET1_GMII_COL_i),
+	  .EMIOENET1GMIICRS        (ENET1_GMII_CRS_i),
+	  .EMIOENET1GMIIRXCLK      (ENET1_GMII_RX_CLK),
+	  .EMIOENET1GMIIRXD        (ENET1_GMII_RXD_i),
+	  .EMIOENET1GMIIRXDV       (ENET1_GMII_RX_DV_i),
+	  .EMIOENET1GMIIRXER       (ENET1_GMII_RX_ER_i),
+	  .EMIOENET1GMIITXCLK      (ENET1_GMII_TX_CLK),
+	  .EMIOENET1MDIOI          (ENET1_MDIO_I),  
+	  .EMIOGPIOI	           (gpio_in63_0  ),
+	  .EMIOI2C0SCLI	           (I2C0_SCL_I),
+	  .EMIOI2C0SDAI	           (I2C0_SDA_I),
+	  .EMIOI2C1SCLI	           (I2C1_SCL_I),
+	  .EMIOI2C1SDAI	           (I2C1_SDA_I),
+	  .EMIOPJTAGTCK		   (PJTAG_TCK),
+	  .EMIOPJTAGTDI		   (PJTAG_TDI),
+	  .EMIOPJTAGTMS		   (PJTAG_TMS),
+	  .EMIOSDIO0CDN            (SDIO0_CDN),
+	  .EMIOSDIO0CLKFB	   (SDIO0_CLK_FB  ),
+	  .EMIOSDIO0CMDI	   (SDIO0_CMD_I   ),
+	  .EMIOSDIO0DATAI	   (SDIO0_DATA_I  ),
+	  .EMIOSDIO0WP             (SDIO0_WP),
+	  .EMIOSDIO1CDN            (SDIO1_CDN),  
+	  .EMIOSDIO1CLKFB	   (SDIO1_CLK_FB  ),
+	  .EMIOSDIO1CMDI	   (SDIO1_CMD_I   ),
+	  .EMIOSDIO1DATAI	   (SDIO1_DATA_I  ),
+	  .EMIOSDIO1WP             (SDIO1_WP),
+	  .EMIOSPI0MI		   (SPI0_MISO_I),
+	  .EMIOSPI0SCLKI	   (SPI0_SCLK_I),
+	  .EMIOSPI0SI		   (SPI0_MOSI_I),
+	  .EMIOSPI0SSIN 	   (SPI0_SS_I),
+	  .EMIOSPI1MI		   (SPI1_MISO_I),
+	  .EMIOSPI1SCLKI	   (SPI1_SCLK_I),
+	  .EMIOSPI1SI		   (SPI1_MOSI_I),
+	  .EMIOSPI1SSIN	           (SPI1_SS_I),
+	  .EMIOSRAMINTIN           (SRAM_INTIN),  
+	  .EMIOTRACECLK		   (TRACE_CLK),
+	  .EMIOTTC0CLKI	           ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
+	  .EMIOTTC1CLKI	           ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
+	  .EMIOUART0CTSN	   (UART0_CTSN),
+	  .EMIOUART0DCDN	   (UART0_DCDN),
+	  .EMIOUART0DSRN	   (UART0_DSRN),
+	  .EMIOUART0RIN		   (UART0_RIN ),
+	  .EMIOUART0RX		   (UART0_RX  ),
+	  .EMIOUART1CTSN	   (UART1_CTSN),
+	  .EMIOUART1DCDN	   (UART1_DCDN),
+	  .EMIOUART1DSRN	   (UART1_DSRN),
+	  .EMIOUART1RIN		   (UART1_RIN ),
+	  .EMIOUART1RX		   (UART1_RX  ),
+	  .EMIOUSB0VBUSPWRFAULT    (USB0_VBUS_PWRFAULT),
+	  .EMIOUSB1VBUSPWRFAULT    (USB1_VBUS_PWRFAULT),  
+	  .EMIOWDTCLKI		   (WDT_CLK_IN),  
+	  .EVENTEVENTI             (EVENT_EVENTI),
+	  .FCLKCLKTRIGN		   (fclk_clktrig_gnd),
+	  .FPGAIDLEN		   (FPGA_IDLE_N),  
+	  .FTMDTRACEINATID	   (FTMD_TRACEIN_ATID_i),  
+	  .FTMDTRACEINCLOCK	   (FTMD_TRACEIN_CLK),
+	  .FTMDTRACEINDATA	   (FTMD_TRACEIN_DATA_i),
+	  .FTMDTRACEINVALID	   (FTMD_TRACEIN_VALID_i),
+	  .FTMTF2PDEBUG		   (FTMT_F2P_DEBUG  ),
+	  .FTMTF2PTRIG		   ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+	  .FTMTP2FTRIGACK	   ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),  
+	  .IRQF2P		   (irq_f2p_i),  
+	  .MAXIGP0ACLK	           (M_AXI_GP0_ACLK_temp),
+	  .MAXIGP0ARREADY	   (M_AXI_GP0_ARREADY),
+	  .MAXIGP0AWREADY	   (M_AXI_GP0_AWREADY),
+	  .MAXIGP0BID	           (M_AXI_GP0_BID_FULL    ),
+	  .MAXIGP0BRESP	           (M_AXI_GP0_BRESP  ),
+	  .MAXIGP0BVALID	   (M_AXI_GP0_BVALID ),
+	  .MAXIGP0RDATA	           (M_AXI_GP0_RDATA  ),
+	  .MAXIGP0RID	           (M_AXI_GP0_RID_FULL    ),
+	  .MAXIGP0RLAST	           (M_AXI_GP0_RLAST  ),
+	  .MAXIGP0RRESP	           (M_AXI_GP0_RRESP  ),
+	  .MAXIGP0RVALID	   (M_AXI_GP0_RVALID ),
+	  .MAXIGP0WREADY	   (M_AXI_GP0_WREADY ),
+	  .MAXIGP1ACLK	           (M_AXI_GP1_ACLK_temp   ),
+	  .MAXIGP1ARREADY	   (M_AXI_GP1_ARREADY),
+	  .MAXIGP1AWREADY	   (M_AXI_GP1_AWREADY),
+	  .MAXIGP1BID	           (M_AXI_GP1_BID_FULL ),
+	  .MAXIGP1BRESP	           (M_AXI_GP1_BRESP  ),
+	  .MAXIGP1BVALID	   (M_AXI_GP1_BVALID ),
+	  .MAXIGP1RDATA	           (M_AXI_GP1_RDATA  ),
+	  .MAXIGP1RID	           (M_AXI_GP1_RID_FULL    ),
+	  .MAXIGP1RLAST	           (M_AXI_GP1_RLAST  ),
+	  .MAXIGP1RRESP	           (M_AXI_GP1_RRESP  ),
+	  .MAXIGP1RVALID	   (M_AXI_GP1_RVALID ),
+	  .MAXIGP1WREADY	   (M_AXI_GP1_WREADY ),  
+	  .SAXIACPACLK	           (S_AXI_ACP_ACLK_temp   ),
+	  .SAXIACPARADDR	   (SAXIACPARADDR_W ),
+	  .SAXIACPARBURST	   (SAXIACPARBURST_W),
+	  .SAXIACPARCACHE	   (SAXIACPARCACHE_W),
+	  .SAXIACPARID	           (S_AXI_ACP_ARID_in   ),
+	  .SAXIACPARLEN	           (SAXIACPARLEN_W  ),
+	  .SAXIACPARLOCK	   (SAXIACPARLOCK_W ),
+	  .SAXIACPARPROT	   (SAXIACPARPROT_W ),
+	  .SAXIACPARQOS	           (S_AXI_ACP_ARQOS  ),
+	  .SAXIACPARSIZE	   (SAXIACPARSIZE_W[1:0] ),
+	  .SAXIACPARUSER	   (SAXIACPARUSER_W ),
+	  .SAXIACPARVALID	   (SAXIACPARVALID_W),
+	  .SAXIACPAWADDR	   (SAXIACPAWADDR_W ),
+	  .SAXIACPAWBURST	   (SAXIACPAWBURST_W),
+	  .SAXIACPAWCACHE	   (SAXIACPAWCACHE_W),
+	  .SAXIACPAWID	           (S_AXI_ACP_AWID_in   ),
+	  .SAXIACPAWLEN	           (SAXIACPAWLEN_W  ),
+	  .SAXIACPAWLOCK	   (SAXIACPAWLOCK_W ),
+	  .SAXIACPAWPROT	   (SAXIACPAWPROT_W ),
+	  .SAXIACPAWQOS	           (S_AXI_ACP_AWQOS  ),
+	  .SAXIACPAWSIZE	   (SAXIACPAWSIZE_W[1:0] ),
+	  .SAXIACPAWUSER	   (SAXIACPAWUSER_W ),
+	  .SAXIACPAWVALID	   (SAXIACPAWVALID_W),
+	  .SAXIACPBREADY	   (SAXIACPBREADY_W ),
+	  .SAXIACPRREADY	   (SAXIACPRREADY_W ),
+	  .SAXIACPWDATA	           (SAXIACPWDATA_W  ),
+	  .SAXIACPWID	           (S_AXI_ACP_WID_in    ),
+	  .SAXIACPWLAST	           (SAXIACPWLAST_W  ),
+	  .SAXIACPWSTRB	           (SAXIACPWSTRB_W  ),
+	  .SAXIACPWVALID	   (SAXIACPWVALID_W ),
+	  .SAXIGP0ACLK             (S_AXI_GP0_ACLK_temp   ),
+	  .SAXIGP0ARADDR           (S_AXI_GP0_ARADDR ),
+	  .SAXIGP0ARBURST          (S_AXI_GP0_ARBURST),
+	  .SAXIGP0ARCACHE          (S_AXI_GP0_ARCACHE),
+	  .SAXIGP0ARID             (S_AXI_GP0_ARID_in   ),
+	  .SAXIGP0ARLEN            (S_AXI_GP0_ARLEN  ),
+	  .SAXIGP0ARLOCK           (S_AXI_GP0_ARLOCK ),
+	  .SAXIGP0ARPROT           (S_AXI_GP0_ARPROT ),
+	  .SAXIGP0ARQOS            (S_AXI_GP0_ARQOS  ),
+	  .SAXIGP0ARSIZE           (S_AXI_GP0_ARSIZE[1:0] ),
+	  .SAXIGP0ARVALID          (S_AXI_GP0_ARVALID),
+	  .SAXIGP0AWADDR           (S_AXI_GP0_AWADDR ),
+	  .SAXIGP0AWBURST          (S_AXI_GP0_AWBURST),
+	  .SAXIGP0AWCACHE          (S_AXI_GP0_AWCACHE),
+	  .SAXIGP0AWID             (S_AXI_GP0_AWID_in   ),
+	  .SAXIGP0AWLEN            (S_AXI_GP0_AWLEN  ),
+	  .SAXIGP0AWLOCK           (S_AXI_GP0_AWLOCK ),
+	  .SAXIGP0AWPROT           (S_AXI_GP0_AWPROT ),
+	  .SAXIGP0AWQOS            (S_AXI_GP0_AWQOS  ),
+	  .SAXIGP0AWSIZE           (S_AXI_GP0_AWSIZE[1:0] ),
+	  .SAXIGP0AWVALID          (S_AXI_GP0_AWVALID),
+	  .SAXIGP0BREADY           (S_AXI_GP0_BREADY ),
+	  .SAXIGP0RREADY           (S_AXI_GP0_RREADY ),
+	  .SAXIGP0WDATA            (S_AXI_GP0_WDATA  ),
+	  .SAXIGP0WID              (S_AXI_GP0_WID_in ),
+	  .SAXIGP0WLAST            (S_AXI_GP0_WLAST  ),
+	  .SAXIGP0WSTRB            (S_AXI_GP0_WSTRB  ),
+	  .SAXIGP0WVALID           (S_AXI_GP0_WVALID ),
+	  .SAXIGP1ACLK	           (S_AXI_GP1_ACLK_temp   ),
+	  .SAXIGP1ARADDR	   (S_AXI_GP1_ARADDR ),
+	  .SAXIGP1ARBURST	   (S_AXI_GP1_ARBURST),
+	  .SAXIGP1ARCACHE	   (S_AXI_GP1_ARCACHE),
+	  .SAXIGP1ARID	           (S_AXI_GP1_ARID_in   ),
+	  .SAXIGP1ARLEN	           (S_AXI_GP1_ARLEN  ),
+	  .SAXIGP1ARLOCK	   (S_AXI_GP1_ARLOCK ),
+	  .SAXIGP1ARPROT	   (S_AXI_GP1_ARPROT ),
+	  .SAXIGP1ARQOS	           (S_AXI_GP1_ARQOS  ),
+	  .SAXIGP1ARSIZE	   (S_AXI_GP1_ARSIZE[1:0] ),
+	  .SAXIGP1ARVALID	   (S_AXI_GP1_ARVALID),
+	  .SAXIGP1AWADDR	   (S_AXI_GP1_AWADDR ),
+	  .SAXIGP1AWBURST	   (S_AXI_GP1_AWBURST),
+	  .SAXIGP1AWCACHE	   (S_AXI_GP1_AWCACHE),
+	  .SAXIGP1AWID	           (S_AXI_GP1_AWID_in   ),
+	  .SAXIGP1AWLEN	           (S_AXI_GP1_AWLEN  ),
+	  .SAXIGP1AWLOCK	   (S_AXI_GP1_AWLOCK ),
+	  .SAXIGP1AWPROT	   (S_AXI_GP1_AWPROT ),
+	  .SAXIGP1AWQOS	           (S_AXI_GP1_AWQOS  ),
+	  .SAXIGP1AWSIZE	   (S_AXI_GP1_AWSIZE[1:0] ),
+	  .SAXIGP1AWVALID	   (S_AXI_GP1_AWVALID),
+	  .SAXIGP1BREADY	   (S_AXI_GP1_BREADY ),
+	  .SAXIGP1RREADY	   (S_AXI_GP1_RREADY ),
+	  .SAXIGP1WDATA	           (S_AXI_GP1_WDATA  ),
+	  .SAXIGP1WID	           (S_AXI_GP1_WID_in    ),
+	  .SAXIGP1WLAST	           (S_AXI_GP1_WLAST  ),
+	  .SAXIGP1WSTRB	           (S_AXI_GP1_WSTRB  ),
+	  .SAXIGP1WVALID	   (S_AXI_GP1_WVALID ),  
+	  .SAXIHP0ACLK             (S_AXI_HP0_ACLK_temp   ),
+	  .SAXIHP0ARADDR           (S_AXI_HP0_ARADDR),
+	  .SAXIHP0ARBURST          (S_AXI_HP0_ARBURST),
+	  .SAXIHP0ARCACHE          (S_AXI_HP0_ARCACHE),
+	  .SAXIHP0ARID             (S_AXI_HP0_ARID_in),
+	  .SAXIHP0ARLEN            (S_AXI_HP0_ARLEN),
+	  .SAXIHP0ARLOCK           (S_AXI_HP0_ARLOCK),
+	  .SAXIHP0ARPROT           (S_AXI_HP0_ARPROT),
+	  .SAXIHP0ARQOS            (S_AXI_HP0_ARQOS),
+	  .SAXIHP0ARSIZE           (S_AXI_HP0_ARSIZE[1:0]),
+	  .SAXIHP0ARVALID          (S_AXI_HP0_ARVALID),
+	  .SAXIHP0AWADDR           (S_AXI_HP0_AWADDR),
+	  .SAXIHP0AWBURST          (S_AXI_HP0_AWBURST),
+	  .SAXIHP0AWCACHE          (S_AXI_HP0_AWCACHE),
+	  .SAXIHP0AWID             (S_AXI_HP0_AWID_in),
+	  .SAXIHP0AWLEN            (S_AXI_HP0_AWLEN),
+	  .SAXIHP0AWLOCK           (S_AXI_HP0_AWLOCK),
+	  .SAXIHP0AWPROT           (S_AXI_HP0_AWPROT),
+	  .SAXIHP0AWQOS            (S_AXI_HP0_AWQOS),
+	  .SAXIHP0AWSIZE           (S_AXI_HP0_AWSIZE[1:0]),
+	  .SAXIHP0AWVALID          (S_AXI_HP0_AWVALID),
+	  .SAXIHP0BREADY           (S_AXI_HP0_BREADY),
+	  .SAXIHP0RDISSUECAP1EN    (S_AXI_HP0_RDISSUECAP1_EN),
+	  .SAXIHP0RREADY           (S_AXI_HP0_RREADY),
+	  .SAXIHP0WDATA            (S_AXI_HP0_WDATA_in),
+	  .SAXIHP0WID              (S_AXI_HP0_WID_in),
+	  .SAXIHP0WLAST            (S_AXI_HP0_WLAST),
+	  .SAXIHP0WRISSUECAP1EN    (S_AXI_HP0_WRISSUECAP1_EN),
+	  .SAXIHP0WSTRB            (S_AXI_HP0_WSTRB_in),
+	  .SAXIHP0WVALID           (S_AXI_HP0_WVALID),
+	  .SAXIHP1ACLK             (S_AXI_HP1_ACLK_temp),
+	  .SAXIHP1ARADDR           (S_AXI_HP1_ARADDR),
+	  .SAXIHP1ARBURST          (S_AXI_HP1_ARBURST),
+	  .SAXIHP1ARCACHE          (S_AXI_HP1_ARCACHE),
+	  .SAXIHP1ARID             (S_AXI_HP1_ARID_in),
+	  .SAXIHP1ARLEN            (S_AXI_HP1_ARLEN),
+	  .SAXIHP1ARLOCK           (S_AXI_HP1_ARLOCK),
+	  .SAXIHP1ARPROT           (S_AXI_HP1_ARPROT),
+	  .SAXIHP1ARQOS            (S_AXI_HP1_ARQOS),
+	  .SAXIHP1ARSIZE           (S_AXI_HP1_ARSIZE[1:0]),
+	  .SAXIHP1ARVALID          (S_AXI_HP1_ARVALID),
+	  .SAXIHP1AWADDR           (S_AXI_HP1_AWADDR),
+	  .SAXIHP1AWBURST          (S_AXI_HP1_AWBURST),
+	  .SAXIHP1AWCACHE          (S_AXI_HP1_AWCACHE),
+	  .SAXIHP1AWID             (S_AXI_HP1_AWID_in),
+	  .SAXIHP1AWLEN            (S_AXI_HP1_AWLEN),
+	  .SAXIHP1AWLOCK           (S_AXI_HP1_AWLOCK),
+	  .SAXIHP1AWPROT           (S_AXI_HP1_AWPROT),
+	  .SAXIHP1AWQOS            (S_AXI_HP1_AWQOS),
+	  .SAXIHP1AWSIZE           (S_AXI_HP1_AWSIZE[1:0]),
+	  .SAXIHP1AWVALID          (S_AXI_HP1_AWVALID),
+	  .SAXIHP1BREADY           (S_AXI_HP1_BREADY),
+	  .SAXIHP1RDISSUECAP1EN    (S_AXI_HP1_RDISSUECAP1_EN),
+	  .SAXIHP1RREADY           (S_AXI_HP1_RREADY),
+	  .SAXIHP1WDATA            (S_AXI_HP1_WDATA_in),
+	  .SAXIHP1WID              (S_AXI_HP1_WID_in),
+	  .SAXIHP1WLAST            (S_AXI_HP1_WLAST),
+	  .SAXIHP1WRISSUECAP1EN    (S_AXI_HP1_WRISSUECAP1_EN),
+	  .SAXIHP1WSTRB            (S_AXI_HP1_WSTRB_in),
+	  .SAXIHP1WVALID           (S_AXI_HP1_WVALID),
+	  .SAXIHP2ACLK             (S_AXI_HP2_ACLK_temp),
+	  .SAXIHP2ARADDR           (S_AXI_HP2_ARADDR),
+	  .SAXIHP2ARBURST          (S_AXI_HP2_ARBURST),
+	  .SAXIHP2ARCACHE          (S_AXI_HP2_ARCACHE),
+	  .SAXIHP2ARID             (S_AXI_HP2_ARID_in),
+	  .SAXIHP2ARLEN            (S_AXI_HP2_ARLEN),
+	  .SAXIHP2ARLOCK           (S_AXI_HP2_ARLOCK),
+	  .SAXIHP2ARPROT           (S_AXI_HP2_ARPROT),
+	  .SAXIHP2ARQOS            (S_AXI_HP2_ARQOS),
+	  .SAXIHP2ARSIZE           (S_AXI_HP2_ARSIZE[1:0]),
+	  .SAXIHP2ARVALID          (S_AXI_HP2_ARVALID),
+	  .SAXIHP2AWADDR           (S_AXI_HP2_AWADDR),
+	  .SAXIHP2AWBURST          (S_AXI_HP2_AWBURST),
+	  .SAXIHP2AWCACHE          (S_AXI_HP2_AWCACHE),
+	  .SAXIHP2AWID             (S_AXI_HP2_AWID_in),
+	  .SAXIHP2AWLEN            (S_AXI_HP2_AWLEN),
+	  .SAXIHP2AWLOCK           (S_AXI_HP2_AWLOCK),
+	  .SAXIHP2AWPROT           (S_AXI_HP2_AWPROT),
+	  .SAXIHP2AWQOS            (S_AXI_HP2_AWQOS),
+	  .SAXIHP2AWSIZE           (S_AXI_HP2_AWSIZE[1:0]),
+	  .SAXIHP2AWVALID          (S_AXI_HP2_AWVALID),
+	  .SAXIHP2BREADY           (S_AXI_HP2_BREADY),
+	  .SAXIHP2RDISSUECAP1EN    (S_AXI_HP2_RDISSUECAP1_EN),
+	  .SAXIHP2RREADY           (S_AXI_HP2_RREADY),
+	  .SAXIHP2WDATA            (S_AXI_HP2_WDATA_in),
+	  .SAXIHP2WID              (S_AXI_HP2_WID_in),
+	  .SAXIHP2WLAST            (S_AXI_HP2_WLAST),
+	  .SAXIHP2WRISSUECAP1EN    (S_AXI_HP2_WRISSUECAP1_EN),
+	  .SAXIHP2WSTRB            (S_AXI_HP2_WSTRB_in),
+	  .SAXIHP2WVALID           (S_AXI_HP2_WVALID),  
+	  .SAXIHP3ACLK             (S_AXI_HP3_ACLK_temp),
+	  .SAXIHP3ARADDR           (S_AXI_HP3_ARADDR ),
+	  .SAXIHP3ARBURST          (S_AXI_HP3_ARBURST),
+	  .SAXIHP3ARCACHE          (S_AXI_HP3_ARCACHE),
+	  .SAXIHP3ARID             (S_AXI_HP3_ARID_in   ),
+	  .SAXIHP3ARLEN            (S_AXI_HP3_ARLEN),
+	  .SAXIHP3ARLOCK           (S_AXI_HP3_ARLOCK),
+	  .SAXIHP3ARPROT           (S_AXI_HP3_ARPROT),
+	  .SAXIHP3ARQOS            (S_AXI_HP3_ARQOS),
+	  .SAXIHP3ARSIZE           (S_AXI_HP3_ARSIZE[1:0]),
+	  .SAXIHP3ARVALID          (S_AXI_HP3_ARVALID),
+	  .SAXIHP3AWADDR           (S_AXI_HP3_AWADDR),
+	  .SAXIHP3AWBURST          (S_AXI_HP3_AWBURST),
+	  .SAXIHP3AWCACHE          (S_AXI_HP3_AWCACHE),
+	  .SAXIHP3AWID             (S_AXI_HP3_AWID_in),
+	  .SAXIHP3AWLEN            (S_AXI_HP3_AWLEN),
+	  .SAXIHP3AWLOCK           (S_AXI_HP3_AWLOCK),
+	  .SAXIHP3AWPROT           (S_AXI_HP3_AWPROT),
+	  .SAXIHP3AWQOS            (S_AXI_HP3_AWQOS),
+	  .SAXIHP3AWSIZE           (S_AXI_HP3_AWSIZE[1:0]),
+	  .SAXIHP3AWVALID          (S_AXI_HP3_AWVALID),
+	  .SAXIHP3BREADY           (S_AXI_HP3_BREADY),
+	  .SAXIHP3RDISSUECAP1EN    (S_AXI_HP3_RDISSUECAP1_EN),
+	  .SAXIHP3RREADY           (S_AXI_HP3_RREADY),
+	  .SAXIHP3WDATA            (S_AXI_HP3_WDATA_in),
+	  .SAXIHP3WID              (S_AXI_HP3_WID_in),
+	  .SAXIHP3WLAST            (S_AXI_HP3_WLAST),
+	  .SAXIHP3WRISSUECAP1EN    (S_AXI_HP3_WRISSUECAP1_EN),
+	  .SAXIHP3WSTRB            (S_AXI_HP3_WSTRB_in),
+	  .SAXIHP3WVALID           (S_AXI_HP3_WVALID),
+	  .DDRA		           (buffered_DDR_Addr),
+	  .DDRBA		   (buffered_DDR_BankAddr),
+	  .DDRCASB		   (buffered_DDR_CAS_n),
+	  .DDRCKE		   (buffered_DDR_CKE),
+	  .DDRCKN		   (buffered_DDR_Clk_n),
+	  .DDRCKP		   (buffered_DDR_Clk),
+	  .DDRCSB		   (buffered_DDR_CS_n),
+	  .DDRDM		   (buffered_DDR_DM),
+	  .DDRDQ		   (buffered_DDR_DQ),
+	  .DDRDQSN		   (buffered_DDR_DQS_n),
+	  .DDRDQSP		   (buffered_DDR_DQS),
+	  .DDRDRSTB                (buffered_DDR_DRSTB),
+	  .DDRODT		   (buffered_DDR_ODT),  
+	  .DDRRASB		   (buffered_DDR_RAS_n),
+	  .DDRVRN          (buffered_DDR_VRN),
+	  .DDRVRP          (buffered_DDR_VRP),
+	  .DDRWEB          (buffered_DDR_WEB),
+	  .MIO			   ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
+	  .PSCLK		   (buffered_PS_CLK),  
+	  .PSPORB		   (buffered_PS_PORB),  
+	  .PSSRSTB		   (buffered_PS_SRSTB)  
+  
+
+);
+ end
+ else begin
+	PS7 PS7_i (
+	  .DMA0DATYPE		   (DMA0_DATYPE ),
+	  .DMA0DAVALID		   (DMA0_DAVALID),
+	  .DMA0DRREADY		   (DMA0_DRREADY),  
+	  .DMA0RSTN		   (DMA0_RSTN   ),  
+	  .DMA1DATYPE		   (DMA1_DATYPE ),
+	  .DMA1DAVALID		   (DMA1_DAVALID),
+	  .DMA1DRREADY		   (DMA1_DRREADY),
+	  .DMA1RSTN		   (DMA1_RSTN   ),
+	  .DMA2DATYPE		   (DMA2_DATYPE ),
+	  .DMA2DAVALID		   (DMA2_DAVALID),
+	  .DMA2DRREADY		   (DMA2_DRREADY),
+	  .DMA2RSTN		   (DMA2_RSTN   ),
+	  .DMA3DATYPE		   (DMA3_DATYPE ),
+	  .DMA3DAVALID		   (DMA3_DAVALID),
+	  .DMA3DRREADY		   (DMA3_DRREADY),
+	  .DMA3RSTN		   (DMA3_RSTN   ),  
+	  .EMIOCAN0PHYTX	   (CAN0_PHY_TX ),
+	  .EMIOCAN1PHYTX	   (CAN1_PHY_TX ),  
+	  .EMIOENET0GMIITXD	  (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
+	  .EMIOENET0GMIITXEN	(ENET0_GMII_TX_EN_i), //  (ENET0_GMII_TX_EN_i),
+	  .EMIOENET0GMIITXER   (ENET0_GMII_TX_ER_i), //	 (ENET0_GMII_TX_ER_i),
+	  .EMIOENET0MDIOMDC	   (ENET0_MDIO_MDC),
+	  .EMIOENET0MDIOO	   (ENET0_MDIO_O  ),
+	  .EMIOENET0MDIOTN	   (ENET0_MDIO_T_n  ),
+	  .EMIOENET0PTPDELAYREQRX  (ENET0_PTP_DELAY_REQ_RX),
+	  .EMIOENET0PTPDELAYREQTX  (ENET0_PTP_DELAY_REQ_TX),
+	  .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
+	  .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
+	  .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
+	  .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
+	  .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
+	  .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
+	  .EMIOENET0SOFRX          (ENET0_SOF_RX),
+	  .EMIOENET0SOFTX          (ENET0_SOF_TX),   
+	  .EMIOENET1GMIITXD	 (ENET1_GMII_TXD_i), //  (ENET1_GMII_TXD_i),
+	  .EMIOENET1GMIITXEN	(ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
+	  .EMIOENET1GMIITXER	(ENET1_GMII_TX_ER_i), //  (ENET1_GMII_TX_ER_i),
+	  .EMIOENET1MDIOMDC	   (ENET1_MDIO_MDC),
+	  .EMIOENET1MDIOO	   (ENET1_MDIO_O  ),
+	  .EMIOENET1MDIOTN	   (ENET1_MDIO_T_n),
+	  .EMIOENET1PTPDELAYREQRX  (ENET1_PTP_DELAY_REQ_RX),
+	  .EMIOENET1PTPDELAYREQTX  (ENET1_PTP_DELAY_REQ_TX),
+	  .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
+	  .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
+	  .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
+	  .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
+	  .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
+	  .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
+	  .EMIOENET1SOFRX          (ENET1_SOF_RX),
+	  .EMIOENET1SOFTX          (ENET1_SOF_TX),  
+	  .EMIOGPIOO	           (gpio_out),
+	  .EMIOGPIOTN	           (gpio_out_t_n),
+	  .EMIOI2C0SCLO            (I2C0_SCL_O),
+	  .EMIOI2C0SCLTN           (I2C0_SCL_T_n),
+	  .EMIOI2C0SDAO	           (I2C0_SDA_O),
+	  .EMIOI2C0SDATN	   (I2C0_SDA_T_n),
+	  .EMIOI2C1SCLO	           (I2C1_SCL_O),
+	  .EMIOI2C1SCLTN           (I2C1_SCL_T_n),
+	  .EMIOI2C1SDAO	           (I2C1_SDA_O),
+	  .EMIOI2C1SDATN	   (I2C1_SDA_T_n),
+	  .EMIOPJTAGTDO  	   (PJTAG_TDO_O),
+	  .EMIOPJTAGTDTN	   (PJTAG_TDO_T_n),
+	  .EMIOSDIO0BUSPOW         (SDIO0_BUSPOW),
+	  .EMIOSDIO0CLK		   (SDIO0_CLK   ),
+	  .EMIOSDIO0CMDO	   (SDIO0_CMD_O ),
+	  .EMIOSDIO0CMDTN	   (SDIO0_CMD_T_n ),
+	  .EMIOSDIO0DATAO	   (SDIO0_DATA_O),
+	  .EMIOSDIO0DATATN	   (SDIO0_DATA_T_n),
+	  .EMIOSDIO0LED            (SDIO0_LED),
+	  .EMIOSDIO1BUSPOW         (SDIO1_BUSPOW),  
+	  .EMIOSDIO1CLK            (SDIO1_CLK   ),
+	  .EMIOSDIO1CMDO           (SDIO1_CMD_O ),
+	  .EMIOSDIO1CMDTN          (SDIO1_CMD_T_n ),
+	  .EMIOSDIO1DATAO          (SDIO1_DATA_O),
+	  .EMIOSDIO1DATATN         (SDIO1_DATA_T_n),
+	  .EMIOSDIO1LED            (SDIO1_LED),  
+	  .EMIOSPI0MO		   (SPI0_MOSI_O),
+	  .EMIOSPI0MOTN	           (SPI0_MOSI_T_n),
+	  .EMIOSPI0SCLKO	   (SPI0_SCLK_O),
+	  .EMIOSPI0SCLKTN	   (SPI0_SCLK_T_n),
+	  .EMIOSPI0SO		   (SPI0_MISO_O),
+	  .EMIOSPI0STN	           (SPI0_MISO_T_n),
+	  .EMIOSPI0SSON	           ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
+	  .EMIOSPI0SSNTN	   (SPI0_SS_T_n),
+	  .EMIOSPI1MO		   (SPI1_MOSI_O),
+	  .EMIOSPI1MOTN	           (SPI1_MOSI_T_n),
+	  .EMIOSPI1SCLKO	   (SPI1_SCLK_O),
+	  .EMIOSPI1SCLKTN	   (SPI1_SCLK_T_n),
+	  .EMIOSPI1SO		   (SPI1_MISO_O),
+	  .EMIOSPI1STN	           (SPI1_MISO_T_n),
+	  .EMIOSPI1SSON	           ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
+	  .EMIOSPI1SSNTN	   (SPI1_SS_T_n),
+	  .EMIOTRACECTL		   (TRACE_CTL_i),
+	  .EMIOTRACEDATA	   (TRACE_DATA_i),
+	  .EMIOTTC0WAVEO	   ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
+	  .EMIOTTC1WAVEO	   ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
+	  .EMIOUART0DTRN	   (UART0_DTRN),
+	  .EMIOUART0RTSN	   (UART0_RTSN),
+	  .EMIOUART0TX		   (UART0_TX  ),
+	  .EMIOUART1DTRN	   (UART1_DTRN),
+	  .EMIOUART1RTSN	   (UART1_RTSN),
+	  .EMIOUART1TX		   (UART1_TX  ),
+	  .EMIOUSB0PORTINDCTL      (USB0_PORT_INDCTL),  
+	  .EMIOUSB0VBUSPWRSELECT   (USB0_VBUS_PWRSELECT),
+	  .EMIOUSB1PORTINDCTL      (USB1_PORT_INDCTL),
+	  .EMIOUSB1VBUSPWRSELECT   (USB1_VBUS_PWRSELECT),  
+	  .EMIOWDTRSTO    	   (WDT_RST_OUT),
+	  .EVENTEVENTO             (EVENT_EVENTO),
+	  .EVENTSTANDBYWFE         (EVENT_STANDBYWFE),
+	  .EVENTSTANDBYWFI         (EVENT_STANDBYWFI),  
+	  .FCLKCLK		   (FCLK_CLK_unbuffered),
+	  .FCLKRESETN		   ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),  
+	  .EMIOSDIO0BUSVOLT        (SDIO0_BUSVOLT), 
+	  .EMIOSDIO1BUSVOLT        (SDIO1_BUSVOLT),  
+	  .FTMTF2PTRIGACK	   ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
+	  .FTMTP2FDEBUG		   (FTMT_P2F_DEBUG  ),
+	  .FTMTP2FTRIG		   ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
+	  .IRQP2F		   ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),    
+	  .MAXIGP0ARADDR	   (M_AXI_GP0_ARADDR),
+	  .MAXIGP0ARBURST	   (M_AXI_GP0_ARBURST),
+	  .MAXIGP0ARCACHE	   (M_AXI_GP0_ARCACHE_t),
+	  .MAXIGP0ARESETN	   (M_AXI_GP0_ARESETN),
+	  .MAXIGP0ARID	           (M_AXI_GP0_ARID_FULL   ),
+	  .MAXIGP0ARLEN	           (M_AXI_GP0_ARLEN  ),
+	  .MAXIGP0ARLOCK	   (M_AXI_GP0_ARLOCK ),
+	  .MAXIGP0ARPROT	   (M_AXI_GP0_ARPROT ),
+	  .MAXIGP0ARQOS	           (M_AXI_GP0_ARQOS  ),
+	  .MAXIGP0ARSIZE	   (M_AXI_GP0_ARSIZE_i ),
+	  .MAXIGP0ARVALID	   (M_AXI_GP0_ARVALID),
+	  .MAXIGP0AWADDR	   (M_AXI_GP0_AWADDR ),
+	  .MAXIGP0AWBURST	   (M_AXI_GP0_AWBURST),
+	  .MAXIGP0AWCACHE	   (M_AXI_GP0_AWCACHE_t),
+	  .MAXIGP0AWID	           (M_AXI_GP0_AWID_FULL   ),
+	  .MAXIGP0AWLEN	           (M_AXI_GP0_AWLEN  ),
+	  .MAXIGP0AWLOCK	   (M_AXI_GP0_AWLOCK ),
+	  .MAXIGP0AWPROT	   (M_AXI_GP0_AWPROT ),
+	  .MAXIGP0AWQOS	           (M_AXI_GP0_AWQOS  ),
+	  .MAXIGP0AWSIZE	   (M_AXI_GP0_AWSIZE_i ),
+	  .MAXIGP0AWVALID	   (M_AXI_GP0_AWVALID),
+	  .MAXIGP0BREADY	   (M_AXI_GP0_BREADY ),
+	  .MAXIGP0RREADY	   (M_AXI_GP0_RREADY ),
+	  .MAXIGP0WDATA	           (M_AXI_GP0_WDATA  ),
+	  .MAXIGP0WID	           (M_AXI_GP0_WID_FULL    ),
+	  .MAXIGP0WLAST	           (M_AXI_GP0_WLAST  ),
+	  .MAXIGP0WSTRB	           (M_AXI_GP0_WSTRB  ),
+	  .MAXIGP0WVALID	   (M_AXI_GP0_WVALID ),
+	  .MAXIGP1ARADDR	   (M_AXI_GP1_ARADDR ),
+	  .MAXIGP1ARBURST	   (M_AXI_GP1_ARBURST),
+	  .MAXIGP1ARCACHE	   (M_AXI_GP1_ARCACHE_t),
+	  .MAXIGP1ARESETN	   (M_AXI_GP1_ARESETN),
+	  .MAXIGP1ARID	           (M_AXI_GP1_ARID_FULL   ),
+	  .MAXIGP1ARLEN	           (M_AXI_GP1_ARLEN  ),
+	  .MAXIGP1ARLOCK	   (M_AXI_GP1_ARLOCK ),
+	  .MAXIGP1ARPROT	   (M_AXI_GP1_ARPROT ),
+	  .MAXIGP1ARQOS	           (M_AXI_GP1_ARQOS  ),
+	  .MAXIGP1ARSIZE	   (M_AXI_GP1_ARSIZE_i ),
+	  .MAXIGP1ARVALID	   (M_AXI_GP1_ARVALID),
+	  .MAXIGP1AWADDR	   (M_AXI_GP1_AWADDR ),
+	  .MAXIGP1AWBURST	   (M_AXI_GP1_AWBURST),
+	  .MAXIGP1AWCACHE	   (M_AXI_GP1_AWCACHE_t),
+	  .MAXIGP1AWID	           (M_AXI_GP1_AWID_FULL   ),
+	  .MAXIGP1AWLEN	           (M_AXI_GP1_AWLEN  ),
+	  .MAXIGP1AWLOCK	   (M_AXI_GP1_AWLOCK ),
+	  .MAXIGP1AWPROT	   (M_AXI_GP1_AWPROT ),
+	  .MAXIGP1AWQOS	           (M_AXI_GP1_AWQOS  ),
+	  .MAXIGP1AWSIZE	   (M_AXI_GP1_AWSIZE_i ),
+	  .MAXIGP1AWVALID	   (M_AXI_GP1_AWVALID),
+	  .MAXIGP1BREADY	   (M_AXI_GP1_BREADY ),
+	  .MAXIGP1RREADY	   (M_AXI_GP1_RREADY ),
+	  .MAXIGP1WDATA	           (M_AXI_GP1_WDATA  ),
+	  .MAXIGP1WID	           (M_AXI_GP1_WID_FULL    ),
+	  .MAXIGP1WLAST	           (M_AXI_GP1_WLAST  ),
+	  .MAXIGP1WSTRB	           (M_AXI_GP1_WSTRB  ),
+	  .MAXIGP1WVALID	   (M_AXI_GP1_WVALID ),
+	  .SAXIACPARESETN	   (S_AXI_ACP_ARESETN),
+	  .SAXIACPARREADY	   (SAXIACPARREADY_W),
+	  .SAXIACPAWREADY	   (SAXIACPAWREADY_W),
+	  .SAXIACPBID	           (S_AXI_ACP_BID_out    ),
+	  .SAXIACPBRESP	           (SAXIACPBRESP_W  ),
+	  .SAXIACPBVALID	   (SAXIACPBVALID_W ),
+	  .SAXIACPRDATA	           (SAXIACPRDATA_W  ),
+	  .SAXIACPRID	           (S_AXI_ACP_RID_out),
+	  .SAXIACPRLAST	           (SAXIACPRLAST_W  ),
+	  .SAXIACPRRESP	           (SAXIACPRRESP_W  ),
+	  .SAXIACPRVALID	   (SAXIACPRVALID_W ),
+	  .SAXIACPWREADY	   (SAXIACPWREADY_W ),
+	  .SAXIGP0ARESETN	   (S_AXI_GP0_ARESETN),
+	  .SAXIGP0ARREADY	   (S_AXI_GP0_ARREADY),
+	  .SAXIGP0AWREADY	   (S_AXI_GP0_AWREADY),
+	  .SAXIGP0BID	           (S_AXI_GP0_BID_out),
+	  .SAXIGP0BRESP	           (S_AXI_GP0_BRESP  ),
+	  .SAXIGP0BVALID	   (S_AXI_GP0_BVALID ),
+	  .SAXIGP0RDATA	           (S_AXI_GP0_RDATA  ),
+	  .SAXIGP0RID	           (S_AXI_GP0_RID_out ),
+	  .SAXIGP0RLAST	           (S_AXI_GP0_RLAST  ),
+	  .SAXIGP0RRESP	           (S_AXI_GP0_RRESP  ),
+	  .SAXIGP0RVALID	   (S_AXI_GP0_RVALID ),
+	  .SAXIGP0WREADY	   (S_AXI_GP0_WREADY ),
+	  .SAXIGP1ARESETN	   (S_AXI_GP1_ARESETN),
+	  .SAXIGP1ARREADY	   (S_AXI_GP1_ARREADY),
+	  .SAXIGP1AWREADY	   (S_AXI_GP1_AWREADY),
+	  .SAXIGP1BID	           (S_AXI_GP1_BID_out    ),
+	  .SAXIGP1BRESP	           (S_AXI_GP1_BRESP  ),
+	  .SAXIGP1BVALID	   (S_AXI_GP1_BVALID ),
+	  .SAXIGP1RDATA	           (S_AXI_GP1_RDATA  ),
+	  .SAXIGP1RID	           (S_AXI_GP1_RID_out    ),
+	  .SAXIGP1RLAST	           (S_AXI_GP1_RLAST  ),
+	  .SAXIGP1RRESP	           (S_AXI_GP1_RRESP  ),
+	  .SAXIGP1RVALID	   (S_AXI_GP1_RVALID ),
+	  .SAXIGP1WREADY	   (S_AXI_GP1_WREADY ),
+	  .SAXIHP0ARESETN	   (S_AXI_HP0_ARESETN),
+	  .SAXIHP0ARREADY	   (S_AXI_HP0_ARREADY),
+	  .SAXIHP0AWREADY	   (S_AXI_HP0_AWREADY),
+	  .SAXIHP0BID	           (S_AXI_HP0_BID_out    ),
+	  .SAXIHP0BRESP	           (S_AXI_HP0_BRESP  ),
+	  .SAXIHP0BVALID	   (S_AXI_HP0_BVALID ),
+	  .SAXIHP0RACOUNT          (S_AXI_HP0_RACOUNT),
+	  .SAXIHP0RCOUNT	   (S_AXI_HP0_RCOUNT),
+	  .SAXIHP0RDATA	           (S_AXI_HP0_RDATA_out),
+	  .SAXIHP0RID	           (S_AXI_HP0_RID_out ),
+	  .SAXIHP0RLAST	           (S_AXI_HP0_RLAST),
+	  .SAXIHP0RRESP	           (S_AXI_HP0_RRESP),
+	  .SAXIHP0RVALID	   (S_AXI_HP0_RVALID),
+	  .SAXIHP0WCOUNT	   (S_AXI_HP0_WCOUNT),
+	  .SAXIHP0WACOUNT          (S_AXI_HP0_WACOUNT),  
+	  .SAXIHP0WREADY	   (S_AXI_HP0_WREADY),
+	  .SAXIHP1ARESETN	   (S_AXI_HP1_ARESETN),
+	  .SAXIHP1ARREADY	   (S_AXI_HP1_ARREADY),
+	  .SAXIHP1AWREADY	   (S_AXI_HP1_AWREADY),
+	  .SAXIHP1BID	           (S_AXI_HP1_BID_out    ),
+	  .SAXIHP1BRESP	           (S_AXI_HP1_BRESP  ),
+	  .SAXIHP1BVALID	   (S_AXI_HP1_BVALID ),
+	  .SAXIHP1RACOUNT	   (S_AXI_HP1_RACOUNT ),  
+	  .SAXIHP1RCOUNT	   (S_AXI_HP1_RCOUNT ),
+	  .SAXIHP1RDATA	           (S_AXI_HP1_RDATA_out),
+	  .SAXIHP1RID	           (S_AXI_HP1_RID_out    ),
+	  .SAXIHP1RLAST	           (S_AXI_HP1_RLAST  ),
+	  .SAXIHP1RRESP	           (S_AXI_HP1_RRESP  ),
+	  .SAXIHP1RVALID	   (S_AXI_HP1_RVALID),
+	  .SAXIHP1WACOUNT	   (S_AXI_HP1_WACOUNT),  
+	  .SAXIHP1WCOUNT	   (S_AXI_HP1_WCOUNT),
+	  .SAXIHP1WREADY	   (S_AXI_HP1_WREADY),
+	  .SAXIHP2ARESETN	   (S_AXI_HP2_ARESETN),
+	  .SAXIHP2ARREADY	   (S_AXI_HP2_ARREADY),
+	  .SAXIHP2AWREADY	   (S_AXI_HP2_AWREADY),
+	  .SAXIHP2BID	           (S_AXI_HP2_BID_out ),
+	  .SAXIHP2BRESP	           (S_AXI_HP2_BRESP),
+	  .SAXIHP2BVALID	   (S_AXI_HP2_BVALID),
+	  .SAXIHP2RACOUNT	   (S_AXI_HP2_RACOUNT),  
+	  .SAXIHP2RCOUNT	   (S_AXI_HP2_RCOUNT),
+	  .SAXIHP2RDATA	           (S_AXI_HP2_RDATA_out),
+	  .SAXIHP2RID	           (S_AXI_HP2_RID_out ),
+	  .SAXIHP2RLAST	           (S_AXI_HP2_RLAST),
+	  .SAXIHP2RRESP	           (S_AXI_HP2_RRESP),
+	  .SAXIHP2RVALID	   (S_AXI_HP2_RVALID),
+	  .SAXIHP2WACOUNT	   (S_AXI_HP2_WACOUNT),  
+	  .SAXIHP2WCOUNT	   (S_AXI_HP2_WCOUNT),
+	  .SAXIHP2WREADY	   (S_AXI_HP2_WREADY),
+	  .SAXIHP3ARESETN	   (S_AXI_HP3_ARESETN),
+	  .SAXIHP3ARREADY	   (S_AXI_HP3_ARREADY),
+	  .SAXIHP3AWREADY	   (S_AXI_HP3_AWREADY),
+	  .SAXIHP3BID	           (S_AXI_HP3_BID_out),
+	  .SAXIHP3BRESP	           (S_AXI_HP3_BRESP),
+	  .SAXIHP3BVALID	   (S_AXI_HP3_BVALID),
+	  .SAXIHP3RACOUNT	   (S_AXI_HP3_RACOUNT),    
+	  .SAXIHP3RCOUNT	   (S_AXI_HP3_RCOUNT),
+	  .SAXIHP3RDATA	           (S_AXI_HP3_RDATA_out),
+	  .SAXIHP3RID	           (S_AXI_HP3_RID_out),
+	  .SAXIHP3RLAST	           (S_AXI_HP3_RLAST),
+	  .SAXIHP3RRESP	           (S_AXI_HP3_RRESP),
+	  .SAXIHP3RVALID	   (S_AXI_HP3_RVALID),
+	  .SAXIHP3WCOUNT	   (S_AXI_HP3_WCOUNT),
+	  .SAXIHP3WACOUNT	   (S_AXI_HP3_WACOUNT),    
+	  .SAXIHP3WREADY	   (S_AXI_HP3_WREADY), 
+	  .DDRARB                  (DDR_ARB), 
+	  .DMA0ACLK		   (DMA0_ACLK   ),
+	  .DMA0DAREADY		   (DMA0_DAREADY),
+	  .DMA0DRLAST		   (DMA0_DRLAST ),
+	  .DMA0DRTYPE              (DMA0_DRTYPE),
+	  .DMA0DRVALID		   (DMA0_DRVALID),
+	  .DMA1ACLK		   (DMA1_ACLK   ),
+	  .DMA1DAREADY		   (DMA1_DAREADY),
+	  .DMA1DRLAST		   (DMA1_DRLAST ),
+	  .DMA1DRTYPE              (DMA1_DRTYPE),  
+	  .DMA1DRVALID		   (DMA1_DRVALID),
+	  .DMA2ACLK		   (DMA2_ACLK   ),
+	  .DMA2DAREADY		   (DMA2_DAREADY),
+	  .DMA2DRLAST		   (DMA2_DRLAST ),
+	  .DMA2DRTYPE              (DMA2_DRTYPE),    
+	  .DMA2DRVALID		   (DMA2_DRVALID),
+	  .DMA3ACLK		   (DMA3_ACLK   ),
+	  .DMA3DAREADY		   (DMA3_DAREADY),
+	  .DMA3DRLAST		   (DMA3_DRLAST ),
+	  .DMA3DRTYPE              (DMA3_DRTYPE),      
+	  .DMA3DRVALID		   (DMA3_DRVALID),
+	  .EMIOCAN0PHYRX	   (CAN0_PHY_RX),  
+	  .EMIOCAN1PHYRX	   (CAN1_PHY_RX),
+	  .EMIOENET0EXTINTIN       (ENET0_EXT_INTIN),  
+	  .EMIOENET0GMIICOL        (ENET0_GMII_COL_i),
+	  .EMIOENET0GMIICRS        (ENET0_GMII_CRS_i),
+	  .EMIOENET0GMIIRXCLK      (ENET0_GMII_RX_CLK),
+	  .EMIOENET0GMIIRXD        (ENET0_GMII_RXD_i),
+	  .EMIOENET0GMIIRXDV       (ENET0_GMII_RX_DV_i),
+	  .EMIOENET0GMIIRXER       (ENET0_GMII_RX_ER_i),
+	  .EMIOENET0GMIITXCLK      (ENET0_GMII_TX_CLK),
+	  .EMIOENET0MDIOI          (ENET0_MDIO_I),
+	  .EMIOENET1EXTINTIN       (ENET1_EXT_INTIN),    
+	  .EMIOENET1GMIICOL        (ENET1_GMII_COL_i),
+	  .EMIOENET1GMIICRS        (ENET1_GMII_CRS_i),
+	  .EMIOENET1GMIIRXCLK      (ENET1_GMII_RX_CLK),
+	  .EMIOENET1GMIIRXD        (ENET1_GMII_RXD_i),
+	  .EMIOENET1GMIIRXDV       (ENET1_GMII_RX_DV_i),
+	  .EMIOENET1GMIIRXER       (ENET1_GMII_RX_ER_i),
+	  .EMIOENET1GMIITXCLK      (ENET1_GMII_TX_CLK),
+	  .EMIOENET1MDIOI          (ENET1_MDIO_I),  
+	  .EMIOGPIOI	           (gpio_in63_0  ),
+	  .EMIOI2C0SCLI	           (I2C0_SCL_I),
+	  .EMIOI2C0SDAI	           (I2C0_SDA_I),
+	  .EMIOI2C1SCLI	           (I2C1_SCL_I),
+	  .EMIOI2C1SDAI	           (I2C1_SDA_I),
+	  .EMIOPJTAGTCK		   (PJTAG_TCK),
+	  .EMIOPJTAGTDI		   (PJTAG_TDI),
+	  .EMIOPJTAGTMS		   (PJTAG_TMS),
+	  .EMIOSDIO0CDN            (SDIO0_CDN),
+	  .EMIOSDIO0CLKFB	   (SDIO0_CLK_FB  ),
+	  .EMIOSDIO0CMDI	   (SDIO0_CMD_I   ),
+	  .EMIOSDIO0DATAI	   (SDIO0_DATA_I  ),
+	  .EMIOSDIO0WP             (SDIO0_WP),
+	  .EMIOSDIO1CDN            (SDIO1_CDN),  
+	  .EMIOSDIO1CLKFB	   (SDIO1_CLK_FB  ),
+	  .EMIOSDIO1CMDI	   (SDIO1_CMD_I   ),
+	  .EMIOSDIO1DATAI	   (SDIO1_DATA_I  ),
+	  .EMIOSDIO1WP             (SDIO1_WP),
+	  .EMIOSPI0MI		   (SPI0_MISO_I),
+	  .EMIOSPI0SCLKI	   (SPI0_SCLK_I),
+	  .EMIOSPI0SI		   (SPI0_MOSI_I),
+	  .EMIOSPI0SSIN 	   (SPI0_SS_I),
+	  .EMIOSPI1MI		   (SPI1_MISO_I),
+	  .EMIOSPI1SCLKI	   (SPI1_SCLK_I),
+	  .EMIOSPI1SI		   (SPI1_MOSI_I),
+	  .EMIOSPI1SSIN	           (SPI1_SS_I),
+	  .EMIOSRAMINTIN           (SRAM_INTIN),  
+	  .EMIOTRACECLK		   (TRACE_CLK),
+	  .EMIOTTC0CLKI	           ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
+	  .EMIOTTC1CLKI	           ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
+	  .EMIOUART0CTSN	   (UART0_CTSN),
+	  .EMIOUART0DCDN	   (UART0_DCDN),
+	  .EMIOUART0DSRN	   (UART0_DSRN),
+	  .EMIOUART0RIN		   (UART0_RIN ),
+	  .EMIOUART0RX		   (UART0_RX  ),
+	  .EMIOUART1CTSN	   (UART1_CTSN),
+	  .EMIOUART1DCDN	   (UART1_DCDN),
+	  .EMIOUART1DSRN	   (UART1_DSRN),
+	  .EMIOUART1RIN		   (UART1_RIN ),
+	  .EMIOUART1RX		   (UART1_RX  ),
+	  .EMIOUSB0VBUSPWRFAULT    (USB0_VBUS_PWRFAULT),
+	  .EMIOUSB1VBUSPWRFAULT    (USB1_VBUS_PWRFAULT),  
+	  .EMIOWDTCLKI		   (WDT_CLK_IN),  
+	  .EVENTEVENTI             (EVENT_EVENTI),
+	  .FCLKCLKTRIGN		   (fclk_clktrig_gnd),
+	  .FPGAIDLEN		   (FPGA_IDLE_N),  
+	  .FTMDTRACEINATID	   (FTMD_TRACEIN_ATID_i),  
+	  .FTMDTRACEINCLOCK	   (FTMD_TRACEIN_CLK),
+	  .FTMDTRACEINDATA	   (FTMD_TRACEIN_DATA_i),
+	  .FTMDTRACEINVALID	   (FTMD_TRACEIN_VALID_i),
+	  .FTMTF2PDEBUG		   (FTMT_F2P_DEBUG  ),
+	  .FTMTF2PTRIG		   ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
+	  .FTMTP2FTRIGACK	   ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),  
+	  .IRQF2P		   (irq_f2p_i),  
+	  .MAXIGP0ACLK	           (M_AXI_GP0_ACLK_temp),
+	  .MAXIGP0ARREADY	   (M_AXI_GP0_ARREADY),
+	  .MAXIGP0AWREADY	   (M_AXI_GP0_AWREADY),
+	  .MAXIGP0BID	           (M_AXI_GP0_BID_FULL    ),
+	  .MAXIGP0BRESP	           (M_AXI_GP0_BRESP  ),
+	  .MAXIGP0BVALID	   (M_AXI_GP0_BVALID ),
+	  .MAXIGP0RDATA	           (M_AXI_GP0_RDATA  ),
+	  .MAXIGP0RID	           (M_AXI_GP0_RID_FULL    ),
+	  .MAXIGP0RLAST	           (M_AXI_GP0_RLAST  ),
+	  .MAXIGP0RRESP	           (M_AXI_GP0_RRESP  ),
+	  .MAXIGP0RVALID	   (M_AXI_GP0_RVALID ),
+	  .MAXIGP0WREADY	   (M_AXI_GP0_WREADY ),
+	  .MAXIGP1ACLK	           (M_AXI_GP1_ACLK_temp ),
+	  .MAXIGP1ARREADY	   (M_AXI_GP1_ARREADY),
+	  .MAXIGP1AWREADY	   (M_AXI_GP1_AWREADY),
+	  .MAXIGP1BID	           (M_AXI_GP1_BID_FULL ),
+	  .MAXIGP1BRESP	           (M_AXI_GP1_BRESP  ),
+	  .MAXIGP1BVALID	   (M_AXI_GP1_BVALID ),
+	  .MAXIGP1RDATA	           (M_AXI_GP1_RDATA  ),
+	  .MAXIGP1RID	           (M_AXI_GP1_RID_FULL    ),
+	  .MAXIGP1RLAST	           (M_AXI_GP1_RLAST  ),
+	  .MAXIGP1RRESP	           (M_AXI_GP1_RRESP  ),
+	  .MAXIGP1RVALID	   (M_AXI_GP1_RVALID ),
+	  .MAXIGP1WREADY	   (M_AXI_GP1_WREADY ),  
+	  .SAXIACPACLK	           (S_AXI_ACP_ACLK_temp),
+	  .SAXIACPARADDR	   (SAXIACPARADDR_W ),
+	  .SAXIACPARBURST	   (SAXIACPARBURST_W),
+	  .SAXIACPARCACHE	   (SAXIACPARCACHE_W),
+	  .SAXIACPARID	           (S_AXI_ACP_ARID_in   ),
+	  .SAXIACPARLEN	           (SAXIACPARLEN_W  ),
+	  .SAXIACPARLOCK	   (SAXIACPARLOCK_W ),
+	  .SAXIACPARPROT	   (SAXIACPARPROT_W ),
+	  .SAXIACPARQOS	           (S_AXI_ACP_ARQOS  ),
+	  .SAXIACPARSIZE	   (SAXIACPARSIZE_W[1:0] ),
+	  .SAXIACPARUSER	   (SAXIACPARUSER_W ),
+	  .SAXIACPARVALID	   (SAXIACPARVALID_W),
+	  .SAXIACPAWADDR	   (SAXIACPAWADDR_W ),
+	  .SAXIACPAWBURST	   (SAXIACPAWBURST_W),
+	  .SAXIACPAWCACHE	   (SAXIACPAWCACHE_W),
+	  .SAXIACPAWID	           (S_AXI_ACP_AWID_in   ),
+	  .SAXIACPAWLEN	           (SAXIACPAWLEN_W  ),
+	  .SAXIACPAWLOCK	   (SAXIACPAWLOCK_W ),
+	  .SAXIACPAWPROT	   (SAXIACPAWPROT_W ),
+	  .SAXIACPAWQOS	           (S_AXI_ACP_AWQOS  ),
+	  .SAXIACPAWSIZE	   (SAXIACPAWSIZE_W[1:0] ),
+	  .SAXIACPAWUSER	   (SAXIACPAWUSER_W ),
+	  .SAXIACPAWVALID	   (SAXIACPAWVALID_W),
+	  .SAXIACPBREADY	   (SAXIACPBREADY_W ),
+	  .SAXIACPRREADY	   (SAXIACPRREADY_W ),
+	  .SAXIACPWDATA	           (SAXIACPWDATA_W  ),
+	  .SAXIACPWID	           (S_AXI_ACP_WID_in    ),
+	  .SAXIACPWLAST	           (SAXIACPWLAST_W  ),
+	  .SAXIACPWSTRB	           (SAXIACPWSTRB_W  ),
+	  .SAXIACPWVALID	   (SAXIACPWVALID_W ),
+	  .SAXIGP0ACLK             (S_AXI_GP0_ACLK_temp   ),
+	  .SAXIGP0ARADDR           (S_AXI_GP0_ARADDR ),
+	  .SAXIGP0ARBURST          (S_AXI_GP0_ARBURST),
+	  .SAXIGP0ARCACHE          (S_AXI_GP0_ARCACHE),
+	  .SAXIGP0ARID             (S_AXI_GP0_ARID_in   ),
+	  .SAXIGP0ARLEN            (S_AXI_GP0_ARLEN  ),
+	  .SAXIGP0ARLOCK           (S_AXI_GP0_ARLOCK ),
+	  .SAXIGP0ARPROT           (S_AXI_GP0_ARPROT ),
+	  .SAXIGP0ARQOS            (S_AXI_GP0_ARQOS  ),
+	  .SAXIGP0ARSIZE           (S_AXI_GP0_ARSIZE[1:0] ),
+	  .SAXIGP0ARVALID          (S_AXI_GP0_ARVALID),
+	  .SAXIGP0AWADDR           (S_AXI_GP0_AWADDR ),
+	  .SAXIGP0AWBURST          (S_AXI_GP0_AWBURST),
+	  .SAXIGP0AWCACHE          (S_AXI_GP0_AWCACHE),
+	  .SAXIGP0AWID             (S_AXI_GP0_AWID_in   ),
+	  .SAXIGP0AWLEN            (S_AXI_GP0_AWLEN  ),
+	  .SAXIGP0AWLOCK           (S_AXI_GP0_AWLOCK ),
+	  .SAXIGP0AWPROT           (S_AXI_GP0_AWPROT ),
+	  .SAXIGP0AWQOS            (S_AXI_GP0_AWQOS  ),
+	  .SAXIGP0AWSIZE           (S_AXI_GP0_AWSIZE[1:0] ),
+	  .SAXIGP0AWVALID          (S_AXI_GP0_AWVALID),
+	  .SAXIGP0BREADY           (S_AXI_GP0_BREADY ),
+	  .SAXIGP0RREADY           (S_AXI_GP0_RREADY ),
+	  .SAXIGP0WDATA            (S_AXI_GP0_WDATA  ),
+	  .SAXIGP0WID              (S_AXI_GP0_WID_in ),
+	  .SAXIGP0WLAST            (S_AXI_GP0_WLAST  ),
+	  .SAXIGP0WSTRB            (S_AXI_GP0_WSTRB  ),
+	  .SAXIGP0WVALID           (S_AXI_GP0_WVALID ),
+	  .SAXIGP1ACLK	           (S_AXI_GP1_ACLK_temp   ),
+	  .SAXIGP1ARADDR	   (S_AXI_GP1_ARADDR ),
+	  .SAXIGP1ARBURST	   (S_AXI_GP1_ARBURST),
+	  .SAXIGP1ARCACHE	   (S_AXI_GP1_ARCACHE),
+	  .SAXIGP1ARID	           (S_AXI_GP1_ARID_in   ),
+	  .SAXIGP1ARLEN	           (S_AXI_GP1_ARLEN  ),
+	  .SAXIGP1ARLOCK	   (S_AXI_GP1_ARLOCK ),
+	  .SAXIGP1ARPROT	   (S_AXI_GP1_ARPROT ),
+	  .SAXIGP1ARQOS	           (S_AXI_GP1_ARQOS  ),
+	  .SAXIGP1ARSIZE	   (S_AXI_GP1_ARSIZE[1:0] ),
+	  .SAXIGP1ARVALID	   (S_AXI_GP1_ARVALID),
+	  .SAXIGP1AWADDR	   (S_AXI_GP1_AWADDR ),
+	  .SAXIGP1AWBURST	   (S_AXI_GP1_AWBURST),
+	  .SAXIGP1AWCACHE	   (S_AXI_GP1_AWCACHE),
+	  .SAXIGP1AWID	           (S_AXI_GP1_AWID_in   ),
+	  .SAXIGP1AWLEN	           (S_AXI_GP1_AWLEN  ),
+	  .SAXIGP1AWLOCK	   (S_AXI_GP1_AWLOCK ),
+	  .SAXIGP1AWPROT	   (S_AXI_GP1_AWPROT ),
+	  .SAXIGP1AWQOS	           (S_AXI_GP1_AWQOS  ),
+	  .SAXIGP1AWSIZE	   (S_AXI_GP1_AWSIZE[1:0] ),
+	  .SAXIGP1AWVALID	   (S_AXI_GP1_AWVALID),
+	  .SAXIGP1BREADY	   (S_AXI_GP1_BREADY ),
+	  .SAXIGP1RREADY	   (S_AXI_GP1_RREADY ),
+	  .SAXIGP1WDATA	           (S_AXI_GP1_WDATA  ),
+	  .SAXIGP1WID	           (S_AXI_GP1_WID_in    ),
+	  .SAXIGP1WLAST	           (S_AXI_GP1_WLAST  ),
+	  .SAXIGP1WSTRB	           (S_AXI_GP1_WSTRB  ),
+	  .SAXIGP1WVALID	   (S_AXI_GP1_WVALID ),  
+	  .SAXIHP0ACLK             (S_AXI_HP0_ACLK_temp   ),
+	  .SAXIHP0ARADDR           (S_AXI_HP0_ARADDR),
+	  .SAXIHP0ARBURST          (S_AXI_HP0_ARBURST),
+	  .SAXIHP0ARCACHE          (S_AXI_HP0_ARCACHE),
+	  .SAXIHP0ARID             (S_AXI_HP0_ARID_in),
+	  .SAXIHP0ARLEN            (S_AXI_HP0_ARLEN),
+	  .SAXIHP0ARLOCK           (S_AXI_HP0_ARLOCK),
+	  .SAXIHP0ARPROT           (S_AXI_HP0_ARPROT),
+	  .SAXIHP0ARQOS            (S_AXI_HP0_ARQOS),
+	  .SAXIHP0ARSIZE           (S_AXI_HP0_ARSIZE[1:0]),
+	  .SAXIHP0ARVALID          (S_AXI_HP0_ARVALID),
+	  .SAXIHP0AWADDR           (S_AXI_HP0_AWADDR),
+	  .SAXIHP0AWBURST          (S_AXI_HP0_AWBURST),
+	  .SAXIHP0AWCACHE          (S_AXI_HP0_AWCACHE),
+	  .SAXIHP0AWID             (S_AXI_HP0_AWID_in),
+	  .SAXIHP0AWLEN            (S_AXI_HP0_AWLEN),
+	  .SAXIHP0AWLOCK           (S_AXI_HP0_AWLOCK),
+	  .SAXIHP0AWPROT           (S_AXI_HP0_AWPROT),
+	  .SAXIHP0AWQOS            (S_AXI_HP0_AWQOS),
+	  .SAXIHP0AWSIZE           (S_AXI_HP0_AWSIZE[1:0]),
+	  .SAXIHP0AWVALID          (S_AXI_HP0_AWVALID),
+	  .SAXIHP0BREADY           (S_AXI_HP0_BREADY),
+	  .SAXIHP0RDISSUECAP1EN    (S_AXI_HP0_RDISSUECAP1_EN),
+	  .SAXIHP0RREADY           (S_AXI_HP0_RREADY),
+	  .SAXIHP0WDATA            (S_AXI_HP0_WDATA_in),
+	  .SAXIHP0WID              (S_AXI_HP0_WID_in),
+	  .SAXIHP0WLAST            (S_AXI_HP0_WLAST),
+	  .SAXIHP0WRISSUECAP1EN    (S_AXI_HP0_WRISSUECAP1_EN),
+	  .SAXIHP0WSTRB            (S_AXI_HP0_WSTRB_in),
+	  .SAXIHP0WVALID           (S_AXI_HP0_WVALID),
+	  .SAXIHP1ACLK             (S_AXI_HP1_ACLK_temp),
+	  .SAXIHP1ARADDR           (S_AXI_HP1_ARADDR),
+	  .SAXIHP1ARBURST          (S_AXI_HP1_ARBURST),
+	  .SAXIHP1ARCACHE          (S_AXI_HP1_ARCACHE),
+	  .SAXIHP1ARID             (S_AXI_HP1_ARID_in),
+	  .SAXIHP1ARLEN            (S_AXI_HP1_ARLEN),
+	  .SAXIHP1ARLOCK           (S_AXI_HP1_ARLOCK),
+	  .SAXIHP1ARPROT           (S_AXI_HP1_ARPROT),
+	  .SAXIHP1ARQOS            (S_AXI_HP1_ARQOS),
+	  .SAXIHP1ARSIZE           (S_AXI_HP1_ARSIZE[1:0]),
+	  .SAXIHP1ARVALID          (S_AXI_HP1_ARVALID),
+	  .SAXIHP1AWADDR           (S_AXI_HP1_AWADDR),
+	  .SAXIHP1AWBURST          (S_AXI_HP1_AWBURST),
+	  .SAXIHP1AWCACHE          (S_AXI_HP1_AWCACHE),
+	  .SAXIHP1AWID             (S_AXI_HP1_AWID_in),
+	  .SAXIHP1AWLEN            (S_AXI_HP1_AWLEN),
+	  .SAXIHP1AWLOCK           (S_AXI_HP1_AWLOCK),
+	  .SAXIHP1AWPROT           (S_AXI_HP1_AWPROT),
+	  .SAXIHP1AWQOS            (S_AXI_HP1_AWQOS),
+	  .SAXIHP1AWSIZE           (S_AXI_HP1_AWSIZE[1:0]),
+	  .SAXIHP1AWVALID          (S_AXI_HP1_AWVALID),
+	  .SAXIHP1BREADY           (S_AXI_HP1_BREADY),
+	  .SAXIHP1RDISSUECAP1EN    (S_AXI_HP1_RDISSUECAP1_EN),
+	  .SAXIHP1RREADY           (S_AXI_HP1_RREADY),
+	  .SAXIHP1WDATA            (S_AXI_HP1_WDATA_in),
+	  .SAXIHP1WID              (S_AXI_HP1_WID_in),
+	  .SAXIHP1WLAST            (S_AXI_HP1_WLAST),
+	  .SAXIHP1WRISSUECAP1EN    (S_AXI_HP1_WRISSUECAP1_EN),
+	  .SAXIHP1WSTRB            (S_AXI_HP1_WSTRB_in),
+	  .SAXIHP1WVALID           (S_AXI_HP1_WVALID),
+	  .SAXIHP2ACLK             (S_AXI_HP2_ACLK_temp),
+	  .SAXIHP2ARADDR           (S_AXI_HP2_ARADDR),
+	  .SAXIHP2ARBURST          (S_AXI_HP2_ARBURST),
+	  .SAXIHP2ARCACHE          (S_AXI_HP2_ARCACHE),
+	  .SAXIHP2ARID             (S_AXI_HP2_ARID_in),
+	  .SAXIHP2ARLEN            (S_AXI_HP2_ARLEN),
+	  .SAXIHP2ARLOCK           (S_AXI_HP2_ARLOCK),
+	  .SAXIHP2ARPROT           (S_AXI_HP2_ARPROT),
+	  .SAXIHP2ARQOS            (S_AXI_HP2_ARQOS),
+	  .SAXIHP2ARSIZE           (S_AXI_HP2_ARSIZE[1:0]),
+	  .SAXIHP2ARVALID          (S_AXI_HP2_ARVALID),
+	  .SAXIHP2AWADDR           (S_AXI_HP2_AWADDR),
+	  .SAXIHP2AWBURST          (S_AXI_HP2_AWBURST),
+	  .SAXIHP2AWCACHE          (S_AXI_HP2_AWCACHE),
+	  .SAXIHP2AWID             (S_AXI_HP2_AWID_in),
+	  .SAXIHP2AWLEN            (S_AXI_HP2_AWLEN),
+	  .SAXIHP2AWLOCK           (S_AXI_HP2_AWLOCK),
+	  .SAXIHP2AWPROT           (S_AXI_HP2_AWPROT),
+	  .SAXIHP2AWQOS            (S_AXI_HP2_AWQOS),
+	  .SAXIHP2AWSIZE           (S_AXI_HP2_AWSIZE[1:0]),
+	  .SAXIHP2AWVALID          (S_AXI_HP2_AWVALID),
+	  .SAXIHP2BREADY           (S_AXI_HP2_BREADY),
+	  .SAXIHP2RDISSUECAP1EN    (S_AXI_HP2_RDISSUECAP1_EN),
+	  .SAXIHP2RREADY           (S_AXI_HP2_RREADY),
+	  .SAXIHP2WDATA            (S_AXI_HP2_WDATA_in),
+	  .SAXIHP2WID              (S_AXI_HP2_WID_in),
+	  .SAXIHP2WLAST            (S_AXI_HP2_WLAST),
+	  .SAXIHP2WRISSUECAP1EN    (S_AXI_HP2_WRISSUECAP1_EN),
+	  .SAXIHP2WSTRB            (S_AXI_HP2_WSTRB_in),
+	  .SAXIHP2WVALID           (S_AXI_HP2_WVALID),  
+	  .SAXIHP3ACLK             (S_AXI_HP3_ACLK_temp),
+	  .SAXIHP3ARADDR           (S_AXI_HP3_ARADDR ),
+	  .SAXIHP3ARBURST          (S_AXI_HP3_ARBURST),
+	  .SAXIHP3ARCACHE          (S_AXI_HP3_ARCACHE),
+	  .SAXIHP3ARID             (S_AXI_HP3_ARID_in   ),
+	  .SAXIHP3ARLEN            (S_AXI_HP3_ARLEN),
+	  .SAXIHP3ARLOCK           (S_AXI_HP3_ARLOCK),
+	  .SAXIHP3ARPROT           (S_AXI_HP3_ARPROT),
+	  .SAXIHP3ARQOS            (S_AXI_HP3_ARQOS),
+	  .SAXIHP3ARSIZE           (S_AXI_HP3_ARSIZE[1:0]),
+	  .SAXIHP3ARVALID          (S_AXI_HP3_ARVALID),
+	  .SAXIHP3AWADDR           (S_AXI_HP3_AWADDR),
+	  .SAXIHP3AWBURST          (S_AXI_HP3_AWBURST),
+	  .SAXIHP3AWCACHE          (S_AXI_HP3_AWCACHE),
+	  .SAXIHP3AWID             (S_AXI_HP3_AWID_in),
+	  .SAXIHP3AWLEN            (S_AXI_HP3_AWLEN),
+	  .SAXIHP3AWLOCK           (S_AXI_HP3_AWLOCK),
+	  .SAXIHP3AWPROT           (S_AXI_HP3_AWPROT),
+	  .SAXIHP3AWQOS            (S_AXI_HP3_AWQOS),
+	  .SAXIHP3AWSIZE           (S_AXI_HP3_AWSIZE[1:0]),
+	  .SAXIHP3AWVALID          (S_AXI_HP3_AWVALID),
+	  .SAXIHP3BREADY           (S_AXI_HP3_BREADY),
+	  .SAXIHP3RDISSUECAP1EN    (S_AXI_HP3_RDISSUECAP1_EN),
+	  .SAXIHP3RREADY           (S_AXI_HP3_RREADY),
+	  .SAXIHP3WDATA            (S_AXI_HP3_WDATA_in),
+	  .SAXIHP3WID              (S_AXI_HP3_WID_in),
+	  .SAXIHP3WLAST            (S_AXI_HP3_WLAST),
+	  .SAXIHP3WRISSUECAP1EN    (S_AXI_HP3_WRISSUECAP1_EN),
+	  .SAXIHP3WSTRB            (S_AXI_HP3_WSTRB_in),
+	  .SAXIHP3WVALID           (S_AXI_HP3_WVALID),
+	  .DDRA		           (buffered_DDR_Addr),
+	  .DDRBA		   (buffered_DDR_BankAddr),
+	  .DDRCASB		   (buffered_DDR_CAS_n),
+	  .DDRCKE		   (buffered_DDR_CKE),
+	  .DDRCKN		   (buffered_DDR_Clk_n),
+	  .DDRCKP		   (buffered_DDR_Clk),
+	  .DDRCSB		   (buffered_DDR_CS_n),
+	  .DDRDM		   (buffered_DDR_DM),
+	  .DDRDQ		   (buffered_DDR_DQ),
+	  .DDRDQSN		   (buffered_DDR_DQS_n),
+	  .DDRDQSP		   (buffered_DDR_DQS),
+	  .DDRDRSTB                (buffered_DDR_DRSTB),
+	  .DDRODT		   (buffered_DDR_ODT),  
+	  .DDRRASB		   (buffered_DDR_RAS_n),
+	  .DDRVRN                  (buffered_DDR_VRN),
+	  .DDRVRP                  (buffered_DDR_VRP),
+	  .DDRWEB                  (buffered_DDR_WEB),
+	  .MIO			   (buffered_MIO),
+	  .PSCLK		   (buffered_PS_CLK),  
+	  .PSPORB		   (buffered_PS_PORB),  
+	  .PSSRSTB		   (buffered_PS_SRSTB)  
+	  
+
+	);
+ 	
+ end
+ endgenerate
+
+
+// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
+// Otherwise a master connected to the ACP port will drive the AxUSER Ports
+assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
+assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
+
+  assign  SAXIACPARADDR_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR  : S_AXI_ACP_ARADDR;
+  assign  SAXIACPARBURST_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
+  assign  SAXIACPARCACHE_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
+  assign  SAXIACPARLEN_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN   : S_AXI_ACP_ARLEN;
+  assign  SAXIACPARLOCK_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK  : S_AXI_ACP_ARLOCK;
+  assign  SAXIACPARPROT_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT  : S_AXI_ACP_ARPROT;
+  assign  SAXIACPARSIZE_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE  : S_AXI_ACP_ARSIZE;
+  //assign  SAXIACPARUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER  : S_AXI_ACP_ARUSER;
+  assign  SAXIACPARUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER  : param_aruser;
+  
+  assign  SAXIACPARVALID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
+  assign  SAXIACPAWADDR_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR  : S_AXI_ACP_AWADDR;
+  assign  SAXIACPAWBURST_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
+  
+  
+  assign  SAXIACPAWCACHE_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
+  assign  SAXIACPAWLEN_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN   : S_AXI_ACP_AWLEN;
+  assign  SAXIACPAWLOCK_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK  : S_AXI_ACP_AWLOCK;
+  assign  SAXIACPAWPROT_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT  : S_AXI_ACP_AWPROT;
+  assign  SAXIACPAWSIZE_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE  : S_AXI_ACP_AWSIZE;
+  //assign  SAXIACPAWUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER  : S_AXI_ACP_AWUSER;
+  assign  SAXIACPAWUSER_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER  : param_awuser;
+  assign  SAXIACPAWVALID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
+  assign  SAXIACPBREADY_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY  : S_AXI_ACP_BREADY;
+  assign  SAXIACPRREADY_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY  : S_AXI_ACP_RREADY;
+  assign  SAXIACPWDATA_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA   : S_AXI_ACP_WDATA;
+  assign  SAXIACPWLAST_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST   : S_AXI_ACP_WLAST;
+  assign  SAXIACPWSTRB_W       = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB   : S_AXI_ACP_WSTRB;  
+  assign  SAXIACPWVALID_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID  : S_AXI_ACP_WVALID;      
+  
+  assign  SAXIACPARID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID    : S_AXI_ACP_ARID;    
+  assign  SAXIACPAWID_W     = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID    : S_AXI_ACP_AWID;      
+  assign  SAXIACPWID_W      = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID     : S_AXI_ACP_WID;        
+  
+
+  generate
+    if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
+    
+    assign S_AXI_ACP_AWREADY          =   SAXIACPAWREADY_W;
+    assign S_AXI_ACP_WREADY           =   SAXIACPWREADY_W;
+    assign S_AXI_ACP_BID              =   SAXIACPBID_W;    
+    assign S_AXI_ACP_BRESP            =   SAXIACPBRESP_W;  
+    assign S_AXI_ACP_BVALID           =   SAXIACPBVALID_W;    
+    assign S_AXI_ACP_RDATA            =	  SAXIACPRDATA_W;    
+    assign S_AXI_ACP_RID              =	  SAXIACPRID_W;        
+    assign S_AXI_ACP_RLAST            =	  SAXIACPRLAST_W;  
+    assign S_AXI_ACP_RRESP            =	  SAXIACPRRESP_W;  
+    assign S_AXI_ACP_RVALID           =	  SAXIACPRVALID_W; 
+    assign S_AXI_ACP_ARREADY          =	  SAXIACPARREADY_W;
+    
+
+    end else begin : gen_atc
+    
+  processing_system7_v5_5_atc #(
+   .C_AXI_ID_WIDTH                   (C_S_AXI_ACP_ID_WIDTH),
+   .C_AXI_AWUSER_WIDTH               (5),
+   .C_AXI_ARUSER_WIDTH               (5)
+   )
+   
+  atc_i (
+
+   // Global Signals
+   .ACLK                                (S_AXI_ACP_ACLK_temp),
+   .ARESETN                             (S_AXI_ACP_ARESETN),
+
+   // Slave Interface Write Address Ports
+   .S_AXI_AWID                           (S_AXI_ACP_AWID),
+   .S_AXI_AWADDR                         (S_AXI_ACP_AWADDR),
+   .S_AXI_AWLEN                          (S_AXI_ACP_AWLEN),
+   .S_AXI_AWSIZE                         (S_AXI_ACP_AWSIZE),
+   .S_AXI_AWBURST                        (S_AXI_ACP_AWBURST),
+   .S_AXI_AWLOCK                         (S_AXI_ACP_AWLOCK),
+   .S_AXI_AWCACHE                        (S_AXI_ACP_AWCACHE),
+   .S_AXI_AWPROT                         (S_AXI_ACP_AWPROT),
+   //.S_AXI_AWUSER                         (S_AXI_ACP_AWUSER),
+   .S_AXI_AWUSER                         (param_awuser),
+   .S_AXI_AWVALID                        (S_AXI_ACP_AWVALID),
+   .S_AXI_AWREADY                        (S_AXI_ACP_AWREADY),
+   // Slave Interface Write Data Ports
+   .S_AXI_WID                            (S_AXI_ACP_WID),
+   .S_AXI_WDATA                          (S_AXI_ACP_WDATA),
+   .S_AXI_WSTRB                          (S_AXI_ACP_WSTRB),
+   .S_AXI_WLAST                          (S_AXI_ACP_WLAST),
+   .S_AXI_WUSER                          (),
+   .S_AXI_WVALID                         (S_AXI_ACP_WVALID),
+   .S_AXI_WREADY                         (S_AXI_ACP_WREADY),
+   // Slave Interface Write Response Ports
+   .S_AXI_BID                            (S_AXI_ACP_BID),
+   .S_AXI_BRESP                          (S_AXI_ACP_BRESP),
+   .S_AXI_BUSER                          (),
+   .S_AXI_BVALID                         (S_AXI_ACP_BVALID),
+   .S_AXI_BREADY                         (S_AXI_ACP_BREADY),
+   // Slave Interface Read Address Ports
+   .S_AXI_ARID                           (S_AXI_ACP_ARID),
+   .S_AXI_ARADDR                         (S_AXI_ACP_ARADDR),
+   .S_AXI_ARLEN                          (S_AXI_ACP_ARLEN),
+   .S_AXI_ARSIZE                         (S_AXI_ACP_ARSIZE),
+   .S_AXI_ARBURST                        (S_AXI_ACP_ARBURST),
+   .S_AXI_ARLOCK                         (S_AXI_ACP_ARLOCK),
+   .S_AXI_ARCACHE                        (S_AXI_ACP_ARCACHE),
+   .S_AXI_ARPROT                         (S_AXI_ACP_ARPROT),
+   //.S_AXI_ARUSER                         (S_AXI_ACP_ARUSER),
+   .S_AXI_ARUSER                         (param_aruser),
+   .S_AXI_ARVALID                        (S_AXI_ACP_ARVALID),
+   .S_AXI_ARREADY                        (S_AXI_ACP_ARREADY),
+   // Slave Interface Read Data Ports
+   .S_AXI_RID                            (S_AXI_ACP_RID),
+   .S_AXI_RDATA                          (S_AXI_ACP_RDATA),
+   .S_AXI_RRESP                          (S_AXI_ACP_RRESP),
+   .S_AXI_RLAST                          (S_AXI_ACP_RLAST),
+   .S_AXI_RUSER                          (),
+   .S_AXI_RVALID                         (S_AXI_ACP_RVALID),
+   .S_AXI_RREADY                         (S_AXI_ACP_RREADY),
+
+    // Slave Interface Write Address Ports
+   .M_AXI_AWID                           (S_AXI_ATC_AWID),
+   .M_AXI_AWADDR                         (S_AXI_ATC_AWADDR),
+   .M_AXI_AWLEN                          (S_AXI_ATC_AWLEN),
+   .M_AXI_AWSIZE                         (S_AXI_ATC_AWSIZE),
+   .M_AXI_AWBURST                        (S_AXI_ATC_AWBURST),
+   .M_AXI_AWLOCK                         (S_AXI_ATC_AWLOCK),
+   .M_AXI_AWCACHE                        (S_AXI_ATC_AWCACHE),
+   .M_AXI_AWPROT                         (S_AXI_ATC_AWPROT),
+   .M_AXI_AWUSER                         (S_AXI_ATC_AWUSER),
+   .M_AXI_AWVALID                        (S_AXI_ATC_AWVALID),
+   .M_AXI_AWREADY                        (SAXIACPAWREADY_W),
+   // Slave Interface Write Data Ports
+   .M_AXI_WID                            (S_AXI_ATC_WID),
+   .M_AXI_WDATA                          (S_AXI_ATC_WDATA),
+   .M_AXI_WSTRB                          (S_AXI_ATC_WSTRB),
+   .M_AXI_WLAST                          (S_AXI_ATC_WLAST),
+   .M_AXI_WUSER                          (),
+   .M_AXI_WVALID                         (S_AXI_ATC_WVALID),
+   .M_AXI_WREADY                         (SAXIACPWREADY_W),
+   // Slave Interface Write Response Ports
+   .M_AXI_BID                            (SAXIACPBID_W),
+   .M_AXI_BRESP                          (SAXIACPBRESP_W),
+   .M_AXI_BUSER                          (),
+   .M_AXI_BVALID                         (SAXIACPBVALID_W),
+   .M_AXI_BREADY                         (S_AXI_ATC_BREADY),
+   // Slave Interface Read Address Ports
+   .M_AXI_ARID                           (S_AXI_ATC_ARID),
+   .M_AXI_ARADDR                         (S_AXI_ATC_ARADDR),
+   .M_AXI_ARLEN                          (S_AXI_ATC_ARLEN),
+   .M_AXI_ARSIZE                         (S_AXI_ATC_ARSIZE),
+   .M_AXI_ARBURST                        (S_AXI_ATC_ARBURST),
+   .M_AXI_ARLOCK                         (S_AXI_ATC_ARLOCK),
+   .M_AXI_ARCACHE                        (S_AXI_ATC_ARCACHE),
+   .M_AXI_ARPROT                         (S_AXI_ATC_ARPROT),
+   .M_AXI_ARUSER                         (S_AXI_ATC_ARUSER),
+   .M_AXI_ARVALID                        (S_AXI_ATC_ARVALID),
+   .M_AXI_ARREADY                        (SAXIACPARREADY_W),
+   // Slave Interface Read Data Ports
+   .M_AXI_RID                            (SAXIACPRID_W),
+   .M_AXI_RDATA                          (SAXIACPRDATA_W),
+   .M_AXI_RRESP                          (SAXIACPRRESP_W),
+   .M_AXI_RLAST                          (SAXIACPRLAST_W),
+   .M_AXI_RUSER                          (),
+   .M_AXI_RVALID                         (SAXIACPRVALID_W),
+   .M_AXI_RREADY                         (S_AXI_ATC_RREADY),
+
+   
+   .ERROR_TRIGGER(),
+   .ERROR_TRANSACTION_ID()
+   );    
+
+
+
+    end
+  endgenerate
+
+
+
+
+endmodule
+
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/system_processing_system7_0_0.hwdef b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/system_processing_system7_0_0.hwdef
new file mode 100644
index 0000000..1511a0c
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/system_processing_system7_0_0.hwdef differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.c b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.c
new file mode 100644
index 0000000..3df7714
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.c
@@ -0,0 +1,12807 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
+* otherwise to promote the sale, use or other dealings in this Software without prior written
+* authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.h b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.h
new file mode 100644
index 0000000..1e0ef54
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.h
@@ -0,0 +1,137 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+* 
+* The above copyright notice and this permission notice shall be included in all copies or 
+* substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 
+* (b) that interact with a Xilinx device through a bus or interconnect.  
+* 
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+* 
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 
+* otherwise to promote the sale, use or other dealings in this Software without prior written 
+* authorization from Xilinx.
+* 
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.html b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.html
new file mode 100644
index 0000000..a0eee88
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.html
@@ -0,0 +1,137694 @@
+
+
+
+
+Zynq PS configuration detail
+
+
+
+
    
+
    
+
+
  • 
+
    Zynq PS Register Summary Viewer
+
    
+
    • 
+    
+
    
+
    
+
    
+
+
    Zynq PS7 Summary Report
+
    
+    
+
    User Configurations
+
    
+
    
+
+
    MIO Configurations
+
    
+    
+
    
+
+
    CLK Configurations
+
    
+    
+
    
+
+
    DDR Configurations
+
    
+    
+
    
+
+
    SMC Configurations
+
    
+    
+
    
+
    
+
    Select Version:
+
+
    
+
    
+
    Zynq Register View
+
    
+
    
+
+
    MIO Registers
+
    
+    
+
+
    PLL Registers
+
    
+    
+
+
    Clock Registers
+
    
+    
+
+
    DDR Registers
+
    
+    
+
+
    Peripherals Registers
+
    
+    
+
    
+
    This design is targeted for xc7z010 board (part number: xc7z010clg400-1)
+
+
    
+
    Zynq Design Summary
    
+
+
+
+
+
+
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+
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+
    
+Device
+
+xc7z010
+
    
+SpeedGrade
+
+-1
+
    
+Part
+
+xc7z010clg400-1
+
    
+Description
+
+Zynq PS Configuration Report with register details
+
    
+Vendor
+
+Xilinx
+
    
+
    MIO Table View
    
+
+
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+
    
+MIO Pin
+
+Peripheral
+
+Signal
+
+IO Type
+
+Speed
+
+Pullup
+
+Direction
+
    
+MIO 0
+
+GPIO
+
+gpio[0]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 1
+
+Quad SPI Flash
+
+qspi0_ss_b
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+out
+
    
+MIO 2
+
+Quad SPI Flash
+
+qspi0_io[0]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 3
+
+Quad SPI Flash
+
+qspi0_io[1]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 4
+
+Quad SPI Flash
+
+qspi0_io[2]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 5
+
+Quad SPI Flash
+
+qspi0_io[3]/HOLD_B
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 6
+
+Quad SPI Flash
+
+qspi0_sclk
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 7
+
+GPIO
+
+gpio[7]
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 8
+
+Quad SPI Flash
+
+qspi_fbclk
+
+LVCMOS 3.3V
+
+slow
+
+disabled
+
+out
+
    
+MIO 9
+
+GPIO
+
+gpio[9]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 10
+
+GPIO
+
+gpio[10]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 11
+
+GPIO
+
+gpio[11]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 12
+
+GPIO
+
+gpio[12]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 13
+
+GPIO
+
+gpio[13]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 14
+
+GPIO
+
+gpio[14]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 15
+
+GPIO
+
+gpio[15]
+
+LVCMOS 3.3V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 16
+
+Enet 0
+
+tx_clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 17
+
+Enet 0
+
+txd[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 18
+
+Enet 0
+
+txd[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 19
+
+Enet 0
+
+txd[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 20
+
+Enet 0
+
+txd[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 21
+
+Enet 0
+
+tx_ctl
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 22
+
+Enet 0
+
+rx_clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 23
+
+Enet 0
+
+rxd[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 24
+
+Enet 0
+
+rxd[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 25
+
+Enet 0
+
+rxd[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 26
+
+Enet 0
+
+rxd[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 27
+
+Enet 0
+
+rx_ctl
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 28
+
+GPIO
+
+gpio[28]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 29
+
+GPIO
+
+gpio[29]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 30
+
+GPIO
+
+gpio[30]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 31
+
+GPIO
+
+gpio[31]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 32
+
+GPIO
+
+gpio[32]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 33
+
+GPIO
+
+gpio[33]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 34
+
+GPIO
+
+gpio[34]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 35
+
+GPIO
+
+gpio[35]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 36
+
+GPIO
+
+gpio[36]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 37
+
+GPIO
+
+gpio[37]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 38
+
+GPIO
+
+gpio[38]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 39
+
+GPIO
+
+gpio[39]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 40
+
+SD 0
+
+clk
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 41
+
+SD 0
+
+cmd
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 42
+
+SD 0
+
+data[0]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 43
+
+SD 0
+
+data[1]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 44
+
+SD 0
+
+data[2]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 45
+
+SD 0
+
+data[3]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 46
+
+GPIO
+
+gpio[46]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 47
+
+SD 0
+
+cd
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 48
+
+UART 1
+
+tx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 49
+
+UART 1
+
+rx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 50
+
+GPIO
+
+gpio[50]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 51
+
+GPIO
+
+gpio[51]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 52
+
+Enet 0
+
+mdc
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 53
+
+Enet 0
+
+mdio
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+
    DDR Memory information
    
+
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+
+
+
+
+
+
+
+
    
+Parameter name
+
+Value
+
+Description
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Memory Part
+
+MT41K256M16 RE-125
+
+
+
    
+DRAM bus width
+
+32 Bit
+
+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
+
    
+ECC
+
+Disabled
+
+ECC is supported only for data width of 16-bit
+
    
+BURST Length (lppdr only)
+
+8
+
+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
+
    
+Internal Vref
+
+0
+
+
+
    
+Operating Frequency (MHz)
+
+533.333333
+
+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
+
    
+HIGH temperature
+
+Normal (0-85)
+
+Select the operating temparature
+
    
+DRAM IC bus width
+
+16 Bits
+
+Provide the width of the DRAM chip
+
    
+DRAM Device Capacity
+
+4096 MBits
+
+
+
    
+Speed Bin
+
+DDR3_1066F
+
+Provide the Speed Bin
+
    
+BANK Address Count
+
+3
+
+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
+
    
+ROW Address Count
+
+15
+
+Provide the Row address for ACTIVE commands
+
    
+COLUMN Address Count
+
+10
+
+Provide the Row address for READ/WRITE commands
+
    
+CAS Latency
+
+7
+
+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
+
    
+CAS Write Latency
+
+6
+
+Select the CAS Write Latency
+
    
+RAS to CAS Delay
+
+7
+
+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
+
    
+RECHARGE Time
+
+7
+
+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
+
    
+tRC (ns )
+
+48.75
+
+Provide the Row cycle time tRC (ns)
+
    
+tRASmin ( ns )
+
+35.0
+
+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
+
    
+tFAW
+
+40.0
+
+It restricts the number of activates that can be done within a certain window of time
+
    
+ADDITIVE Latency
+
+0
+
+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
+
    
+Write levelling
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+DQS to Clock delay [0] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [1] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [2] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [3] (ns)
+
+0.0
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+Board delay [0] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [1] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [2] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [3] (ns)
+
+0.25
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+
    PS Clocks information
    
+
    PS Reference Clock : 33.333333
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Peripheral
+
+PLL source
+
+Frequency (MHz)
+
    
+CPU 6x Freq (MHz)
+
+ARM PLL
+
+666.666687
+
    
+QSPI Flash Freq (MHz)
+
+IO PLL
+
+200.000000
+
    
+ENET0 Freq (MHz)
+
+IO PLL
+
+125.000000
+
    
+SDIO Freq (MHz)
+
+IO PLL
+
+100.000000
+
    
+UART Freq (MHz)
+
+IO PLL
+
+100.000000
+
    
+FPGA0 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+FPGA1 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+FPGA2 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+FPGA3 Freq (MHz)
+
+IO PLL
+
+10.000000
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Ref Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reserved_reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Reserved. Do not modify.
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+7ffff
+
+
+
+1081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_en_dfi_dram_clk_disable
+
+23:23
+
+800000
+
+0
+
+0
+
+Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+7fdffffc
+
+
+
+270872d0
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffc3
+
+
+
+0
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reserved_reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+Reserved. Do not modify.
+
    
+reserved_reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3f03f
+
+
+
+3c008
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+10000
+
+
+
+0
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum d'128)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+200
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_64@0XF8006190
+
+31:0
+
+6ffffefe
+
+
+
+40080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff5
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits
+
    
+reserved_VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+reserved_REFIO_TEST
+
+11:10
+
+c00
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+260
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+1
+
+
+
+1
+
+DDR IOB DCI Config
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialize flops in DCI system
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDR IOB DCI Config
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1
+
    
+reserved_VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT1
+
+15:14
+
+c000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update Mode. Use the values in the Calibration Table.
+
    
+reserved_INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7feffff
+
+
+
+823
+
+DDR IOB DCI Config
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables Pullup on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Divider Register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Generator Register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control Register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode Register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+Baud Rate Divider Register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud Rate Generator Register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter 1: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control Register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+3ff
+
+
+
+20
+
+UART Mode Register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_LVL_INP_EN_0
+
+3:3
+
+8
+
+1
+
+8
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_0
+
+2:2
+
+4
+
+1
+
+4
+
+Level shifter enable to drive signals from PS to PL
+
    
+USER_LVL_INP_EN_1
+
+1:1
+
+2
+
+1
+
+2
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_1
+
+0:0
+
+1
+
+1
+
+1
+
+Level shifter enable to drive signals from PS to PL
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    AFI2 SECURE REGISTER
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Ref Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ration: 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config0
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config1
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 1.
+
    
+
+PHY_Config2
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 2.
+
    
+
+PHY_Config3
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 3.
+
    
+
+phy_init_ratio0
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio1
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 1.
+
    
+
+phy_init_ratio2
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 2.
+
    
+
+phy_init_ratio3
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 3.
+
    
+
+phy_rd_dqs_cfg0
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg1
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 1.
+
    
+
+phy_rd_dqs_cfg2
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 2.
+
    
+
+phy_rd_dqs_cfg3
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 3.
+
    
+
+phy_wr_dqs_cfg0
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg1
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 1.
+
    
+
+phy_wr_dqs_cfg2
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 2.
+
    
+
+phy_wr_dqs_cfg3
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 3.
+
    
+
+phy_we_cfg0
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg1
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
+phy_we_cfg2
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
+phy_we_cfg3
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
+wr_data_slv0
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv1
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 1.
+
    
+
+wr_data_slv2
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 2.
+
    
+
+wr_data_slv3
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 3.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port0
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port1
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 1.
+
    
+
+axi_priority_wr_port2
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 2.
+
    
+
+axi_priority_wr_port3
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 3.
+
    
+
+axi_priority_rd_port0
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port1
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 1.
+
    
+
+axi_priority_rd_port2
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 2.
+
    
+
+axi_priority_rd_port3
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 3.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1: sdram device 0: non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+272872d0
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config0
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config0@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config1
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config1@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )PHY_Config2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config2
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config2@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )PHY_Config3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config3
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config3@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_init_ratio0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio0
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio0@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio1
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio1@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_init_ratio2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio2
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio2@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_init_ratio3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio3
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio3@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg0
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg0@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg1
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg1@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg2
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg2@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg3
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg3@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg0
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg0@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg1
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg1@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg2
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg2@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg3
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg3@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_we_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg0
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg0@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg1
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg1@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_we_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg2
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg2@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_we_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg3
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg3@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
    
+
    Register ( slcr )wr_data_slv0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv0
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv0@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv1
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv1@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 1.
+
    
+
    
+
    Register ( slcr )wr_data_slv2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv2
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv2@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 2.
+
    
+
    
+
    Register ( slcr )wr_data_slv3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv3
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv3@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio config for data slice 3.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port0
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port0@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port1
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port1@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port2
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port2@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port3
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port3@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 3.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port0
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port0@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port1
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port1@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port2
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port2@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port3
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port3@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 3.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 0
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 1
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Address
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Data
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Diff
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Clock
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 0
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 1
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDR IOB Slew for Address
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Data
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Diff
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Clock
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+REFIO_TEST
+
+11:10
+
+c00
+
+0
+
+0
+
+Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+260
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables pull-up on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud rate divider register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: start break transmission, 1: stop break transmission.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter, 0: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: disable, 1: enable
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CORTEX A9 Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CORTEX A9 Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Divisor value for the ddr_3xclk
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Linear Quad-SPI Reference Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Reference Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Reference Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP 2X Clock Contol
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+FPGA 0 Output Clock Control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+6:2:1 ratio clock, if set
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+f
+
+f00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+7
+
+700000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+700f01
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+100801
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Linear Quad-SPI Reference Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+a01
+
+SDIO Reference Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+a
+
+a00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+a02
+
+UART Reference Clock Control
+
    
+
    
+
    TRACE CLOCK
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active 0 - Clock is disabled 1 - Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP 2X Clock Contol
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+400500
+
+FPGA 0 Output Clock Control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+6:2:1 ratio clock, if set
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+0
+
+0
+
+CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ec044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
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+
+
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+
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+
+
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+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
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+
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+
+
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+
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+
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+
+
+
+
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+
+
+
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+
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+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two rank configuration register
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control register
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control register
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control register
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM initialization parameters register
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access register
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access register
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM burst 8 read/write register
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ register
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM bank address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT register
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO register
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration register
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold register
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller register 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller register 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller register 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller register 4
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters register
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters register
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown register
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control register
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug register
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing register
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear register
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction register
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status register
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count register
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub register
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control register (2)
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control register (3)
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask register
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0 Register
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1 Register
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2 Register
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3 Register
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control Register
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two rank configuration register
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control register
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control register
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control register
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1a
+
+1a
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+a0
+
+2800
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4281a
+
+DRAM Parameters register 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+16
+
+5800
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+13
+
+4c00000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+44e458d2
+
+DRAM Parameters register 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM RELATED.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters register 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+6
+
+c0
+
+tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1 = sdram device 0 = non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1 = disable the pad power down feature 0 = Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+272872d0
+
+DRAM Parameters register 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1 = DDRC will use 2T timing 0 = DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1 = Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 1 = read 0 = write
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters register 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM initialization parameters register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access register
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+16d
+
+16d0
+
+Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+116d4
+
+DRAM burst 8 read/write register
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ register
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Selects the address bits used as DRAM bank address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Selects the address bits used as DRAM column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Selects the address bits used as DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT register
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1 = stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO register
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration register
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold register
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+When 1, disable Write Combine
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller register 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller register 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller register 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller register 4
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters register
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters register
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown register
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control register
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug register
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing register
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear register
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction register
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status register
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count register
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub register
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+0
+
+0
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+a4
+
+29000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+29000
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+80
+
+80
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+80
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+f9
+
+f9
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+f9
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+c0
+
+c0
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+c0
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control register (2)
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control register (3)
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask register
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3 Register
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control Register
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 0 Configuartion Register
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 1 Configuration Register
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential Clock Configuration Register
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Address Register
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Data Register
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Clcok Register
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DDR Control Register
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 0
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 1
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 2
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 3
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 4
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 5
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 6
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 7
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 8
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 9
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 10
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 11
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 12
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 13
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 14
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 15
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 16
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 17
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 18
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 19
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 20
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 21
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 22
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 23
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 24
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 25
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 26
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 27
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 28
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 29
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 30
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 31
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 32
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 33
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 34
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 35
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 36
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 37
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 38
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 39
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 40
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 41
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 42
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 43
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 44
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 45
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 46
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 47
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 48
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 49
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 50
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 51
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 52
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 53
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 0 Configuartion Register
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Differential Clock Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDRIOB Drive Slew Address Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Data Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Clcok Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+0
+
+0
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+0
+
+0
+
+Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+3
+
+60
+
+Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+73ff
+
+
+
+260
+
+DDRIOB DDR Control Register
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 0
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1602
+
+MIO Control for Pin 1
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 2
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 3
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 4
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 5
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 6
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+600
+
+MIO Control for Pin 7
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+602
+
+MIO Control for Pin 8
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 9
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 10
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 11
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 12
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 13
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 14
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+3
+
+600
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3fff
+
+
+
+1600
+
+MIO Control for Pin 15
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 16
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 17
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 18
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 19
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 20
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 21
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 22
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 23
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 24
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 25
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 26
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+1203
+
+MIO Control for Pin 27
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 28
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 29
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 30
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 31
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 32
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 33
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 34
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 35
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 36
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 37
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 38
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 39
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 40
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 41
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 42
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 43
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 44
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 45
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 46
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Control for Pin 47
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+12e0
+
+MIO Control for Pin 48
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+12e1
+
+MIO Control for Pin 49
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 50
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 51
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 52
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+1280
+
+MIO Control for Pin 53
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+37
+
+37
+
+SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+2f
+
+2f0000
+
+SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+2f0037
+
+SDIO 0 WP CD select register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+7c
+
+7c
+
+Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+7c
+
+Baud rate divider register
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break. 1 = stop transmission of the break.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter 1 = receiver timeout counter is restarted
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable. 1, the transmitter is disabled
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable. 1= receiver is enabled
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    USB0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    USB1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    ENET0 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET1 RESET
    
+
    DIR MODE BANK 0
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    I2C0 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C1 RESET
    
+
    DIR MODE GPIO BANK0
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    NOR CHIP SELECT
    
+
    DIR MODE BANK 0
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    OUTPUT ENABLE BANK 0
    
+
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.tcl b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.tcl
new file mode 100644
index 0000000..e735d59
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init.tcl
@@ -0,0 +1,832 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00100801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00000A01
+    mask_write 0XF8000154 0x00003F33 0x00000A02
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004281A
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001600
+    mask_write 0XF8000704 0x00003FFF 0x00001602
+    mask_write 0XF8000708 0x00003FFF 0x00000602
+    mask_write 0XF800070C 0x00003FFF 0x00000602
+    mask_write 0XF8000710 0x00003FFF 0x00000602
+    mask_write 0XF8000714 0x00003FFF 0x00000602
+    mask_write 0XF8000718 0x00003FFF 0x00000602
+    mask_write 0XF800071C 0x00003FFF 0x00000600
+    mask_write 0XF8000720 0x00003FFF 0x00000602
+    mask_write 0XF8000724 0x00003FFF 0x00001600
+    mask_write 0XF8000728 0x00003FFF 0x00001600
+    mask_write 0XF800072C 0x00003FFF 0x00001600
+    mask_write 0XF8000730 0x00003FFF 0x00001600
+    mask_write 0XF8000734 0x00003FFF 0x00001600
+    mask_write 0XF8000738 0x00003FFF 0x00001600
+    mask_write 0XF800073C 0x00003FFF 0x00001600
+    mask_write 0XF8000740 0x00003FFF 0x00001202
+    mask_write 0XF8000744 0x00003FFF 0x00001202
+    mask_write 0XF8000748 0x00003FFF 0x00001202
+    mask_write 0XF800074C 0x00003FFF 0x00001202
+    mask_write 0XF8000750 0x00003FFF 0x00001202
+    mask_write 0XF8000754 0x00003FFF 0x00001202
+    mask_write 0XF8000758 0x00003FFF 0x00001203
+    mask_write 0XF800075C 0x00003FFF 0x00001203
+    mask_write 0XF8000760 0x00003FFF 0x00001203
+    mask_write 0XF8000764 0x00003FFF 0x00001203
+    mask_write 0XF8000768 0x00003FFF 0x00001203
+    mask_write 0XF800076C 0x00003FFF 0x00001203
+    mask_write 0XF8000770 0x00003FFF 0x00001200
+    mask_write 0XF8000774 0x00003FFF 0x00001200
+    mask_write 0XF8000778 0x00003FFF 0x00001200
+    mask_write 0XF800077C 0x00003FFF 0x00001200
+    mask_write 0XF8000780 0x00003FFF 0x00001200
+    mask_write 0XF8000784 0x00003FFF 0x00001200
+    mask_write 0XF8000788 0x00003FFF 0x00001200
+    mask_write 0XF800078C 0x00003FFF 0x00001200
+    mask_write 0XF8000790 0x00003FFF 0x00001200
+    mask_write 0XF8000794 0x00003FFF 0x00001200
+    mask_write 0XF8000798 0x00003FFF 0x00001200
+    mask_write 0XF800079C 0x00003FFF 0x00001200
+    mask_write 0XF80007A0 0x00003FFF 0x00001280
+    mask_write 0XF80007A4 0x00003FFF 0x00001280
+    mask_write 0XF80007A8 0x00003FFF 0x00001280
+    mask_write 0XF80007AC 0x00003FFF 0x00001280
+    mask_write 0XF80007B0 0x00003FFF 0x00001280
+    mask_write 0XF80007B4 0x00003FFF 0x00001280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003F01 0x00001201
+    mask_write 0XF80007C0 0x00003FFF 0x000012E0
+    mask_write 0XF80007C4 0x00003FFF 0x000012E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001200
+    mask_write 0XF80007CC 0x00003FFF 0x00001200
+    mask_write 0XF80007D0 0x00003FFF 0x00001280
+    mask_write 0XF80007D4 0x00003FFF 0x00001280
+    mask_write 0XF8000830 0x003F003F 0x002F0037
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000007C
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+    mask_delay 0XF8F00200 1
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  666666666
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.c b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.c
new file mode 100644
index 0000000..0e45185
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.c
@@ -0,0 +1,12798 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see 
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. .. START: AFI2 SECURE REGISTER
+    // .. .. FINISH: AFI2 SECURE REGISTER
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0xf
+    // .. ==> 0XF8000128[13:8] = 0x0000000FU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
+    // .. DIVISOR1 = 0x7
+    // .. ==> 0XF8000128[25:20] = 0x00000007U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000150[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF8000154[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A02U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0x5
+    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x5
+    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. .. DIVISOR1 = 0x4
+    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. .. SDI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
+    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006134[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa4
+    // .. .. ==> 0XF8006138[19:10] = 0x000000A4U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00029000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006154[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006158[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF800615C[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
+    // .. .. ==> 0XF8006160[9:0] = 0x00000080U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000080U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006170[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf9
+    // .. .. ==> 0XF8006174[10:0] = 0x000000F9U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F9U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc0
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C0U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x0
+    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
+    // .. VREF_EXT_EN = 0x3
+    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000740[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000744[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000748[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800074C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000750[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000754[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000758[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800075C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000760[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000764[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000768[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800076C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000770[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000770[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000774[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000774[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000774[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000778[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000778[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800077C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800077C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800077C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000780[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000780[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000784[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000784[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000788[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000788[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800078C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800078C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000790[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000790[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000790[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000794[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000794[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000798[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000798[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800079C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800079C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007A8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007AC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D0[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007D4[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
+    // .. SDIO0_WP_SEL = 55
+    // .. ==> 0XF8000830[5:0] = 0x00000037U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F0037U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x7c
+    // .. ==> 0XE0001018[15:0] = 0x0000007CU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_WRITE(0XF8000004, 0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+  
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.h b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.h
new file mode 100644
index 0000000..1e0ef54
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_init_gpl.h
@@ -0,0 +1,137 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this
+* software and associated documentation files (the "Software"), to deal in the Software
+* without restriction, including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
+* persons to whom the Software is furnished to do so, subject to the following conditions:
+* 
+* The above copyright notice and this permission notice shall be included in all copies or 
+* substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 
+* (b) that interact with a Xilinx device through a bus or interconnect.  
+* 
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+* 
+* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 
+* otherwise to promote the sale, use or other dealings in this Software without prior written 
+* authorization from Xilinx.
+* 
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  100000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_parameters.xml b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_parameters.xml
new file mode 100644
index 0000000..bd7a3f7
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_parameters.xml
@@ -0,0 +1,643 @@
+ 
+
+
+  
+    
+      
+      
+      
+      
+      
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+  
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.dll b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.dll
new file mode 100644
index 0000000..870988e
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.dll differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.so b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.so
new file mode 100644
index 0000000..9e8be57
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libps7.so differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.dll b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.dll
new file mode 100644
index 0000000..dd1d912
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.dll differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.so b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.so
new file mode 100644
index 0000000..f7ccf59
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/libremoteport.so differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv
new file mode 100644
index 0000000..82f9334
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.sv
@@ -0,0 +1,1117 @@
+`timescale 1ns/1ps
+
+//PORTS
+
+      bit  CAN0_PHY_TX;
+      bit  CAN0_PHY_RX;
+      bit  CAN1_PHY_TX;
+      bit  CAN1_PHY_RX;
+      bit  [0 : 0] ENET0_GMII_TX_EN;
+      bit  [0 : 0] ENET0_GMII_TX_ER;
+      bit  ENET0_MDIO_MDC;
+      bit  ENET0_MDIO_O;
+      bit  ENET0_MDIO_T;
+      bit  ENET0_PTP_DELAY_REQ_RX;
+      bit  ENET0_PTP_DELAY_REQ_TX;
+      bit  ENET0_PTP_PDELAY_REQ_RX;
+      bit  ENET0_PTP_PDELAY_REQ_TX;
+      bit  ENET0_PTP_PDELAY_RESP_RX;
+      bit  ENET0_PTP_PDELAY_RESP_TX;
+      bit  ENET0_PTP_SYNC_FRAME_RX;
+      bit  ENET0_PTP_SYNC_FRAME_TX;
+      bit  ENET0_SOF_RX;
+      bit  ENET0_SOF_TX;
+      bit  [7 : 0] ENET0_GMII_TXD;
+      bit  ENET0_GMII_COL;
+      bit  ENET0_GMII_CRS;
+      bit  ENET0_GMII_RX_CLK;
+      bit  ENET0_GMII_RX_DV;
+      bit  ENET0_GMII_RX_ER;
+      bit  ENET0_GMII_TX_CLK;
+      bit  ENET0_MDIO_I;
+      bit  ENET0_EXT_INTIN;
+      bit  [7 : 0] ENET0_GMII_RXD;
+      bit  [0 : 0] ENET1_GMII_TX_EN;
+      bit  [0 : 0] ENET1_GMII_TX_ER;
+      bit  ENET1_MDIO_MDC;
+      bit  ENET1_MDIO_O;
+      bit  ENET1_MDIO_T;
+      bit  ENET1_PTP_DELAY_REQ_RX;
+      bit  ENET1_PTP_DELAY_REQ_TX;
+      bit  ENET1_PTP_PDELAY_REQ_RX;
+      bit  ENET1_PTP_PDELAY_REQ_TX;
+      bit  ENET1_PTP_PDELAY_RESP_RX;
+      bit  ENET1_PTP_PDELAY_RESP_TX;
+      bit  ENET1_PTP_SYNC_FRAME_RX;
+      bit  ENET1_PTP_SYNC_FRAME_TX;
+      bit  ENET1_SOF_RX;
+      bit  ENET1_SOF_TX;
+      bit  [7 : 0] ENET1_GMII_TXD;
+      bit  ENET1_GMII_COL;
+      bit  ENET1_GMII_CRS;
+      bit  ENET1_GMII_RX_CLK;
+      bit  ENET1_GMII_RX_DV;
+      bit  ENET1_GMII_RX_ER;
+      bit  ENET1_GMII_TX_CLK;
+      bit  ENET1_MDIO_I;
+      bit  ENET1_EXT_INTIN;
+      bit  [7 : 0] ENET1_GMII_RXD;
+      bit  [63 : 0] GPIO_I;
+      bit  [63 : 0] GPIO_O;
+      bit  [63 : 0] GPIO_T;
+      bit  I2C0_SDA_I;
+      bit  I2C0_SDA_O;
+      bit  I2C0_SDA_T;
+      bit  I2C0_SCL_I;
+      bit  I2C0_SCL_O;
+      bit  I2C0_SCL_T;
+      bit  I2C1_SDA_I;
+      bit  I2C1_SDA_O;
+      bit  I2C1_SDA_T;
+      bit  I2C1_SCL_I;
+      bit  I2C1_SCL_O;
+      bit  I2C1_SCL_T;
+      bit  PJTAG_TCK;
+      bit  PJTAG_TMS;
+      bit  PJTAG_TDI;
+      bit  PJTAG_TDO;
+      bit  SDIO0_CLK;
+      bit  SDIO0_CLK_FB;
+      bit  SDIO0_CMD_O;
+      bit  SDIO0_CMD_I;
+      bit  SDIO0_CMD_T;
+      bit  [3 : 0] SDIO0_DATA_I;
+      bit  [3 : 0] SDIO0_DATA_O;
+      bit  [3 : 0] SDIO0_DATA_T;
+      bit  SDIO0_LED;
+      bit  SDIO0_CDN;
+      bit  SDIO0_WP;
+      bit  SDIO0_BUSPOW;
+      bit  [2 : 0] SDIO0_BUSVOLT;
+      bit  SDIO1_CLK;
+      bit  SDIO1_CLK_FB;
+      bit  SDIO1_CMD_O;
+      bit  SDIO1_CMD_I;
+      bit  SDIO1_CMD_T;
+      bit  [3 : 0] SDIO1_DATA_I;
+      bit  [3 : 0] SDIO1_DATA_O;
+      bit  [3 : 0] SDIO1_DATA_T;
+      bit  SDIO1_LED;
+      bit  SDIO1_CDN;
+      bit  SDIO1_WP;
+      bit  SDIO1_BUSPOW;
+      bit  [2 : 0] SDIO1_BUSVOLT;
+      bit  SPI0_SCLK_I;
+      bit  SPI0_SCLK_O;
+      bit  SPI0_SCLK_T;
+      bit  SPI0_MOSI_I;
+      bit  SPI0_MOSI_O;
+      bit  SPI0_MOSI_T;
+      bit  SPI0_MISO_I;
+      bit  SPI0_MISO_O;
+      bit  SPI0_MISO_T;
+      bit  SPI0_SS_I;
+      bit  SPI0_SS_O;
+      bit  SPI0_SS1_O;
+      bit  SPI0_SS2_O;
+      bit  SPI0_SS_T;
+      bit  SPI1_SCLK_I;
+      bit  SPI1_SCLK_O;
+      bit  SPI1_SCLK_T;
+      bit  SPI1_MOSI_I;
+      bit  SPI1_MOSI_O;
+      bit  SPI1_MOSI_T;
+      bit  SPI1_MISO_I;
+      bit  SPI1_MISO_O;
+      bit  SPI1_MISO_T;
+      bit  SPI1_SS_I;
+      bit  SPI1_SS_O;
+      bit  SPI1_SS1_O;
+      bit  SPI1_SS2_O;
+      bit  SPI1_SS_T;
+      bit  UART0_DTRN;
+      bit  UART0_RTSN;
+      bit  UART0_TX;
+      bit  UART0_CTSN;
+      bit  UART0_DCDN;
+      bit  UART0_DSRN;
+      bit  UART0_RIN;
+      bit  UART0_RX;
+      bit  UART1_DTRN;
+      bit  UART1_RTSN;
+      bit  UART1_TX;
+      bit  UART1_CTSN;
+      bit  UART1_DCDN;
+      bit  UART1_DSRN;
+      bit  UART1_RIN;
+      bit  UART1_RX;
+      bit  TTC0_WAVE0_OUT;
+      bit  TTC0_WAVE1_OUT;
+      bit  TTC0_WAVE2_OUT;
+      bit  TTC0_CLK0_IN;
+      bit  TTC0_CLK1_IN;
+      bit  TTC0_CLK2_IN;
+      bit  TTC1_WAVE0_OUT;
+      bit  TTC1_WAVE1_OUT;
+      bit  TTC1_WAVE2_OUT;
+      bit  TTC1_CLK0_IN;
+      bit  TTC1_CLK1_IN;
+      bit  TTC1_CLK2_IN;
+      bit  WDT_CLK_IN;
+      bit  WDT_RST_OUT;
+      bit  TRACE_CLK;
+      bit  TRACE_CLK_OUT;
+      bit  TRACE_CTL;
+      bit  [1 : 0] TRACE_DATA;
+      bit  [1 : 0] USB0_PORT_INDCTL;
+      bit  USB0_VBUS_PWRSELECT;
+      bit  USB0_VBUS_PWRFAULT;
+      bit  [1 : 0] USB1_PORT_INDCTL;
+      bit  USB1_VBUS_PWRSELECT;
+      bit  USB1_VBUS_PWRFAULT;
+      bit  SRAM_INTIN;
+      bit  M_AXI_GP0_ARVALID;
+      bit  M_AXI_GP0_AWVALID;
+      bit  M_AXI_GP0_BREADY;
+      bit  M_AXI_GP0_RREADY;
+      bit  M_AXI_GP0_WLAST;
+      bit  M_AXI_GP0_WVALID;
+      bit  [11 : 0] M_AXI_GP0_ARID;
+      bit  [11 : 0] M_AXI_GP0_AWID;
+      bit  [11 : 0] M_AXI_GP0_WID;
+      bit  [1 : 0] M_AXI_GP0_ARBURST;
+      bit  [1 : 0] M_AXI_GP0_ARLOCK;
+      bit  [2 : 0] M_AXI_GP0_ARSIZE;
+      bit  [1 : 0] M_AXI_GP0_AWBURST;
+      bit  [1 : 0] M_AXI_GP0_AWLOCK;
+      bit  [2 : 0] M_AXI_GP0_AWSIZE;
+      bit  [2 : 0] M_AXI_GP0_ARPROT;
+      bit  [2 : 0] M_AXI_GP0_AWPROT;
+      bit  [31 : 0] M_AXI_GP0_ARADDR;
+      bit  [31 : 0] M_AXI_GP0_AWADDR;
+      bit  [31 : 0] M_AXI_GP0_WDATA;
+      bit  [3 : 0] M_AXI_GP0_ARCACHE;
+      bit  [3 : 0] M_AXI_GP0_ARLEN;
+      bit  [3 : 0] M_AXI_GP0_ARQOS;
+      bit  [3 : 0] M_AXI_GP0_AWCACHE;
+      bit  [3 : 0] M_AXI_GP0_AWLEN;
+      bit  [3 : 0] M_AXI_GP0_AWQOS;
+      bit  [3 : 0] M_AXI_GP0_WSTRB;
+      bit  M_AXI_GP0_ACLK;
+      bit  M_AXI_GP0_ARREADY;
+      bit  M_AXI_GP0_AWREADY;
+      bit  M_AXI_GP0_BVALID;
+      bit  M_AXI_GP0_RLAST;
+      bit  M_AXI_GP0_RVALID;
+      bit  M_AXI_GP0_WREADY;
+      bit  [11 : 0] M_AXI_GP0_BID;
+      bit  [11 : 0] M_AXI_GP0_RID;
+      bit  [1 : 0] M_AXI_GP0_BRESP;
+      bit  [1 : 0] M_AXI_GP0_RRESP;
+      bit  [31 : 0] M_AXI_GP0_RDATA;
+      bit  M_AXI_GP1_ARVALID;
+      bit  M_AXI_GP1_AWVALID;
+      bit  M_AXI_GP1_BREADY;
+      bit  M_AXI_GP1_RREADY;
+      bit  M_AXI_GP1_WLAST;
+      bit  M_AXI_GP1_WVALID;
+      bit  [11 : 0] M_AXI_GP1_ARID;
+      bit  [11 : 0] M_AXI_GP1_AWID;
+      bit  [11 : 0] M_AXI_GP1_WID;
+      bit  [1 : 0] M_AXI_GP1_ARBURST;
+      bit  [1 : 0] M_AXI_GP1_ARLOCK;
+      bit  [2 : 0] M_AXI_GP1_ARSIZE;
+      bit  [1 : 0] M_AXI_GP1_AWBURST;
+      bit  [1 : 0] M_AXI_GP1_AWLOCK;
+      bit  [2 : 0] M_AXI_GP1_AWSIZE;
+      bit  [2 : 0] M_AXI_GP1_ARPROT;
+      bit  [2 : 0] M_AXI_GP1_AWPROT;
+      bit  [31 : 0] M_AXI_GP1_ARADDR;
+      bit  [31 : 0] M_AXI_GP1_AWADDR;
+      bit  [31 : 0] M_AXI_GP1_WDATA;
+      bit  [3 : 0] M_AXI_GP1_ARCACHE;
+      bit  [3 : 0] M_AXI_GP1_ARLEN;
+      bit  [3 : 0] M_AXI_GP1_ARQOS;
+      bit  [3 : 0] M_AXI_GP1_AWCACHE;
+      bit  [3 : 0] M_AXI_GP1_AWLEN;
+      bit  [3 : 0] M_AXI_GP1_AWQOS;
+      bit  [3 : 0] M_AXI_GP1_WSTRB;
+      bit  M_AXI_GP1_ACLK;
+      bit  M_AXI_GP1_ARREADY;
+      bit  M_AXI_GP1_AWREADY;
+      bit  M_AXI_GP1_BVALID;
+      bit  M_AXI_GP1_RLAST;
+      bit  M_AXI_GP1_RVALID;
+      bit  M_AXI_GP1_WREADY;
+      bit  [11 : 0] M_AXI_GP1_BID;
+      bit  [11 : 0] M_AXI_GP1_RID;
+      bit  [1 : 0] M_AXI_GP1_BRESP;
+      bit  [1 : 0] M_AXI_GP1_RRESP;
+      bit  [31 : 0] M_AXI_GP1_RDATA;
+      bit  S_AXI_GP0_ARREADY;
+      bit  S_AXI_GP0_AWREADY;
+      bit  S_AXI_GP0_BVALID;
+      bit  S_AXI_GP0_RLAST;
+      bit  S_AXI_GP0_RVALID;
+      bit  S_AXI_GP0_WREADY;
+      bit  [1 : 0] S_AXI_GP0_BRESP;
+      bit  [1 : 0] S_AXI_GP0_RRESP;
+      bit  [31 : 0] S_AXI_GP0_RDATA;
+      bit  [5 : 0] S_AXI_GP0_BID;
+      bit  [5 : 0] S_AXI_GP0_RID;
+      bit  S_AXI_GP0_ACLK;
+      bit  S_AXI_GP0_ARVALID;
+      bit  S_AXI_GP0_AWVALID;
+      bit  S_AXI_GP0_BREADY;
+      bit  S_AXI_GP0_RREADY;
+      bit  S_AXI_GP0_WLAST;
+      bit  S_AXI_GP0_WVALID;
+      bit  [1 : 0] S_AXI_GP0_ARBURST;
+      bit  [1 : 0] S_AXI_GP0_ARLOCK;
+      bit  [2 : 0] S_AXI_GP0_ARSIZE;
+      bit  [1 : 0] S_AXI_GP0_AWBURST;
+      bit  [1 : 0] S_AXI_GP0_AWLOCK;
+      bit  [2 : 0] S_AXI_GP0_AWSIZE;
+      bit  [2 : 0] S_AXI_GP0_ARPROT;
+      bit  [2 : 0] S_AXI_GP0_AWPROT;
+      bit  [31 : 0] S_AXI_GP0_ARADDR;
+      bit  [31 : 0] S_AXI_GP0_AWADDR;
+      bit  [31 : 0] S_AXI_GP0_WDATA;
+      bit  [3 : 0] S_AXI_GP0_ARCACHE;
+      bit  [3 : 0] S_AXI_GP0_ARLEN;
+      bit  [3 : 0] S_AXI_GP0_ARQOS;
+      bit  [3 : 0] S_AXI_GP0_AWCACHE;
+      bit  [3 : 0] S_AXI_GP0_AWLEN;
+      bit  [3 : 0] S_AXI_GP0_AWQOS;
+      bit  [3 : 0] S_AXI_GP0_WSTRB;
+      bit  [5 : 0] S_AXI_GP0_ARID;
+      bit  [5 : 0] S_AXI_GP0_AWID;
+      bit  [5 : 0] S_AXI_GP0_WID;
+      bit  S_AXI_GP1_ARREADY;
+      bit  S_AXI_GP1_AWREADY;
+      bit  S_AXI_GP1_BVALID;
+      bit  S_AXI_GP1_RLAST;
+      bit  S_AXI_GP1_RVALID;
+      bit  S_AXI_GP1_WREADY;
+      bit  [1 : 0] S_AXI_GP1_BRESP;
+      bit  [1 : 0] S_AXI_GP1_RRESP;
+      bit  [31 : 0] S_AXI_GP1_RDATA;
+      bit  [5 : 0] S_AXI_GP1_BID;
+      bit  [5 : 0] S_AXI_GP1_RID;
+      bit  S_AXI_GP1_ACLK;
+      bit  S_AXI_GP1_ARVALID;
+      bit  S_AXI_GP1_AWVALID;
+      bit  S_AXI_GP1_BREADY;
+      bit  S_AXI_GP1_RREADY;
+      bit  S_AXI_GP1_WLAST;
+      bit  S_AXI_GP1_WVALID;
+      bit  [1 : 0] S_AXI_GP1_ARBURST;
+      bit  [1 : 0] S_AXI_GP1_ARLOCK;
+      bit  [2 : 0] S_AXI_GP1_ARSIZE;
+      bit  [1 : 0] S_AXI_GP1_AWBURST;
+      bit  [1 : 0] S_AXI_GP1_AWLOCK;
+      bit  [2 : 0] S_AXI_GP1_AWSIZE;
+      bit  [2 : 0] S_AXI_GP1_ARPROT;
+      bit  [2 : 0] S_AXI_GP1_AWPROT;
+      bit  [31 : 0] S_AXI_GP1_ARADDR;
+      bit  [31 : 0] S_AXI_GP1_AWADDR;
+      bit  [31 : 0] S_AXI_GP1_WDATA;
+      bit  [3 : 0] S_AXI_GP1_ARCACHE;
+      bit  [3 : 0] S_AXI_GP1_ARLEN;
+      bit  [3 : 0] S_AXI_GP1_ARQOS;
+      bit  [3 : 0] S_AXI_GP1_AWCACHE;
+      bit  [3 : 0] S_AXI_GP1_AWLEN;
+      bit  [3 : 0] S_AXI_GP1_AWQOS;
+      bit  [3 : 0] S_AXI_GP1_WSTRB;
+      bit  [5 : 0] S_AXI_GP1_ARID;
+      bit  [5 : 0] S_AXI_GP1_AWID;
+      bit  [5 : 0] S_AXI_GP1_WID;
+      bit  S_AXI_ACP_ARREADY;
+      bit  S_AXI_ACP_AWREADY;
+      bit  S_AXI_ACP_BVALID;
+      bit  S_AXI_ACP_RLAST;
+      bit  S_AXI_ACP_RVALID;
+      bit  S_AXI_ACP_WREADY;
+      bit  [1 : 0] S_AXI_ACP_BRESP;
+      bit  [1 : 0] S_AXI_ACP_RRESP;
+      bit  [2 : 0] S_AXI_ACP_BID;
+      bit  [2 : 0] S_AXI_ACP_RID;
+      bit  [63 : 0] S_AXI_ACP_RDATA;
+      bit  S_AXI_ACP_ACLK;
+      bit  S_AXI_ACP_ARVALID;
+      bit  S_AXI_ACP_AWVALID;
+      bit  S_AXI_ACP_BREADY;
+      bit  S_AXI_ACP_RREADY;
+      bit  S_AXI_ACP_WLAST;
+      bit  S_AXI_ACP_WVALID;
+      bit  [2 : 0] S_AXI_ACP_ARID;
+      bit  [2 : 0] S_AXI_ACP_ARPROT;
+      bit  [2 : 0] S_AXI_ACP_AWID;
+      bit  [2 : 0] S_AXI_ACP_AWPROT;
+      bit  [2 : 0] S_AXI_ACP_WID;
+      bit  [31 : 0] S_AXI_ACP_ARADDR;
+      bit  [31 : 0] S_AXI_ACP_AWADDR;
+      bit  [3 : 0] S_AXI_ACP_ARCACHE;
+      bit  [3 : 0] S_AXI_ACP_ARLEN;
+      bit  [3 : 0] S_AXI_ACP_ARQOS;
+      bit  [3 : 0] S_AXI_ACP_AWCACHE;
+      bit  [3 : 0] S_AXI_ACP_AWLEN;
+      bit  [3 : 0] S_AXI_ACP_AWQOS;
+      bit  [1 : 0] S_AXI_ACP_ARBURST;
+      bit  [1 : 0] S_AXI_ACP_ARLOCK;
+      bit  [2 : 0] S_AXI_ACP_ARSIZE;
+      bit  [1 : 0] S_AXI_ACP_AWBURST;
+      bit  [1 : 0] S_AXI_ACP_AWLOCK;
+      bit  [2 : 0] S_AXI_ACP_AWSIZE;
+      bit  [4 : 0] S_AXI_ACP_ARUSER;
+      bit  [4 : 0] S_AXI_ACP_AWUSER;
+      bit  [63 : 0] S_AXI_ACP_WDATA;
+      bit  [7 : 0] S_AXI_ACP_WSTRB;
+      bit  S_AXI_HP0_ARREADY;
+      bit  S_AXI_HP0_AWREADY;
+      bit  S_AXI_HP0_BVALID;
+      bit  S_AXI_HP0_RLAST;
+      bit  S_AXI_HP0_RVALID;
+      bit  S_AXI_HP0_WREADY;
+      bit  [1 : 0] S_AXI_HP0_BRESP;
+      bit  [1 : 0] S_AXI_HP0_RRESP;
+      bit  [5 : 0] S_AXI_HP0_BID;
+      bit  [5 : 0] S_AXI_HP0_RID;
+      bit  [63 : 0] S_AXI_HP0_RDATA;
+      bit  [7 : 0] S_AXI_HP0_RCOUNT;
+      bit  [7 : 0] S_AXI_HP0_WCOUNT;
+      bit  [2 : 0] S_AXI_HP0_RACOUNT;
+      bit  [5 : 0] S_AXI_HP0_WACOUNT;
+      bit  S_AXI_HP0_ACLK;
+      bit  S_AXI_HP0_ARVALID;
+      bit  S_AXI_HP0_AWVALID;
+      bit  S_AXI_HP0_BREADY;
+      bit  S_AXI_HP0_RDISSUECAP1_EN;
+      bit  S_AXI_HP0_RREADY;
+      bit  S_AXI_HP0_WLAST;
+      bit  S_AXI_HP0_WRISSUECAP1_EN;
+      bit  S_AXI_HP0_WVALID;
+      bit  [1 : 0] S_AXI_HP0_ARBURST;
+      bit  [1 : 0] S_AXI_HP0_ARLOCK;
+      bit  [2 : 0] S_AXI_HP0_ARSIZE;
+      bit  [1 : 0] S_AXI_HP0_AWBURST;
+      bit  [1 : 0] S_AXI_HP0_AWLOCK;
+      bit  [2 : 0] S_AXI_HP0_AWSIZE;
+      bit  [2 : 0] S_AXI_HP0_ARPROT;
+      bit  [2 : 0] S_AXI_HP0_AWPROT;
+      bit  [31 : 0] S_AXI_HP0_ARADDR;
+      bit  [31 : 0] S_AXI_HP0_AWADDR;
+      bit  [3 : 0] S_AXI_HP0_ARCACHE;
+      bit  [3 : 0] S_AXI_HP0_ARLEN;
+      bit  [3 : 0] S_AXI_HP0_ARQOS;
+      bit  [3 : 0] S_AXI_HP0_AWCACHE;
+      bit  [3 : 0] S_AXI_HP0_AWLEN;
+      bit  [3 : 0] S_AXI_HP0_AWQOS;
+      bit  [5 : 0] S_AXI_HP0_ARID;
+      bit  [5 : 0] S_AXI_HP0_AWID;
+      bit  [5 : 0] S_AXI_HP0_WID;
+      bit  [63 : 0] S_AXI_HP0_WDATA;
+      bit  [7 : 0] S_AXI_HP0_WSTRB;
+      bit  S_AXI_HP1_ARREADY;
+      bit  S_AXI_HP1_AWREADY;
+      bit  S_AXI_HP1_BVALID;
+      bit  S_AXI_HP1_RLAST;
+      bit  S_AXI_HP1_RVALID;
+      bit  S_AXI_HP1_WREADY;
+      bit  [1 : 0] S_AXI_HP1_BRESP;
+      bit  [1 : 0] S_AXI_HP1_RRESP;
+      bit  [5 : 0] S_AXI_HP1_BID;
+      bit  [5 : 0] S_AXI_HP1_RID;
+      bit  [63 : 0] S_AXI_HP1_RDATA;
+      bit  [7 : 0] S_AXI_HP1_RCOUNT;
+      bit  [7 : 0] S_AXI_HP1_WCOUNT;
+      bit  [2 : 0] S_AXI_HP1_RACOUNT;
+      bit  [5 : 0] S_AXI_HP1_WACOUNT;
+      bit  S_AXI_HP1_ACLK;
+      bit  S_AXI_HP1_ARVALID;
+      bit  S_AXI_HP1_AWVALID;
+      bit  S_AXI_HP1_BREADY;
+      bit  S_AXI_HP1_RDISSUECAP1_EN;
+      bit  S_AXI_HP1_RREADY;
+      bit  S_AXI_HP1_WLAST;
+      bit  S_AXI_HP1_WRISSUECAP1_EN;
+      bit  S_AXI_HP1_WVALID;
+      bit  [1 : 0] S_AXI_HP1_ARBURST;
+      bit  [1 : 0] S_AXI_HP1_ARLOCK;
+      bit  [2 : 0] S_AXI_HP1_ARSIZE;
+      bit  [1 : 0] S_AXI_HP1_AWBURST;
+      bit  [1 : 0] S_AXI_HP1_AWLOCK;
+      bit  [2 : 0] S_AXI_HP1_AWSIZE;
+      bit  [2 : 0] S_AXI_HP1_ARPROT;
+      bit  [2 : 0] S_AXI_HP1_AWPROT;
+      bit  [31 : 0] S_AXI_HP1_ARADDR;
+      bit  [31 : 0] S_AXI_HP1_AWADDR;
+      bit  [3 : 0] S_AXI_HP1_ARCACHE;
+      bit  [3 : 0] S_AXI_HP1_ARLEN;
+      bit  [3 : 0] S_AXI_HP1_ARQOS;
+      bit  [3 : 0] S_AXI_HP1_AWCACHE;
+      bit  [3 : 0] S_AXI_HP1_AWLEN;
+      bit  [3 : 0] S_AXI_HP1_AWQOS;
+      bit  [5 : 0] S_AXI_HP1_ARID;
+      bit  [5 : 0] S_AXI_HP1_AWID;
+      bit  [5 : 0] S_AXI_HP1_WID;
+      bit  [63 : 0] S_AXI_HP1_WDATA;
+      bit  [7 : 0] S_AXI_HP1_WSTRB;
+      bit  S_AXI_HP2_ARREADY;
+      bit  S_AXI_HP2_AWREADY;
+      bit  S_AXI_HP2_BVALID;
+      bit  S_AXI_HP2_RLAST;
+      bit  S_AXI_HP2_RVALID;
+      bit  S_AXI_HP2_WREADY;
+      bit  [1 : 0] S_AXI_HP2_BRESP;
+      bit  [1 : 0] S_AXI_HP2_RRESP;
+      bit  [5 : 0] S_AXI_HP2_BID;
+      bit  [5 : 0] S_AXI_HP2_RID;
+      bit  [63 : 0] S_AXI_HP2_RDATA;
+      bit  [7 : 0] S_AXI_HP2_RCOUNT;
+      bit  [7 : 0] S_AXI_HP2_WCOUNT;
+      bit  [2 : 0] S_AXI_HP2_RACOUNT;
+      bit  [5 : 0] S_AXI_HP2_WACOUNT;
+      bit  S_AXI_HP2_ACLK;
+      bit  S_AXI_HP2_ARVALID;
+      bit  S_AXI_HP2_AWVALID;
+      bit  S_AXI_HP2_BREADY;
+      bit  S_AXI_HP2_RDISSUECAP1_EN;
+      bit  S_AXI_HP2_RREADY;
+      bit  S_AXI_HP2_WLAST;
+      bit  S_AXI_HP2_WRISSUECAP1_EN;
+      bit  S_AXI_HP2_WVALID;
+      bit  [1 : 0] S_AXI_HP2_ARBURST;
+      bit  [1 : 0] S_AXI_HP2_ARLOCK;
+      bit  [2 : 0] S_AXI_HP2_ARSIZE;
+      bit  [1 : 0] S_AXI_HP2_AWBURST;
+      bit  [1 : 0] S_AXI_HP2_AWLOCK;
+      bit  [2 : 0] S_AXI_HP2_AWSIZE;
+      bit  [2 : 0] S_AXI_HP2_ARPROT;
+      bit  [2 : 0] S_AXI_HP2_AWPROT;
+      bit  [31 : 0] S_AXI_HP2_ARADDR;
+      bit  [31 : 0] S_AXI_HP2_AWADDR;
+      bit  [3 : 0] S_AXI_HP2_ARCACHE;
+      bit  [3 : 0] S_AXI_HP2_ARLEN;
+      bit  [3 : 0] S_AXI_HP2_ARQOS;
+      bit  [3 : 0] S_AXI_HP2_AWCACHE;
+      bit  [3 : 0] S_AXI_HP2_AWLEN;
+      bit  [3 : 0] S_AXI_HP2_AWQOS;
+      bit  [5 : 0] S_AXI_HP2_ARID;
+      bit  [5 : 0] S_AXI_HP2_AWID;
+      bit  [5 : 0] S_AXI_HP2_WID;
+      bit  [63 : 0] S_AXI_HP2_WDATA;
+      bit  [7 : 0] S_AXI_HP2_WSTRB;
+      bit  S_AXI_HP3_ARREADY;
+      bit  S_AXI_HP3_AWREADY;
+      bit  S_AXI_HP3_BVALID;
+      bit  S_AXI_HP3_RLAST;
+      bit  S_AXI_HP3_RVALID;
+      bit  S_AXI_HP3_WREADY;
+      bit  [1 : 0] S_AXI_HP3_BRESP;
+      bit  [1 : 0] S_AXI_HP3_RRESP;
+      bit  [5 : 0] S_AXI_HP3_BID;
+      bit  [5 : 0] S_AXI_HP3_RID;
+      bit  [63 : 0] S_AXI_HP3_RDATA;
+      bit  [7 : 0] S_AXI_HP3_RCOUNT;
+      bit  [7 : 0] S_AXI_HP3_WCOUNT;
+      bit  [2 : 0] S_AXI_HP3_RACOUNT;
+      bit  [5 : 0] S_AXI_HP3_WACOUNT;
+      bit  S_AXI_HP3_ACLK;
+      bit  S_AXI_HP3_ARVALID;
+      bit  S_AXI_HP3_AWVALID;
+      bit  S_AXI_HP3_BREADY;
+      bit  S_AXI_HP3_RDISSUECAP1_EN;
+      bit  S_AXI_HP3_RREADY;
+      bit  S_AXI_HP3_WLAST;
+      bit  S_AXI_HP3_WRISSUECAP1_EN;
+      bit  S_AXI_HP3_WVALID;
+      bit  [1 : 0] S_AXI_HP3_ARBURST;
+      bit  [1 : 0] S_AXI_HP3_ARLOCK;
+      bit  [2 : 0] S_AXI_HP3_ARSIZE;
+      bit  [1 : 0] S_AXI_HP3_AWBURST;
+      bit  [1 : 0] S_AXI_HP3_AWLOCK;
+      bit  [2 : 0] S_AXI_HP3_AWSIZE;
+      bit  [2 : 0] S_AXI_HP3_ARPROT;
+      bit  [2 : 0] S_AXI_HP3_AWPROT;
+      bit  [31 : 0] S_AXI_HP3_ARADDR;
+      bit  [31 : 0] S_AXI_HP3_AWADDR;
+      bit  [3 : 0] S_AXI_HP3_ARCACHE;
+      bit  [3 : 0] S_AXI_HP3_ARLEN;
+      bit  [3 : 0] S_AXI_HP3_ARQOS;
+      bit  [3 : 0] S_AXI_HP3_AWCACHE;
+      bit  [3 : 0] S_AXI_HP3_AWLEN;
+      bit  [3 : 0] S_AXI_HP3_AWQOS;
+      bit  [5 : 0] S_AXI_HP3_ARID;
+      bit  [5 : 0] S_AXI_HP3_AWID;
+      bit  [5 : 0] S_AXI_HP3_WID;
+      bit  [63 : 0] S_AXI_HP3_WDATA;
+      bit  [7 : 0] S_AXI_HP3_WSTRB;
+      bit  IRQ_P2F_DMAC_ABORT;
+      bit  IRQ_P2F_DMAC0;
+      bit  IRQ_P2F_DMAC1;
+      bit  IRQ_P2F_DMAC2;
+      bit  IRQ_P2F_DMAC3;
+      bit  IRQ_P2F_DMAC4;
+      bit  IRQ_P2F_DMAC5;
+      bit  IRQ_P2F_DMAC6;
+      bit  IRQ_P2F_DMAC7;
+      bit  IRQ_P2F_SMC;
+      bit  IRQ_P2F_QSPI;
+      bit  IRQ_P2F_CTI;
+      bit  IRQ_P2F_GPIO;
+      bit  IRQ_P2F_USB0;
+      bit  IRQ_P2F_ENET0;
+      bit  IRQ_P2F_ENET_WAKE0;
+      bit  IRQ_P2F_SDIO0;
+      bit  IRQ_P2F_I2C0;
+      bit  IRQ_P2F_SPI0;
+      bit  IRQ_P2F_UART0;
+      bit  IRQ_P2F_CAN0;
+      bit  IRQ_P2F_USB1;
+      bit  IRQ_P2F_ENET1;
+      bit  IRQ_P2F_ENET_WAKE1;
+      bit  IRQ_P2F_SDIO1;
+      bit  IRQ_P2F_I2C1;
+      bit  IRQ_P2F_SPI1;
+      bit  IRQ_P2F_UART1;
+      bit  IRQ_P2F_CAN1;
+      bit  [1 : 0] IRQ_F2P;
+      bit  Core0_nFIQ;
+      bit  Core0_nIRQ;
+      bit  Core1_nFIQ;
+      bit  Core1_nIRQ;
+      bit  [1 : 0] DMA0_DATYPE;
+      bit  DMA0_DAVALID;
+      bit  DMA0_DRREADY;
+      bit  [1 : 0] DMA1_DATYPE;
+      bit  DMA1_DAVALID;
+      bit  DMA1_DRREADY;
+      bit  [1 : 0] DMA2_DATYPE;
+      bit  DMA2_DAVALID;
+      bit  DMA2_DRREADY;
+      bit  [1 : 0] DMA3_DATYPE;
+      bit  DMA3_DAVALID;
+      bit  DMA3_DRREADY;
+      bit  DMA0_ACLK;
+      bit  DMA0_DAREADY;
+      bit  DMA0_DRLAST;
+      bit  DMA0_DRVALID;
+      bit  DMA1_ACLK;
+      bit  DMA1_DAREADY;
+      bit  DMA1_DRLAST;
+      bit  DMA1_DRVALID;
+      bit  DMA2_ACLK;
+      bit  DMA2_DAREADY;
+      bit  DMA2_DRLAST;
+      bit  DMA2_DRVALID;
+      bit  DMA3_ACLK;
+      bit  DMA3_DAREADY;
+      bit  DMA3_DRLAST;
+      bit  DMA3_DRVALID;
+      bit  [1 : 0] DMA0_DRTYPE;
+      bit  [1 : 0] DMA1_DRTYPE;
+      bit  [1 : 0] DMA2_DRTYPE;
+      bit  [1 : 0] DMA3_DRTYPE;
+      bit  FCLK_CLK0;
+      bit  FCLK_CLK1;
+      bit  FCLK_CLK2;
+      bit  FCLK_CLK3;
+      bit  FCLK_CLKTRIG0_N;
+      bit  FCLK_CLKTRIG1_N;
+      bit  FCLK_CLKTRIG2_N;
+      bit  FCLK_CLKTRIG3_N;
+      bit  FCLK_RESET0_N;
+      bit  FCLK_RESET1_N;
+      bit  FCLK_RESET2_N;
+      bit  FCLK_RESET3_N;
+      bit  [31 : 0] FTMD_TRACEIN_DATA;
+      bit  FTMD_TRACEIN_VALID;
+      bit  FTMD_TRACEIN_CLK;
+      bit  [3 : 0] FTMD_TRACEIN_ATID;
+      bit  FTMT_F2P_TRIG_0;
+      bit  FTMT_F2P_TRIGACK_0;
+      bit  FTMT_F2P_TRIG_1;
+      bit  FTMT_F2P_TRIGACK_1;
+      bit  FTMT_F2P_TRIG_2;
+      bit  FTMT_F2P_TRIGACK_2;
+      bit  FTMT_F2P_TRIG_3;
+      bit  FTMT_F2P_TRIGACK_3;
+      bit  [31 : 0] FTMT_F2P_DEBUG;
+      bit  FTMT_P2F_TRIGACK_0;
+      bit  FTMT_P2F_TRIG_0;
+      bit  FTMT_P2F_TRIGACK_1;
+      bit  FTMT_P2F_TRIG_1;
+      bit  FTMT_P2F_TRIGACK_2;
+      bit  FTMT_P2F_TRIG_2;
+      bit  FTMT_P2F_TRIGACK_3;
+      bit  FTMT_P2F_TRIG_3;
+      bit  [31 : 0] FTMT_P2F_DEBUG;
+      bit  FPGA_IDLE_N;
+      bit  EVENT_EVENTO;
+      bit  [1 : 0] EVENT_STANDBYWFE;
+      bit  [1 : 0] EVENT_STANDBYWFI;
+      bit  EVENT_EVENTI;
+      bit  [3 : 0] DDR_ARB;
+      bit  [53 : 0] MIO;
+      bit  DDR_CAS_n;
+      bit  DDR_CKE;
+      bit  DDR_Clk_n;
+      bit  DDR_Clk;
+      bit  DDR_CS_n;
+      bit  DDR_DRSTB;
+      bit  DDR_ODT;
+      bit  DDR_RAS_n;
+      bit  DDR_WEB;
+      bit  [2 : 0] DDR_BankAddr;
+      bit  [14 : 0] DDR_Addr;
+      bit  DDR_VRN;
+      bit  DDR_VRP;
+      bit  [3 : 0] DDR_DM;
+      bit  [31 : 0] DDR_DQ;
+      bit  [3 : 0] DDR_DQS_n;
+      bit  [3 : 0] DDR_DQS;
+      bit  PS_SRSTB;
+      bit  PS_CLK;
+      bit  PS_PORB;
+
+//MODULE DECLARATION
+ module system_processing_system7_0_0 (
+  M_AXI_GP0_ARVALID,
+  M_AXI_GP0_AWVALID,
+  M_AXI_GP0_BREADY,
+  M_AXI_GP0_RREADY,
+  M_AXI_GP0_WLAST,
+  M_AXI_GP0_WVALID,
+  M_AXI_GP0_ARID,
+  M_AXI_GP0_AWID,
+  M_AXI_GP0_WID,
+  M_AXI_GP0_ARBURST,
+  M_AXI_GP0_ARLOCK,
+  M_AXI_GP0_ARSIZE,
+  M_AXI_GP0_AWBURST,
+  M_AXI_GP0_AWLOCK,
+  M_AXI_GP0_AWSIZE,
+  M_AXI_GP0_ARPROT,
+  M_AXI_GP0_AWPROT,
+  M_AXI_GP0_ARADDR,
+  M_AXI_GP0_AWADDR,
+  M_AXI_GP0_WDATA,
+  M_AXI_GP0_ARCACHE,
+  M_AXI_GP0_ARLEN,
+  M_AXI_GP0_ARQOS,
+  M_AXI_GP0_AWCACHE,
+  M_AXI_GP0_AWLEN,
+  M_AXI_GP0_AWQOS,
+  M_AXI_GP0_WSTRB,
+  M_AXI_GP0_ACLK,
+  M_AXI_GP0_ARREADY,
+  M_AXI_GP0_AWREADY,
+  M_AXI_GP0_BVALID,
+  M_AXI_GP0_RLAST,
+  M_AXI_GP0_RVALID,
+  M_AXI_GP0_WREADY,
+  M_AXI_GP0_BID,
+  M_AXI_GP0_RID,
+  M_AXI_GP0_BRESP,
+  M_AXI_GP0_RRESP,
+  M_AXI_GP0_RDATA,
+  FCLK_CLK0,
+  FCLK_RESET0_N,
+  MIO,
+  DDR_CAS_n,
+  DDR_CKE,
+  DDR_Clk_n,
+  DDR_Clk,
+  DDR_CS_n,
+  DDR_DRSTB,
+  DDR_ODT,
+  DDR_RAS_n,
+  DDR_WEB,
+  DDR_BankAddr,
+  DDR_Addr,
+  DDR_VRN,
+  DDR_VRP,
+  DDR_DM,
+  DDR_DQ,
+  DDR_DQS_n,
+  DDR_DQS,
+  PS_SRSTB,
+  PS_CLK,
+  PS_PORB
+ );
+
+//PARAMETERS
+
+      parameter C_EN_EMIO_PJTAG = 0;
+      parameter C_EN_EMIO_ENET0 = 0;
+      parameter C_EN_EMIO_ENET1 = 0;
+      parameter C_EN_EMIO_TRACE = 0;
+      parameter C_INCLUDE_TRACE_BUFFER = 0;
+      parameter C_TRACE_BUFFER_FIFO_SIZE = 128;
+      parameter USE_TRACE_DATA_EDGE_DETECTOR = 0;
+      parameter C_TRACE_PIPELINE_WIDTH = 8;
+      parameter C_TRACE_BUFFER_CLOCK_DELAY = 12;
+      parameter C_EMIO_GPIO_WIDTH = 64;
+      parameter C_INCLUDE_ACP_TRANS_CHECK = 0;
+      parameter C_USE_DEFAULT_ACP_USER_VAL = 0;
+      parameter C_S_AXI_ACP_ARUSER_VAL = 31;
+      parameter C_S_AXI_ACP_AWUSER_VAL = 31;
+      parameter C_M_AXI_GP0_ID_WIDTH = 12;
+      parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
+      parameter C_M_AXI_GP1_ID_WIDTH = 12;
+      parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
+      parameter C_S_AXI_GP0_ID_WIDTH = 6;
+      parameter C_S_AXI_GP1_ID_WIDTH = 6;
+      parameter C_S_AXI_ACP_ID_WIDTH = 3;
+      parameter C_S_AXI_HP0_ID_WIDTH = 6;
+      parameter C_S_AXI_HP0_DATA_WIDTH = 64;
+      parameter C_S_AXI_HP1_ID_WIDTH = 6;
+      parameter C_S_AXI_HP1_DATA_WIDTH = 64;
+      parameter C_S_AXI_HP2_ID_WIDTH = 6;
+      parameter C_S_AXI_HP2_DATA_WIDTH = 64;
+      parameter C_S_AXI_HP3_ID_WIDTH = 6;
+      parameter C_S_AXI_HP3_DATA_WIDTH = 64;
+      parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
+      parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
+      parameter C_NUM_F2P_INTR_INPUTS = 2;
+      parameter C_IRQ_F2P_MODE = "DIRECT";
+      parameter C_DQ_WIDTH = 32;
+      parameter C_DQS_WIDTH = 4;
+      parameter C_DM_WIDTH = 4;
+      parameter C_MIO_PRIMITIVE = 54;
+      parameter C_TRACE_INTERNAL_WIDTH = 2;
+      parameter C_USE_AXI_NONSECURE = 0;
+      parameter C_USE_M_AXI_GP0 = 1;
+      parameter C_USE_M_AXI_GP1 = 0;
+      parameter C_USE_S_AXI_GP0 = 0;
+      parameter C_USE_S_AXI_GP1 = 0;
+      parameter C_USE_S_AXI_HP0 = 0;
+      parameter C_USE_S_AXI_HP1 = 0;
+      parameter C_USE_S_AXI_HP2 = 0;
+      parameter C_USE_S_AXI_HP3 = 0;
+      parameter C_USE_S_AXI_ACP = 0;
+      parameter C_PS7_SI_REV = "PRODUCTION";
+      parameter C_FCLK_CLK0_BUF = "TRUE";
+      parameter C_FCLK_CLK1_BUF = "FALSE";
+      parameter C_FCLK_CLK2_BUF = "FALSE";
+      parameter C_FCLK_CLK3_BUF = "FALSE";
+      parameter C_PACKAGE_NAME = "clg400";
+      parameter C_GP0_EN_MODIFIABLE_TXN = "0";
+      parameter C_GP1_EN_MODIFIABLE_TXN = "0";
+
+//INPUT AND OUTPUT PORTS
+
+      output  M_AXI_GP0_ARVALID;
+      output  M_AXI_GP0_AWVALID;
+      output  M_AXI_GP0_BREADY;
+      output  M_AXI_GP0_RREADY;
+      output  M_AXI_GP0_WLAST;
+      output  M_AXI_GP0_WVALID;
+      output  [11 : 0] M_AXI_GP0_ARID;
+      output  [11 : 0] M_AXI_GP0_AWID;
+      output  [11 : 0] M_AXI_GP0_WID;
+      output  [1 : 0] M_AXI_GP0_ARBURST;
+      output  [1 : 0] M_AXI_GP0_ARLOCK;
+      output  [2 : 0] M_AXI_GP0_ARSIZE;
+      output  [1 : 0] M_AXI_GP0_AWBURST;
+      output  [1 : 0] M_AXI_GP0_AWLOCK;
+      output  [2 : 0] M_AXI_GP0_AWSIZE;
+      output  [2 : 0] M_AXI_GP0_ARPROT;
+      output  [2 : 0] M_AXI_GP0_AWPROT;
+      output  [31 : 0] M_AXI_GP0_ARADDR;
+      output  [31 : 0] M_AXI_GP0_AWADDR;
+      output  [31 : 0] M_AXI_GP0_WDATA;
+      output  [3 : 0] M_AXI_GP0_ARCACHE;
+      output  [3 : 0] M_AXI_GP0_ARLEN;
+      output  [3 : 0] M_AXI_GP0_ARQOS;
+      output  [3 : 0] M_AXI_GP0_AWCACHE;
+      output  [3 : 0] M_AXI_GP0_AWLEN;
+      output  [3 : 0] M_AXI_GP0_AWQOS;
+      output  [3 : 0] M_AXI_GP0_WSTRB;
+      input  M_AXI_GP0_ACLK;
+      input  M_AXI_GP0_ARREADY;
+      input  M_AXI_GP0_AWREADY;
+      input  M_AXI_GP0_BVALID;
+      input  M_AXI_GP0_RLAST;
+      input  M_AXI_GP0_RVALID;
+      input  M_AXI_GP0_WREADY;
+      input  [11 : 0] M_AXI_GP0_BID;
+      input  [11 : 0] M_AXI_GP0_RID;
+      input  [1 : 0] M_AXI_GP0_BRESP;
+      input  [1 : 0] M_AXI_GP0_RRESP;
+      input  [31 : 0] M_AXI_GP0_RDATA;
+      output  FCLK_CLK0;
+      output  FCLK_RESET0_N;
+      inout  [53 : 0] MIO;
+      inout  DDR_CAS_n;
+      inout  DDR_CKE;
+      inout  DDR_Clk_n;
+      inout  DDR_Clk;
+      inout  DDR_CS_n;
+      inout  DDR_DRSTB;
+      inout  DDR_ODT;
+      inout  DDR_RAS_n;
+      inout  DDR_WEB;
+      inout  [2 : 0] DDR_BankAddr;
+      inout  [14 : 0] DDR_Addr;
+      inout  DDR_VRN;
+      inout  DDR_VRP;
+      inout  [3 : 0] DDR_DM;
+      inout  [31 : 0] DDR_DQ;
+      inout  [3 : 0] DDR_DQS_n;
+      inout  [3 : 0] DDR_DQS;
+      inout  PS_SRSTB;
+      inout  PS_CLK;
+      inout  PS_PORB;
+
+//REG DECLARATIONS
+
+      reg M_AXI_GP0_ARVALID;
+      reg M_AXI_GP0_AWVALID;
+      reg M_AXI_GP0_BREADY;
+      reg M_AXI_GP0_RREADY;
+      reg M_AXI_GP0_WLAST;
+      reg M_AXI_GP0_WVALID;
+      reg [11 : 0] M_AXI_GP0_ARID;
+      reg [11 : 0] M_AXI_GP0_AWID;
+      reg [11 : 0] M_AXI_GP0_WID;
+      reg [1 : 0] M_AXI_GP0_ARBURST;
+      reg [1 : 0] M_AXI_GP0_ARLOCK;
+      reg [2 : 0] M_AXI_GP0_ARSIZE;
+      reg [1 : 0] M_AXI_GP0_AWBURST;
+      reg [1 : 0] M_AXI_GP0_AWLOCK;
+      reg [2 : 0] M_AXI_GP0_AWSIZE;
+      reg [2 : 0] M_AXI_GP0_ARPROT;
+      reg [2 : 0] M_AXI_GP0_AWPROT;
+      reg [31 : 0] M_AXI_GP0_ARADDR;
+      reg [31 : 0] M_AXI_GP0_AWADDR;
+      reg [31 : 0] M_AXI_GP0_WDATA;
+      reg [3 : 0] M_AXI_GP0_ARCACHE;
+      reg [3 : 0] M_AXI_GP0_ARLEN;
+      reg [3 : 0] M_AXI_GP0_ARQOS;
+      reg [3 : 0] M_AXI_GP0_AWCACHE;
+      reg [3 : 0] M_AXI_GP0_AWLEN;
+      reg [3 : 0] M_AXI_GP0_AWQOS;
+      reg [3 : 0] M_AXI_GP0_WSTRB;
+      reg FCLK_CLK0;
+      reg FCLK_RESET0_N;
+      string ip_name;
+      reg disable_port;
+
+//DPI DECLARATIONS
+import "DPI-C" function void ps7_set_ip_context(input string ip_name);
+import "DPI-C" function void ps7_set_str_param(input string name,input string val);
+import "DPI-C" function void ps7_set_int_param(input string name,input longint val);
+import "DPI-C" function void ps7_init_c_model();
+import "DPI-C" function void ps7_init_m_axi_gp0(input int M_AXI_GP0_AWID_size,input int M_AXI_GP0_AWADDR_size,input int M_AXI_GP0_AWLEN_size,input int M_AXI_GP0_AWSIZE_size,input int M_AXI_GP0_AWBURST_size,input int M_AXI_GP0_AWLOCK_size,input int M_AXI_GP0_AWCACHE_size,input int M_AXI_GP0_AWPROT_size,input int M_AXI_GP0_AWQOS_size,input int M_AXI_GP0_AWVALID_size,input int M_AXI_GP0_AWREADY_size,input int M_AXI_GP0_WID_size,input int M_AXI_GP0_WDATA_size,input int M_AXI_GP0_WSTRB_size,input int M_AXI_GP0_WLAST_size,input int M_AXI_GP0_WVALID_size,input int M_AXI_GP0_WREADY_size,input int M_AXI_GP0_BID_size,input int M_AXI_GP0_BRESP_size,input int M_AXI_GP0_BVALID_size,input int M_AXI_GP0_BREADY_size,input int M_AXI_GP0_ARID_size,input int M_AXI_GP0_ARADDR_size,input int M_AXI_GP0_ARLEN_size,input int M_AXI_GP0_ARSIZE_size,input int M_AXI_GP0_ARBURST_size,input int M_AXI_GP0_ARLOCK_size,input int M_AXI_GP0_ARCACHE_size,input int M_AXI_GP0_ARPROT_size,input int M_AXI_GP0_ARQOS_size,input int M_AXI_GP0_ARVALID_size,input int M_AXI_GP0_ARREADY_size,input int M_AXI_GP0_RID_size,input int M_AXI_GP0_RDATA_size,input int M_AXI_GP0_RRESP_size,input int M_AXI_GP0_RLAST_size,input int M_AXI_GP0_RVALID_size,input int M_AXI_GP0_RREADY_size);
+import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0();
+import "DPI-C" function void ps7_simulate_single_cycle_M_AXI_GP0_ACLK();
+import "DPI-C" function void ps7_set_inputs_m_axi_gp0_M_AXI_GP0_ACLK(
+input bit M_AXI_GP0_AWREADY,
+input bit M_AXI_GP0_WREADY,
+input bit [11 : 0] M_AXI_GP0_BID,
+input bit [1 : 0] M_AXI_GP0_BRESP,
+input bit M_AXI_GP0_BVALID,
+input bit M_AXI_GP0_ARREADY,
+input bit [11 : 0] M_AXI_GP0_RID,
+input bit [31 : 0] M_AXI_GP0_RDATA,
+input bit [1 : 0] M_AXI_GP0_RRESP,
+input bit M_AXI_GP0_RLAST,
+input bit M_AXI_GP0_RVALID
+);
+import "DPI-C" function void ps7_get_outputs_m_axi_gp0_M_AXI_GP0_ACLK(
+output bit [11 : 0] M_AXI_GP0_AWID,
+output bit [31 : 0] M_AXI_GP0_AWADDR,
+output bit [3 : 0] M_AXI_GP0_AWLEN,
+output bit [2 : 0] M_AXI_GP0_AWSIZE,
+output bit [1 : 0] M_AXI_GP0_AWBURST,
+output bit [1 : 0] M_AXI_GP0_AWLOCK,
+output bit [3 : 0] M_AXI_GP0_AWCACHE,
+output bit [2 : 0] M_AXI_GP0_AWPROT,
+output bit [3 : 0] M_AXI_GP0_AWQOS,
+output bit M_AXI_GP0_AWVALID,
+output bit [11 : 0] M_AXI_GP0_WID,
+output bit [31 : 0] M_AXI_GP0_WDATA,
+output bit [3 : 0] M_AXI_GP0_WSTRB,
+output bit M_AXI_GP0_WLAST,
+output bit M_AXI_GP0_WVALID,
+output bit M_AXI_GP0_BREADY,
+output bit [11 : 0] M_AXI_GP0_ARID,
+output bit [31 : 0] M_AXI_GP0_ARADDR,
+output bit [3 : 0] M_AXI_GP0_ARLEN,
+output bit [2 : 0] M_AXI_GP0_ARSIZE,
+output bit [1 : 0] M_AXI_GP0_ARBURST,
+output bit [1 : 0] M_AXI_GP0_ARLOCK,
+output bit [3 : 0] M_AXI_GP0_ARCACHE,
+output bit [2 : 0] M_AXI_GP0_ARPROT,
+output bit [3 : 0] M_AXI_GP0_ARQOS,
+output bit M_AXI_GP0_ARVALID,
+output bit M_AXI_GP0_RREADY
+);
+
+   export "DPI-C" function ps7_stop_sim;
+   function void ps7_stop_sim();
+        $display("End of simulation");
+        $finish(0);
+   endfunction
+   export "DPI-C" function ps7_get_time;
+   function real ps7_get_time();
+       ps7_get_time = $time;
+   endfunction
+
+   export "DPI-C" function ps7_set_output_pins_FCLK_RESET0_N;
+   function void ps7_set_output_pins_FCLK_RESET0_N(int value);
+       FCLK_RESET0_N = value; 
+   endfunction
+
+   export "DPI-C" function ps7_set_output_pins_FCLK_RESET1_N;
+   function void ps7_set_output_pins_FCLK_RESET1_N(int value);
+       FCLK_RESET1_N = value; 
+   endfunction
+
+   export "DPI-C" function ps7_set_output_pins_FCLK_RESET2_N;
+   function void ps7_set_output_pins_FCLK_RESET2_N(int value);
+       FCLK_RESET2_N = value; 
+   endfunction
+
+   export "DPI-C" function ps7_set_output_pins_FCLK_RESET3_N;
+   function void ps7_set_output_pins_FCLK_RESET3_N(int value);
+       FCLK_RESET3_N = value; 
+   endfunction
+
+
+//INITIAL BLOCK
+
+   initial
+   begin
+  $sformat(ip_name,"%m");
+      ps7_set_ip_context(ip_name);
+      ps7_set_int_param ( "C_EN_EMIO_PJTAG",C_EN_EMIO_PJTAG );
+      ps7_set_int_param ( "C_EN_EMIO_ENET0",C_EN_EMIO_ENET0 );
+      ps7_set_int_param ( "C_EN_EMIO_ENET1",C_EN_EMIO_ENET1 );
+      ps7_set_int_param ( "C_EN_EMIO_TRACE",C_EN_EMIO_TRACE );
+      ps7_set_int_param ( "C_INCLUDE_TRACE_BUFFER",C_INCLUDE_TRACE_BUFFER );
+      ps7_set_int_param ( "C_TRACE_BUFFER_FIFO_SIZE",C_TRACE_BUFFER_FIFO_SIZE );
+      ps7_set_int_param ( "USE_TRACE_DATA_EDGE_DETECTOR",USE_TRACE_DATA_EDGE_DETECTOR );
+      ps7_set_int_param ( "C_TRACE_PIPELINE_WIDTH",C_TRACE_PIPELINE_WIDTH );
+      ps7_set_int_param ( "C_TRACE_BUFFER_CLOCK_DELAY",C_TRACE_BUFFER_CLOCK_DELAY );
+      ps7_set_int_param ( "C_EMIO_GPIO_WIDTH",C_EMIO_GPIO_WIDTH );
+      ps7_set_int_param ( "C_INCLUDE_ACP_TRANS_CHECK",C_INCLUDE_ACP_TRANS_CHECK );
+      ps7_set_int_param ( "C_USE_DEFAULT_ACP_USER_VAL",C_USE_DEFAULT_ACP_USER_VAL );
+      ps7_set_int_param ( "C_S_AXI_ACP_ARUSER_VAL",C_S_AXI_ACP_ARUSER_VAL );
+      ps7_set_int_param ( "C_S_AXI_ACP_AWUSER_VAL",C_S_AXI_ACP_AWUSER_VAL );
+      ps7_set_int_param ( "C_M_AXI_GP0_ID_WIDTH",C_M_AXI_GP0_ID_WIDTH );
+      ps7_set_int_param ( "C_M_AXI_GP0_ENABLE_STATIC_REMAP",C_M_AXI_GP0_ENABLE_STATIC_REMAP );
+      ps7_set_int_param ( "C_M_AXI_GP1_ID_WIDTH",C_M_AXI_GP1_ID_WIDTH );
+      ps7_set_int_param ( "C_M_AXI_GP1_ENABLE_STATIC_REMAP",C_M_AXI_GP1_ENABLE_STATIC_REMAP );
+      ps7_set_int_param ( "C_S_AXI_GP0_ID_WIDTH",C_S_AXI_GP0_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_GP1_ID_WIDTH",C_S_AXI_GP1_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_ACP_ID_WIDTH",C_S_AXI_ACP_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP0_ID_WIDTH",C_S_AXI_HP0_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP0_DATA_WIDTH",C_S_AXI_HP0_DATA_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP1_ID_WIDTH",C_S_AXI_HP1_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP1_DATA_WIDTH",C_S_AXI_HP1_DATA_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP2_ID_WIDTH",C_S_AXI_HP2_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP2_DATA_WIDTH",C_S_AXI_HP2_DATA_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP3_ID_WIDTH",C_S_AXI_HP3_ID_WIDTH );
+      ps7_set_int_param ( "C_S_AXI_HP3_DATA_WIDTH",C_S_AXI_HP3_DATA_WIDTH );
+      ps7_set_int_param ( "C_M_AXI_GP0_THREAD_ID_WIDTH",C_M_AXI_GP0_THREAD_ID_WIDTH );
+      ps7_set_int_param ( "C_M_AXI_GP1_THREAD_ID_WIDTH",C_M_AXI_GP1_THREAD_ID_WIDTH );
+      ps7_set_int_param ( "C_NUM_F2P_INTR_INPUTS",C_NUM_F2P_INTR_INPUTS );
+      ps7_set_str_param ( "C_IRQ_F2P_MODE",C_IRQ_F2P_MODE );
+      ps7_set_int_param ( "C_DQ_WIDTH",C_DQ_WIDTH );
+      ps7_set_int_param ( "C_DQS_WIDTH",C_DQS_WIDTH );
+      ps7_set_int_param ( "C_DM_WIDTH",C_DM_WIDTH );
+      ps7_set_int_param ( "C_MIO_PRIMITIVE",C_MIO_PRIMITIVE );
+      ps7_set_int_param ( "C_TRACE_INTERNAL_WIDTH",C_TRACE_INTERNAL_WIDTH );
+      ps7_set_int_param ( "C_USE_AXI_NONSECURE",C_USE_AXI_NONSECURE );
+      ps7_set_int_param ( "C_USE_M_AXI_GP0",C_USE_M_AXI_GP0 );
+      ps7_set_int_param ( "C_USE_M_AXI_GP1",C_USE_M_AXI_GP1 );
+      ps7_set_int_param ( "C_USE_S_AXI_GP0",C_USE_S_AXI_GP0 );
+      ps7_set_int_param ( "C_USE_S_AXI_GP1",C_USE_S_AXI_GP1 );
+      ps7_set_int_param ( "C_USE_S_AXI_HP0",C_USE_S_AXI_HP0 );
+      ps7_set_int_param ( "C_USE_S_AXI_HP1",C_USE_S_AXI_HP1 );
+      ps7_set_int_param ( "C_USE_S_AXI_HP2",C_USE_S_AXI_HP2 );
+      ps7_set_int_param ( "C_USE_S_AXI_HP3",C_USE_S_AXI_HP3 );
+      ps7_set_int_param ( "C_USE_S_AXI_ACP",C_USE_S_AXI_ACP );
+      ps7_set_str_param ( "C_PS7_SI_REV",C_PS7_SI_REV );
+      ps7_set_str_param ( "C_FCLK_CLK0_BUF",C_FCLK_CLK0_BUF );
+      ps7_set_str_param ( "C_FCLK_CLK1_BUF",C_FCLK_CLK1_BUF );
+      ps7_set_str_param ( "C_FCLK_CLK2_BUF",C_FCLK_CLK2_BUF );
+      ps7_set_str_param ( "C_FCLK_CLK3_BUF",C_FCLK_CLK3_BUF );
+      ps7_set_str_param ( "C_PACKAGE_NAME",C_PACKAGE_NAME );
+      ps7_set_str_param ( "C_GP0_EN_MODIFIABLE_TXN",C_GP0_EN_MODIFIABLE_TXN );
+      ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN );
+
+  ps7_init_m_axi_gp0($bits(M_AXI_GP0_AWID),$bits(M_AXI_GP0_AWADDR),$bits(M_AXI_GP0_AWLEN),$bits(M_AXI_GP0_AWSIZE),$bits(M_AXI_GP0_AWBURST),$bits(M_AXI_GP0_AWLOCK),$bits(M_AXI_GP0_AWCACHE),$bits(M_AXI_GP0_AWPROT),$bits(M_AXI_GP0_AWQOS),$bits(M_AXI_GP0_AWVALID),$bits(M_AXI_GP0_AWREADY),$bits(M_AXI_GP0_WID),$bits(M_AXI_GP0_WDATA),$bits(M_AXI_GP0_WSTRB),$bits(M_AXI_GP0_WLAST),$bits(M_AXI_GP0_WVALID),$bits(M_AXI_GP0_WREADY),$bits(M_AXI_GP0_BID),$bits(M_AXI_GP0_BRESP),$bits(M_AXI_GP0_BVALID),$bits(M_AXI_GP0_BREADY),$bits(M_AXI_GP0_ARID),$bits(M_AXI_GP0_ARADDR),$bits(M_AXI_GP0_ARLEN),$bits(M_AXI_GP0_ARSIZE),$bits(M_AXI_GP0_ARBURST),$bits(M_AXI_GP0_ARLOCK),$bits(M_AXI_GP0_ARCACHE),$bits(M_AXI_GP0_ARPROT),$bits(M_AXI_GP0_ARQOS),$bits(M_AXI_GP0_ARVALID),$bits(M_AXI_GP0_ARREADY),$bits(M_AXI_GP0_RID),$bits(M_AXI_GP0_RDATA),$bits(M_AXI_GP0_RRESP),$bits(M_AXI_GP0_RLAST),$bits(M_AXI_GP0_RVALID),$bits(M_AXI_GP0_RREADY));
+  ps7_init_c_model();
+  end
+  initial
+  begin
+     FCLK_CLK0 = 1'b0;
+  end
+
+  always #(10.0) FCLK_CLK0 <= ~FCLK_CLK0;
+
+  always@(posedge FCLK_CLK0)
+  begin
+   ps7_set_ip_context(ip_name);
+   ps7_simulate_single_cycle_FCLK_CLK0();
+  end
+
+
+always@(posedge M_AXI_GP0_ACLK)
+  begin
+
+   ps7_set_ip_context(ip_name);
+
+   ps7_set_inputs_m_axi_gp0_M_AXI_GP0_ACLK(
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID
+  );
+
+   ps7_simulate_single_cycle_M_AXI_GP0_ACLK();
+
+   ps7_get_outputs_m_axi_gp0_M_AXI_GP0_ACLK(
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_RREADY
+  );
+   end
+
+endmodule
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v
new file mode 100644
index 0000000..c917432
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v
@@ -0,0 +1,578 @@
+ 
+
+
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+module system_processing_system7_0_0 (
+M_AXI_GP0_ARVALID, 
+M_AXI_GP0_AWVALID, 
+M_AXI_GP0_BREADY, 
+M_AXI_GP0_RREADY, 
+M_AXI_GP0_WLAST, 
+M_AXI_GP0_WVALID, 
+M_AXI_GP0_ARID, 
+M_AXI_GP0_AWID, 
+M_AXI_GP0_WID, 
+M_AXI_GP0_ARBURST, 
+M_AXI_GP0_ARLOCK, 
+M_AXI_GP0_ARSIZE, 
+M_AXI_GP0_AWBURST, 
+M_AXI_GP0_AWLOCK, 
+M_AXI_GP0_AWSIZE, 
+M_AXI_GP0_ARPROT, 
+M_AXI_GP0_AWPROT, 
+M_AXI_GP0_ARADDR, 
+M_AXI_GP0_AWADDR, 
+M_AXI_GP0_WDATA, 
+M_AXI_GP0_ARCACHE, 
+M_AXI_GP0_ARLEN, 
+M_AXI_GP0_ARQOS, 
+M_AXI_GP0_AWCACHE, 
+M_AXI_GP0_AWLEN, 
+M_AXI_GP0_AWQOS, 
+M_AXI_GP0_WSTRB, 
+M_AXI_GP0_ACLK, 
+M_AXI_GP0_ARREADY, 
+M_AXI_GP0_AWREADY, 
+M_AXI_GP0_BVALID, 
+M_AXI_GP0_RLAST, 
+M_AXI_GP0_RVALID, 
+M_AXI_GP0_WREADY, 
+M_AXI_GP0_BID, 
+M_AXI_GP0_RID, 
+M_AXI_GP0_BRESP, 
+M_AXI_GP0_RRESP, 
+M_AXI_GP0_RDATA, 
+FCLK_CLK0, 
+FCLK_RESET0_N, 
+MIO, 
+DDR_CAS_n, 
+DDR_CKE, 
+DDR_Clk_n, 
+DDR_Clk, 
+DDR_CS_n, 
+DDR_DRSTB, 
+DDR_ODT, 
+DDR_RAS_n, 
+DDR_WEB, 
+DDR_BankAddr, 
+DDR_Addr, 
+DDR_VRN, 
+DDR_VRP, 
+DDR_DM, 
+DDR_DQ, 
+DDR_DQS_n, 
+DDR_DQS, 
+PS_SRSTB, 
+PS_CLK, 
+PS_PORB 
+);
+output M_AXI_GP0_ARVALID;
+output M_AXI_GP0_AWVALID;
+output M_AXI_GP0_BREADY;
+output M_AXI_GP0_RREADY;
+output M_AXI_GP0_WLAST;
+output M_AXI_GP0_WVALID;
+output [11 : 0] M_AXI_GP0_ARID;
+output [11 : 0] M_AXI_GP0_AWID;
+output [11 : 0] M_AXI_GP0_WID;
+output [1 : 0] M_AXI_GP0_ARBURST;
+output [1 : 0] M_AXI_GP0_ARLOCK;
+output [2 : 0] M_AXI_GP0_ARSIZE;
+output [1 : 0] M_AXI_GP0_AWBURST;
+output [1 : 0] M_AXI_GP0_AWLOCK;
+output [2 : 0] M_AXI_GP0_AWSIZE;
+output [2 : 0] M_AXI_GP0_ARPROT;
+output [2 : 0] M_AXI_GP0_AWPROT;
+output [31 : 0] M_AXI_GP0_ARADDR;
+output [31 : 0] M_AXI_GP0_AWADDR;
+output [31 : 0] M_AXI_GP0_WDATA;
+output [3 : 0] M_AXI_GP0_ARCACHE;
+output [3 : 0] M_AXI_GP0_ARLEN;
+output [3 : 0] M_AXI_GP0_ARQOS;
+output [3 : 0] M_AXI_GP0_AWCACHE;
+output [3 : 0] M_AXI_GP0_AWLEN;
+output [3 : 0] M_AXI_GP0_AWQOS;
+output [3 : 0] M_AXI_GP0_WSTRB;
+input M_AXI_GP0_ACLK;
+input M_AXI_GP0_ARREADY;
+input M_AXI_GP0_AWREADY;
+input M_AXI_GP0_BVALID;
+input M_AXI_GP0_RLAST;
+input M_AXI_GP0_RVALID;
+input M_AXI_GP0_WREADY;
+input [11 : 0] M_AXI_GP0_BID;
+input [11 : 0] M_AXI_GP0_RID;
+input [1 : 0] M_AXI_GP0_BRESP;
+input [1 : 0] M_AXI_GP0_RRESP;
+input [31 : 0] M_AXI_GP0_RDATA;
+output FCLK_CLK0;
+output FCLK_RESET0_N;
+input [53 : 0] MIO;
+input DDR_CAS_n;
+input DDR_CKE;
+input DDR_Clk_n;
+input DDR_Clk;
+input DDR_CS_n;
+input DDR_DRSTB;
+input DDR_ODT;
+input DDR_RAS_n;
+input DDR_WEB;
+input [2 : 0] DDR_BankAddr;
+input [14 : 0] DDR_Addr;
+input DDR_VRN;
+input DDR_VRP;
+input [3 : 0] DDR_DM;
+input [31 : 0] DDR_DQ;
+input [3 : 0] DDR_DQS_n;
+input [3 : 0] DDR_DQS;
+input PS_SRSTB;
+input PS_CLK;
+input PS_PORB;
+
+  processing_system7_vip_v1_0_3 #(
+    .C_USE_M_AXI_GP0(1),
+    .C_USE_M_AXI_GP1(0),
+    .C_USE_S_AXI_ACP(0),
+    .C_USE_S_AXI_GP0(0),
+    .C_USE_S_AXI_GP1(0),
+    .C_USE_S_AXI_HP0(0),
+    .C_USE_S_AXI_HP1(0),
+    .C_USE_S_AXI_HP2(0),
+    .C_USE_S_AXI_HP3(0),
+    .C_S_AXI_HP0_DATA_WIDTH(64),
+    .C_S_AXI_HP1_DATA_WIDTH(64),
+    .C_S_AXI_HP2_DATA_WIDTH(64),
+    .C_S_AXI_HP3_DATA_WIDTH(64),
+    .C_HIGH_OCM_EN(0),
+    .C_FCLK_CLK0_FREQ(50.0),
+    .C_FCLK_CLK1_FREQ(10.0),
+    .C_FCLK_CLK2_FREQ(10.0),
+    .C_FCLK_CLK3_FREQ(10.0),
+	.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
+	.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
+	.C_M_AXI_GP0_THREAD_ID_WIDTH (12), 
+	.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
+  ) inst (
+    .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+    .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+    .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+    .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+    .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+    .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+    .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+    .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+    .M_AXI_GP0_WID(M_AXI_GP0_WID),
+    .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+    .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+    .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+    .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+    .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+    .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+    .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+    .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+    .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+    .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+    .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+    .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+    .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+    .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+    .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+    .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+    .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+    .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+    .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+    .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+    .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+    .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+    .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+    .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+    .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+    .M_AXI_GP0_BID(M_AXI_GP0_BID),
+    .M_AXI_GP0_RID(M_AXI_GP0_RID),
+    .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+    .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+    .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+    .M_AXI_GP1_ARVALID(),
+    .M_AXI_GP1_AWVALID(),
+    .M_AXI_GP1_BREADY(),
+    .M_AXI_GP1_RREADY(),
+    .M_AXI_GP1_WLAST(),
+    .M_AXI_GP1_WVALID(),
+    .M_AXI_GP1_ARID(),
+    .M_AXI_GP1_AWID(),
+    .M_AXI_GP1_WID(),
+    .M_AXI_GP1_ARBURST(),
+    .M_AXI_GP1_ARLOCK(),
+    .M_AXI_GP1_ARSIZE(),
+    .M_AXI_GP1_AWBURST(),
+    .M_AXI_GP1_AWLOCK(),
+    .M_AXI_GP1_AWSIZE(),
+    .M_AXI_GP1_ARPROT(),
+    .M_AXI_GP1_AWPROT(),
+    .M_AXI_GP1_ARADDR(),
+    .M_AXI_GP1_AWADDR(),
+    .M_AXI_GP1_WDATA(),
+    .M_AXI_GP1_ARCACHE(),
+    .M_AXI_GP1_ARLEN(),
+    .M_AXI_GP1_ARQOS(),
+    .M_AXI_GP1_AWCACHE(),
+    .M_AXI_GP1_AWLEN(),
+    .M_AXI_GP1_AWQOS(),
+    .M_AXI_GP1_WSTRB(),
+    .M_AXI_GP1_ACLK(1'B0),
+    .M_AXI_GP1_ARREADY(1'B0),
+    .M_AXI_GP1_AWREADY(1'B0),
+    .M_AXI_GP1_BVALID(1'B0),
+    .M_AXI_GP1_RLAST(1'B0),
+    .M_AXI_GP1_RVALID(1'B0),
+    .M_AXI_GP1_WREADY(1'B0),
+    .M_AXI_GP1_BID(12'B0),
+    .M_AXI_GP1_RID(12'B0),
+    .M_AXI_GP1_BRESP(2'B0),
+    .M_AXI_GP1_RRESP(2'B0),
+    .M_AXI_GP1_RDATA(32'B0),
+    .S_AXI_GP0_ARREADY(),
+    .S_AXI_GP0_AWREADY(),
+    .S_AXI_GP0_BVALID(),
+    .S_AXI_GP0_RLAST(),
+    .S_AXI_GP0_RVALID(),
+    .S_AXI_GP0_WREADY(),
+    .S_AXI_GP0_BRESP(),
+    .S_AXI_GP0_RRESP(),
+    .S_AXI_GP0_RDATA(),
+    .S_AXI_GP0_BID(),
+    .S_AXI_GP0_RID(),
+    .S_AXI_GP0_ACLK(1'B0),
+    .S_AXI_GP0_ARVALID(1'B0),
+    .S_AXI_GP0_AWVALID(1'B0),
+    .S_AXI_GP0_BREADY(1'B0),
+    .S_AXI_GP0_RREADY(1'B0),
+    .S_AXI_GP0_WLAST(1'B0),
+    .S_AXI_GP0_WVALID(1'B0),
+    .S_AXI_GP0_ARBURST(2'B0),
+    .S_AXI_GP0_ARLOCK(2'B0),
+    .S_AXI_GP0_ARSIZE(3'B0),
+    .S_AXI_GP0_AWBURST(2'B0),
+    .S_AXI_GP0_AWLOCK(2'B0),
+    .S_AXI_GP0_AWSIZE(3'B0),
+    .S_AXI_GP0_ARPROT(3'B0),
+    .S_AXI_GP0_AWPROT(3'B0),
+    .S_AXI_GP0_ARADDR(32'B0),
+    .S_AXI_GP0_AWADDR(32'B0),
+    .S_AXI_GP0_WDATA(32'B0),
+    .S_AXI_GP0_ARCACHE(4'B0),
+    .S_AXI_GP0_ARLEN(4'B0),
+    .S_AXI_GP0_ARQOS(4'B0),
+    .S_AXI_GP0_AWCACHE(4'B0),
+    .S_AXI_GP0_AWLEN(4'B0),
+    .S_AXI_GP0_AWQOS(4'B0),
+    .S_AXI_GP0_WSTRB(4'B0),
+    .S_AXI_GP0_ARID(6'B0),
+    .S_AXI_GP0_AWID(6'B0),
+    .S_AXI_GP0_WID(6'B0),
+    .S_AXI_GP1_ARREADY(),
+    .S_AXI_GP1_AWREADY(),
+    .S_AXI_GP1_BVALID(),
+    .S_AXI_GP1_RLAST(),
+    .S_AXI_GP1_RVALID(),
+    .S_AXI_GP1_WREADY(),
+    .S_AXI_GP1_BRESP(),
+    .S_AXI_GP1_RRESP(),
+    .S_AXI_GP1_RDATA(),
+    .S_AXI_GP1_BID(),
+    .S_AXI_GP1_RID(),
+    .S_AXI_GP1_ACLK(1'B0),
+    .S_AXI_GP1_ARVALID(1'B0),
+    .S_AXI_GP1_AWVALID(1'B0),
+    .S_AXI_GP1_BREADY(1'B0),
+    .S_AXI_GP1_RREADY(1'B0),
+    .S_AXI_GP1_WLAST(1'B0),
+    .S_AXI_GP1_WVALID(1'B0),
+    .S_AXI_GP1_ARBURST(2'B0),
+    .S_AXI_GP1_ARLOCK(2'B0),
+    .S_AXI_GP1_ARSIZE(3'B0),
+    .S_AXI_GP1_AWBURST(2'B0),
+    .S_AXI_GP1_AWLOCK(2'B0),
+    .S_AXI_GP1_AWSIZE(3'B0),
+    .S_AXI_GP1_ARPROT(3'B0),
+    .S_AXI_GP1_AWPROT(3'B0),
+    .S_AXI_GP1_ARADDR(32'B0),
+    .S_AXI_GP1_AWADDR(32'B0),
+    .S_AXI_GP1_WDATA(32'B0),
+    .S_AXI_GP1_ARCACHE(4'B0),
+    .S_AXI_GP1_ARLEN(4'B0),
+    .S_AXI_GP1_ARQOS(4'B0),
+    .S_AXI_GP1_AWCACHE(4'B0),
+    .S_AXI_GP1_AWLEN(4'B0),
+    .S_AXI_GP1_AWQOS(4'B0),
+    .S_AXI_GP1_WSTRB(4'B0),
+    .S_AXI_GP1_ARID(6'B0),
+    .S_AXI_GP1_AWID(6'B0),
+    .S_AXI_GP1_WID(6'B0),
+    .S_AXI_ACP_ARREADY(),
+    .S_AXI_ACP_AWREADY(),
+    .S_AXI_ACP_BVALID(),
+    .S_AXI_ACP_RLAST(),
+    .S_AXI_ACP_RVALID(),
+    .S_AXI_ACP_WREADY(),
+    .S_AXI_ACP_BRESP(),
+    .S_AXI_ACP_RRESP(),
+    .S_AXI_ACP_BID(),
+    .S_AXI_ACP_RID(),
+    .S_AXI_ACP_RDATA(),
+    .S_AXI_ACP_ACLK(1'B0),
+    .S_AXI_ACP_ARVALID(1'B0),
+    .S_AXI_ACP_AWVALID(1'B0),
+    .S_AXI_ACP_BREADY(1'B0),
+    .S_AXI_ACP_RREADY(1'B0),
+    .S_AXI_ACP_WLAST(1'B0),
+    .S_AXI_ACP_WVALID(1'B0),
+    .S_AXI_ACP_ARID(3'B0),
+    .S_AXI_ACP_ARPROT(3'B0),
+    .S_AXI_ACP_AWID(3'B0),
+    .S_AXI_ACP_AWPROT(3'B0),
+    .S_AXI_ACP_WID(3'B0),
+    .S_AXI_ACP_ARADDR(32'B0),
+    .S_AXI_ACP_AWADDR(32'B0),
+    .S_AXI_ACP_ARCACHE(4'B0),
+    .S_AXI_ACP_ARLEN(4'B0),
+    .S_AXI_ACP_ARQOS(4'B0),
+    .S_AXI_ACP_AWCACHE(4'B0),
+    .S_AXI_ACP_AWLEN(4'B0),
+    .S_AXI_ACP_AWQOS(4'B0),
+    .S_AXI_ACP_ARBURST(2'B0),
+    .S_AXI_ACP_ARLOCK(2'B0),
+    .S_AXI_ACP_ARSIZE(3'B0),
+    .S_AXI_ACP_AWBURST(2'B0),
+    .S_AXI_ACP_AWLOCK(2'B0),
+    .S_AXI_ACP_AWSIZE(3'B0),
+    .S_AXI_ACP_ARUSER(5'B0),
+    .S_AXI_ACP_AWUSER(5'B0),
+    .S_AXI_ACP_WDATA(64'B0),
+    .S_AXI_ACP_WSTRB(8'B0),
+    .S_AXI_HP0_ARREADY(),
+    .S_AXI_HP0_AWREADY(),
+    .S_AXI_HP0_BVALID(),
+    .S_AXI_HP0_RLAST(),
+    .S_AXI_HP0_RVALID(),
+    .S_AXI_HP0_WREADY(),
+    .S_AXI_HP0_BRESP(),
+    .S_AXI_HP0_RRESP(),
+    .S_AXI_HP0_BID(),
+    .S_AXI_HP0_RID(),
+    .S_AXI_HP0_RDATA(),
+    .S_AXI_HP0_ACLK(1'B0),
+    .S_AXI_HP0_ARVALID(1'B0),
+    .S_AXI_HP0_AWVALID(1'B0),
+    .S_AXI_HP0_BREADY(1'B0),
+    .S_AXI_HP0_RREADY(1'B0),
+    .S_AXI_HP0_WLAST(1'B0),
+    .S_AXI_HP0_WVALID(1'B0),
+    .S_AXI_HP0_ARBURST(2'B0),
+    .S_AXI_HP0_ARLOCK(2'B0),
+    .S_AXI_HP0_ARSIZE(3'B0),
+    .S_AXI_HP0_AWBURST(2'B0),
+    .S_AXI_HP0_AWLOCK(2'B0),
+    .S_AXI_HP0_AWSIZE(3'B0),
+    .S_AXI_HP0_ARPROT(3'B0),
+    .S_AXI_HP0_AWPROT(3'B0),
+    .S_AXI_HP0_ARADDR(32'B0),
+    .S_AXI_HP0_AWADDR(32'B0),
+    .S_AXI_HP0_ARCACHE(4'B0),
+    .S_AXI_HP0_ARLEN(4'B0),
+    .S_AXI_HP0_ARQOS(4'B0),
+    .S_AXI_HP0_AWCACHE(4'B0),
+    .S_AXI_HP0_AWLEN(4'B0),
+    .S_AXI_HP0_AWQOS(4'B0),
+    .S_AXI_HP0_ARID(6'B0),
+    .S_AXI_HP0_AWID(6'B0),
+    .S_AXI_HP0_WID(6'B0),
+    .S_AXI_HP0_WDATA(64'B0),
+    .S_AXI_HP0_WSTRB(8'B0),
+    .S_AXI_HP1_ARREADY(),
+    .S_AXI_HP1_AWREADY(),
+    .S_AXI_HP1_BVALID(),
+    .S_AXI_HP1_RLAST(),
+    .S_AXI_HP1_RVALID(),
+    .S_AXI_HP1_WREADY(),
+    .S_AXI_HP1_BRESP(),
+    .S_AXI_HP1_RRESP(),
+    .S_AXI_HP1_BID(),
+    .S_AXI_HP1_RID(),
+    .S_AXI_HP1_RDATA(),
+    .S_AXI_HP1_ACLK(1'B0),
+    .S_AXI_HP1_ARVALID(1'B0),
+    .S_AXI_HP1_AWVALID(1'B0),
+    .S_AXI_HP1_BREADY(1'B0),
+    .S_AXI_HP1_RREADY(1'B0),
+    .S_AXI_HP1_WLAST(1'B0),
+    .S_AXI_HP1_WVALID(1'B0),
+    .S_AXI_HP1_ARBURST(2'B0),
+    .S_AXI_HP1_ARLOCK(2'B0),
+    .S_AXI_HP1_ARSIZE(3'B0),
+    .S_AXI_HP1_AWBURST(2'B0),
+    .S_AXI_HP1_AWLOCK(2'B0),
+    .S_AXI_HP1_AWSIZE(3'B0),
+    .S_AXI_HP1_ARPROT(3'B0),
+    .S_AXI_HP1_AWPROT(3'B0),
+    .S_AXI_HP1_ARADDR(32'B0),
+    .S_AXI_HP1_AWADDR(32'B0),
+    .S_AXI_HP1_ARCACHE(4'B0),
+    .S_AXI_HP1_ARLEN(4'B0),
+    .S_AXI_HP1_ARQOS(4'B0),
+    .S_AXI_HP1_AWCACHE(4'B0),
+    .S_AXI_HP1_AWLEN(4'B0),
+    .S_AXI_HP1_AWQOS(4'B0),
+    .S_AXI_HP1_ARID(6'B0),
+    .S_AXI_HP1_AWID(6'B0),
+    .S_AXI_HP1_WID(6'B0),
+    .S_AXI_HP1_WDATA(64'B0),
+    .S_AXI_HP1_WSTRB(8'B0),
+    .S_AXI_HP2_ARREADY(),
+    .S_AXI_HP2_AWREADY(),
+    .S_AXI_HP2_BVALID(),
+    .S_AXI_HP2_RLAST(),
+    .S_AXI_HP2_RVALID(),
+    .S_AXI_HP2_WREADY(),
+    .S_AXI_HP2_BRESP(),
+    .S_AXI_HP2_RRESP(),
+    .S_AXI_HP2_BID(),
+    .S_AXI_HP2_RID(),
+    .S_AXI_HP2_RDATA(),
+    .S_AXI_HP2_ACLK(1'B0),
+    .S_AXI_HP2_ARVALID(1'B0),
+    .S_AXI_HP2_AWVALID(1'B0),
+    .S_AXI_HP2_BREADY(1'B0),
+    .S_AXI_HP2_RREADY(1'B0),
+    .S_AXI_HP2_WLAST(1'B0),
+    .S_AXI_HP2_WVALID(1'B0),
+    .S_AXI_HP2_ARBURST(2'B0),
+    .S_AXI_HP2_ARLOCK(2'B0),
+    .S_AXI_HP2_ARSIZE(3'B0),
+    .S_AXI_HP2_AWBURST(2'B0),
+    .S_AXI_HP2_AWLOCK(2'B0),
+    .S_AXI_HP2_AWSIZE(3'B0),
+    .S_AXI_HP2_ARPROT(3'B0),
+    .S_AXI_HP2_AWPROT(3'B0),
+    .S_AXI_HP2_ARADDR(32'B0),
+    .S_AXI_HP2_AWADDR(32'B0),
+    .S_AXI_HP2_ARCACHE(4'B0),
+    .S_AXI_HP2_ARLEN(4'B0),
+    .S_AXI_HP2_ARQOS(4'B0),
+    .S_AXI_HP2_AWCACHE(4'B0),
+    .S_AXI_HP2_AWLEN(4'B0),
+    .S_AXI_HP2_AWQOS(4'B0),
+    .S_AXI_HP2_ARID(6'B0),
+    .S_AXI_HP2_AWID(6'B0),
+    .S_AXI_HP2_WID(6'B0),
+    .S_AXI_HP2_WDATA(64'B0),
+    .S_AXI_HP2_WSTRB(8'B0),
+    .S_AXI_HP3_ARREADY(),
+    .S_AXI_HP3_AWREADY(),
+    .S_AXI_HP3_BVALID(),
+    .S_AXI_HP3_RLAST(),
+    .S_AXI_HP3_RVALID(),
+    .S_AXI_HP3_WREADY(),
+    .S_AXI_HP3_BRESP(),
+    .S_AXI_HP3_RRESP(),
+    .S_AXI_HP3_BID(),
+    .S_AXI_HP3_RID(),
+    .S_AXI_HP3_RDATA(),
+    .S_AXI_HP3_ACLK(1'B0),
+    .S_AXI_HP3_ARVALID(1'B0),
+    .S_AXI_HP3_AWVALID(1'B0),
+    .S_AXI_HP3_BREADY(1'B0),
+    .S_AXI_HP3_RREADY(1'B0),
+    .S_AXI_HP3_WLAST(1'B0),
+    .S_AXI_HP3_WVALID(1'B0),
+    .S_AXI_HP3_ARBURST(2'B0),
+    .S_AXI_HP3_ARLOCK(2'B0),
+    .S_AXI_HP3_ARSIZE(3'B0),
+    .S_AXI_HP3_AWBURST(2'B0),
+    .S_AXI_HP3_AWLOCK(2'B0),
+    .S_AXI_HP3_AWSIZE(3'B0),
+    .S_AXI_HP3_ARPROT(3'B0),
+    .S_AXI_HP3_AWPROT(3'B0),
+    .S_AXI_HP3_ARADDR(32'B0),
+    .S_AXI_HP3_AWADDR(32'B0),
+    .S_AXI_HP3_ARCACHE(4'B0),
+    .S_AXI_HP3_ARLEN(4'B0),
+    .S_AXI_HP3_ARQOS(4'B0),
+    .S_AXI_HP3_AWCACHE(4'B0),
+    .S_AXI_HP3_AWLEN(4'B0),
+    .S_AXI_HP3_AWQOS(4'B0),
+    .S_AXI_HP3_ARID(6'B0),
+    .S_AXI_HP3_AWID(6'B0),
+    .S_AXI_HP3_WID(6'B0),
+    .S_AXI_HP3_WDATA(64'B0),
+    .S_AXI_HP3_WSTRB(8'B0),
+    .FCLK_CLK0(FCLK_CLK0),
+	
+    .FCLK_CLK1(),
+	
+    .FCLK_CLK2(),
+	
+    .FCLK_CLK3(),
+    .FCLK_RESET0_N(FCLK_RESET0_N),
+    .FCLK_RESET1_N(),
+    .FCLK_RESET2_N(),
+    .FCLK_RESET3_N(),
+    .IRQ_F2P(IRQ_F2P),
+    .PS_SRSTB(PS_SRSTB),
+    .PS_CLK(PS_CLK),
+    .PS_PORB(PS_PORB)
+  );
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v
new file mode 100644
index 0000000..506d804
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v
@@ -0,0 +1,987 @@
+// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:processing_system7:5.5
+// IP Revision: 6
+
+(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4" *)
+(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
+(* CORE_GENERATION_INFO = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2017.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHEC\
+K=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M\
+_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TXN=\
+0,C_GP1_EN_MODIFIABLE_TXN=0}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_processing_system7_0_0 (
+  M_AXI_GP0_ARVALID,
+  M_AXI_GP0_AWVALID,
+  M_AXI_GP0_BREADY,
+  M_AXI_GP0_RREADY,
+  M_AXI_GP0_WLAST,
+  M_AXI_GP0_WVALID,
+  M_AXI_GP0_ARID,
+  M_AXI_GP0_AWID,
+  M_AXI_GP0_WID,
+  M_AXI_GP0_ARBURST,
+  M_AXI_GP0_ARLOCK,
+  M_AXI_GP0_ARSIZE,
+  M_AXI_GP0_AWBURST,
+  M_AXI_GP0_AWLOCK,
+  M_AXI_GP0_AWSIZE,
+  M_AXI_GP0_ARPROT,
+  M_AXI_GP0_AWPROT,
+  M_AXI_GP0_ARADDR,
+  M_AXI_GP0_AWADDR,
+  M_AXI_GP0_WDATA,
+  M_AXI_GP0_ARCACHE,
+  M_AXI_GP0_ARLEN,
+  M_AXI_GP0_ARQOS,
+  M_AXI_GP0_AWCACHE,
+  M_AXI_GP0_AWLEN,
+  M_AXI_GP0_AWQOS,
+  M_AXI_GP0_WSTRB,
+  M_AXI_GP0_ACLK,
+  M_AXI_GP0_ARREADY,
+  M_AXI_GP0_AWREADY,
+  M_AXI_GP0_BVALID,
+  M_AXI_GP0_RLAST,
+  M_AXI_GP0_RVALID,
+  M_AXI_GP0_WREADY,
+  M_AXI_GP0_BID,
+  M_AXI_GP0_RID,
+  M_AXI_GP0_BRESP,
+  M_AXI_GP0_RRESP,
+  M_AXI_GP0_RDATA,
+  FCLK_CLK0,
+  FCLK_RESET0_N,
+  MIO,
+  DDR_CAS_n,
+  DDR_CKE,
+  DDR_Clk_n,
+  DDR_Clk,
+  DDR_CS_n,
+  DDR_DRSTB,
+  DDR_ODT,
+  DDR_RAS_n,
+  DDR_WEB,
+  DDR_BankAddr,
+  DDR_Addr,
+  DDR_VRN,
+  DDR_VRP,
+  DDR_DM,
+  DDR_DQ,
+  DDR_DQS_n,
+  DDR_DQS,
+  PS_SRSTB,
+  PS_CLK,
+  PS_PORB
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
+output wire M_AXI_GP0_ARVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
+output wire M_AXI_GP0_AWVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
+output wire M_AXI_GP0_BREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
+output wire M_AXI_GP0_RREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
+output wire M_AXI_GP0_WLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
+output wire M_AXI_GP0_WVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
+output wire [11 : 0] M_AXI_GP0_ARID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
+output wire [11 : 0] M_AXI_GP0_AWID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
+output wire [11 : 0] M_AXI_GP0_WID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
+output wire [1 : 0] M_AXI_GP0_ARBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
+output wire [1 : 0] M_AXI_GP0_ARLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
+output wire [2 : 0] M_AXI_GP0_ARSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
+output wire [1 : 0] M_AXI_GP0_AWBURST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
+output wire [1 : 0] M_AXI_GP0_AWLOCK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
+output wire [2 : 0] M_AXI_GP0_AWSIZE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
+output wire [2 : 0] M_AXI_GP0_ARPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
+output wire [2 : 0] M_AXI_GP0_AWPROT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
+output wire [31 : 0] M_AXI_GP0_ARADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
+output wire [31 : 0] M_AXI_GP0_AWADDR;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
+output wire [31 : 0] M_AXI_GP0_WDATA;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
+output wire [3 : 0] M_AXI_GP0_ARCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
+output wire [3 : 0] M_AXI_GP0_ARLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
+output wire [3 : 0] M_AXI_GP0_ARQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
+output wire [3 : 0] M_AXI_GP0_AWCACHE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
+output wire [3 : 0] M_AXI_GP0_AWLEN;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
+output wire [3 : 0] M_AXI_GP0_AWQOS;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
+output wire [3 : 0] M_AXI_GP0_WSTRB;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
+input wire M_AXI_GP0_ACLK;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
+input wire M_AXI_GP0_ARREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
+input wire M_AXI_GP0_AWREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
+input wire M_AXI_GP0_BVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
+input wire M_AXI_GP0_RLAST;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
+input wire M_AXI_GP0_RVALID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
+input wire M_AXI_GP0_WREADY;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
+input wire [11 : 0] M_AXI_GP0_BID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
+input wire [11 : 0] M_AXI_GP0_RID;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
+input wire [1 : 0] M_AXI_GP0_BRESP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
+input wire [1 : 0] M_AXI_GP0_RRESP;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
+input wire [31 : 0] M_AXI_GP0_RDATA;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
+output wire FCLK_CLK0;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
+output wire FCLK_RESET0_N;
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
+inout wire [53 : 0] MIO;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
+inout wire DDR_CAS_n;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
+inout wire DDR_CKE;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
+inout wire DDR_Clk_n;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
+inout wire DDR_Clk;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
+inout wire DDR_CS_n;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
+inout wire DDR_DRSTB;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
+inout wire DDR_ODT;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
+inout wire DDR_RAS_n;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
+inout wire DDR_WEB;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
+inout wire [2 : 0] DDR_BankAddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
+inout wire [14 : 0] DDR_Addr;
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
+inout wire DDR_VRN;
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
+inout wire DDR_VRP;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
+inout wire [3 : 0] DDR_DM;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
+inout wire [31 : 0] DDR_DQ;
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
+inout wire [3 : 0] DDR_DQS_n;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
+inout wire [3 : 0] DDR_DQS;
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
+inout wire PS_SRSTB;
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
+inout wire PS_CLK;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
+(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
+inout wire PS_PORB;
+
+  processing_system7_v5_5_processing_system7 #(
+    .C_EN_EMIO_PJTAG(0),
+    .C_EN_EMIO_ENET0(0),
+    .C_EN_EMIO_ENET1(0),
+    .C_EN_EMIO_TRACE(0),
+    .C_INCLUDE_TRACE_BUFFER(0),
+    .C_TRACE_BUFFER_FIFO_SIZE(128),
+    .USE_TRACE_DATA_EDGE_DETECTOR(0),
+    .C_TRACE_PIPELINE_WIDTH(8),
+    .C_TRACE_BUFFER_CLOCK_DELAY(12),
+    .C_EMIO_GPIO_WIDTH(64),
+    .C_INCLUDE_ACP_TRANS_CHECK(0),
+    .C_USE_DEFAULT_ACP_USER_VAL(0),
+    .C_S_AXI_ACP_ARUSER_VAL(31),
+    .C_S_AXI_ACP_AWUSER_VAL(31),
+    .C_M_AXI_GP0_ID_WIDTH(12),
+    .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
+    .C_M_AXI_GP1_ID_WIDTH(12),
+    .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
+    .C_S_AXI_GP0_ID_WIDTH(6),
+    .C_S_AXI_GP1_ID_WIDTH(6),
+    .C_S_AXI_ACP_ID_WIDTH(3),
+    .C_S_AXI_HP0_ID_WIDTH(6),
+    .C_S_AXI_HP0_DATA_WIDTH(64),
+    .C_S_AXI_HP1_ID_WIDTH(6),
+    .C_S_AXI_HP1_DATA_WIDTH(64),
+    .C_S_AXI_HP2_ID_WIDTH(6),
+    .C_S_AXI_HP2_DATA_WIDTH(64),
+    .C_S_AXI_HP3_ID_WIDTH(6),
+    .C_S_AXI_HP3_DATA_WIDTH(64),
+    .C_M_AXI_GP0_THREAD_ID_WIDTH(12),
+    .C_M_AXI_GP1_THREAD_ID_WIDTH(12),
+    .C_NUM_F2P_INTR_INPUTS(2),
+    .C_IRQ_F2P_MODE("DIRECT"),
+    .C_DQ_WIDTH(32),
+    .C_DQS_WIDTH(4),
+    .C_DM_WIDTH(4),
+    .C_MIO_PRIMITIVE(54),
+    .C_TRACE_INTERNAL_WIDTH(2),
+    .C_USE_AXI_NONSECURE(0),
+    .C_USE_M_AXI_GP0(1),
+    .C_USE_M_AXI_GP1(0),
+    .C_USE_S_AXI_GP0(0),
+    .C_USE_S_AXI_GP1(0),
+    .C_USE_S_AXI_HP0(0),
+    .C_USE_S_AXI_HP1(0),
+    .C_USE_S_AXI_HP2(0),
+    .C_USE_S_AXI_HP3(0),
+    .C_USE_S_AXI_ACP(0),
+    .C_PS7_SI_REV("PRODUCTION"),
+    .C_FCLK_CLK0_BUF("TRUE"),
+    .C_FCLK_CLK1_BUF("FALSE"),
+    .C_FCLK_CLK2_BUF("FALSE"),
+    .C_FCLK_CLK3_BUF("FALSE"),
+    .C_PACKAGE_NAME("clg400"),
+    .C_GP0_EN_MODIFIABLE_TXN(0),
+    .C_GP1_EN_MODIFIABLE_TXN(0)
+  ) inst (
+    .CAN0_PHY_TX(),
+    .CAN0_PHY_RX(1'B0),
+    .CAN1_PHY_TX(),
+    .CAN1_PHY_RX(1'B0),
+    .ENET0_GMII_TX_EN(),
+    .ENET0_GMII_TX_ER(),
+    .ENET0_MDIO_MDC(),
+    .ENET0_MDIO_O(),
+    .ENET0_MDIO_T(),
+    .ENET0_PTP_DELAY_REQ_RX(),
+    .ENET0_PTP_DELAY_REQ_TX(),
+    .ENET0_PTP_PDELAY_REQ_RX(),
+    .ENET0_PTP_PDELAY_REQ_TX(),
+    .ENET0_PTP_PDELAY_RESP_RX(),
+    .ENET0_PTP_PDELAY_RESP_TX(),
+    .ENET0_PTP_SYNC_FRAME_RX(),
+    .ENET0_PTP_SYNC_FRAME_TX(),
+    .ENET0_SOF_RX(),
+    .ENET0_SOF_TX(),
+    .ENET0_GMII_TXD(),
+    .ENET0_GMII_COL(1'B0),
+    .ENET0_GMII_CRS(1'B0),
+    .ENET0_GMII_RX_CLK(1'B0),
+    .ENET0_GMII_RX_DV(1'B0),
+    .ENET0_GMII_RX_ER(1'B0),
+    .ENET0_GMII_TX_CLK(1'B0),
+    .ENET0_MDIO_I(1'B0),
+    .ENET0_EXT_INTIN(1'B0),
+    .ENET0_GMII_RXD(8'B0),
+    .ENET1_GMII_TX_EN(),
+    .ENET1_GMII_TX_ER(),
+    .ENET1_MDIO_MDC(),
+    .ENET1_MDIO_O(),
+    .ENET1_MDIO_T(),
+    .ENET1_PTP_DELAY_REQ_RX(),
+    .ENET1_PTP_DELAY_REQ_TX(),
+    .ENET1_PTP_PDELAY_REQ_RX(),
+    .ENET1_PTP_PDELAY_REQ_TX(),
+    .ENET1_PTP_PDELAY_RESP_RX(),
+    .ENET1_PTP_PDELAY_RESP_TX(),
+    .ENET1_PTP_SYNC_FRAME_RX(),
+    .ENET1_PTP_SYNC_FRAME_TX(),
+    .ENET1_SOF_RX(),
+    .ENET1_SOF_TX(),
+    .ENET1_GMII_TXD(),
+    .ENET1_GMII_COL(1'B0),
+    .ENET1_GMII_CRS(1'B0),
+    .ENET1_GMII_RX_CLK(1'B0),
+    .ENET1_GMII_RX_DV(1'B0),
+    .ENET1_GMII_RX_ER(1'B0),
+    .ENET1_GMII_TX_CLK(1'B0),
+    .ENET1_MDIO_I(1'B0),
+    .ENET1_EXT_INTIN(1'B0),
+    .ENET1_GMII_RXD(8'B0),
+    .GPIO_I(64'B0),
+    .GPIO_O(),
+    .GPIO_T(),
+    .I2C0_SDA_I(1'B0),
+    .I2C0_SDA_O(),
+    .I2C0_SDA_T(),
+    .I2C0_SCL_I(1'B0),
+    .I2C0_SCL_O(),
+    .I2C0_SCL_T(),
+    .I2C1_SDA_I(1'B0),
+    .I2C1_SDA_O(),
+    .I2C1_SDA_T(),
+    .I2C1_SCL_I(1'B0),
+    .I2C1_SCL_O(),
+    .I2C1_SCL_T(),
+    .PJTAG_TCK(1'B0),
+    .PJTAG_TMS(1'B0),
+    .PJTAG_TDI(1'B0),
+    .PJTAG_TDO(),
+    .SDIO0_CLK(),
+    .SDIO0_CLK_FB(1'B0),
+    .SDIO0_CMD_O(),
+    .SDIO0_CMD_I(1'B0),
+    .SDIO0_CMD_T(),
+    .SDIO0_DATA_I(4'B0),
+    .SDIO0_DATA_O(),
+    .SDIO0_DATA_T(),
+    .SDIO0_LED(),
+    .SDIO0_CDN(1'B0),
+    .SDIO0_WP(1'B0),
+    .SDIO0_BUSPOW(),
+    .SDIO0_BUSVOLT(),
+    .SDIO1_CLK(),
+    .SDIO1_CLK_FB(1'B0),
+    .SDIO1_CMD_O(),
+    .SDIO1_CMD_I(1'B0),
+    .SDIO1_CMD_T(),
+    .SDIO1_DATA_I(4'B0),
+    .SDIO1_DATA_O(),
+    .SDIO1_DATA_T(),
+    .SDIO1_LED(),
+    .SDIO1_CDN(1'B0),
+    .SDIO1_WP(1'B0),
+    .SDIO1_BUSPOW(),
+    .SDIO1_BUSVOLT(),
+    .SPI0_SCLK_I(1'B0),
+    .SPI0_SCLK_O(),
+    .SPI0_SCLK_T(),
+    .SPI0_MOSI_I(1'B0),
+    .SPI0_MOSI_O(),
+    .SPI0_MOSI_T(),
+    .SPI0_MISO_I(1'B0),
+    .SPI0_MISO_O(),
+    .SPI0_MISO_T(),
+    .SPI0_SS_I(1'B0),
+    .SPI0_SS_O(),
+    .SPI0_SS1_O(),
+    .SPI0_SS2_O(),
+    .SPI0_SS_T(),
+    .SPI1_SCLK_I(1'B0),
+    .SPI1_SCLK_O(),
+    .SPI1_SCLK_T(),
+    .SPI1_MOSI_I(1'B0),
+    .SPI1_MOSI_O(),
+    .SPI1_MOSI_T(),
+    .SPI1_MISO_I(1'B0),
+    .SPI1_MISO_O(),
+    .SPI1_MISO_T(),
+    .SPI1_SS_I(1'B0),
+    .SPI1_SS_O(),
+    .SPI1_SS1_O(),
+    .SPI1_SS2_O(),
+    .SPI1_SS_T(),
+    .UART0_DTRN(),
+    .UART0_RTSN(),
+    .UART0_TX(),
+    .UART0_CTSN(1'B0),
+    .UART0_DCDN(1'B0),
+    .UART0_DSRN(1'B0),
+    .UART0_RIN(1'B0),
+    .UART0_RX(1'B1),
+    .UART1_DTRN(),
+    .UART1_RTSN(),
+    .UART1_TX(),
+    .UART1_CTSN(1'B0),
+    .UART1_DCDN(1'B0),
+    .UART1_DSRN(1'B0),
+    .UART1_RIN(1'B0),
+    .UART1_RX(1'B1),
+    .TTC0_WAVE0_OUT(),
+    .TTC0_WAVE1_OUT(),
+    .TTC0_WAVE2_OUT(),
+    .TTC0_CLK0_IN(1'B0),
+    .TTC0_CLK1_IN(1'B0),
+    .TTC0_CLK2_IN(1'B0),
+    .TTC1_WAVE0_OUT(),
+    .TTC1_WAVE1_OUT(),
+    .TTC1_WAVE2_OUT(),
+    .TTC1_CLK0_IN(1'B0),
+    .TTC1_CLK1_IN(1'B0),
+    .TTC1_CLK2_IN(1'B0),
+    .WDT_CLK_IN(1'B0),
+    .WDT_RST_OUT(),
+    .TRACE_CLK(1'B0),
+    .TRACE_CLK_OUT(),
+    .TRACE_CTL(),
+    .TRACE_DATA(),
+    .USB0_PORT_INDCTL(),
+    .USB0_VBUS_PWRSELECT(),
+    .USB0_VBUS_PWRFAULT(1'B0),
+    .USB1_PORT_INDCTL(),
+    .USB1_VBUS_PWRSELECT(),
+    .USB1_VBUS_PWRFAULT(1'B0),
+    .SRAM_INTIN(1'B0),
+    .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
+    .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
+    .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
+    .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
+    .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
+    .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
+    .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
+    .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
+    .M_AXI_GP0_WID(M_AXI_GP0_WID),
+    .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
+    .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
+    .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
+    .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
+    .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
+    .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
+    .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
+    .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
+    .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
+    .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
+    .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
+    .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
+    .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
+    .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
+    .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
+    .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
+    .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
+    .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
+    .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
+    .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
+    .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
+    .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
+    .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
+    .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
+    .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
+    .M_AXI_GP0_BID(M_AXI_GP0_BID),
+    .M_AXI_GP0_RID(M_AXI_GP0_RID),
+    .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
+    .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
+    .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
+    .M_AXI_GP1_ARVALID(),
+    .M_AXI_GP1_AWVALID(),
+    .M_AXI_GP1_BREADY(),
+    .M_AXI_GP1_RREADY(),
+    .M_AXI_GP1_WLAST(),
+    .M_AXI_GP1_WVALID(),
+    .M_AXI_GP1_ARID(),
+    .M_AXI_GP1_AWID(),
+    .M_AXI_GP1_WID(),
+    .M_AXI_GP1_ARBURST(),
+    .M_AXI_GP1_ARLOCK(),
+    .M_AXI_GP1_ARSIZE(),
+    .M_AXI_GP1_AWBURST(),
+    .M_AXI_GP1_AWLOCK(),
+    .M_AXI_GP1_AWSIZE(),
+    .M_AXI_GP1_ARPROT(),
+    .M_AXI_GP1_AWPROT(),
+    .M_AXI_GP1_ARADDR(),
+    .M_AXI_GP1_AWADDR(),
+    .M_AXI_GP1_WDATA(),
+    .M_AXI_GP1_ARCACHE(),
+    .M_AXI_GP1_ARLEN(),
+    .M_AXI_GP1_ARQOS(),
+    .M_AXI_GP1_AWCACHE(),
+    .M_AXI_GP1_AWLEN(),
+    .M_AXI_GP1_AWQOS(),
+    .M_AXI_GP1_WSTRB(),
+    .M_AXI_GP1_ACLK(1'B0),
+    .M_AXI_GP1_ARREADY(1'B0),
+    .M_AXI_GP1_AWREADY(1'B0),
+    .M_AXI_GP1_BVALID(1'B0),
+    .M_AXI_GP1_RLAST(1'B0),
+    .M_AXI_GP1_RVALID(1'B0),
+    .M_AXI_GP1_WREADY(1'B0),
+    .M_AXI_GP1_BID(12'B0),
+    .M_AXI_GP1_RID(12'B0),
+    .M_AXI_GP1_BRESP(2'B0),
+    .M_AXI_GP1_RRESP(2'B0),
+    .M_AXI_GP1_RDATA(32'B0),
+    .S_AXI_GP0_ARREADY(),
+    .S_AXI_GP0_AWREADY(),
+    .S_AXI_GP0_BVALID(),
+    .S_AXI_GP0_RLAST(),
+    .S_AXI_GP0_RVALID(),
+    .S_AXI_GP0_WREADY(),
+    .S_AXI_GP0_BRESP(),
+    .S_AXI_GP0_RRESP(),
+    .S_AXI_GP0_RDATA(),
+    .S_AXI_GP0_BID(),
+    .S_AXI_GP0_RID(),
+    .S_AXI_GP0_ACLK(1'B0),
+    .S_AXI_GP0_ARVALID(1'B0),
+    .S_AXI_GP0_AWVALID(1'B0),
+    .S_AXI_GP0_BREADY(1'B0),
+    .S_AXI_GP0_RREADY(1'B0),
+    .S_AXI_GP0_WLAST(1'B0),
+    .S_AXI_GP0_WVALID(1'B0),
+    .S_AXI_GP0_ARBURST(2'B0),
+    .S_AXI_GP0_ARLOCK(2'B0),
+    .S_AXI_GP0_ARSIZE(3'B0),
+    .S_AXI_GP0_AWBURST(2'B0),
+    .S_AXI_GP0_AWLOCK(2'B0),
+    .S_AXI_GP0_AWSIZE(3'B0),
+    .S_AXI_GP0_ARPROT(3'B0),
+    .S_AXI_GP0_AWPROT(3'B0),
+    .S_AXI_GP0_ARADDR(32'B0),
+    .S_AXI_GP0_AWADDR(32'B0),
+    .S_AXI_GP0_WDATA(32'B0),
+    .S_AXI_GP0_ARCACHE(4'B0),
+    .S_AXI_GP0_ARLEN(4'B0),
+    .S_AXI_GP0_ARQOS(4'B0),
+    .S_AXI_GP0_AWCACHE(4'B0),
+    .S_AXI_GP0_AWLEN(4'B0),
+    .S_AXI_GP0_AWQOS(4'B0),
+    .S_AXI_GP0_WSTRB(4'B0),
+    .S_AXI_GP0_ARID(6'B0),
+    .S_AXI_GP0_AWID(6'B0),
+    .S_AXI_GP0_WID(6'B0),
+    .S_AXI_GP1_ARREADY(),
+    .S_AXI_GP1_AWREADY(),
+    .S_AXI_GP1_BVALID(),
+    .S_AXI_GP1_RLAST(),
+    .S_AXI_GP1_RVALID(),
+    .S_AXI_GP1_WREADY(),
+    .S_AXI_GP1_BRESP(),
+    .S_AXI_GP1_RRESP(),
+    .S_AXI_GP1_RDATA(),
+    .S_AXI_GP1_BID(),
+    .S_AXI_GP1_RID(),
+    .S_AXI_GP1_ACLK(1'B0),
+    .S_AXI_GP1_ARVALID(1'B0),
+    .S_AXI_GP1_AWVALID(1'B0),
+    .S_AXI_GP1_BREADY(1'B0),
+    .S_AXI_GP1_RREADY(1'B0),
+    .S_AXI_GP1_WLAST(1'B0),
+    .S_AXI_GP1_WVALID(1'B0),
+    .S_AXI_GP1_ARBURST(2'B0),
+    .S_AXI_GP1_ARLOCK(2'B0),
+    .S_AXI_GP1_ARSIZE(3'B0),
+    .S_AXI_GP1_AWBURST(2'B0),
+    .S_AXI_GP1_AWLOCK(2'B0),
+    .S_AXI_GP1_AWSIZE(3'B0),
+    .S_AXI_GP1_ARPROT(3'B0),
+    .S_AXI_GP1_AWPROT(3'B0),
+    .S_AXI_GP1_ARADDR(32'B0),
+    .S_AXI_GP1_AWADDR(32'B0),
+    .S_AXI_GP1_WDATA(32'B0),
+    .S_AXI_GP1_ARCACHE(4'B0),
+    .S_AXI_GP1_ARLEN(4'B0),
+    .S_AXI_GP1_ARQOS(4'B0),
+    .S_AXI_GP1_AWCACHE(4'B0),
+    .S_AXI_GP1_AWLEN(4'B0),
+    .S_AXI_GP1_AWQOS(4'B0),
+    .S_AXI_GP1_WSTRB(4'B0),
+    .S_AXI_GP1_ARID(6'B0),
+    .S_AXI_GP1_AWID(6'B0),
+    .S_AXI_GP1_WID(6'B0),
+    .S_AXI_ACP_ARREADY(),
+    .S_AXI_ACP_AWREADY(),
+    .S_AXI_ACP_BVALID(),
+    .S_AXI_ACP_RLAST(),
+    .S_AXI_ACP_RVALID(),
+    .S_AXI_ACP_WREADY(),
+    .S_AXI_ACP_BRESP(),
+    .S_AXI_ACP_RRESP(),
+    .S_AXI_ACP_BID(),
+    .S_AXI_ACP_RID(),
+    .S_AXI_ACP_RDATA(),
+    .S_AXI_ACP_ACLK(1'B0),
+    .S_AXI_ACP_ARVALID(1'B0),
+    .S_AXI_ACP_AWVALID(1'B0),
+    .S_AXI_ACP_BREADY(1'B0),
+    .S_AXI_ACP_RREADY(1'B0),
+    .S_AXI_ACP_WLAST(1'B0),
+    .S_AXI_ACP_WVALID(1'B0),
+    .S_AXI_ACP_ARID(3'B0),
+    .S_AXI_ACP_ARPROT(3'B0),
+    .S_AXI_ACP_AWID(3'B0),
+    .S_AXI_ACP_AWPROT(3'B0),
+    .S_AXI_ACP_WID(3'B0),
+    .S_AXI_ACP_ARADDR(32'B0),
+    .S_AXI_ACP_AWADDR(32'B0),
+    .S_AXI_ACP_ARCACHE(4'B0),
+    .S_AXI_ACP_ARLEN(4'B0),
+    .S_AXI_ACP_ARQOS(4'B0),
+    .S_AXI_ACP_AWCACHE(4'B0),
+    .S_AXI_ACP_AWLEN(4'B0),
+    .S_AXI_ACP_AWQOS(4'B0),
+    .S_AXI_ACP_ARBURST(2'B0),
+    .S_AXI_ACP_ARLOCK(2'B0),
+    .S_AXI_ACP_ARSIZE(3'B0),
+    .S_AXI_ACP_AWBURST(2'B0),
+    .S_AXI_ACP_AWLOCK(2'B0),
+    .S_AXI_ACP_AWSIZE(3'B0),
+    .S_AXI_ACP_ARUSER(5'B0),
+    .S_AXI_ACP_AWUSER(5'B0),
+    .S_AXI_ACP_WDATA(64'B0),
+    .S_AXI_ACP_WSTRB(8'B0),
+    .S_AXI_HP0_ARREADY(),
+    .S_AXI_HP0_AWREADY(),
+    .S_AXI_HP0_BVALID(),
+    .S_AXI_HP0_RLAST(),
+    .S_AXI_HP0_RVALID(),
+    .S_AXI_HP0_WREADY(),
+    .S_AXI_HP0_BRESP(),
+    .S_AXI_HP0_RRESP(),
+    .S_AXI_HP0_BID(),
+    .S_AXI_HP0_RID(),
+    .S_AXI_HP0_RDATA(),
+    .S_AXI_HP0_RCOUNT(),
+    .S_AXI_HP0_WCOUNT(),
+    .S_AXI_HP0_RACOUNT(),
+    .S_AXI_HP0_WACOUNT(),
+    .S_AXI_HP0_ACLK(1'B0),
+    .S_AXI_HP0_ARVALID(1'B0),
+    .S_AXI_HP0_AWVALID(1'B0),
+    .S_AXI_HP0_BREADY(1'B0),
+    .S_AXI_HP0_RDISSUECAP1_EN(1'B0),
+    .S_AXI_HP0_RREADY(1'B0),
+    .S_AXI_HP0_WLAST(1'B0),
+    .S_AXI_HP0_WRISSUECAP1_EN(1'B0),
+    .S_AXI_HP0_WVALID(1'B0),
+    .S_AXI_HP0_ARBURST(2'B0),
+    .S_AXI_HP0_ARLOCK(2'B0),
+    .S_AXI_HP0_ARSIZE(3'B0),
+    .S_AXI_HP0_AWBURST(2'B0),
+    .S_AXI_HP0_AWLOCK(2'B0),
+    .S_AXI_HP0_AWSIZE(3'B0),
+    .S_AXI_HP0_ARPROT(3'B0),
+    .S_AXI_HP0_AWPROT(3'B0),
+    .S_AXI_HP0_ARADDR(32'B0),
+    .S_AXI_HP0_AWADDR(32'B0),
+    .S_AXI_HP0_ARCACHE(4'B0),
+    .S_AXI_HP0_ARLEN(4'B0),
+    .S_AXI_HP0_ARQOS(4'B0),
+    .S_AXI_HP0_AWCACHE(4'B0),
+    .S_AXI_HP0_AWLEN(4'B0),
+    .S_AXI_HP0_AWQOS(4'B0),
+    .S_AXI_HP0_ARID(6'B0),
+    .S_AXI_HP0_AWID(6'B0),
+    .S_AXI_HP0_WID(6'B0),
+    .S_AXI_HP0_WDATA(64'B0),
+    .S_AXI_HP0_WSTRB(8'B0),
+    .S_AXI_HP1_ARREADY(),
+    .S_AXI_HP1_AWREADY(),
+    .S_AXI_HP1_BVALID(),
+    .S_AXI_HP1_RLAST(),
+    .S_AXI_HP1_RVALID(),
+    .S_AXI_HP1_WREADY(),
+    .S_AXI_HP1_BRESP(),
+    .S_AXI_HP1_RRESP(),
+    .S_AXI_HP1_BID(),
+    .S_AXI_HP1_RID(),
+    .S_AXI_HP1_RDATA(),
+    .S_AXI_HP1_RCOUNT(),
+    .S_AXI_HP1_WCOUNT(),
+    .S_AXI_HP1_RACOUNT(),
+    .S_AXI_HP1_WACOUNT(),
+    .S_AXI_HP1_ACLK(1'B0),
+    .S_AXI_HP1_ARVALID(1'B0),
+    .S_AXI_HP1_AWVALID(1'B0),
+    .S_AXI_HP1_BREADY(1'B0),
+    .S_AXI_HP1_RDISSUECAP1_EN(1'B0),
+    .S_AXI_HP1_RREADY(1'B0),
+    .S_AXI_HP1_WLAST(1'B0),
+    .S_AXI_HP1_WRISSUECAP1_EN(1'B0),
+    .S_AXI_HP1_WVALID(1'B0),
+    .S_AXI_HP1_ARBURST(2'B0),
+    .S_AXI_HP1_ARLOCK(2'B0),
+    .S_AXI_HP1_ARSIZE(3'B0),
+    .S_AXI_HP1_AWBURST(2'B0),
+    .S_AXI_HP1_AWLOCK(2'B0),
+    .S_AXI_HP1_AWSIZE(3'B0),
+    .S_AXI_HP1_ARPROT(3'B0),
+    .S_AXI_HP1_AWPROT(3'B0),
+    .S_AXI_HP1_ARADDR(32'B0),
+    .S_AXI_HP1_AWADDR(32'B0),
+    .S_AXI_HP1_ARCACHE(4'B0),
+    .S_AXI_HP1_ARLEN(4'B0),
+    .S_AXI_HP1_ARQOS(4'B0),
+    .S_AXI_HP1_AWCACHE(4'B0),
+    .S_AXI_HP1_AWLEN(4'B0),
+    .S_AXI_HP1_AWQOS(4'B0),
+    .S_AXI_HP1_ARID(6'B0),
+    .S_AXI_HP1_AWID(6'B0),
+    .S_AXI_HP1_WID(6'B0),
+    .S_AXI_HP1_WDATA(64'B0),
+    .S_AXI_HP1_WSTRB(8'B0),
+    .S_AXI_HP2_ARREADY(),
+    .S_AXI_HP2_AWREADY(),
+    .S_AXI_HP2_BVALID(),
+    .S_AXI_HP2_RLAST(),
+    .S_AXI_HP2_RVALID(),
+    .S_AXI_HP2_WREADY(),
+    .S_AXI_HP2_BRESP(),
+    .S_AXI_HP2_RRESP(),
+    .S_AXI_HP2_BID(),
+    .S_AXI_HP2_RID(),
+    .S_AXI_HP2_RDATA(),
+    .S_AXI_HP2_RCOUNT(),
+    .S_AXI_HP2_WCOUNT(),
+    .S_AXI_HP2_RACOUNT(),
+    .S_AXI_HP2_WACOUNT(),
+    .S_AXI_HP2_ACLK(1'B0),
+    .S_AXI_HP2_ARVALID(1'B0),
+    .S_AXI_HP2_AWVALID(1'B0),
+    .S_AXI_HP2_BREADY(1'B0),
+    .S_AXI_HP2_RDISSUECAP1_EN(1'B0),
+    .S_AXI_HP2_RREADY(1'B0),
+    .S_AXI_HP2_WLAST(1'B0),
+    .S_AXI_HP2_WRISSUECAP1_EN(1'B0),
+    .S_AXI_HP2_WVALID(1'B0),
+    .S_AXI_HP2_ARBURST(2'B0),
+    .S_AXI_HP2_ARLOCK(2'B0),
+    .S_AXI_HP2_ARSIZE(3'B0),
+    .S_AXI_HP2_AWBURST(2'B0),
+    .S_AXI_HP2_AWLOCK(2'B0),
+    .S_AXI_HP2_AWSIZE(3'B0),
+    .S_AXI_HP2_ARPROT(3'B0),
+    .S_AXI_HP2_AWPROT(3'B0),
+    .S_AXI_HP2_ARADDR(32'B0),
+    .S_AXI_HP2_AWADDR(32'B0),
+    .S_AXI_HP2_ARCACHE(4'B0),
+    .S_AXI_HP2_ARLEN(4'B0),
+    .S_AXI_HP2_ARQOS(4'B0),
+    .S_AXI_HP2_AWCACHE(4'B0),
+    .S_AXI_HP2_AWLEN(4'B0),
+    .S_AXI_HP2_AWQOS(4'B0),
+    .S_AXI_HP2_ARID(6'B0),
+    .S_AXI_HP2_AWID(6'B0),
+    .S_AXI_HP2_WID(6'B0),
+    .S_AXI_HP2_WDATA(64'B0),
+    .S_AXI_HP2_WSTRB(8'B0),
+    .S_AXI_HP3_ARREADY(),
+    .S_AXI_HP3_AWREADY(),
+    .S_AXI_HP3_BVALID(),
+    .S_AXI_HP3_RLAST(),
+    .S_AXI_HP3_RVALID(),
+    .S_AXI_HP3_WREADY(),
+    .S_AXI_HP3_BRESP(),
+    .S_AXI_HP3_RRESP(),
+    .S_AXI_HP3_BID(),
+    .S_AXI_HP3_RID(),
+    .S_AXI_HP3_RDATA(),
+    .S_AXI_HP3_RCOUNT(),
+    .S_AXI_HP3_WCOUNT(),
+    .S_AXI_HP3_RACOUNT(),
+    .S_AXI_HP3_WACOUNT(),
+    .S_AXI_HP3_ACLK(1'B0),
+    .S_AXI_HP3_ARVALID(1'B0),
+    .S_AXI_HP3_AWVALID(1'B0),
+    .S_AXI_HP3_BREADY(1'B0),
+    .S_AXI_HP3_RDISSUECAP1_EN(1'B0),
+    .S_AXI_HP3_RREADY(1'B0),
+    .S_AXI_HP3_WLAST(1'B0),
+    .S_AXI_HP3_WRISSUECAP1_EN(1'B0),
+    .S_AXI_HP3_WVALID(1'B0),
+    .S_AXI_HP3_ARBURST(2'B0),
+    .S_AXI_HP3_ARLOCK(2'B0),
+    .S_AXI_HP3_ARSIZE(3'B0),
+    .S_AXI_HP3_AWBURST(2'B0),
+    .S_AXI_HP3_AWLOCK(2'B0),
+    .S_AXI_HP3_AWSIZE(3'B0),
+    .S_AXI_HP3_ARPROT(3'B0),
+    .S_AXI_HP3_AWPROT(3'B0),
+    .S_AXI_HP3_ARADDR(32'B0),
+    .S_AXI_HP3_AWADDR(32'B0),
+    .S_AXI_HP3_ARCACHE(4'B0),
+    .S_AXI_HP3_ARLEN(4'B0),
+    .S_AXI_HP3_ARQOS(4'B0),
+    .S_AXI_HP3_AWCACHE(4'B0),
+    .S_AXI_HP3_AWLEN(4'B0),
+    .S_AXI_HP3_AWQOS(4'B0),
+    .S_AXI_HP3_ARID(6'B0),
+    .S_AXI_HP3_AWID(6'B0),
+    .S_AXI_HP3_WID(6'B0),
+    .S_AXI_HP3_WDATA(64'B0),
+    .S_AXI_HP3_WSTRB(8'B0),
+    .IRQ_P2F_DMAC_ABORT(),
+    .IRQ_P2F_DMAC0(),
+    .IRQ_P2F_DMAC1(),
+    .IRQ_P2F_DMAC2(),
+    .IRQ_P2F_DMAC3(),
+    .IRQ_P2F_DMAC4(),
+    .IRQ_P2F_DMAC5(),
+    .IRQ_P2F_DMAC6(),
+    .IRQ_P2F_DMAC7(),
+    .IRQ_P2F_SMC(),
+    .IRQ_P2F_QSPI(),
+    .IRQ_P2F_CTI(),
+    .IRQ_P2F_GPIO(),
+    .IRQ_P2F_USB0(),
+    .IRQ_P2F_ENET0(),
+    .IRQ_P2F_ENET_WAKE0(),
+    .IRQ_P2F_SDIO0(),
+    .IRQ_P2F_I2C0(),
+    .IRQ_P2F_SPI0(),
+    .IRQ_P2F_UART0(),
+    .IRQ_P2F_CAN0(),
+    .IRQ_P2F_USB1(),
+    .IRQ_P2F_ENET1(),
+    .IRQ_P2F_ENET_WAKE1(),
+    .IRQ_P2F_SDIO1(),
+    .IRQ_P2F_I2C1(),
+    .IRQ_P2F_SPI1(),
+    .IRQ_P2F_UART1(),
+    .IRQ_P2F_CAN1(),
+    .IRQ_F2P(2'B0),
+    .Core0_nFIQ(1'B0),
+    .Core0_nIRQ(1'B0),
+    .Core1_nFIQ(1'B0),
+    .Core1_nIRQ(1'B0),
+    .DMA0_DATYPE(),
+    .DMA0_DAVALID(),
+    .DMA0_DRREADY(),
+    .DMA1_DATYPE(),
+    .DMA1_DAVALID(),
+    .DMA1_DRREADY(),
+    .DMA2_DATYPE(),
+    .DMA2_DAVALID(),
+    .DMA2_DRREADY(),
+    .DMA3_DATYPE(),
+    .DMA3_DAVALID(),
+    .DMA3_DRREADY(),
+    .DMA0_ACLK(1'B0),
+    .DMA0_DAREADY(1'B0),
+    .DMA0_DRLAST(1'B0),
+    .DMA0_DRVALID(1'B0),
+    .DMA1_ACLK(1'B0),
+    .DMA1_DAREADY(1'B0),
+    .DMA1_DRLAST(1'B0),
+    .DMA1_DRVALID(1'B0),
+    .DMA2_ACLK(1'B0),
+    .DMA2_DAREADY(1'B0),
+    .DMA2_DRLAST(1'B0),
+    .DMA2_DRVALID(1'B0),
+    .DMA3_ACLK(1'B0),
+    .DMA3_DAREADY(1'B0),
+    .DMA3_DRLAST(1'B0),
+    .DMA3_DRVALID(1'B0),
+    .DMA0_DRTYPE(2'B0),
+    .DMA1_DRTYPE(2'B0),
+    .DMA2_DRTYPE(2'B0),
+    .DMA3_DRTYPE(2'B0),
+    .FCLK_CLK0(FCLK_CLK0),
+    .FCLK_CLK1(),
+    .FCLK_CLK2(),
+    .FCLK_CLK3(),
+    .FCLK_CLKTRIG0_N(1'B0),
+    .FCLK_CLKTRIG1_N(1'B0),
+    .FCLK_CLKTRIG2_N(1'B0),
+    .FCLK_CLKTRIG3_N(1'B0),
+    .FCLK_RESET0_N(FCLK_RESET0_N),
+    .FCLK_RESET1_N(),
+    .FCLK_RESET2_N(),
+    .FCLK_RESET3_N(),
+    .FTMD_TRACEIN_DATA(32'B0),
+    .FTMD_TRACEIN_VALID(1'B0),
+    .FTMD_TRACEIN_CLK(1'B0),
+    .FTMD_TRACEIN_ATID(4'B0),
+    .FTMT_F2P_TRIG_0(1'B0),
+    .FTMT_F2P_TRIGACK_0(),
+    .FTMT_F2P_TRIG_1(1'B0),
+    .FTMT_F2P_TRIGACK_1(),
+    .FTMT_F2P_TRIG_2(1'B0),
+    .FTMT_F2P_TRIGACK_2(),
+    .FTMT_F2P_TRIG_3(1'B0),
+    .FTMT_F2P_TRIGACK_3(),
+    .FTMT_F2P_DEBUG(32'B0),
+    .FTMT_P2F_TRIGACK_0(1'B0),
+    .FTMT_P2F_TRIG_0(),
+    .FTMT_P2F_TRIGACK_1(1'B0),
+    .FTMT_P2F_TRIG_1(),
+    .FTMT_P2F_TRIGACK_2(1'B0),
+    .FTMT_P2F_TRIG_2(),
+    .FTMT_P2F_TRIGACK_3(1'B0),
+    .FTMT_P2F_TRIG_3(),
+    .FTMT_P2F_DEBUG(),
+    .FPGA_IDLE_N(1'B0),
+    .EVENT_EVENTO(),
+    .EVENT_STANDBYWFE(),
+    .EVENT_STANDBYWFI(),
+    .EVENT_EVENTI(1'B0),
+    .DDR_ARB(4'B0),
+    .MIO(MIO),
+    .DDR_CAS_n(DDR_CAS_n),
+    .DDR_CKE(DDR_CKE),
+    .DDR_Clk_n(DDR_Clk_n),
+    .DDR_Clk(DDR_Clk),
+    .DDR_CS_n(DDR_CS_n),
+    .DDR_DRSTB(DDR_DRSTB),
+    .DDR_ODT(DDR_ODT),
+    .DDR_RAS_n(DDR_RAS_n),
+    .DDR_WEB(DDR_WEB),
+    .DDR_BankAddr(DDR_BankAddr),
+    .DDR_Addr(DDR_Addr),
+    .DDR_VRN(DDR_VRN),
+    .DDR_VRP(DDR_VRP),
+    .DDR_DM(DDR_DM),
+    .DDR_DQ(DDR_DQ),
+    .DDR_DQS_n(DDR_DQS_n),
+    .DDR_DQS(DDR_DQS),
+    .PS_SRSTB(PS_SRSTB),
+    .PS_CLK(PS_CLK),
+    .PS_PORB(PS_PORB)
+  );
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.upgrade_log b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.upgrade_log
new file mode 100644
index 0000000..cb9a18a
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.upgrade_log
@@ -0,0 +1,53 @@
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
+| Date         : Sun Feb 12 15:47:35 2017
+| Host         : AFAAW-704030720 running 64-bit major release  (build 9200)
+| Command      : upgrade_ip
+| Device       : xc7z020clg400-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_processing_system7_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the update of system_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 3)) to current project options.
+
+2. Upgrade messages
+-------------------
+
+WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
+
+
+
+
+
+
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
+| Date         : Fri Jan 20 14:35:29 2017
+| Host         : admin running 64-bit major release  (build 9200)
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_processing_system7_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the update of system_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 3)) to current project options.
+
+2. Upgrade messages
+-------------------
+
+WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
+WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci
new file mode 100644
index 0000000..4a64f42
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci
@@ -0,0 +1,2248 @@
+
+
+  xilinx.com
+  xci
+  unknown
+  1.0
+  
+    
+      system_processing_system7_0_0
+      
+      
+        1
+        LEVEL_HIGH
+        1
+        LEVEL_HIGH
+        1
+        LEVEL_HIGH
+        1
+        LEVEL_HIGH
+        TDM
+        8
+        false
+        11
+        11
+        true
+        
+        true
+        8
+        
+        COMPONENTS
+        ROW_COLUMN_BANK
+        Single
+        1250
+        
+        100000000
+        0
+        0
+        1
+        0
+        undef
+        0.000
+        1
+        0
+        0
+        0
+        
+        
+        100000000
+        0.000
+        
+        100000000
+        0
+        0
+        1
+        0
+        undef
+        0.000
+        1
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+        0
+        0
+        
+        100000000
+        0
+        0
+        1
+        0
+        undef
+        0.000
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+        0
+        0
+        
+        
+        100000000
+        0.000
+        
+        100000000
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+        0
+        undef
+        0.000
+        1
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+        0
+        
+        100000000
+        0
+        0
+        1
+        0
+        undef
+        0.000
+        1
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+        0
+        0
+        
+        
+        100000000
+        0.000
+        
+        100000000
+        0
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+        0.000
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+        
+        100000000
+        0.000
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+        1
+        0
+        undef
+        0.000
+        1
+        0
+        0
+        0
+        1
+        LEVEL_HIGH
+        1
+        LEVEL_HIGH
+        
+        
+        system_processing_system7_0_0_FCLK_CLK0
+        50000000
+        0.000
+        
+        
+        
+        0.000
+        
+        
+        
+        0.000
+        
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+        
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+        ACTIVE_LOW
+        false
+        
+        
+        100000000
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+        100000000
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+        undef
+        0.000
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+        0
+        1
+        LEVEL_HIGH
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        false
+        false
+        32
+        0
+        0
+        0
+        system_processing_system7_0_0_FCLK_CLK0
+        32
+        50000000
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        12
+        16
+        4
+        4
+        0.000
+        AXI3
+        READ_WRITE
+        0
+        0
+        0
+        0
+        0
+        
+        system_processing_system7_0_0_FCLK_CLK0
+        50000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
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+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        0
+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
+        0
+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
+        0
+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
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+        1
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+        READ_WRITE
+        0
+        0
+        1
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+        0
+        
+        
+        100000000
+        0.000
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+        0
+        0
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+        100000000
+        1
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+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
+        0
+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
+        0
+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        256
+        1
+        1
+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
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+        0
+        
+        
+        100000000
+        0.000
+        32
+        0
+        0
+        0
+        
+        32
+        100000000
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        1
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+        0.000
+        AXI4
+        READ_WRITE
+        0
+        0
+        1
+        0
+        0
+        
+        
+        100000000
+        0.000
+        system_processing_system7_0_0
+        666.666687
+        23.8095
+        23.8095
+        10.000000
+        10.158730
+        125.000000
+        10.000000
+        50.000000
+        10.000000
+        10.000000
+        10.000000
+        50
+        200.000000
+        200.000000
+        100.000000
+        10.000000
+        10.000000
+        200.000000
+        111.111115
+        111.111115
+        111.111115
+        111.111115
+        111.111115
+        111.111115
+        50
+        100.000000
+        60
+        60
+        111.111115
+        6:2:1
+        666.666666
+        40
+        0xE0008000
+        <Select>
+        0
+        <Select>
+        0xE0008FFF
+        External
+        0
+        -1
+        0xE0009000
+        <Select>
+        0
+        <Select>
+        0xE0009FFF
+        External
+        0
+        -1
+        IO PLL
+        1
+        1
+        100
+        0
+        50000000
+        10000000
+        10000000
+        10000000
+        0
+        0
+        0
+        0
+        667
+        1333.333
+        ARM PLL
+        2
+        33.333333
+        DDR PLL
+        15
+        7
+        10.159
+        32
+        1066.667
+        HPR(0)/LPR(32)
+        15
+        2
+        DDR PLL
+        2
+        0
+        0
+        0
+        0
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        0x00100000
+        0x3FFFFFFF
+        2
+        4
+        4
+        32
+        <Select>
+        <Select>
+        0xE000B000
+        MIO 16 .. 27
+        1
+        MIO 52 .. 53
+        0xE000BFFF
+        IO PLL
+        8
+        1
+        1
+        1000 Mbps
+        0
+        <Select>
+        0xE000C000
+        <Select>
+        0
+        <Select>
+        0xE000CFFF
+        IO PLL
+        1
+        1
+        0
+        1000 Mbps
+        0
+        <Select>
+        1
+        Active Low
+        Share reset pin
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        1
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        IO PLL
+        5
+        4
+        IO PLL
+        1
+        1
+        IO PLL
+        1
+        1
+        IO PLL
+        1
+        1
+        TRUE
+        FALSE
+        FALSE
+        FALSE
+        50
+        50
+        50
+        50
+        1
+        0
+        0
+        0
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        <Select>
+        0
+        4
+        4
+        0
+        4
+        4
+        0xE000A000
+        0
+        <Select>
+        64
+        0xE000AFFF
+        1
+        MIO
+        0
+        0xE0004000
+        0
+        <Select>
+        0xE0004FFF
+        <Select>
+        0
+        0
+        <Select>
+        0xE0005000
+        0
+        <Select>
+        0xE0005FFF
+        <Select>
+        0
+        0
+        <Select>
+        25
+        1
+        Active Low
+        <Select>
+        None
+        0
+        0
+        30
+        1000.000
+        1
+        DIRECT
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 3.3V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        disabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        disabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        in
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        disabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        out
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 1.8V
+        enabled
+        slow
+        inout
+        LVCMOS 3.3V
+        disabled
+        slow
+        out
+        LVCMOS 3.3V
+        disabled
+        slow
+        out
+        LVCMOS 3.3V
+        disabled
+        slow
+        out
+        LVCMOS 3.3V
+        disabled
+        slow
+        inout
+        LVCMOS 3.3V
+        enabled
+        slow
+        54
+        GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0
+        gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio
+        0
+        50
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+        12
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+        1
+        1
+        11
+        1
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+        <Select>
+        <Select>
+        0
+        1
+        1
+        11
+        1
+        11
+        1
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+        1
+        1
+        11
+        1
+        11
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+        0
+        <Select>
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+        <Select>
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+        11
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+        0
+        0
+        0
+        0
+        0
+        0
+        0.063
+        0.062
+        0.065
+        0.083
+        -0.007
+        -0.010
+        -0.006
+        -0.048
+        clg400
+        IO PLL
+        5
+        200
+        None
+        0
+        <Select>
+        0
+        LVCMOS 3.3V
+        LVCMOS 1.8V
+        PRODUCTION
+        1
+        MIO 8
+        0
+        <Select>
+        1
+        MIO 1 .. 6
+        0
+        <Select>
+        0xFCFFFFFF
+        IO PLL
+        5
+        1
+        200
+        MIO 1 .. 6
+        1
+        MIO 47
+        0
+        <Select>
+        0
+        <Select>
+        1
+        MIO 40 .. 45
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0xE0100000
+        0xE0100FFF
+        0xE0101000
+        0xE0101FFF
+        IO PLL
+        10
+        100
+        1
+        x4
+        NA
+        NA
+        NA
+        NA
+        NA
+        NA
+        NA
+        IO PLL
+        1
+        100
+        0
+        0xE0006000
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0xE0006FFF
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+        0xE0007000
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0xE0007FFF
+        0
+        <Select>
+        IO PLL
+        1
+        166.666666
+        0
+        31
+        31
+        10
+        3
+        10
+        6
+        10
+        6
+        64
+        10
+        6
+        64
+        10
+        6
+        64
+        10
+        6
+        64
+        10
+        6
+        External
+        1
+        200
+        12
+        128
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        0
+        <Select>
+        2
+        0
+        8
+        <Select>
+        0xE0104000
+        CPU_1X
+        1
+        133.333333
+        CPU_1X
+        1
+        133.333333
+        CPU_1X
+        1
+        133.333333
+        0xE0104fff
+        0
+        <Select>
+        0xE0105000
+        CPU_1X
+        1
+        133.333333
+        CPU_1X
+        1
+        133.333333
+        CPU_1X
+        1
+        133.333333
+        0xE0105fff
+        0
+        <Select>
+        50
+        0xE0000000
+        115200
+        0
+        <Select>
+        0xE0000FFF
+        0
+        <Select>
+        0xE0001000
+        115200
+        0
+        <Select>
+        0xE0001FFF
+        1
+        MIO 48 .. 49
+        IO PLL
+        10
+        100
+        1
+        533.333374
+        0
+        0
+        3
+        8
+        0.25
+        0.25
+        0.25
+        0.25
+        32 Bit
+        7
+        0
+        61.0905
+        160
+        0
+        61.0905
+        160
+        0
+        61.0905
+        160
+        0
+        61.0905
+        160
+        0
+        10
+        6
+        4096 MBits
+        0
+        68.4725
+        160
+        0
+        71.086
+        160
+        0
+        66.794
+        160
+        0
+        108.7385
+        160
+        0.0
+        0.0
+        0.0
+        0.0
+        0
+        64.1705
+        160
+        0
+        63.686
+        160
+        0
+        68.46
+        160
+        0
+        105.4895
+        160
+        16 Bits
+        Disabled
+        1
+        533.333333
+        Normal (0-85)
+        DDR 3
+        MT41K256M16 RE-125
+        15
+        DDR3_1066F
+        1
+        1
+        1
+        40.0
+        35.0
+        48.75
+        7
+        7
+        0
+        NA
+        0xE0102000
+        0xE0102fff
+        0
+        60
+        0
+        <Select>
+        <Select>
+        0xE0103000
+        0xE0103fff
+        0
+        60
+        0
+        <Select>
+        <Select>
+        1
+        Active Low
+        <Select>
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        3
+        CPU_1X
+        1
+        0
+        133.333333
+        <Select>
+        None
+        zynq
+        
+        xc7z010
+        clg400
+        VERILOG
+        
+        MIXED
+        -1
+        
+        TRUE
+        TRUE
+        IP_Integrator
+        6
+        TRUE
+        .
+        
+        ../../ipshared
+        2017.4
+        OUT_OF_CONTEXT
+      
+      
+        
+          
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+          
+        
+      
+    
+  
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc
new file mode 100644
index 0000000..053eb05
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc
@@ -0,0 +1,701 @@
+############################################################################
+##
+##  Xilinx, Inc. 2006            www.xilinx.com
+############################################################################
+##  File name :       ps7_constraints.xdc
+##
+##  Details :     Constraints file
+##                    FPGA family:       zynq
+##                    FPGA:              xc7z010clg400-1
+##                    Device Size:        xc7z010
+##                    Package:            clg400
+##                    Speedgrade:         -1
+##
+##
+############################################################################
+############################################################################
+############################################################################
+# Clock constraints                                                        #
+############################################################################
+create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
+set_input_jitter clk_fpga_0 0.6
+#The clocks are asynchronous, user should constrain them appropriately.#
+
+
+############################################################################
+# I/O STANDARDS and Location Constraints                                   #
+############################################################################
+
+#  Enet 0 / mdio / MIO[53]
+set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
+set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
+set_property slew "slow" [get_ports "MIO[53]"]
+set_property drive "8" [get_ports "MIO[53]"]
+set_property pullup "TRUE" [get_ports "MIO[53]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
+#  Enet 0 / mdc / MIO[52]
+set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
+set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
+set_property slew "slow" [get_ports "MIO[52]"]
+set_property drive "8" [get_ports "MIO[52]"]
+set_property pullup "TRUE" [get_ports "MIO[52]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
+#  GPIO / gpio[51] / MIO[51]
+set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
+set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
+set_property slew "slow" [get_ports "MIO[51]"]
+set_property drive "8" [get_ports "MIO[51]"]
+set_property pullup "TRUE" [get_ports "MIO[51]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
+#  GPIO / gpio[50] / MIO[50]
+set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
+set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
+set_property slew "slow" [get_ports "MIO[50]"]
+set_property drive "8" [get_ports "MIO[50]"]
+set_property pullup "TRUE" [get_ports "MIO[50]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
+#  UART 1 / rx / MIO[49]
+set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
+set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
+set_property slew "slow" [get_ports "MIO[49]"]
+set_property drive "8" [get_ports "MIO[49]"]
+set_property pullup "TRUE" [get_ports "MIO[49]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
+#  UART 1 / tx / MIO[48]
+set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
+set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
+set_property slew "slow" [get_ports "MIO[48]"]
+set_property drive "8" [get_ports "MIO[48]"]
+set_property pullup "TRUE" [get_ports "MIO[48]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
+#  SD 0 / cd / MIO[47]
+set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
+set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
+set_property slew "slow" [get_ports "MIO[47]"]
+set_property drive "8" [get_ports "MIO[47]"]
+set_property pullup "TRUE" [get_ports "MIO[47]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
+#  GPIO / gpio[46] / MIO[46]
+set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
+set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
+set_property slew "slow" [get_ports "MIO[46]"]
+set_property drive "8" [get_ports "MIO[46]"]
+set_property pullup "TRUE" [get_ports "MIO[46]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
+#  SD 0 / data[3] / MIO[45]
+set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
+set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
+set_property slew "slow" [get_ports "MIO[45]"]
+set_property drive "8" [get_ports "MIO[45]"]
+set_property pullup "TRUE" [get_ports "MIO[45]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
+#  SD 0 / data[2] / MIO[44]
+set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
+set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
+set_property slew "slow" [get_ports "MIO[44]"]
+set_property drive "8" [get_ports "MIO[44]"]
+set_property pullup "TRUE" [get_ports "MIO[44]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
+#  SD 0 / data[1] / MIO[43]
+set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
+set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
+set_property slew "slow" [get_ports "MIO[43]"]
+set_property drive "8" [get_ports "MIO[43]"]
+set_property pullup "TRUE" [get_ports "MIO[43]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
+#  SD 0 / data[0] / MIO[42]
+set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
+set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
+set_property slew "slow" [get_ports "MIO[42]"]
+set_property drive "8" [get_ports "MIO[42]"]
+set_property pullup "TRUE" [get_ports "MIO[42]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
+#  SD 0 / cmd / MIO[41]
+set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
+set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
+set_property slew "slow" [get_ports "MIO[41]"]
+set_property drive "8" [get_ports "MIO[41]"]
+set_property pullup "TRUE" [get_ports "MIO[41]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
+#  SD 0 / clk / MIO[40]
+set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
+set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
+set_property slew "slow" [get_ports "MIO[40]"]
+set_property drive "8" [get_ports "MIO[40]"]
+set_property pullup "TRUE" [get_ports "MIO[40]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
+#  GPIO / gpio[39] / MIO[39]
+set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
+set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
+set_property slew "slow" [get_ports "MIO[39]"]
+set_property drive "8" [get_ports "MIO[39]"]
+set_property pullup "TRUE" [get_ports "MIO[39]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
+#  GPIO / gpio[38] / MIO[38]
+set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
+set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
+set_property slew "slow" [get_ports "MIO[38]"]
+set_property drive "8" [get_ports "MIO[38]"]
+set_property pullup "TRUE" [get_ports "MIO[38]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
+#  GPIO / gpio[37] / MIO[37]
+set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
+set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
+set_property slew "slow" [get_ports "MIO[37]"]
+set_property drive "8" [get_ports "MIO[37]"]
+set_property pullup "TRUE" [get_ports "MIO[37]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
+#  GPIO / gpio[36] / MIO[36]
+set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
+set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
+set_property slew "slow" [get_ports "MIO[36]"]
+set_property drive "8" [get_ports "MIO[36]"]
+set_property pullup "TRUE" [get_ports "MIO[36]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"]
+#  GPIO / gpio[35] / MIO[35]
+set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
+set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
+set_property slew "slow" [get_ports "MIO[35]"]
+set_property drive "8" [get_ports "MIO[35]"]
+set_property pullup "TRUE" [get_ports "MIO[35]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
+#  GPIO / gpio[34] / MIO[34]
+set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
+set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
+set_property slew "slow" [get_ports "MIO[34]"]
+set_property drive "8" [get_ports "MIO[34]"]
+set_property pullup "TRUE" [get_ports "MIO[34]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
+#  GPIO / gpio[33] / MIO[33]
+set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
+set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
+set_property slew "slow" [get_ports "MIO[33]"]
+set_property drive "8" [get_ports "MIO[33]"]
+set_property pullup "TRUE" [get_ports "MIO[33]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
+#  GPIO / gpio[32] / MIO[32]
+set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
+set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
+set_property slew "slow" [get_ports "MIO[32]"]
+set_property drive "8" [get_ports "MIO[32]"]
+set_property pullup "TRUE" [get_ports "MIO[32]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
+#  GPIO / gpio[31] / MIO[31]
+set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
+set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
+set_property slew "slow" [get_ports "MIO[31]"]
+set_property drive "8" [get_ports "MIO[31]"]
+set_property pullup "TRUE" [get_ports "MIO[31]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"]
+#  GPIO / gpio[30] / MIO[30]
+set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
+set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
+set_property slew "slow" [get_ports "MIO[30]"]
+set_property drive "8" [get_ports "MIO[30]"]
+set_property pullup "TRUE" [get_ports "MIO[30]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"]
+#  GPIO / gpio[29] / MIO[29]
+set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
+set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
+set_property slew "slow" [get_ports "MIO[29]"]
+set_property drive "8" [get_ports "MIO[29]"]
+set_property pullup "TRUE" [get_ports "MIO[29]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"]
+#  GPIO / gpio[28] / MIO[28]
+set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
+set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
+set_property slew "slow" [get_ports "MIO[28]"]
+set_property drive "8" [get_ports "MIO[28]"]
+set_property pullup "TRUE" [get_ports "MIO[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
+#  Enet 0 / rx_ctl / MIO[27]
+set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
+set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
+set_property slew "slow" [get_ports "MIO[27]"]
+set_property drive "8" [get_ports "MIO[27]"]
+set_property pullup "TRUE" [get_ports "MIO[27]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
+#  Enet 0 / rxd[3] / MIO[26]
+set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
+set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
+set_property slew "slow" [get_ports "MIO[26]"]
+set_property drive "8" [get_ports "MIO[26]"]
+set_property pullup "TRUE" [get_ports "MIO[26]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
+#  Enet 0 / rxd[2] / MIO[25]
+set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
+set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
+set_property slew "slow" [get_ports "MIO[25]"]
+set_property drive "8" [get_ports "MIO[25]"]
+set_property pullup "TRUE" [get_ports "MIO[25]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
+#  Enet 0 / rxd[1] / MIO[24]
+set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
+set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
+set_property slew "slow" [get_ports "MIO[24]"]
+set_property drive "8" [get_ports "MIO[24]"]
+set_property pullup "TRUE" [get_ports "MIO[24]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
+#  Enet 0 / rxd[0] / MIO[23]
+set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
+set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
+set_property slew "slow" [get_ports "MIO[23]"]
+set_property drive "8" [get_ports "MIO[23]"]
+set_property pullup "TRUE" [get_ports "MIO[23]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
+#  Enet 0 / rx_clk / MIO[22]
+set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
+set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
+set_property slew "slow" [get_ports "MIO[22]"]
+set_property drive "8" [get_ports "MIO[22]"]
+set_property pullup "TRUE" [get_ports "MIO[22]"]
+set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
+#  Enet 0 / tx_ctl / MIO[21]
+set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
+set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
+set_property slew "slow" [get_ports "MIO[21]"]
+set_property drive "8" [get_ports "MIO[21]"]
+set_property pullup "TRUE" [get_ports "MIO[21]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
+#  Enet 0 / txd[3] / MIO[20]
+set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
+set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
+set_property slew "slow" [get_ports "MIO[20]"]
+set_property drive "8" [get_ports "MIO[20]"]
+set_property pullup "TRUE" [get_ports "MIO[20]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
+#  Enet 0 / txd[2] / MIO[19]
+set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
+set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
+set_property slew "slow" [get_ports "MIO[19]"]
+set_property drive "8" [get_ports "MIO[19]"]
+set_property pullup "TRUE" [get_ports "MIO[19]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
+#  Enet 0 / txd[1] / MIO[18]
+set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
+set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
+set_property slew "slow" [get_ports "MIO[18]"]
+set_property drive "8" [get_ports "MIO[18]"]
+set_property pullup "TRUE" [get_ports "MIO[18]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
+#  Enet 0 / txd[0] / MIO[17]
+set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
+set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
+set_property slew "slow" [get_ports "MIO[17]"]
+set_property drive "8" [get_ports "MIO[17]"]
+set_property pullup "TRUE" [get_ports "MIO[17]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
+#  Enet 0 / tx_clk / MIO[16]
+set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
+set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
+set_property slew "slow" [get_ports "MIO[16]"]
+set_property drive "8" [get_ports "MIO[16]"]
+set_property pullup "TRUE" [get_ports "MIO[16]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
+#  GPIO / gpio[15] / MIO[15]
+set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
+set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
+set_property slew "slow" [get_ports "MIO[15]"]
+set_property drive "8" [get_ports "MIO[15]"]
+set_property pullup "TRUE" [get_ports "MIO[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
+#  GPIO / gpio[14] / MIO[14]
+set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
+set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
+set_property slew "slow" [get_ports "MIO[14]"]
+set_property drive "8" [get_ports "MIO[14]"]
+set_property pullup "TRUE" [get_ports "MIO[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
+#  GPIO / gpio[13] / MIO[13]
+set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
+set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
+set_property slew "slow" [get_ports "MIO[13]"]
+set_property drive "8" [get_ports "MIO[13]"]
+set_property pullup "TRUE" [get_ports "MIO[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
+#  GPIO / gpio[12] / MIO[12]
+set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
+set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
+set_property slew "slow" [get_ports "MIO[12]"]
+set_property drive "8" [get_ports "MIO[12]"]
+set_property pullup "TRUE" [get_ports "MIO[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
+#  GPIO / gpio[11] / MIO[11]
+set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
+set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
+set_property slew "slow" [get_ports "MIO[11]"]
+set_property drive "8" [get_ports "MIO[11]"]
+set_property pullup "TRUE" [get_ports "MIO[11]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
+#  GPIO / gpio[10] / MIO[10]
+set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
+set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
+set_property slew "slow" [get_ports "MIO[10]"]
+set_property drive "8" [get_ports "MIO[10]"]
+set_property pullup "TRUE" [get_ports "MIO[10]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
+#  GPIO / gpio[9] / MIO[9]
+set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
+set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
+set_property slew "slow" [get_ports "MIO[9]"]
+set_property drive "8" [get_ports "MIO[9]"]
+set_property pullup "TRUE" [get_ports "MIO[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
+#  Quad SPI Flash / qspi_fbclk / MIO[8]
+set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
+set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
+set_property slew "slow" [get_ports "MIO[8]"]
+set_property drive "8" [get_ports "MIO[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
+#  GPIO / gpio[7] / MIO[7]
+set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
+set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
+set_property slew "slow" [get_ports "MIO[7]"]
+set_property drive "8" [get_ports "MIO[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
+#  Quad SPI Flash / qspi0_sclk / MIO[6]
+set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
+set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
+set_property slew "slow" [get_ports "MIO[6]"]
+set_property drive "8" [get_ports "MIO[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
+#  Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
+set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
+set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
+set_property slew "slow" [get_ports "MIO[5]"]
+set_property drive "8" [get_ports "MIO[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
+#  Quad SPI Flash / qspi0_io[2] / MIO[4]
+set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
+set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
+set_property slew "slow" [get_ports "MIO[4]"]
+set_property drive "8" [get_ports "MIO[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
+#  Quad SPI Flash / qspi0_io[1] / MIO[3]
+set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
+set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
+set_property slew "slow" [get_ports "MIO[3]"]
+set_property drive "8" [get_ports "MIO[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
+#  Quad SPI Flash / qspi0_io[0] / MIO[2]
+set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
+set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
+set_property slew "slow" [get_ports "MIO[2]"]
+set_property drive "8" [get_ports "MIO[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
+#  Quad SPI Flash / qspi0_ss_b / MIO[1]
+set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
+set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
+set_property slew "slow" [get_ports "MIO[1]"]
+set_property drive "8" [get_ports "MIO[1]"]
+set_property pullup "TRUE" [get_ports "MIO[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
+#  GPIO / gpio[0] / MIO[0]
+set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
+set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
+set_property slew "slow" [get_ports "MIO[0]"]
+set_property drive "8" [get_ports "MIO[0]"]
+set_property pullup "TRUE" [get_ports "MIO[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
+set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
+set_property slew "FAST" [get_ports "DDR_VRP"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
+set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
+set_property slew "FAST" [get_ports "DDR_VRN"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
+set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
+set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
+set_property slew "SLOW" [get_ports "DDR_WEB"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
+set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
+set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
+set_property slew "SLOW" [get_ports "DDR_RAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
+set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
+set_property slew "SLOW" [get_ports "DDR_ODT"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
+set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
+set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
+set_property slew "FAST" [get_ports "DDR_DRSTB"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
+set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
+set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
+set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
+set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
+set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
+set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
+set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
+set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
+set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
+set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
+set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
+set_property slew "FAST" [get_ports "DDR_DQ[9]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
+set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
+set_property slew "FAST" [get_ports "DDR_DQ[8]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
+set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
+set_property slew "FAST" [get_ports "DDR_DQ[7]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
+set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
+set_property slew "FAST" [get_ports "DDR_DQ[6]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
+set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
+set_property slew "FAST" [get_ports "DDR_DQ[5]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
+set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
+set_property slew "FAST" [get_ports "DDR_DQ[4]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
+set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
+set_property slew "FAST" [get_ports "DDR_DQ[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
+set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
+set_property slew "FAST" [get_ports "DDR_DQ[31]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
+set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
+set_property slew "FAST" [get_ports "DDR_DQ[30]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
+set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
+set_property slew "FAST" [get_ports "DDR_DQ[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
+set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
+set_property slew "FAST" [get_ports "DDR_DQ[29]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
+set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
+set_property slew "FAST" [get_ports "DDR_DQ[28]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
+set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
+set_property slew "FAST" [get_ports "DDR_DQ[27]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
+set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
+set_property slew "FAST" [get_ports "DDR_DQ[26]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
+set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
+set_property slew "FAST" [get_ports "DDR_DQ[25]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
+set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
+set_property slew "FAST" [get_ports "DDR_DQ[24]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
+set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
+set_property slew "FAST" [get_ports "DDR_DQ[23]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
+set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
+set_property slew "FAST" [get_ports "DDR_DQ[22]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
+set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
+set_property slew "FAST" [get_ports "DDR_DQ[21]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
+set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
+set_property slew "FAST" [get_ports "DDR_DQ[20]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
+set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
+set_property slew "FAST" [get_ports "DDR_DQ[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
+set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
+set_property slew "FAST" [get_ports "DDR_DQ[19]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
+set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
+set_property slew "FAST" [get_ports "DDR_DQ[18]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
+set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
+set_property slew "FAST" [get_ports "DDR_DQ[17]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
+set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
+set_property slew "FAST" [get_ports "DDR_DQ[16]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
+set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
+set_property slew "FAST" [get_ports "DDR_DQ[15]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
+set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
+set_property slew "FAST" [get_ports "DDR_DQ[14]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
+set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
+set_property slew "FAST" [get_ports "DDR_DQ[13]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
+set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
+set_property slew "FAST" [get_ports "DDR_DQ[12]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
+set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
+set_property slew "FAST" [get_ports "DDR_DQ[11]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
+set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
+set_property slew "FAST" [get_ports "DDR_DQ[10]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
+set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
+set_property slew "FAST" [get_ports "DDR_DQ[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
+set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
+set_property slew "FAST" [get_ports "DDR_DM[3]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
+set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
+set_property slew "FAST" [get_ports "DDR_DM[2]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
+set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
+set_property slew "FAST" [get_ports "DDR_DM[1]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
+set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
+set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
+set_property slew "FAST" [get_ports "DDR_DM[0]"]
+set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
+set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
+set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
+set_property slew "SLOW" [get_ports "DDR_CS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
+set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
+set_property slew "SLOW" [get_ports "DDR_CKE"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
+set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
+set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
+set_property slew "FAST" [get_ports "DDR_Clk"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
+set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
+set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
+set_property slew "FAST" [get_ports "DDR_Clk_n"]
+set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
+set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
+set_property slew "SLOW" [get_ports "DDR_CAS_n"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
+set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
+set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
+set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
+set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
+set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
+set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
+set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
+set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
+set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
+set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
+set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
+set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
+set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
+set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
+set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
+set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
+set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
+set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
+set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
+set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
+set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
+set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
+set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
+set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
+set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
+set_property slew "fast" [get_ports "PS_PORB"]
+set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
+set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
+set_property slew "fast" [get_ports "PS_SRSTB"]
+set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
+set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
+set_property slew "fast" [get_ports "PS_CLK"]
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xml b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xml
new file mode 100644
index 0000000..3a357ce
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xml
@@ -0,0 +1,39289 @@
+
+
+  xilinx.com
+  customized_ip
+  system_processing_system7_0_0
+  1.0
+  
+    
+      GMII_ETHERNET_0
+      
+      
+      
+      
+        
+          
+            TX_EN
+          
+          
+            ENET0_GMII_TX_EN
+          
+        
+        
+          
+            TX_ER
+          
+          
+            ENET0_GMII_TX_ER
+          
+        
+        
+          
+            TXD
+          
+          
+            ENET0_GMII_TXD
+          
+        
+        
+          
+            COL
+          
+          
+            ENET0_GMII_COL
+          
+        
+        
+          
+            CRS
+          
+          
+            ENET0_GMII_CRS
+          
+        
+        
+          
+            RX_CLK
+          
+          
+            ENET0_GMII_RX_CLK
+          
+        
+        
+          
+            RX_DV
+          
+          
+            ENET0_GMII_RX_DV
+          
+        
+        
+          
+            RX_ER
+          
+          
+            ENET0_GMII_RX_ER
+          
+        
+        
+          
+            TX_CLK
+          
+          
+            ENET0_GMII_TX_CLK
+          
+        
+        
+          
+            RXD
+          
+          
+            ENET0_GMII_RXD
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      MDIO_ETHERNET_0
+      
+      
+      
+      
+        
+          
+            MDC
+          
+          
+            ENET0_MDIO_MDC
+          
+        
+        
+          
+            MDIO_O
+          
+          
+            ENET0_MDIO_O
+          
+        
+        
+          
+            MDIO_T
+          
+          
+            ENET0_MDIO_T
+          
+        
+        
+          
+            MDIO_I
+          
+          
+            ENET0_MDIO_I
+          
+        
+      
+      
+        
+          CAN_DEBUG
+          false
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PTP_ETHERNET_0
+      
+      
+      
+      
+        
+          
+            DELAY_REQ_RX
+          
+          
+            ENET0_PTP_DELAY_REQ_RX
+          
+        
+        
+          
+            DELAY_REQ_TX
+          
+          
+            ENET0_PTP_DELAY_REQ_TX
+          
+        
+        
+          
+            PDELAY_REQ_RX
+          
+          
+            ENET0_PTP_PDELAY_REQ_RX
+          
+        
+        
+          
+            PDELAY_REQ_TX
+          
+          
+            ENET0_PTP_PDELAY_REQ_TX
+          
+        
+        
+          
+            PDELAY_RESP_RX
+          
+          
+            ENET0_PTP_PDELAY_RESP_RX
+          
+        
+        
+          
+            PDELAY_RESP_TX
+          
+          
+            ENET0_PTP_PDELAY_RESP_TX
+          
+        
+        
+          
+            SYNC_FRAME_RX
+          
+          
+            ENET0_PTP_SYNC_FRAME_RX
+          
+        
+        
+          
+            SYNC_FRAME_TX
+          
+          
+            ENET0_PTP_SYNC_FRAME_TX
+          
+        
+        
+          
+            SOF_RX
+          
+          
+            ENET0_SOF_RX
+          
+        
+        
+          
+            SOF_TX
+          
+          
+            ENET0_SOF_TX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      ENET0_EXT_INTIN
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            ENET0_EXT_INTIN
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      GMII_ETHERNET_1
+      
+      
+      
+      
+        
+          
+            TX_EN
+          
+          
+            ENET1_GMII_TX_EN
+          
+        
+        
+          
+            TX_ER
+          
+          
+            ENET1_GMII_TX_ER
+          
+        
+        
+          
+            TXD
+          
+          
+            ENET1_GMII_TXD
+          
+        
+        
+          
+            COL
+          
+          
+            ENET1_GMII_COL
+          
+        
+        
+          
+            CRS
+          
+          
+            ENET1_GMII_CRS
+          
+        
+        
+          
+            RX_CLK
+          
+          
+            ENET1_GMII_RX_CLK
+          
+        
+        
+          
+            RX_DV
+          
+          
+            ENET1_GMII_RX_DV
+          
+        
+        
+          
+            RX_ER
+          
+          
+            ENET1_GMII_RX_ER
+          
+        
+        
+          
+            TX_CLK
+          
+          
+            ENET1_GMII_TX_CLK
+          
+        
+        
+          
+            RXD
+          
+          
+            ENET1_GMII_RXD
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      MDIO_ETHERNET_1
+      
+      
+      
+      
+        
+          
+            MDC
+          
+          
+            ENET1_MDIO_MDC
+          
+        
+        
+          
+            MDIO_O
+          
+          
+            ENET1_MDIO_O
+          
+        
+        
+          
+            MDIO_T
+          
+          
+            ENET1_MDIO_T
+          
+        
+        
+          
+            MDIO_I
+          
+          
+            ENET1_MDIO_I
+          
+        
+      
+      
+        
+          CAN_DEBUG
+          false
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PTP_ETHERNET_1
+      
+      
+      
+      
+        
+          
+            DELAY_REQ_RX
+          
+          
+            ENET1_PTP_DELAY_REQ_RX
+          
+        
+        
+          
+            DELAY_REQ_TX
+          
+          
+            ENET1_PTP_DELAY_REQ_TX
+          
+        
+        
+          
+            PDELAY_REQ_RX
+          
+          
+            ENET1_PTP_PDELAY_REQ_RX
+          
+        
+        
+          
+            PDELAY_REQ_TX
+          
+          
+            ENET1_PTP_PDELAY_REQ_TX
+          
+        
+        
+          
+            PDELAY_RESP_RX
+          
+          
+            ENET1_PTP_PDELAY_RESP_RX
+          
+        
+        
+          
+            PDELAY_RESP_TX
+          
+          
+            ENET1_PTP_PDELAY_RESP_TX
+          
+        
+        
+          
+            SYNC_FRAME_RX
+          
+          
+            ENET1_PTP_SYNC_FRAME_RX
+          
+        
+        
+          
+            SYNC_FRAME_TX
+          
+          
+            ENET1_PTP_SYNC_FRAME_TX
+          
+        
+        
+          
+            SOF_RX
+          
+          
+            ENET1_SOF_RX
+          
+        
+        
+          
+            SOF_TX
+          
+          
+            ENET1_SOF_TX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      ENET1_EXT_INTIN
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            ENET1_EXT_INTIN
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      GPIO_0
+      
+      
+      
+      
+        
+          
+            TRI_I
+          
+          
+            GPIO_I
+          
+        
+        
+          
+            TRI_O
+          
+          
+            GPIO_O
+          
+        
+        
+          
+            TRI_T
+          
+          
+            GPIO_T
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DDR
+      
+      
+      
+      
+        
+          
+            CAS_N
+          
+          
+            DDR_CAS_n
+          
+        
+        
+          
+            CKE
+          
+          
+            DDR_CKE
+          
+        
+        
+          
+            CK_N
+          
+          
+            DDR_Clk_n
+          
+        
+        
+          
+            CK_P
+          
+          
+            DDR_Clk
+          
+        
+        
+          
+            CS_N
+          
+          
+            DDR_CS_n
+          
+        
+        
+          
+            RESET_N
+          
+          
+            DDR_DRSTB
+          
+        
+        
+          
+            ODT
+          
+          
+            DDR_ODT
+          
+        
+        
+          
+            RAS_N
+          
+          
+            DDR_RAS_n
+          
+        
+        
+          
+            WE_N
+          
+          
+            DDR_WEB
+          
+        
+        
+          
+            BA
+          
+          
+            DDR_BankAddr
+          
+        
+        
+          
+            ADDR
+          
+          
+            DDR_Addr
+          
+        
+        
+          
+            DM
+          
+          
+            DDR_DM
+          
+        
+        
+          
+            DQ
+          
+          
+            DDR_DQ
+          
+        
+        
+          
+            DQS_N
+          
+          
+            DDR_DQS_n
+          
+        
+        
+          
+            DQS_P
+          
+          
+            DDR_DQS
+          
+        
+      
+      
+        
+          CAN_DEBUG
+          false
+          
+            
+              none
+            
+          
+        
+        
+          TIMEPERIOD_PS
+          1250
+          
+            
+              none
+            
+          
+        
+        
+          MEMORY_TYPE
+          COMPONENTS
+          
+            
+              none
+            
+          
+        
+        
+          MEMORY_PART
+          
+          
+            
+              none
+            
+          
+        
+        
+          DATA_WIDTH
+          8
+          
+            
+              none
+            
+          
+        
+        
+          CS_ENABLED
+          true
+          
+            
+              none
+            
+          
+        
+        
+          DATA_MASK_ENABLED
+          true
+          
+            
+              none
+            
+          
+        
+        
+          SLOT
+          Single
+          
+            
+              none
+            
+          
+        
+        
+          CUSTOM_PARTS
+          
+          
+            
+              none
+            
+          
+        
+        
+          MEM_ADDR_MAP
+          ROW_COLUMN_BANK
+          
+            
+              none
+            
+          
+        
+        
+          BURST_LENGTH
+          8
+          
+            
+              none
+            
+          
+        
+        
+          AXI_ARBITRATION_SCHEME
+          TDM
+          
+            
+              none
+            
+          
+        
+        
+          CAS_LATENCY
+          11
+          
+            
+              none
+            
+          
+        
+        
+          CAS_WRITE_LATENCY
+          11
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      FIXED_IO
+      
+      
+      
+      
+        
+          
+            MIO
+          
+          
+            MIO
+          
+        
+        
+          
+            DDR_VRN
+          
+          
+            DDR_VRN
+          
+        
+        
+          
+            DDR_VRP
+          
+          
+            DDR_VRP
+          
+        
+        
+          
+            PS_SRSTB
+          
+          
+            PS_SRSTB
+          
+        
+        
+          
+            PS_CLK
+          
+          
+            PS_CLK
+          
+        
+        
+          
+            PS_PORB
+          
+          
+            PS_PORB
+          
+        
+      
+      
+        
+          CAN_DEBUG
+          false
+          
+            
+              none
+            
+          
+        
+      
+    
+    
+      UART_0
+      
+      
+      
+      
+        
+          
+            DTRn
+          
+          
+            UART0_DTRN
+          
+        
+        
+          
+            RTSn
+          
+          
+            UART0_RTSN
+          
+        
+        
+          
+            TxD
+          
+          
+            UART0_TX
+          
+        
+        
+          
+            CTSn
+          
+          
+            UART0_CTSN
+          
+        
+        
+          
+            DCDn
+          
+          
+            UART0_DCDN
+          
+        
+        
+          
+            DSRn
+          
+          
+            UART0_DSRN
+          
+        
+        
+          
+            RI
+          
+          
+            UART0_RIN
+          
+        
+        
+          
+            RxD
+          
+          
+            UART0_RX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      UART_1
+      
+      
+      
+      
+        
+          
+            DTRn
+          
+          
+            UART1_DTRN
+          
+        
+        
+          
+            RTSn
+          
+          
+            UART1_RTSN
+          
+        
+        
+          
+            TxD
+          
+          
+            UART1_TX
+          
+        
+        
+          
+            CTSn
+          
+          
+            UART1_CTSN
+          
+        
+        
+          
+            DCDn
+          
+          
+            UART1_DCDN
+          
+        
+        
+          
+            DSRn
+          
+          
+            UART1_DSRN
+          
+        
+        
+          
+            RI
+          
+          
+            UART1_RIN
+          
+        
+        
+          
+            RxD
+          
+          
+            UART1_RX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IIC_0
+      
+      
+      
+      
+        
+          
+            SDA_I
+          
+          
+            I2C0_SDA_I
+          
+        
+        
+          
+            SDA_O
+          
+          
+            I2C0_SDA_O
+          
+        
+        
+          
+            SDA_T
+          
+          
+            I2C0_SDA_T
+          
+        
+        
+          
+            SCL_I
+          
+          
+            I2C0_SCL_I
+          
+        
+        
+          
+            SCL_O
+          
+          
+            I2C0_SCL_O
+          
+        
+        
+          
+            SCL_T
+          
+          
+            I2C0_SCL_T
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IIC_1
+      
+      
+      
+      
+        
+          
+            SDA_I
+          
+          
+            I2C1_SDA_I
+          
+        
+        
+          
+            SDA_O
+          
+          
+            I2C1_SDA_O
+          
+        
+        
+          
+            SDA_T
+          
+          
+            I2C1_SDA_T
+          
+        
+        
+          
+            SCL_I
+          
+          
+            I2C1_SCL_I
+          
+        
+        
+          
+            SCL_O
+          
+          
+            I2C1_SCL_O
+          
+        
+        
+          
+            SCL_T
+          
+          
+            I2C1_SCL_T
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      SPI_0
+      
+      
+      
+      
+        
+          
+            SCK_I
+          
+          
+            SPI0_SCLK_I
+          
+        
+        
+          
+            SCK_O
+          
+          
+            SPI0_SCLK_O
+          
+        
+        
+          
+            SCK_T
+          
+          
+            SPI0_SCLK_T
+          
+        
+        
+          
+            IO0_I
+          
+          
+            SPI0_MOSI_I
+          
+        
+        
+          
+            IO0_O
+          
+          
+            SPI0_MOSI_O
+          
+        
+        
+          
+            IO0_T
+          
+          
+            SPI0_MOSI_T
+          
+        
+        
+          
+            IO1_I
+          
+          
+            SPI0_MISO_I
+          
+        
+        
+          
+            IO1_O
+          
+          
+            SPI0_MISO_O
+          
+        
+        
+          
+            IO1_T
+          
+          
+            SPI0_MISO_T
+          
+        
+        
+          
+            SS_I
+          
+          
+            SPI0_SS_I
+          
+        
+        
+          
+            SS_O
+          
+          
+            SPI0_SS_O
+          
+        
+        
+          
+            SS1_O
+          
+          
+            SPI0_SS1_O
+          
+        
+        
+          
+            SS2_O
+          
+          
+            SPI0_SS2_O
+          
+        
+        
+          
+            SS_T
+          
+          
+            SPI0_SS_T
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      SPI_1
+      
+      
+      
+      
+        
+          
+            SCK_I
+          
+          
+            SPI1_SCLK_I
+          
+        
+        
+          
+            SCK_O
+          
+          
+            SPI1_SCLK_O
+          
+        
+        
+          
+            SCK_T
+          
+          
+            SPI1_SCLK_T
+          
+        
+        
+          
+            IO0_I
+          
+          
+            SPI1_MOSI_I
+          
+        
+        
+          
+            IO0_O
+          
+          
+            SPI1_MOSI_O
+          
+        
+        
+          
+            IO0_T
+          
+          
+            SPI1_MOSI_T
+          
+        
+        
+          
+            IO1_I
+          
+          
+            SPI1_MISO_I
+          
+        
+        
+          
+            IO1_O
+          
+          
+            SPI1_MISO_O
+          
+        
+        
+          
+            IO1_T
+          
+          
+            SPI1_MISO_T
+          
+        
+        
+          
+            SS_I
+          
+          
+            SPI1_SS_I
+          
+        
+        
+          
+            SS_O
+          
+          
+            SPI1_SS_O
+          
+        
+        
+          
+            SS1_O
+          
+          
+            SPI1_SS1_O
+          
+        
+        
+          
+            SS2_O
+          
+          
+            SPI1_SS2_O
+          
+        
+        
+          
+            SS_T
+          
+          
+            SPI1_SS_T
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      CAN_0
+      
+      
+      
+      
+        
+          
+            TX
+          
+          
+            CAN0_PHY_TX
+          
+        
+        
+          
+            RX
+          
+          
+            CAN0_PHY_RX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      CAN_1
+      
+      
+      
+      
+        
+          
+            TX
+          
+          
+            CAN1_PHY_TX
+          
+        
+        
+          
+            RX
+          
+          
+            CAN1_PHY_RX
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PJTAG
+      
+      
+      
+      
+        
+          
+            TCK
+          
+          
+            PJTAG_TCK
+          
+        
+        
+          
+            TMS
+          
+          
+            PJTAG_TMS
+          
+        
+        
+          
+            TDI
+          
+          
+            PJTAG_TDI
+          
+        
+        
+          
+            TDO
+          
+          
+            PJTAG_TDO
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      SDIO_0
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            SDIO0_CLK
+          
+        
+        
+          
+            CLK_FB
+          
+          
+            SDIO0_CLK_FB
+          
+        
+        
+          
+            CMD_O
+          
+          
+            SDIO0_CMD_O
+          
+        
+        
+          
+            CMD_I
+          
+          
+            SDIO0_CMD_I
+          
+        
+        
+          
+            CMD_T
+          
+          
+            SDIO0_CMD_T
+          
+        
+        
+          
+            DATA_I
+          
+          
+            SDIO0_DATA_I
+          
+        
+        
+          
+            DATA_O
+          
+          
+            SDIO0_DATA_O
+          
+        
+        
+          
+            DATA_T
+          
+          
+            SDIO0_DATA_T
+          
+        
+        
+          
+            LED
+          
+          
+            SDIO0_LED
+          
+        
+        
+          
+            CDN
+          
+          
+            SDIO0_CDN
+          
+        
+        
+          
+            WP
+          
+          
+            SDIO0_WP
+          
+        
+        
+          
+            BUSPOW
+          
+          
+            SDIO0_BUSPOW
+          
+        
+        
+          
+            BUSVOLT
+          
+          
+            SDIO0_BUSVOLT
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      SDIO_1
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            SDIO1_CLK
+          
+        
+        
+          
+            CLK_FB
+          
+          
+            SDIO1_CLK_FB
+          
+        
+        
+          
+            CMD_O
+          
+          
+            SDIO1_CMD_O
+          
+        
+        
+          
+            CMD_I
+          
+          
+            SDIO1_CMD_I
+          
+        
+        
+          
+            CMD_T
+          
+          
+            SDIO1_CMD_T
+          
+        
+        
+          
+            DATA_I
+          
+          
+            SDIO1_DATA_I
+          
+        
+        
+          
+            DATA_O
+          
+          
+            SDIO1_DATA_O
+          
+        
+        
+          
+            DATA_T
+          
+          
+            SDIO1_DATA_T
+          
+        
+        
+          
+            LED
+          
+          
+            SDIO1_LED
+          
+        
+        
+          
+            CDN
+          
+          
+            SDIO1_CDN
+          
+        
+        
+          
+            WP
+          
+          
+            SDIO1_WP
+          
+        
+        
+          
+            BUSPOW
+          
+          
+            SDIO1_BUSPOW
+          
+        
+        
+          
+            BUSVOLT
+          
+          
+            SDIO1_BUSVOLT
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRACE_0
+      
+      
+      
+      
+        
+          
+            CLK_O
+          
+          
+            TRACE_CLK_OUT
+          
+        
+        
+          
+            CLK_I
+          
+          
+            TRACE_CLK
+          
+        
+        
+          
+            CTL
+          
+          
+            TRACE_CTL
+          
+        
+        
+          
+            DATA
+          
+          
+            TRACE_DATA
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      USBIND_0
+      
+      
+      
+      
+        
+          
+            PORT_INDCTL
+          
+          
+            USB0_PORT_INDCTL
+          
+        
+        
+          
+            VBUS_PWRSELECT
+          
+          
+            USB0_VBUS_PWRSELECT
+          
+        
+        
+          
+            VBUS_PWRFAULT
+          
+          
+            USB0_VBUS_PWRFAULT
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      USBIND_1
+      
+      
+      
+      
+        
+          
+            PORT_INDCTL
+          
+          
+            USB1_PORT_INDCTL
+          
+        
+        
+          
+            VBUS_PWRSELECT
+          
+          
+            USB1_VBUS_PWRSELECT
+          
+        
+        
+          
+            VBUS_PWRFAULT
+          
+          
+            USB1_VBUS_PWRFAULT
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP0_FIFO_CTRL
+      
+      
+      
+      
+        
+          
+            RCOUNT
+          
+          
+            S_AXI_HP0_RCOUNT
+          
+        
+        
+          
+            WCOUNT
+          
+          
+            S_AXI_HP0_WCOUNT
+          
+        
+        
+          
+            RACOUNT
+          
+          
+            S_AXI_HP0_RACOUNT
+          
+        
+        
+          
+            WACOUNT
+          
+          
+            S_AXI_HP0_WACOUNT
+          
+        
+        
+          
+            RDISSUECAPEN
+          
+          
+            S_AXI_HP0_RDISSUECAP1_EN
+          
+        
+        
+          
+            WRISSUECAPEN
+          
+          
+            S_AXI_HP0_WRISSUECAP1_EN
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP1_FIFO_CTRL
+      
+      
+      
+      
+        
+          
+            RCOUNT
+          
+          
+            S_AXI_HP1_RCOUNT
+          
+        
+        
+          
+            WCOUNT
+          
+          
+            S_AXI_HP1_WCOUNT
+          
+        
+        
+          
+            RACOUNT
+          
+          
+            S_AXI_HP1_RACOUNT
+          
+        
+        
+          
+            WACOUNT
+          
+          
+            S_AXI_HP1_WACOUNT
+          
+        
+        
+          
+            RDISSUECAPEN
+          
+          
+            S_AXI_HP1_RDISSUECAP1_EN
+          
+        
+        
+          
+            WRISSUECAPEN
+          
+          
+            S_AXI_HP1_WRISSUECAP1_EN
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP2_FIFO_CTRL
+      
+      
+      
+      
+        
+          
+            RCOUNT
+          
+          
+            S_AXI_HP2_RCOUNT
+          
+        
+        
+          
+            WCOUNT
+          
+          
+            S_AXI_HP2_WCOUNT
+          
+        
+        
+          
+            RACOUNT
+          
+          
+            S_AXI_HP2_RACOUNT
+          
+        
+        
+          
+            WACOUNT
+          
+          
+            S_AXI_HP2_WACOUNT
+          
+        
+        
+          
+            RDISSUECAPEN
+          
+          
+            S_AXI_HP2_RDISSUECAP1_EN
+          
+        
+        
+          
+            WRISSUECAPEN
+          
+          
+            S_AXI_HP2_WRISSUECAP1_EN
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP3_FIFO_CTRL
+      
+      
+      
+      
+        
+          
+            RCOUNT
+          
+          
+            S_AXI_HP3_RCOUNT
+          
+        
+        
+          
+            WCOUNT
+          
+          
+            S_AXI_HP3_WCOUNT
+          
+        
+        
+          
+            RACOUNT
+          
+          
+            S_AXI_HP3_RACOUNT
+          
+        
+        
+          
+            WACOUNT
+          
+          
+            S_AXI_HP3_WACOUNT
+          
+        
+        
+          
+            RDISSUECAPEN
+          
+          
+            S_AXI_HP3_RDISSUECAP1_EN
+          
+        
+        
+          
+            WRISSUECAPEN
+          
+          
+            S_AXI_HP3_WRISSUECAP1_EN
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA0_REQ
+      
+      
+      
+      
+        
+          
+            TREADY
+          
+          
+            DMA0_DRREADY
+          
+        
+        
+          
+            TLAST
+          
+          
+            DMA0_DRLAST
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA0_DRVALID
+          
+        
+        
+          
+            TUSER
+          
+          
+            DMA0_DRTYPE
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA0_ACK
+      
+      
+      
+      
+        
+          
+            TUSER
+          
+          
+            DMA0_DATYPE
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA0_DAVALID
+          
+        
+        
+          
+            TREADY
+          
+          
+            DMA0_DAREADY
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA1_REQ
+      
+      
+      
+      
+        
+          
+            TREADY
+          
+          
+            DMA1_DRREADY
+          
+        
+        
+          
+            TLAST
+          
+          
+            DMA1_DRLAST
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA1_DRVALID
+          
+        
+        
+          
+            TUSER
+          
+          
+            DMA1_DRTYPE
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA1_ACK
+      
+      
+      
+      
+        
+          
+            TUSER
+          
+          
+            DMA1_DATYPE
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA1_DAVALID
+          
+        
+        
+          
+            TREADY
+          
+          
+            DMA1_DAREADY
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA2_REQ
+      
+      
+      
+      
+        
+          
+            TREADY
+          
+          
+            DMA2_DRREADY
+          
+        
+        
+          
+            TLAST
+          
+          
+            DMA2_DRLAST
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA2_DRVALID
+          
+        
+        
+          
+            TUSER
+          
+          
+            DMA2_DRTYPE
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA2_ACK
+      
+      
+      
+      
+        
+          
+            TUSER
+          
+          
+            DMA2_DATYPE
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA2_DAVALID
+          
+        
+        
+          
+            TREADY
+          
+          
+            DMA2_DAREADY
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
+            
+          
+        
+        
+          TDEST_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TID_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          TUSER_WIDTH
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TREADY
+          1
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TSTRB
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TKEEP
+          0
+          
+            
+              none
+            
+          
+        
+        
+          HAS_TLAST
+          0
+          
+            
+              none
+            
+          
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          LAYERED_METADATA
+          undef
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA3_REQ
+      
+      
+      
+      
+        
+          
+            TREADY
+          
+          
+            DMA3_DRREADY
+          
+        
+        
+          
+            TLAST
+          
+          
+            DMA3_DRLAST
+          
+        
+        
+          
+            TVALID
+          
+          
+            DMA3_DRVALID
+          
+        
+        
+          
+            TUSER
+          
+          
+            DMA3_DRTYPE
+          
+        
+      
+      
+        
+          TDATA_NUM_BYTES
+          1
+          
+            
+              none
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+          
+            S_AXI_HP2_WSTRB
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+      
+        
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+          NUM WRITE OUTSTANDING
+          8
+        
+        
+          NUM_READ_OUTSTANDING
+          NUM READ OUTSTANDING
+          8
+        
+        
+          DATA_WIDTH
+          32
+          
+            
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+          
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+            S_AXI_HP3_ARREADY
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+          
+            AWREADY
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+            S_AXI_HP3_AWREADY
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+            S_AXI_HP3_BVALID
+          
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+          
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+          
+            ARADDR
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+          
+            AWADDR
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+          
+            S_AXI_HP3_AWADDR
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+        
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+          
+            ARCACHE
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+            S_AXI_HP3_ARCACHE
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+        
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+          
+            S_AXI_HP3_ARLEN
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+        
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+          
+            S_AXI_HP3_ARQOS
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+          
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+          
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+            ARID
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+          
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+          
+            WSTRB
+          
+          
+            S_AXI_HP3_WSTRB
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+      
+        
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+          NUM WRITE OUTSTANDING
+          8
+        
+        
+          NUM_READ_OUTSTANDING
+          NUM READ OUTSTANDING
+          8
+        
+        
+          DATA_WIDTH
+          32
+          
+            
+              none
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+          0
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+          1
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+          1
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+          1
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+          1
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+          1
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+          1
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+          1
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+          1
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+          1
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+          256
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+            
+              none
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+        
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+          1
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+          1
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+          0
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+        
+          
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+      FCLK_CLK0
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+      
+      
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+            CLK
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+          
+            FCLK_CLK0
+          
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+        
+          FREQ_HZ
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+        
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+          system_processing_system7_0_0_FCLK_CLK0
+          
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+          
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+            
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+            
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+        
+          
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+          
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+      FCLK_CLK1
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+      
+      
+      
+        
+          
+            CLK
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+          
+            FCLK_CLK1
+          
+        
+      
+      
+        
+          FREQ_HZ
+          1e+07
+        
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+            
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+            
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+        
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+            
+              none
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+        
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+      
+        
+          
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+    
+      FCLK_CLK2
+      
+      
+      
+      
+        
+          
+            CLK
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+          
+            FCLK_CLK2
+          
+        
+      
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+        
+          FREQ_HZ
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+        
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+          PHASE
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+            
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+          
+            
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+        
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+            
+              none
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+          
+        
+      
+      
+        
+          
+            false
+          
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+    
+      FCLK_CLK3
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+      
+      
+      
+        
+          
+            CLK
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+          
+            FCLK_CLK3
+          
+        
+      
+      
+        
+          FREQ_HZ
+          1e+07
+        
+        
+          PHASE
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+            
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+          
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+        
+          CLK_DOMAIN
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+          
+            
+              none
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+          
+        
+        
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+          
+          
+            
+              none
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+        
+        
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+          
+          
+            
+              none
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+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      FCLK_RESET0_N
+      
+      
+      
+      
+        
+          
+            RST
+          
+          
+            FCLK_RESET0_N
+          
+        
+      
+      
+        
+          POLARITY
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+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      FCLK_RESET1_N
+      
+      
+      
+      
+        
+          
+            RST
+          
+          
+            FCLK_RESET1_N
+          
+        
+      
+      
+        
+          POLARITY
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+          
+            
+              none
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+          
+        
+      
+      
+        
+          
+            false
+          
+        
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+    
+    
+      FCLK_RESET2_N
+      
+      
+      
+      
+        
+          
+            RST
+          
+          
+            FCLK_RESET2_N
+          
+        
+      
+      
+        
+          POLARITY
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+          
+            
+              none
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+          
+        
+      
+      
+        
+          
+            false
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+        
+      
+    
+    
+      FCLK_RESET3_N
+      
+      
+      
+      
+        
+          
+            RST
+          
+          
+            FCLK_RESET3_N
+          
+        
+      
+      
+        
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+            
+              none
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+          
+        
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+      
+        
+          
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+        
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+    
+    
+      IRQ_P2F_DMAC_ABORT
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC_ABORT
+          
+        
+      
+      
+        
+          SENSITIVITY
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+        
+        
+          PortWidth
+          1
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+            
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+            
+          
+        
+      
+      
+        
+          
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+          
+        
+      
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+    
+      IRQ_P2F_DMAC0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC0
+          
+        
+      
+      
+        
+          SENSITIVITY
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+        
+        
+          PortWidth
+          1
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+            
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+          
+        
+      
+      
+        
+          
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+        
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+    
+    
+      IRQ_P2F_DMAC1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC1
+          
+        
+      
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+        
+          SENSITIVITY
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+        
+        
+          PortWidth
+          1
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+            
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+          
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+      
+      
+        
+          
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+          
+        
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+    
+      IRQ_P2F_DMAC2
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC2
+          
+        
+      
+      
+        
+          SENSITIVITY
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+        
+          PortWidth
+          1
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+      
+        
+          
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+    
+      IRQ_P2F_DMAC3
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC3
+          
+        
+      
+      
+        
+          SENSITIVITY
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+        
+        
+          PortWidth
+          1
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+            
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+      
+        
+          
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+          
+        
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+    
+    
+      IRQ_P2F_DMAC4
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC4
+          
+        
+      
+      
+        
+          SENSITIVITY
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+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_DMAC5
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC5
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_DMAC6
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC6
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_DMAC7
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_DMAC7
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_SMC
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_SMC
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_QSPI
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_QSPI
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_CTI
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_CTI
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_GPIO
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_GPIO
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_USB0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_USB0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_ENET0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_ENET0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_ENET_WAKE0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_ENET_WAKE0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          EDGE_RISING
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_SDIO0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_SDIO0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_I2C0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_I2C0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_SPI0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_SPI0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_UART0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_UART0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_CAN0
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_CAN0
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_USB1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_USB1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_ENET1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_ENET1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_ENET_WAKE1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_ENET_WAKE1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          EDGE_RISING
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_SDIO1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_SDIO1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_I2C1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_I2C1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_SPI1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_SPI1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_UART1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_UART1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_P2F_CAN1
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_P2F_CAN1
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      IRQ_F2P
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            IRQ_F2P
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      Core0_nFIQ
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            Core0_nFIQ
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      Core0_nIRQ
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            Core0_nIRQ
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      Core1_nFIQ
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            Core1_nFIQ
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      Core1_nIRQ
+      
+      
+      
+      
+        
+          
+            INTERRUPT
+          
+          
+            Core1_nIRQ
+          
+        
+      
+      
+        
+          SENSITIVITY
+          LEVEL_HIGH
+          
+            
+              none
+            
+          
+        
+        
+          PortWidth
+          1
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      M_AXI_GP0_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            M_AXI_GP0_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          M_AXI_GP0
+        
+        
+          FREQ_HZ
+          50000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          system_processing_system7_0_0_FCLK_CLK0
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      M_AXI_GP1_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            M_AXI_GP1_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          M_AXI_GP1
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_ACP_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_ACP_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_ACP
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_GP0_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_GP0_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_GP0
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_GP1_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_GP1_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_GP1
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP0_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_HP0_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_HP0
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP1_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_HP1_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_HP1
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP2_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_HP2_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_HP2
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP3_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            S_AXI_HP3_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          S_AXI_HP3
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      FTMD_TRACEIN_CLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            FTMD_TRACEIN_CLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          FTM_TRACE_DATA
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA0_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            DMA0_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          DMA0_ACK:DMA0_REQ
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA1_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            DMA1_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          DMA1_ACK:DMA1_REQ
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA2_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            DMA2_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          DMA2_ACK:DMA2_REQ
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      DMA3_ACLK
+      
+      
+      
+      
+        
+          
+            CLK
+          
+          
+            DMA3_ACLK
+          
+        
+      
+      
+        
+          ASSOCIATED_BUSIF
+          DMA3_ACK:DMA3_REQ
+        
+        
+          FREQ_HZ
+          100000000
+          
+            
+              none
+            
+          
+        
+        
+          PHASE
+          0.000
+          
+            
+              none
+            
+          
+        
+        
+          CLK_DOMAIN
+          
+          
+            
+              none
+            
+          
+        
+        
+          ASSOCIATED_RESET
+          
+          
+            
+              none
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_IN_0
+      
+      
+      
+      
+        
+          
+            TRIG
+          
+          
+            FTMT_F2P_TRIG_0
+          
+        
+        
+          
+            ACK
+          
+          
+            FTMT_F2P_TRIGACK_0
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_IN_1
+      
+      
+      
+      
+        
+          
+            TRIG
+          
+          
+            FTMT_F2P_TRIG_1
+          
+        
+        
+          
+            ACK
+          
+          
+            FTMT_F2P_TRIGACK_1
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_IN_2
+      
+      
+      
+      
+        
+          
+            TRIG
+          
+          
+            FTMT_F2P_TRIG_2
+          
+        
+        
+          
+            ACK
+          
+          
+            FTMT_F2P_TRIGACK_2
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_IN_3
+      
+      
+      
+      
+        
+          
+            TRIG
+          
+          
+            FTMT_F2P_TRIG_3
+          
+        
+        
+          
+            ACK
+          
+          
+            FTMT_F2P_TRIGACK_3
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_OUT_0
+      
+      
+      
+      
+        
+          
+            ACK
+          
+          
+            FTMT_P2F_TRIGACK_0
+          
+        
+        
+          
+            TRIG
+          
+          
+            FTMT_P2F_TRIG_0
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_OUT_1
+      
+      
+      
+      
+        
+          
+            ACK
+          
+          
+            FTMT_P2F_TRIGACK_1
+          
+        
+        
+          
+            TRIG
+          
+          
+            FTMT_P2F_TRIG_1
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_OUT_2
+      
+      
+      
+      
+        
+          
+            ACK
+          
+          
+            FTMT_P2F_TRIGACK_2
+          
+        
+        
+          
+            TRIG
+          
+          
+            FTMT_P2F_TRIG_2
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      TRIGGER_OUT_3
+      
+      
+      
+      
+        
+          
+            ACK
+          
+          
+            FTMT_P2F_TRIGACK_3
+          
+        
+        
+          
+            TRIG
+          
+          
+            FTMT_P2F_TRIG_3
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+  
+  
+    
+      Data
+      Data
+      4G
+      32
+      
+        
+          segment1
+          segment1
+          0x00000000
+          0x00040000
+        
+        
+          segment2
+          segment2
+          0x00040000
+          0x00040000
+        
+        
+          segment3
+          segment3
+          0x00080000
+          0x00080000
+        
+        
+          segment4
+          segment4
+          0x00100000
+          0x3ff00000
+        
+        
+          M_AXI_GP0
+          M_AXI_GP0
+          0x40000000
+          0x40000000
+        
+        
+          M_AXI_GP1
+          M_AXI_GP1
+          0x80000000
+          0x40000000
+        
+        
+          IO_Peripheral_Registers
+          IO Peripheral Registers
+          0xe0000000
+          0x00300000
+        
+        
+          SMC_Memories
+          SMC Memories
+          0xe1000000
+          0x05000000
+        
+        
+          SLCR_Registers
+          SLCR Registers
+          0xf8000000
+          0x00000c00
+        
+        
+          PS_System_Registers
+          PS System Registers
+          0xf8001000
+          0x0080f000
+        
+        
+          CPU_Private_Registers
+          CPU Private Registers
+          0xf8900000
+          0x00603000
+        
+        
+          segment5
+          segment5
+          0xfc000000
+          0x02000000
+        
+        
+          segment6
+          segment6
+          0xfffc0000
+          0x00040000
+        
+      
+    
+  
+  
+    
+      S_AXI_HP0
+      
+        HP0_LOW_OCM
+        HP0 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        HP0_DDR_LOWOCM
+        HP0 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        HP0_HIGH_OCM
+        HP0 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP1
+      
+        HP1_LOW_OCM
+        HP1 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        HP1_DDR_LOWOCM
+        HP1 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        HP1_HIGH_OCM
+        HP1 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP2
+      
+        HP2_LOW_OCM
+        HP2 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        HP2_DDR_LOWOCM
+        HP2 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        HP2_HIGH_OCM
+        HP2 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_HP3
+      
+        HP3_LOW_OCM
+        HP3 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        HP3_DDR_LOWOCM
+        HP3 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        HP3_HIGH_OCM
+        HP3 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_GP0
+      
+        GP0_LOW_OCM
+        GP0 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_DDR_LOWOCM
+        GP0 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP0_HIGH_OCM
+        GP0 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_QSPI_LINEAR
+        GP0 QSPI LINEAR
+        0xfc000000
+        16777216
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP0_SRAM_NOR0
+        GP0 SRAM NOR 0
+        0xe2000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SRAM_NOR1
+        GP0 SRAM NOR 1
+        0xe4000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_NAND
+        GP0 NAND
+        0xe1000000
+        0x01000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_IOP
+        GP0 IOP
+        0xe0000000
+        0x00400000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP0_UART0
+        GP0 UART0
+        0xe0000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_UART1
+        GP0 UART0
+        0xe0001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_USB0
+        GP0 USB0
+        0xe0002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_USB1
+        GP0 USB1
+        0xe0003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_IIC0
+        GP0 IIC0
+        0xe0004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_IIC1
+        GP0 IIC1
+        0xe0005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SPI0
+        GP0 SPI0
+        0xe0006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SPI1
+        GP0 SPI1
+        0xe0007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_CAN0
+        GP0 CAN0
+        0xe0008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_CAN1
+        GP0 CAN1
+        0xe0009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_GPIO
+        GP0 GPIO
+        0xe000A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_ENET0
+        GP0 ENET0
+        0xe000B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_ENET1
+        GP0 ENET1
+        0xe000C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_QSPI
+        GP0 QSPI
+        0xe000D000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SMC
+        GP0 SMC
+        0xe000e000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SDIO0
+        GP0 SDIO0
+        0xe0100000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SDIO1
+        GP0 SDIO1
+        0xe0101000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_PS_SLCR_REGS
+        GP0 PS REG
+        0xf8000000
+        0x00010000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SLCR
+        GP0 SLCR
+        0xf8000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_TTC0
+        GP0 TTC0
+        0xf8001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_TTC1
+        GP0 TTC1
+        0xf8002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_DMAC_S
+        GP0 DMAC S
+        0xf8003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_DMAC_NS
+        GP0 DMAC NS
+        0xf8004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_SWDT
+        GP0 SWDT
+        0xf8005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_DDRC
+        GP0 DDRC
+        0xf8006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_DEVCFG
+        GP0 DEVCFG
+        0xf8007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_AFI0
+        GP0 AFI0
+        0xf8008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_AFI1
+        GP0 AFI1
+        0xf8009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_AFI2
+        GP0 AFI2
+        0xf800A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_AFI3
+        GP0 AFI3
+        0xf800B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_OCM_REG
+        GP0 OCM REG
+        0xf800C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_CORESIGHT
+        GP0 CORESIGHT
+        0xf8800000
+        0x00100000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP0_M_AXI_GP0
+        GP0 M AXI GP0
+        0x40000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP0_M_AXI_GP1
+        GP0 M AXI GP1
+        0x80000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_GP1
+      
+        GP1_LOW_OCM
+        GP1 LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_DDR_LOWOCM
+        GP1 DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP1_HIGH_OCM
+        GP1 HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_QSPI_LINEAR
+        GP1 QSPI LINEAR
+        0xfc000000
+        16777216
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP1_SRAM_NOR0
+        GP1 SRAM NOR 0
+        0xe2000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SRAM_NOR1
+        GP1 SRAM NOR 1
+        0xe4000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_NAND
+        GP1 NAND
+        0xe1000000
+        0x01000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_IOP
+        GP1 IOP
+        0xe0000000
+        0x00400000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP1_UART0
+        GP1 UART0
+        0xe0000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_UART1
+        GP1 UART0
+        0xe0001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_USB0
+        GP1 USB0
+        0xe0002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_USB1
+        GP1 USB1
+        0xe0003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_IIC0
+        GP1 IIC0
+        0xe0004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_IIC1
+        GP1 IIC1
+        0xe0005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SPI0
+        GP1 SPI0
+        0xe0006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SPI1
+        GP1 SPI1
+        0xe0007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_CAN0
+        GP1 CAN0
+        0xe0008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_CAN1
+        GP1 CAN1
+        0xe0009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_GPIO
+        GP1 GPIO
+        0xe000A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_ENET0
+        GP1 ENET0
+        0xe000B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_ENET1
+        GP1 ENET1
+        0xe000C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_QSPI
+        GP1 QSPI
+        0xe000D000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SMC
+        GP1 SMC
+        0xe000e000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SDIO0
+        GP1 SDIO0
+        0xe0100000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SDIO1
+        GP1 SDIO1
+        0xe0101000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_PS_SLCR_REGS
+        GP1 PS REG
+        0xf8000000
+        0x00010000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SLCR
+        GP1 SLCR
+        0xf8000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_TTC0
+        GP1 TTC0
+        0xf8001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_TTC1
+        GP1 TTC1
+        0xf8002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_DMAC_S
+        GP1 DMAC S
+        0xf8003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_DMAC_NS
+        GP1 DMAC NS
+        0xf8004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_SWDT
+        GP1 SWDT
+        0xf8005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_DDRC
+        GP1 DDRC
+        0xf8006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_DEVCFG
+        GP1 DEVCFG
+        0xf8007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_AFI0
+        GP1 AFI0
+        0xf8008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_AFI1
+        GP1 AFI1
+        0xf8009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_AFI2
+        GP1 AFI2
+        0xf800A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_AFI3
+        GP1 AFI3
+        0xf800B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_OCM_REG
+        GP1 OCM REG
+        0xf800C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_CORESIGHT
+        GP1 CORESIGHT
+        0xf8800000
+        0x00100000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        GP1_M_AXI_GP0
+        GP1 M AXI GP0
+        0x40000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        GP1_M_AXI_GP1
+        GP1 M AXI GP1
+        0x80000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      S_AXI_ACP
+      
+        ACP_LOW_OCM
+        ACP LOW OCM
+        0x00000000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_DDR_LOWOCM
+        ACP DDR LOWOCM
+        0x00000000
+        1073741824
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        ACP_HIGH_OCM
+        ACP HIGH OCM
+        0xfffc0000
+        0x00040000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_QSPI_LINEAR
+        ACP QSPI LINEAR
+        0xfc000000
+        16777216
+        32
+        memory
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        ACP_SRAM_NOR0
+        ACP SRAM NOR 0
+        0xe2000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SRAM_NOR1
+        ACP SRAM NOR 1
+        0xe4000000
+        0x02000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_NAND
+        ACP NAND
+        0xe1000000
+        0x01000000
+        32
+        memory
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_IOP
+        ACP IOP
+        0xe0000000
+        0x00400000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        ACP_UART0
+        ACP UART0
+        0xe0000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_UART1
+        ACP UART0
+        0xe0001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_USB0
+        ACP USB0
+        0xe0002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_USB1
+        ACP USB1
+        0xe0003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_IIC0
+        ACP IIC0
+        0xe0004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_IIC1
+        ACP IIC1
+        0xe0005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SPI0
+        ACP SPI0
+        0xe0006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SPI1
+        ACP SPI1
+        0xe0007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_CAN0
+        ACP CAN0
+        0xe0008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_CAN1
+        ACP CAN1
+        0xe0009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_GPIO
+        ACP GPIO
+        0xe000A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_ENET0
+        ACP ENET0
+        0xe000B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_ENET1
+        ACP ENET1
+        0xe000C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_QSPI
+        ACP QSPI
+        0xe000D000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SMC
+        ACP SMC
+        0xe000e000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SDIO0
+        ACP SDIO0
+        0xe0100000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SDIO1
+        ACP SDIO1
+        0xe0101000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_PS_SLCR_REGS
+        ACP PS REG
+        0xf8000000
+        0x00010000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SLCR
+        ACP SLCR
+        0xf8000000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_TTC0
+        ACP TTC0
+        0xf8001000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_TTC1
+        ACP TTC1
+        0xf8002000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_DMAC_S
+        ACP DMAC S
+        0xf8003000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_DMAC_NS
+        ACP DMAC NS
+        0xf8004000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_SWDT
+        ACP SWDT
+        0xf8005000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_DDRC
+        ACP DDRC
+        0xf8006000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_DEVCFG
+        ACP DEVCFG
+        0xf8007000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_AFI0
+        ACP AFI0
+        0xf8008000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_AFI1
+        ACP AFI1
+        0xf8009000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_AFI2
+        ACP AFI2
+        0xf800A000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_AFI3
+        ACP AFI3
+        0xf800B000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_OCM_REG
+        ACP OCM REG
+        0xf800C000
+        0x00001000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_CORESIGHT
+        ACP CORESIGHT
+        0xf8800000
+        0x00100000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        ACP_M_AXI_GP0
+        ACP M AXI GP0
+        0x40000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        ACP_M_AXI_GP1
+        ACP M AXI GP1
+        0x80000000
+        0x40000000
+        32
+        register
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        
+          
+            false
+          
+        
+      
+    
+  
+  
+    
+      
+        xilinx_anylanguagesynthesis
+        Synthesis
+        :vivado.xilinx.com:synthesis
+        
+          xilinx_anylanguagesynthesis_view_fileset
+        
+        
+          
+            GENtimestamp
+            Sat May 25 05:08:20 UTC 2019
+          
+          
+            outputProductCRC
+            7:627ca085
+          
+        
+      
+      
+        xilinx_verilogsynthesiswrapper
+        Verilog Synthesis Wrapper
+        verilogSource:vivado.xilinx.com:synthesis.wrapper
+        verilog
+        
+          xilinx_verilogsynthesiswrapper_view_fileset
+        
+        
+          
+            GENtimestamp
+            Sat May 25 05:08:20 UTC 2019
+          
+          
+            outputProductCRC
+            7:627ca085
+          
+        
+      
+      
+        xilinx_anylanguagebehavioralsimulation
+        Simulation
+        :vivado.xilinx.com:simulation
+        
+          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset
+        
+        
+          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_sc_util_1_0__ref_view_fileset
+        
+        
+          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_protocol_checker_2_0__ref_view_fileset
+        
+        
+          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_vip_1_1__ref_view_fileset
+        
+        
+          xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_processing_system7_vip_1_0__ref_view_fileset
+        
+        
+          
+            outputProductCRC
+            7:8dc5b251
+          
+        
+      
+      
+        xilinx_anylanguagebehavioralsimulation_1
+        Simulation
+        :vivado.xilinx.com:simulation
+        
+          xilinx_anylanguagebehavioralsimulation_1_view_fileset
+        
+        
+          
+            GENtimestamp
+            Sat May 25 05:08:20 UTC 2019
+          
+          
+            outputProductCRC
+            7:8dc5b251
+          
+          
+            sim_type
+            tlm_dpi
+          
+          
+            sls_compatible
+            yes
+          
+        
+      
+      
+        xilinx_anylanguagesimulationwrapper
+        Simulation Wrapper
+        :vivado.xilinx.com:simulation.wrapper
+        
+          xilinx_anylanguagesimulationwrapper_view_fileset
+        
+        
+          
+            GENtimestamp
+            Sat May 25 05:08:21 UTC 2019
+          
+          
+            outputProductCRC
+            7:8dc5b251
+          
+        
+      
+      
+        xilinx_anylanguagesimulationwrapper_1
+        Simulation Wrapper
+        :vivado.xilinx.com:simulation.wrapper
+        
+          xilinx_anylanguagesimulationwrapper_1_view_fileset
+        
+        
+          
+            GENtimestamp
+            Sat May 25 05:08:25 UTC 2019
+          
+          
+            outputProductCRC
+            7:8dc5b251
+          
+          
+            sim_type
+            tlm_dpi
+          
+        
+      
+    
+    
+      
+        CAN0_PHY_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        CAN0_PHY_RX
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
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+      
+        CAN1_PHY_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+        
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+        
+          in
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+            
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+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
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+          
+            0
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+        
+        
+          
+            
+              false
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+          
+        
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+        ENET0_GMII_TX_EN
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+          
+            0
+            0
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+          
+            
+              reg
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+        
+        
+          
+            
+              false
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+        
+      
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+        ENET0_GMII_TX_ER
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+          
+            0
+            0
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+          
+            
+              reg
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_MDIO_MDC
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        ENET0_MDIO_O
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_MDIO_T
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        ENET0_PTP_DELAY_REQ_RX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
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+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_PTP_DELAY_REQ_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_PTP_PDELAY_REQ_RX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
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+        
+        
+          
+            
+              false
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+        
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+      
+        ENET0_PTP_PDELAY_REQ_TX
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+        
+        
+          
+            
+              false
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+        
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+        ENET0_PTP_PDELAY_RESP_RX
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+        
+        
+          
+            
+              false
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+        
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+        ENET0_PTP_PDELAY_RESP_TX
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_PTP_SYNC_FRAME_RX
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        ENET0_PTP_SYNC_FRAME_TX
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        ENET0_SOF_RX
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+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_SOF_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
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+            
+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        ENET0_GMII_TXD
+        
+          out
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+            7
+            0
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+          
+            
+              reg
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_GMII_COL
+        
+          in
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+            
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+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
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+        
+        
+          
+            
+              false
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+        
+      
+      
+        ENET0_GMII_CRS
+        
+          in
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+          
+            0
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+        
+        
+          
+            
+              false
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+        
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+      
+        ENET0_GMII_RX_CLK
+        
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
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+            
+          
+        
+        
+          
+            
+              false
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+        
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+      
+        ENET0_GMII_RX_DV
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+            
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+              xilinx_anylanguagesynthesis
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+            
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+            0
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+        
+        
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+            
+              false
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+        
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+        
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+            
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+            0
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+        
+        
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+            
+              false
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+        
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+            
+              std_logic
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+            
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+        
+        
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+            
+              false
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+            0
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+            
+              false
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+            0
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+            
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+            
+              std_logic_vector
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+        
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+          
+            
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+        ENET1_GMII_TX_EN
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+            0
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+            
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+          
+            
+              false
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+        ENET1_GMII_TX_ER
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+            0
+            0
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+            
+              reg
+              xilinx_anylanguagesynthesis
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+        
+        
+          
+            
+              false
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+        
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+      
+        ENET1_MDIO_MDC
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
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+          
+        
+        
+          
+            
+              false
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+        ENET1_MDIO_O
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+            
+              std_logic
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+          
+        
+        
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+            
+              false
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+        ENET1_MDIO_T
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+            
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+          
+        
+        
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+            
+              false
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+        ENET1_PTP_DELAY_REQ_RX
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+            
+              std_logic
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+        
+        
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+            
+              false
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+        
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+        ENET1_PTP_DELAY_REQ_TX
+        
+          out
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+            
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+            
+              false
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+        ENET1_PTP_PDELAY_REQ_RX
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+            
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+        
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+            
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+        ENET1_PTP_PDELAY_REQ_TX
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+            
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+        
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+            
+              false
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+        ENET1_PTP_PDELAY_RESP_RX
+        
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+            
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+            
+              false
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+        ENET1_PTP_PDELAY_RESP_TX
+        
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+            
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+            
+              false
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+        
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+      
+        ENET1_PTP_SYNC_FRAME_RX
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+          out
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+            
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+        
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+            
+              false
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+      
+        ENET1_PTP_SYNC_FRAME_TX
+        
+          out
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+            
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+            
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+        
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+            
+              false
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+        ENET1_SOF_RX
+        
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+            
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+            
+              false
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+      
+        ENET1_SOF_TX
+        
+          out
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+            
+              std_logic
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+            
+              false
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+        ENET1_GMII_TXD
+        
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+            7
+            0
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+          
+            
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+        
+        
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+            
+              false
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+            
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+            0
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+        ENET1_GMII_CRS
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+            
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+          
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+            0
+          
+        
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+            
+              false
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+        
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+      
+        ENET1_GMII_RX_CLK
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
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+            
+          
+        
+        
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+            
+              false
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+      
+        ENET1_GMII_RX_DV
+        
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+            
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+            
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+          
+            0
+          
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+        
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+            
+              false
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+        ENET1_GMII_RX_ER
+        
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+            
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+            
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+            0
+          
+        
+        
+          
+            
+              false
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+        
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+      
+        ENET1_GMII_TX_CLK
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
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+        
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+      
+        ENET1_MDIO_I
+        
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+            
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+              xilinx_anylanguagesynthesis
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+            
+          
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+            0
+          
+        
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+            
+              false
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+        ENET1_EXT_INTIN
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+            0
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+            
+              false
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+        ENET1_GMII_RXD
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+            7
+            0
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+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+            0
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+        
+          
+            
+              false
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+        GPIO_I
+        
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+          
+            63
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+            0
+          
+        
+        
+          
+            
+              false
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+        GPIO_O
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+            63
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+        
+        
+          
+            
+              false
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+        GPIO_T
+        
+          out
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+            63
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+        
+        
+          
+            
+              false
+            
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+        
+      
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+        I2C0_SDA_I
+        
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
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+              false
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+        I2C0_SDA_O
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+            
+              std_logic
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+        
+        
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+            
+              false
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+        I2C0_SDA_T
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+            
+              std_logic
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+        
+        
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+            
+              false
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+        I2C0_SCL_I
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+            
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+              xilinx_anylanguagebehavioralsimulation
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+            0
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+              false
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+        I2C0_SCL_O
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+              false
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+        I2C0_SCL_T
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+              false
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+        I2C1_SDA_I
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+            0
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+              false
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+        I2C1_SDA_T
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+        I2C1_SCL_I
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+        I2C1_SCL_T
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+        PJTAG_TCK
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+            
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+        PJTAG_TMS
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+            
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+              xilinx_anylanguagesynthesis
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+        
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+        
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+        
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+        
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+              false
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+        
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+              false
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+        
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+            0
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+            
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+            
+          
+        
+        
+          
+            
+              false
+            
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+        
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+      
+        SPI1_SS1_O
+        
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        SPI1_SS2_O
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        SPI1_SS_T
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART0_DTRN
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART0_RTSN
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART0_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART0_CTSN
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART0_DCDN
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
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+        
+      
+      
+        UART0_DSRN
+        
+          in
+          
+            
+              std_logic
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+              xilinx_anylanguagebehavioralsimulation
+            
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+          
+            0
+          
+        
+        
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+            
+              false
+            
+          
+        
+      
+      
+        UART0_RIN
+        
+          in
+          
+            
+              std_logic
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+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
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+            
+              false
+            
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+        
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+      
+        UART0_RX
+        
+          in
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+            
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+              xilinx_anylanguagebehavioralsimulation
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+          
+            1
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+              false
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+      
+        UART1_DTRN
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
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+            
+              false
+            
+          
+        
+      
+      
+        UART1_RTSN
+        
+          out
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+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART1_TX
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART1_CTSN
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART1_DCDN
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART1_DSRN
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        UART1_RIN
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+        
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+        
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+            0
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+              std_logic_vector
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+              xilinx_anylanguagesynthesis
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+        
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+          
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+          
+          
+            0
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARVALID
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWVALID
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_BREADY
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RREADY
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WLAST
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WVALID
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARID
+        
+          out
+          
+            11
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWID
+        
+          out
+          
+            11
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WID
+        
+          out
+          
+            11
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARBURST
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARLOCK
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARSIZE
+        
+          out
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWBURST
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWLOCK
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWSIZE
+        
+          out
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARPROT
+        
+          out
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWPROT
+        
+          out
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARADDR
+        
+          out
+          
+            31
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWADDR
+        
+          out
+          
+            31
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WDATA
+        
+          out
+          
+            31
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARCACHE
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARLEN
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARQOS
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWCACHE
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWLEN
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWQOS
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WSTRB
+        
+          out
+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ACLK
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_ARREADY
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_AWREADY
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_BVALID
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RLAST
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RVALID
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_WREADY
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_BID
+        
+          in
+          
+            11
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RID
+        
+          in
+          
+            11
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_BRESP
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RRESP
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        M_AXI_GP1_RDATA
+        
+          in
+          
+            31
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ARREADY
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_AWREADY
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_BVALID
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RLAST
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RVALID
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_WREADY
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_BRESP
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RRESP
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RDATA
+        
+          out
+          
+            31
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_BID
+        
+          out
+          
+            5
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RID
+        
+          out
+          
+            5
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ACLK
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ARVALID
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_AWVALID
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_BREADY
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_RREADY
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_WLAST
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_WVALID
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ARBURST
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ARLOCK
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_ARSIZE
+        
+          in
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_AWBURST
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_AWLOCK
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        S_AXI_GP0_AWSIZE
+        
+          in
+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
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+              xilinx_anylanguagebehavioralsimulation
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+        
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+            5
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+          
+        
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+            
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+        
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+          
+            5
+            0
+          
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+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
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+      
+        S_AXI_HP3_WID
+        
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+          
+            5
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
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+            0
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+        
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+            
+              false
+            
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+        
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+      
+        S_AXI_HP3_WDATA
+        
+          in
+          
+            63
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
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+            
+              false
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+        
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+      
+        S_AXI_HP3_WSTRB
+        
+          in
+          
+            7
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
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+          
+        
+      
+      
+        IRQ_P2F_DMAC_ABORT
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC2
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC3
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC4
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC5
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC6
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_DMAC7
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_SMC
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_QSPI
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_CTI
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_GPIO
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_USB0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_ENET0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_ENET_WAKE0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_SDIO0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_I2C0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_SPI0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_UART0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_CAN0
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_USB1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_ENET1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_ENET_WAKE1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_SDIO1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_I2C1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_SPI1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_UART1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_P2F_CAN1
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        IRQ_F2P
+        
+          in
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        Core0_nFIQ
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        Core0_nIRQ
+        
+          in
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        Core1_nFIQ
+        
+          in
+          
+            
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+              std_logic
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+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        EVENT_EVENTO
+        
+          out
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        EVENT_STANDBYWFE
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        EVENT_STANDBYWFI
+        
+          out
+          
+            1
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
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+        
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+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
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+        
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+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+          
+            0
+          
+        
+        
+          
+            
+              false
+            
+          
+        
+      
+      
+        MIO
+        
+          inout
+          
+            53
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+      
+      
+        DDR_CAS_n
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_CKE
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_Clk_n
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_Clk
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_CS_n
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_DRSTB
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_ODT
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_RAS_n
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_WEB
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_BankAddr
+        
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+          
+            2
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_Addr
+        
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+          
+            14
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_VRN
+        
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+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
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+      
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+        
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+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        DDR_DM
+        
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+          
+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
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+        
+          
+            
+              true
+            
+          
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+      
+        DDR_DQ
+        
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+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
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+              true
+            
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+      
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+            3
+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
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+      
+      
+        DDR_DQS
+        
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+          
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+            0
+          
+          
+            
+              std_logic_vector
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+        
+          
+            
+              true
+            
+          
+        
+      
+      
+        PS_SRSTB
+        
+          inout
+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+      
+      
+        PS_CLK
+        
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+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
+        
+      
+      
+        PS_PORB
+        
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+          
+            
+              std_logic
+              xilinx_anylanguagesynthesis
+              xilinx_anylanguagebehavioralsimulation
+            
+          
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+    
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+      
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+        0
+      
+      
+        C_EN_EMIO_ENET1
+        0
+      
+      
+        C_EN_EMIO_TRACE
+        0
+      
+      
+        C_INCLUDE_TRACE_BUFFER
+        0
+      
+      
+        C_TRACE_BUFFER_FIFO_SIZE
+        128
+      
+      
+        USE_TRACE_DATA_EDGE_DETECTOR
+        0
+      
+      
+        C_TRACE_PIPELINE_WIDTH
+        8
+      
+      
+        C_TRACE_BUFFER_CLOCK_DELAY
+        12
+      
+      
+        C_EMIO_GPIO_WIDTH
+        64
+      
+      
+        C_INCLUDE_ACP_TRANS_CHECK
+        0
+      
+      
+        C_USE_DEFAULT_ACP_USER_VAL
+        0
+      
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+        31
+      
+      
+        C_S_AXI_ACP_AWUSER_VAL
+        31
+      
+      
+        C_M_AXI_GP0_ID_WIDTH
+        12
+      
+      
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+        0
+      
+      
+        C_M_AXI_GP1_ID_WIDTH
+        12
+      
+      
+        C_M_AXI_GP1_ENABLE_STATIC_REMAP
+        0
+      
+      
+        C_S_AXI_GP0_ID_WIDTH
+        6
+      
+      
+        C_S_AXI_GP1_ID_WIDTH
+        6
+      
+      
+        C_S_AXI_ACP_ID_WIDTH
+        3
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+      
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+        C_S_AXI_HP1_ID_WIDTH
+        6
+      
+      
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+        64
+      
+      
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+        6
+      
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+        C_S_AXI_HP2_DATA_WIDTH
+        64
+      
+      
+        C_S_AXI_HP3_ID_WIDTH
+        6
+      
+      
+        C_S_AXI_HP3_DATA_WIDTH
+        64
+      
+      
+        C_M_AXI_GP0_THREAD_ID_WIDTH
+        12
+      
+      
+        C_M_AXI_GP1_THREAD_ID_WIDTH
+        12
+      
+      
+        C_NUM_F2P_INTR_INPUTS
+        2
+      
+      
+        C_IRQ_F2P_MODE
+        DIRECT
+      
+      
+        C_DQ_WIDTH
+        32
+      
+      
+        C_DQS_WIDTH
+        4
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+      
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+        4
+      
+      
+        C_MIO_PRIMITIVE
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+      
+      
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+        2
+      
+      
+        C_USE_AXI_NONSECURE
+        0
+      
+      
+        C_USE_M_AXI_GP0
+        1
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+        0
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+      
+        C_USE_S_AXI_HP2
+        0
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+        C_USE_S_AXI_HP3
+        0
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+      
+        C_USE_S_AXI_ACP
+        0
+      
+      
+        C_PS7_SI_REV
+        PRODUCTION
+      
+      
+        C_FCLK_CLK0_BUF
+        TRUE
+      
+      
+        C_FCLK_CLK1_BUF
+        FALSE
+      
+      
+        C_FCLK_CLK2_BUF
+        FALSE
+      
+      
+        C_FCLK_CLK3_BUF
+        FALSE
+      
+      
+        C_PACKAGE_NAME
+        clg400
+      
+      
+        C_GP0_EN_MODIFIABLE_TXN
+        0
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+      
+        C_GP1_EN_MODIFIABLE_TXN
+        0
+      
+    
+  
+  
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+      1
+      2
+      3
+      4
+      5
+      6
+      7
+      8
+    
+    
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+      ARM PLL
+      DDR PLL
+      IO PLL
+      External
+    
+    
+      choice_list_0f5c91ba
+      EMIO
+      MIO 8 .. 9
+      MIO 12 .. 13
+      MIO 16 .. 17
+      MIO 20 .. 21
+      MIO 24 .. 25
+      MIO 28 .. 29
+      MIO 32 .. 33
+      MIO 36 .. 37
+      MIO 40 .. 41
+      MIO 44 .. 45
+      MIO 48 .. 49
+      MIO 52 .. 53
+    
+    
+      choice_list_1075ca33
+      4
+      2
+    
+    
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+      <Select>
+      EMIO
+      MIO 18
+      MIO 30
+      MIO 42
+    
+    
+      choice_list_1a80fa5a
+      <Select>
+      EMIO
+      MIO 18 .. 19
+      MIO 30 .. 31
+      MIO 42 .. 43
+    
+    
+      choice_list_2091a159
+      <Select>
+      MIO 0 2.. 14
+    
+    
+      choice_list_20dc6536
+      32
+      16
+    
+    
+      choice_list_2328412a
+      HPR(0)/LPR(32)
+      HPR(8)/LPR(24)
+      HPR(16)/LPR(16)
+      HPR(24)/LPR(8)
+      HPR(32)/LPR(0)
+    
+    
+      choice_list_27376075
+      12
+    
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+      disabled
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+    
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+      High (95 Max)
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+      MIO 1
+    
+    
+      choice_list_30d18a73
+      0xE0105fff
+    
+    
+      choice_list_319636fe
+      0xE0104fff
+    
+    
+      choice_list_31d1d296
+      <Select>
+      DISABLED
+      CPU0 DBG_ACK
+      CPU1 DBG_ACK
+      BOTH
+    
+    
+      choice_list_32c7371b
+      128 MBits
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+      512 MBits
+      1024 MBits
+      2048 MBits
+      4096 MBits
+      8192 MBits
+    
+    
+      choice_list_353a343d
+      <Select>
+      MIO 3 .. 39
+    
+    
+      choice_list_35b40bd0
+      6
+    
+    
+      choice_list_3607bdd0
+      0xE0102fff
+    
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+      LVCMOS 1.8V
+      HSTL 1.8V
+    
+    
+      choice_list_3740015d
+      0xE0103fff
+    
+    
+      choice_list_390b0393
+      <Select>
+      EMIO
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+      MIO 28 .. 33
+      MIO 40 .. 45
+    
+    
+      choice_list_3b9f1944
+      <Select>
+      x8
+    
+    
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+      MIO 2
+      MIO 4
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+      MIO 8
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+      MIO 24
+      MIO 26
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+      MIO 30
+      MIO 32
+      MIO 34
+      MIO 36
+      MIO 38
+      MIO 40
+      MIO 42
+      MIO 44
+      MIO 46
+      MIO 48
+      MIO 50
+      MIO 52
+    
+    
+      choice_list_3f5f808e
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+      LVCMOS 2.5V
+      HSTL 1.8V
+      LVCMOS 1.8V
+    
+    
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+      <Select>
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+      MIO 26 .. 27
+    
+    
+      choice_list_46eb370a
+      DIRECT
+      REVERSE
+    
+    
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+      0x00100000
+      0x00040000
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+    
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+    
+    
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+      MIO 8
+    
+    
+      choice_list_56e9f994
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+      MIO 10 .. 13
+      MIO 22 .. 25
+      MIO 34 .. 37
+      MIO 46 .. 49
+    
+    
+      choice_list_5beb845c
+      x1
+      x2
+      x4
+    
+    
+      choice_list_5d0f73c4
+      <Select>
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+      MIO 14 .. 15
+      MIO 18 .. 19
+      MIO 22 .. 23
+      MIO 26 .. 27
+      MIO 30 .. 31
+      MIO 34 .. 35
+      MIO 38 .. 39
+      MIO 42 .. 43
+      MIO 46 .. 47
+      MIO 50 .. 51
+    
+    
+      choice_list_5d70a6b7
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+      1
+      2
+      3
+      4
+      5
+      6
+      7
+      8
+      9
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+      28
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+      33
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+      52
+      53
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+      64
+    
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+      MIO 52 .. 53
+    
+    
+      choice_list_606c1634
+      <Select>
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+      MIO 52 .. 53
+    
+    
+      choice_list_6727dfa6
+      1
+      0
+    
+    
+      choice_list_6a282484
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+      MIO 1
+      MIO 2
+      MIO 3
+      MIO 4
+      MIO 5
+      MIO 6
+      MIO 9
+      MIO 10
+      MIO 11
+      MIO 12
+      MIO 13
+      MIO 14
+      MIO 15
+      MIO 16
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+      MIO 18
+      MIO 19
+      MIO 20
+      MIO 21
+      MIO 22
+      MIO 23
+      MIO 24
+      MIO 25
+      MIO 26
+      MIO 27
+      MIO 28
+      MIO 29
+      MIO 30
+      MIO 31
+      MIO 32
+      MIO 33
+      MIO 34
+      MIO 35
+      MIO 36
+      MIO 37
+      MIO 38
+      MIO 39
+      MIO 40
+      MIO 41
+      MIO 42
+      MIO 43
+      MIO 44
+      MIO 45
+      MIO 46
+      MIO 47
+      MIO 48
+      MIO 49
+      MIO 50
+      MIO 51
+      MIO 52
+      MIO 53
+    
+    
+      choice_list_6a48f1e0
+      MIO
+    
+    
+      choice_list_6bc4d474
+      LVCMOS 3.3V
+    
+    
+      choice_list_6bd7fb73
+      Active High
+      Active Low
+    
+    
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+      LVCMOS 2.5V
+      LVCMOS 3.3V
+      HSTL 1.8V
+    
+    
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+      MIO 1
+      MIO 2
+      MIO 3
+      MIO 4
+      MIO 5
+      MIO 6
+      MIO 9
+      MIO 10
+      MIO 11
+      MIO 12
+      MIO 13
+      MIO 14
+      MIO 15
+      MIO 16
+      MIO 17
+      MIO 18
+      MIO 19
+      MIO 20
+      MIO 21
+      MIO 22
+      MIO 23
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+      MIO 25
+      MIO 26
+      MIO 27
+      MIO 28
+      MIO 29
+      MIO 30
+      MIO 31
+      MIO 32
+      MIO 33
+      MIO 34
+      MIO 35
+      MIO 36
+      MIO 37
+      MIO 38
+      MIO 39
+      MIO 40
+      MIO 41
+      MIO 42
+      MIO 43
+      MIO 44
+      MIO 45
+      MIO 46
+      MIO 47
+      MIO 48
+      MIO 49
+      MIO 50
+      MIO 51
+      MIO 52
+      MIO 53
+    
+    
+      choice_list_767f870c
+      External
+    
+    
+      choice_list_7abc2131
+      16 Bit
+      32 Bit
+    
+    
+      choice_list_7bfdc3d8
+      <Select>
+      EMIO
+      MIO 20
+      MIO 32
+      MIO 44
+    
+    
+      choice_list_7d098ed6
+      ARM PLL
+      IO PLL
+      DDR PLL
+      External
+    
+    
+      choice_list_7d6d1b3f
+      1
+      2
+      3
+    
+    
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+      DDR3_800E
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+    
+    
+      PCW_I2C0_HIGHADDR
+      PCW I2C0 HIGHADDR
+      0xE0004FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_BASEADDR
+      PCW I2C1 BASEADDR
+      0xE0005000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_HIGHADDR
+      PCW I2C1 HIGHADDR
+      0xE0005FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_BASEADDR
+      PCW SPI0 BASEADDR
+      0xE0006000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_HIGHADDR
+      PCW SPI0 HIGHADDR
+      0xE0006FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_BASEADDR
+      PCW SPI1 BASEADDR
+      0xE0007000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_HIGHADDR
+      PCW SPI1 HIGHADDR
+      0xE0007FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_BASEADDR
+      PCW CAN0 BASEADDR
+      0xE0008000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_HIGHADDR
+      PCW CAN0 HIGHADDR
+      0xE0008FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_BASEADDR
+      PCW CAN1 BASEADDR
+      0xE0009000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_HIGHADDR
+      PCW CAN1 HIGHADDR
+      0xE0009FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_GPIO_BASEADDR
+      PCW GPIO BASEADDR
+      0xE000A000
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_GPIO_HIGHADDR
+      PCW GPIO HIGHADDR
+      0xE000AFFF
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_ENET0_BASEADDR
+      PCW ENET0 BASEADDR
+      0xE000B000
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_ENET0_HIGHADDR
+      PCW ENET0 HIGHADDR
+      0xE000BFFF
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_ENET1_BASEADDR
+      PCW ENET1 BASEADDR
+      0xE000C000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_HIGHADDR
+      PCW ENET1 HIGHADDR
+      0xE000CFFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SDIO0_BASEADDR
+      PCW SDIO0 BASEADDR
+      0xE0100000
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_SDIO0_HIGHADDR
+      PCW SDIO0 HIGHADDR
+      0xE0100FFF
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_SDIO1_BASEADDR
+      PCW SDIO1 BASEADDR
+      0xE0101000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SDIO1_HIGHADDR
+      PCW SDIO1 HIGHADDR
+      0xE0101FFF
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_BASEADDR
+      PCW USB0 BASEADDR
+      0xE0102000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_HIGHADDR
+      PCW USB0 HIGHADDR
+      0xE0102fff
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_BASEADDR
+      PCW USB1 BASEADDR
+      0xE0103000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_HIGHADDR
+      PCW USB1 HIGHADDR
+      0xE0103fff
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_BASEADDR
+      PCW TTC0 BASEADDR
+      0xE0104000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_HIGHADDR
+      PCW TTC0 HIGHADDR
+      0xE0104fff
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_BASEADDR
+      PCW TTC1 BASEADDR
+      0xE0105000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_HIGHADDR
+      PCW TTC1 HIGHADDR
+      0xE0105fff
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK_CLK0_BUF
+      PCW FCLK CLK0 BUF
+      TRUE
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_FCLK_CLK1_BUF
+      PCW FCLK CLK1 BUF
+      FALSE
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK_CLK2_BUF
+      PCW FCLK CLK2 BUF
+      FALSE
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK_CLK3_BUF
+      PCW FCLK CLK3 BUF
+      FALSE
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_FREQ_MHZ
+      PCW UIPARAM DDR FREQ MHZ
+      533.333333
+    
+    
+      PCW_UIPARAM_DDR_BANK_ADDR_COUNT
+      PCW UIPARAM DDR BANK ADDR COUNT
+      3
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_ROW_ADDR_COUNT
+      PCW UIPARAM DDR ROW ADDR COUNT
+      15
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_COL_ADDR_COUNT
+      PCW UIPARAM DDR COL ADDR COUNT
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_CL
+      PCW UIPARAM DDR CL
+      7
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_CWL
+      PCW UIPARAM DDR CWL
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_T_RCD
+      PCW UIPARAM DDR T RCD
+      7
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_T_RP
+      PCW UIPARAM DDR T RP
+      7
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_T_RC
+      PCW UIPARAM DDR T RC
+      48.75
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_T_RAS_MIN
+      PCW UIPARAM DDR T RAS MIN
+      35.0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_T_FAW
+      PCW UIPARAM DDR T FAW
+      40.0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_AL
+      PCW UIPARAM DDR AL
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0
+      PCW UIPARAM DDR DQS TO CLK DELAY 0
+      0.0
+    
+    
+      PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1
+      PCW UIPARAM DDR DQS TO CLK DELAY 1
+      0.0
+    
+    
+      PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2
+      PCW UIPARAM DDR DQS TO CLK DELAY 2
+      0.0
+    
+    
+      PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3
+      PCW UIPARAM DDR DQS TO CLK DELAY 3
+      0.0
+    
+    
+      PCW_UIPARAM_DDR_BOARD_DELAY0
+      PCW UIPARAM DDR BOARD DELAY0
+      0.25
+    
+    
+      PCW_UIPARAM_DDR_BOARD_DELAY1
+      PCW UIPARAM DDR BOARD DELAY1
+      0.25
+    
+    
+      PCW_UIPARAM_DDR_BOARD_DELAY2
+      PCW UIPARAM DDR BOARD DELAY2
+      0.25
+    
+    
+      PCW_UIPARAM_DDR_BOARD_DELAY3
+      PCW UIPARAM DDR BOARD DELAY3
+      0.25
+    
+    
+      PCW_UIPARAM_DDR_DQS_0_LENGTH_MM
+      PCW UIPARAM DDR DQS 0 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQS_1_LENGTH_MM
+      PCW UIPARAM DDR DQS 1 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQS_2_LENGTH_MM
+      PCW UIPARAM DDR DQS 2 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQS_3_LENGTH_MM
+      PCW UIPARAM DDR DQS 3 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQ_0_LENGTH_MM
+      PCW UIPARAM DDR DQ 0 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQ_1_LENGTH_MM
+      PCW UIPARAM DDR DQ 1 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQ_2_LENGTH_MM
+      PCW UIPARAM DDR DQ 2 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQ_3_LENGTH_MM
+      PCW UIPARAM DDR DQ 3 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM
+      PCW UIPARAM DDR CLOCK 0 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM
+      PCW UIPARAM DDR CLOCK 1 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM
+      PCW UIPARAM DDR CLOCK 2 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM
+      PCW UIPARAM DDR CLOCK 3 LENGTH MM
+      0
+    
+    
+      PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQS 0 PACKAGE LENGTH
+      68.4725
+    
+    
+      PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQS 1 PACKAGE LENGTH
+      71.086
+    
+    
+      PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQS 2 PACKAGE LENGTH
+      66.794
+    
+    
+      PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQS 3 PACKAGE LENGTH
+      108.7385
+    
+    
+      PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQ 0 PACKAGE LENGTH
+      64.1705
+    
+    
+      PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQ 1 PACKAGE LENGTH
+      63.686
+    
+    
+      PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQ 2 PACKAGE LENGTH
+      68.46
+    
+    
+      PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH
+      PCW UIPARAM DDR DQ 3 PACKAGE LENGTH
+      105.4895
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH
+      PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH
+      61.0905
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH
+      PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH
+      61.0905
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH
+      PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH
+      61.0905
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH
+      PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH
+      61.0905
+    
+    
+      PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQS 0 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQS 1 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQS 2 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQS 3 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQ 0 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQ 1 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQ 2 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY
+      PCW UIPARAM DDR DQ 3 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY
+      PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY
+      PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY
+      PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY
+      160
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY
+      PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY
+      160
+    
+    
+      PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0
+      PCW PACKAGE DDR DQS TO CLK DELAY 0
+      -0.007
+    
+    
+      PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1
+      PCW PACKAGE DDR DQS TO CLK DELAY 1
+      -0.010
+    
+    
+      PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2
+      PCW PACKAGE DDR DQS TO CLK DELAY 2
+      -0.006
+    
+    
+      PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3
+      PCW PACKAGE DDR DQS TO CLK DELAY 3
+      -0.048
+    
+    
+      PCW_PACKAGE_DDR_BOARD_DELAY0
+      PCW PACKAGE DDR BOARD DELAY0
+      0.063
+    
+    
+      PCW_PACKAGE_DDR_BOARD_DELAY1
+      PCW PACKAGE DDR BOARD DELAY1
+      0.062
+    
+    
+      PCW_PACKAGE_DDR_BOARD_DELAY2
+      PCW PACKAGE DDR BOARD DELAY2
+      0.065
+    
+    
+      PCW_PACKAGE_DDR_BOARD_DELAY3
+      PCW PACKAGE DDR BOARD DELAY3
+      0.083
+    
+    
+      PCW_CPU_CPU_6X4X_MAX_RANGE
+      PCW CPU CPU 6X4X MAX RANGE
+      667
+    
+    
+      PCW_CRYSTAL_PERIPHERAL_FREQMHZ
+      PCW CRYSTAL PERIPHERAL FREQMHZ
+      33.333333
+    
+    
+      PCW_APU_PERIPHERAL_FREQMHZ
+      PCW APU PERIPHERAL FREQMHZ
+      666.666666
+    
+    
+      PCW_DCI_PERIPHERAL_FREQMHZ
+      PCW DCI PERIPHERAL FREQMHZ
+      10.159
+    
+    
+      PCW_QSPI_PERIPHERAL_FREQMHZ
+      PCW QSPI PERIPHERAL FREQMHZ
+      200
+    
+    
+      PCW_SMC_PERIPHERAL_FREQMHZ
+      PCW SMC PERIPHERAL FREQMHZ
+      100
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_PERIPHERAL_FREQMHZ
+      PCW USB0 PERIPHERAL FREQMHZ
+      60
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_PERIPHERAL_FREQMHZ
+      PCW USB1 PERIPHERAL FREQMHZ
+      60
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SDIO_PERIPHERAL_FREQMHZ
+      PCW SDIO PERIPHERAL FREQMHZ
+      100
+    
+    
+      PCW_UART_PERIPHERAL_FREQMHZ
+      PCW UART PERIPHERAL FREQMHZ
+      100
+    
+    
+      PCW_SPI_PERIPHERAL_FREQMHZ
+      PCW SPI PERIPHERAL FREQMHZ
+      166.666666
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN_PERIPHERAL_FREQMHZ
+      PCW CAN PERIPHERAL FREQMHZ
+      100
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_PERIPHERAL_FREQMHZ
+      PCW CAN0 PERIPHERAL FREQMHZ
+      -1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_PERIPHERAL_FREQMHZ
+      PCW CAN1 PERIPHERAL FREQMHZ
+      -1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C_PERIPHERAL_FREQMHZ
+      PCW I2C PERIPHERAL FREQMHZ
+      25
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_WDT_PERIPHERAL_FREQMHZ
+      PCW WDT PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC_PERIPHERAL_FREQMHZ
+      PCW TTC PERIPHERAL FREQMHZ
+      50
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ
+      PCW TTC0 CLK0 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ
+      PCW TTC0 CLK1 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ
+      PCW TTC0 CLK2 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ
+      PCW TTC1 CLK0 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ
+      PCW TTC1 CLK1 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ
+      PCW TTC1 CLK2 PERIPHERAL FREQMHZ
+      133.333333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_PCAP_PERIPHERAL_FREQMHZ
+      PCW PCAP PERIPHERAL FREQMHZ
+      200
+    
+    
+      PCW_TPIU_PERIPHERAL_FREQMHZ
+      PCW TPIU PERIPHERAL FREQMHZ
+      200
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FPGA0_PERIPHERAL_FREQMHZ
+      PCW FPGA0 PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_FPGA1_PERIPHERAL_FREQMHZ
+      PCW FPGA1 PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_FPGA2_PERIPHERAL_FREQMHZ
+      PCW FPGA2 PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_FPGA3_PERIPHERAL_FREQMHZ
+      PCW FPGA3 PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_ACT_APU_PERIPHERAL_FREQMHZ
+      PCW ACT APU PERIPHERAL FREQMHZ
+      666.666687
+    
+    
+      PCW_UIPARAM_ACT_DDR_FREQ_MHZ
+      PCW UIPARAM ACT DDR FREQ MHZ
+      533.333374
+    
+    
+      PCW_ACT_DCI_PERIPHERAL_FREQMHZ
+      PCW ACT DCI PERIPHERAL FREQMHZ
+      10.158730
+    
+    
+      PCW_ACT_QSPI_PERIPHERAL_FREQMHZ
+      PCW ACT QSPI PERIPHERAL FREQMHZ
+      200.000000
+    
+    
+      PCW_ACT_SMC_PERIPHERAL_FREQMHZ
+      PCW ACT SMC PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_ENET0_PERIPHERAL_FREQMHZ
+      PCW ACT ENET0 PERIPHERAL FREQMHZ
+      125.000000
+    
+    
+      PCW_ACT_ENET1_PERIPHERAL_FREQMHZ
+      PCW ACT ENET1 PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_USB0_PERIPHERAL_FREQMHZ
+      PCW ACT USB0 PERIPHERAL FREQMHZ
+      60
+    
+    
+      PCW_ACT_USB1_PERIPHERAL_FREQMHZ
+      PCW ACT USB1 PERIPHERAL FREQMHZ
+      60
+    
+    
+      PCW_ACT_SDIO_PERIPHERAL_FREQMHZ
+      PCW ACT SDIO PERIPHERAL FREQMHZ
+      100.000000
+    
+    
+      PCW_ACT_UART_PERIPHERAL_FREQMHZ
+      PCW ACT UART PERIPHERAL FREQMHZ
+      100.000000
+    
+    
+      PCW_ACT_SPI_PERIPHERAL_FREQMHZ
+      PCW ACT SPI PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_CAN_PERIPHERAL_FREQMHZ
+      PCW ACT CAN PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_CAN0_PERIPHERAL_FREQMHZ
+      PCW ACT CAN0 PERIPHERAL FREQMHZ
+      23.8095
+    
+    
+      PCW_ACT_CAN1_PERIPHERAL_FREQMHZ
+      PCW ACT CAN0 PERIPHERAL FREQMHZ
+      23.8095
+    
+    
+      PCW_ACT_I2C_PERIPHERAL_FREQMHZ
+      PCW ACT I2C PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_ACT_WDT_PERIPHERAL_FREQMHZ
+      PCW ACT WDT PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC_PERIPHERAL_FREQMHZ
+      PCW ACT TTC PERIPHERAL FREQMHZ
+      50
+    
+    
+      PCW_ACT_PCAP_PERIPHERAL_FREQMHZ
+      PCW ACT PCAP PERIPHERAL FREQMHZ
+      200.000000
+    
+    
+      PCW_ACT_TPIU_PERIPHERAL_FREQMHZ
+      PCW ACT TPIU PERIPHERAL FREQMHZ
+      200.000000
+    
+    
+      PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ
+      PCW ACT FPGA0 PERIPHERAL FREQMHZ
+      50.000000
+    
+    
+      PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ
+      PCW ACT FPGA1 PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ
+      PCW ACT FPGA2 PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ
+      PCW ACT FPGA3 PERIPHERAL FREQMHZ
+      10.000000
+    
+    
+      PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ
+      PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ
+      PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ
+      PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ
+      PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ
+      PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ
+      PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ
+      111.111115
+    
+    
+      PCW_CLK0_FREQ
+      PCW CLK0 FREQ
+      50000000
+    
+    
+      PCW_CLK1_FREQ
+      PCW CLK1 FREQ
+      10000000
+    
+    
+      PCW_CLK2_FREQ
+      PCW CLK2 FREQ
+      10000000
+    
+    
+      PCW_CLK3_FREQ
+      PCW CLK3 FREQ
+      10000000
+    
+    
+      PCW_OVERRIDE_BASIC_CLOCK
+      PCW OVERRIDE FREQ
+      0
+    
+    
+      PCW_CPU_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      2
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      2
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SMC_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_QSPI_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      5
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SDIO_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK0_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      5
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK1_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK2_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK3_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK0_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      4
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK1_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK2_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FCLK3_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET0_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      8
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET0_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TPIU_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DCI_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      15
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DCI_PERIPHERAL_DIVISOR1
+      CLKPARAM
+      7
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_PCAP_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      5
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_WDT_PERIPHERAL_DIVISOR0
+      CLKPARAM
+      1
+    
+    
+      PCW_ARMPLL_CTRL_FBDIV
+      CLKPARAM
+      40
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_IOPLL_CTRL_FBDIV
+      CLKPARAM
+      30
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDRPLL_CTRL_FBDIV
+      CLKPARAM
+      32
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CPU_CPU_PLL_FREQMHZ
+      CLKPARAM
+      1333.333
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_IO_IO_PLL_FREQMHZ
+      CLKPARAM
+      1000.000
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_DDR_PLL_FREQMHZ
+      CLKPARAM
+      1066.667
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SMC_PERIPHERAL_VALID
+      PCW SMC PERIPHERAL VALID
+      0
+    
+    
+      PCW_SDIO_PERIPHERAL_VALID
+      PCW SDIO PERIPHERAL VALID
+      1
+    
+    
+      PCW_SPI_PERIPHERAL_VALID
+      PCW SPI PERIPHERAL VALID
+      0
+    
+    
+      PCW_CAN_PERIPHERAL_VALID
+      PCW CAN PERIPHERAL VALID
+      0
+    
+    
+      PCW_UART_PERIPHERAL_VALID
+      PCW UART PERIPHERAL VALID
+      1
+    
+    
+      PCW_EN_EMIO_CAN0
+      PCW EN EMIO CAN0
+      0
+    
+    
+      PCW_EN_EMIO_CAN1
+      PCW EN EMIO CAN1
+      0
+    
+    
+      PCW_EN_EMIO_ENET0
+      PCW EN EMIO ENET0
+      0
+    
+    
+      PCW_EN_EMIO_ENET1
+      PCW EN EMIO ENET1
+      0
+    
+    
+      PCW_EN_PTP_ENET0
+      PCW EN PTP ENET0
+      0
+    
+    
+      PCW_EN_PTP_ENET1
+      PCW EN PTP ENET1
+      0
+    
+    
+      PCW_EN_EMIO_GPIO
+      PCW EN EMIO GPIO
+      0
+    
+    
+      PCW_EN_EMIO_I2C0
+      PCW EN EMIO I2C0
+      0
+    
+    
+      PCW_EN_EMIO_I2C1
+      PCW EN EMIO I2C1
+      0
+    
+    
+      PCW_EN_EMIO_PJTAG
+      PCW EN EMIO PJTAG
+      0
+    
+    
+      PCW_EN_EMIO_SDIO0
+      PCW EN EMIO SDIO0
+      0
+    
+    
+      PCW_EN_EMIO_CD_SDIO0
+      PCW EN EMIO CD SDIO0
+      0
+    
+    
+      PCW_EN_EMIO_WP_SDIO0
+      PCW EN EMIO WP SDIO0
+      0
+    
+    
+      PCW_EN_EMIO_SDIO1
+      PCW EN EMIO SDIO1
+      0
+    
+    
+      PCW_EN_EMIO_CD_SDIO1
+      PCW EN EMIO CD SDIO1
+      0
+    
+    
+      PCW_EN_EMIO_WP_SDIO1
+      PCW EN EMIO WP SDIO1
+      0
+    
+    
+      PCW_EN_EMIO_SPI0
+      PCW EN EMIO SPI0
+      0
+    
+    
+      PCW_EN_EMIO_SPI1
+      PCW EN EMIO SPI1
+      0
+    
+    
+      PCW_EN_EMIO_UART0
+      PCW EN EMIO UART0
+      0
+    
+    
+      PCW_EN_EMIO_UART1
+      PCW EN EMIO UART1
+      0
+    
+    
+      PCW_EN_EMIO_MODEM_UART0
+      PCW EN EMIO MODEM UART0
+      0
+    
+    
+      PCW_EN_EMIO_MODEM_UART1
+      PCW EN EMIO MODEM UART1
+      0
+    
+    
+      PCW_EN_EMIO_TTC0
+      PCW EN EMIO TTC0
+      0
+    
+    
+      PCW_EN_EMIO_TTC1
+      PCW EN EMIO TTC1
+      0
+    
+    
+      PCW_EN_EMIO_WDT
+      PCW EN EMIO WDT
+      0
+    
+    
+      PCW_EN_EMIO_TRACE
+      PCW EN EMIO TRACE
+      0
+    
+    
+      PCW_USE_AXI_NONSECURE
+      PCW USE AXI NON SECURE
+      0
+    
+    
+      PCW_USE_M_AXI_GP0
+      PCW USE M AXI GP0
+      1
+    
+    
+      PCW_USE_M_AXI_GP1
+      PCW USE M AXI GP1
+      0
+    
+    
+      PCW_USE_S_AXI_GP0
+      PCW USE S AXI GP0
+      0
+    
+    
+      PCW_USE_S_AXI_GP1
+      PCW USE S AXI GP1
+      0
+    
+    
+      PCW_USE_S_AXI_ACP
+      PCW USE S AXI ACP
+      0
+    
+    
+      PCW_USE_S_AXI_HP0
+      PCW USE S AXI HP0
+      0
+    
+    
+      PCW_USE_S_AXI_HP1
+      PCW USE S AXI HP1
+      0
+    
+    
+      PCW_USE_S_AXI_HP2
+      PCW USE S AXI HP2
+      0
+    
+    
+      PCW_USE_S_AXI_HP3
+      PCW USE S AXI HP3
+      0
+    
+    
+      PCW_M_AXI_GP0_FREQMHZ
+      PCW M AXI GP0 FREQMHZ
+      50
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP1_FREQMHZ
+      PCW M AXI GP1 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_GP0_FREQMHZ
+      PCW S AXI GP0 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_GP1_FREQMHZ
+      PCW S AXI GP1 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_ACP_FREQMHZ
+      PCW S AXI ACP FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP0_FREQMHZ
+      PCW S AXI HP0 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP1_FREQMHZ
+      PCW S AXI HP1 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP2_FREQMHZ
+      PCW S AXI HP2 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP3_FREQMHZ
+      PCW S AXI HP3 FREQMHZ
+      10
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USE_DMA0
+      PCW USE DMA0
+      0
+    
+    
+      PCW_USE_DMA1
+      PCW USE DMA1
+      0
+    
+    
+      PCW_USE_DMA2
+      PCW USE DMA2
+      0
+    
+    
+      PCW_USE_DMA3
+      PCW USE DMA3
+      0
+    
+    
+      PCW_USE_TRACE
+      PCW USE TRACE
+      Enable FTM Trace interface used to capture data from PL to PS debug system
+      0
+    
+    
+      PCW_TRACE_PIPELINE_WIDTH
+      PCW TRACE PIPELINE WIDTH
+      8
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_INCLUDE_TRACE_BUFFER
+      PCW INCLUDE TRACE BUFFER
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_BUFFER_FIFO_SIZE
+      PCW TRACE BUFFER FIFO SIZE
+      128
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USE_TRACE_DATA_EDGE_DETECTOR
+      PCW USE TRACE DATA EDGE DETECTOR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_BUFFER_CLOCK_DELAY
+      PCW TRACE BUFFER CLOCK DELAY
+      12
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USE_CROSS_TRIGGER
+      PCW USE CROSS TRIGGER
+      0
+    
+    
+      PCW_FTM_CTI_IN0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_IN1
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_IN2
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_IN3
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_OUT0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_OUT1
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_OUT2
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FTM_CTI_OUT3
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USE_DEBUG
+      PCW USE DEBUG
+      0
+    
+    
+      PCW_USE_CR_FABRIC
+      PCW USE CR FABRIC
+      1
+    
+    
+      PCW_USE_AXI_FABRIC_IDLE
+      PCW USE AXI FABRIC IDLE
+      Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL
+      0
+    
+    
+      PCW_USE_DDR_BYPASS
+      PCW USE DDR BYPASS
+      Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller
+      0
+    
+    
+      PCW_USE_FABRIC_INTERRUPT
+      PCW USE FABRIC INTERRUPT
+      0
+    
+    
+      PCW_USE_PROC_EVENT_BUS
+      PCW USE PROC EVENT BUS
+      0
+    
+    
+      PCW_USE_EXPANDED_IOP
+      PCW USE EXPANDED IOP
+      0
+    
+    
+      PCW_USE_HIGH_OCM
+      PCW USE HIGH OCM
+      0
+    
+    
+      PCW_USE_PS_SLCR_REGISTERS
+      PCW USE PS SLCR REGISTERS
+      0
+    
+    
+      PCW_USE_EXPANDED_PS_SLCR_REGISTERS
+      PCW USE EXPANDED PS SLCR REGISTERS
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USE_CORESIGHT
+      PCW USE CORESIGHT
+      0
+    
+    
+      PCW_EN_EMIO_SRAM_INT
+      PCW EN EMIO SRAM INT
+      0
+    
+    
+      PCW_GPIO_EMIO_GPIO_WIDTH
+      PCW EMIO GPIO WIDTH
+      64
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_GP0_NUM_WRITE_THREADS
+      GP0 NUM WRITE THREADS
+      4
+    
+    
+      PCW_GP0_NUM_READ_THREADS
+      GP0 NUM READ THREADS
+      4
+    
+    
+      PCW_GP1_NUM_WRITE_THREADS
+      GP1 NUM WRITE THREADS
+      4
+    
+    
+      PCW_GP1_NUM_READ_THREADS
+      GP1 NUM READ THREADS
+      4
+    
+    
+      PCW_UART0_BAUD_RATE
+      PCW UART0 BAUD RATE
+      Configure baud rate to determine UART0 operating frequency
+      115200
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART1_BAUD_RATE
+      PCW UART1 BAUD RATE
+      Configure baud rate to determine UART1 operating frequency
+      115200
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_4K_TIMER
+      PCW EN 4K TIMER
+      0
+    
+    
+      PCW_M_AXI_GP0_ID_WIDTH
+      PCW M AXI GP0 ID WIDTH
+      12
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP0_ENABLE_STATIC_REMAP
+      PCW M AXI GP0 ENABLE STATIC REMAP
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP0_SUPPORT_NARROW_BURST
+      PCW M AXI GP0 SUPPORT NARROW BURST
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP0_THREAD_ID_WIDTH
+      PCW M AXI GP0 THREAD ID WIDTH
+      12
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP1_ID_WIDTH
+      PCW M AXI GP1 ID WIDTH
+      12
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP1_ENABLE_STATIC_REMAP
+      PCW M AXI GP1 ENABLE STATIC REMAP
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP1_SUPPORT_NARROW_BURST
+      PCW M AXI GP1 SUPPORT NARROW BURST
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_M_AXI_GP1_THREAD_ID_WIDTH
+      PCW M AXI GP1 THREAD ID WIDTH
+      12
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_GP0_ID_WIDTH
+      PCW S AXI GP0 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_GP1_ID_WIDTH
+      PCW S AXI GP1 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_ACP_ID_WIDTH
+      PCW S AXI ACP ID WIDTH
+      3
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_INCLUDE_ACP_TRANS_CHECK
+      PCW INCLUDE ACP TRANS CHECK
+      0
+    
+    
+      PCW_USE_DEFAULT_ACP_USER_VAL
+      PCW USE DEFAULT ACP USER VAL
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_ACP_ARUSER_VAL
+      PCW S AXI ACP ARUSER VAL
+      31
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_ACP_AWUSER_VAL
+      PCW S AXI ACP AWUSER VAL
+      31
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP0_ID_WIDTH
+      PCW S AXI HP0 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP0_DATA_WIDTH
+      PCW S AXI HP0 DATA WIDTH
+      64
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP1_ID_WIDTH
+      PCW S AXI HP1 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP1_DATA_WIDTH
+      PCW S AXI HP1 DATA WIDTH
+      64
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP2_ID_WIDTH
+      PCW S AXI HP2 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP2_DATA_WIDTH
+      PCW S AXI HP2 DATA WIDTH
+      64
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP3_ID_WIDTH
+      PCW S AXI HP3 ID WIDTH
+      6
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_S_AXI_HP3_DATA_WIDTH
+      PCW S AXI HP3 DATA WIDTH
+      64
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NUM_F2P_INTR_INPUTS
+      PCW NUM F2P INTR INPUTS
+      2
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_DDR
+      PCW EN DDR
+      1
+    
+    
+      PCW_EN_SMC
+      PCW EN SMC
+      0
+    
+    
+      PCW_EN_QSPI
+      PCW EN QSPI
+      1
+    
+    
+      PCW_EN_CAN0
+      PCW EN CAN0
+      0
+    
+    
+      PCW_EN_CAN1
+      PCW EN CAN1
+      0
+    
+    
+      PCW_EN_ENET0
+      PCW EN ENET0
+      1
+    
+    
+      PCW_EN_ENET1
+      PCW EN ENET1
+      0
+    
+    
+      PCW_EN_GPIO
+      PCW EN GPIO
+      1
+    
+    
+      PCW_EN_I2C0
+      PCW EN I2C0
+      0
+    
+    
+      PCW_EN_I2C1
+      PCW EN I2C1
+      0
+    
+    
+      PCW_EN_PJTAG
+      PCW EN PJTAG
+      0
+    
+    
+      PCW_EN_SDIO0
+      PCW EN SDIO0
+      1
+    
+    
+      PCW_EN_SDIO1
+      PCW EN SDIO1
+      0
+    
+    
+      PCW_EN_SPI0
+      PCW EN SPI0
+      0
+    
+    
+      PCW_EN_SPI1
+      PCW EN SPI1
+      0
+    
+    
+      PCW_EN_UART0
+      PCW EN UART0
+      0
+    
+    
+      PCW_EN_UART1
+      PCW EN UART1
+      1
+    
+    
+      PCW_EN_MODEM_UART0
+      PCW EN MODEM UART0
+      0
+    
+    
+      PCW_EN_MODEM_UART1
+      PCW EN MODEM UART1
+      0
+    
+    
+      PCW_EN_TTC0
+      PCW EN TTC0
+      0
+    
+    
+      PCW_EN_TTC1
+      PCW EN TTC1
+      0
+    
+    
+      PCW_EN_WDT
+      PCW EN WDT
+      0
+    
+    
+      PCW_EN_TRACE
+      PCW EN TRACE
+      0
+    
+    
+      PCW_EN_USB0
+      PCW EN USB0
+      0
+    
+    
+      PCW_EN_USB1
+      PCW EN USB1
+      0
+    
+    
+      PCW_DQ_WIDTH
+      PCW DQ WIDTH
+      32
+    
+    
+      PCW_DQS_WIDTH
+      PCW DQS WIDTH
+      4
+    
+    
+      PCW_DM_WIDTH
+      PCW DM WIDTH
+      4
+    
+    
+      PCW_MIO_PRIMITIVE
+      PCW MIO PRIMITIVE
+      54
+    
+    
+      PCW_EN_CLK0_PORT
+      PCW EN CLK0 PORT
+      1
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLK1_PORT
+      PCW EN CLK1 PORT
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLK2_PORT
+      PCW EN CLK2 PORT
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLK3_PORT
+      PCW EN CLK3 PORT
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_RST0_PORT
+      PCW EN RST0 PORT
+      Enables general purpose reset signal 0 for PL logic
+      1
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_RST1_PORT
+      PCW EN RST1 PORT
+      Enables general purpose reset signal 1 for PL logic
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_RST2_PORT
+      PCW EN RST2 PORT
+      Enables general purpose reset signal 2 for PL logic
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_RST3_PORT
+      PCW EN RST3 PORT
+      Enables general purpose reset signal 3 for PL logic
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLKTRIG0_PORT
+      PCW EN CLKTRIG0 PORT
+      Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLKTRIG1_PORT
+      PCW EN CLKTRIG1 PORT
+      Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLKTRIG2_PORT
+      PCW EN CLKTRIG2 PORT
+      Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_EN_CLKTRIG3_PORT
+      PCW EN CLKTRIG3 PORT
+      Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses
+      0
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC_ABORT_INTR
+      PCW P2F DMAC ABORT INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC0_INTR
+      PCW P2F DMAC0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC1_INTR
+      PCW P2F DMAC1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC2_INTR
+      PCW P2F DMAC2 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC3_INTR
+      PCW P2F DMAC3 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC4_INTR
+      PCW P2F DMAC4 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC5_INTR
+      PCW P2F DMAC5 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC6_INTR
+      PCW P2F DMAC6 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_DMAC7_INTR
+      PCW P2F DMAC7 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_SMC_INTR
+      PCW P2F SMC INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_QSPI_INTR
+      PCW P2F QSPI INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_CTI_INTR
+      PCW P2F CTI INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_GPIO_INTR
+      PCW P2F GPIO INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_USB0_INTR
+      PCW P2F USB0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_ENET0_INTR
+      PCW P2F ENET0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_SDIO0_INTR
+      PCW P2F SDIO0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_I2C0_INTR
+      PCW P2F I2C0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_SPI0_INTR
+      PCW P2F SPI0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_UART0_INTR
+      PCW P2F UART0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_CAN0_INTR
+      PCW P2F CAN0 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_USB1_INTR
+      PCW P2F USB1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_ENET1_INTR
+      PCW P2F ENET1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_SDIO1_INTR
+      PCW P2F SDIO1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_I2C1_INTR
+      PCW P2F I2C1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_SPI1_INTR
+      PCW P2F SPI1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_UART1_INTR
+      PCW P2F UART1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_P2F_CAN1_INTR
+      PCW P2F CAN1 INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_IRQ_F2P_INTR
+      PCW IRQ F2P INTR
+      1
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_IRQ_F2P_MODE
+      PCW IRQ F2P MODE
+      DIRECT
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_CORE0_FIQ_INTR
+      PCW CORE0 FIQ INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CORE0_IRQ_INTR
+      PCW CORE0 IRQ INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CORE1_FIQ_INTR
+      PCW CORE1 FIQ INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CORE1_IRQ_INTR
+      PCW CORE1 IRQ INTR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_VALUE_SILVERSION
+      PCW VALUE SILVERSION
+      3
+    
+    
+      PCW_GP0_EN_MODIFIABLE_TXN
+      PCW GP0 EN MODIFIABLE TXN
+      0
+    
+    
+      PCW_GP1_EN_MODIFIABLE_TXN
+      PCW GP1 EN MODIFIABLE TXN
+      0
+    
+    
+      PCW_IMPORT_BOARD_PRESET
+      PCW IMPORT BOARD PRESET
+      None
+    
+    
+      PCW_PERIPHERAL_BOARD_PRESET
+      PCW PERIPHERAL BOARD PRESET
+      None
+    
+    
+      PCW_PRESET_BANK0_VOLTAGE
+      PCW PRESET BANK0 VOLTAGE
+      LVCMOS 3.3V
+    
+    
+      PCW_PRESET_BANK1_VOLTAGE
+      PCW PRESET BANK1 VOLTAGE
+      LVCMOS 1.8V
+    
+    
+      PCW_UIPARAM_DDR_ENABLE
+      PCW UIPARAM DDR ENABLE
+      1
+    
+    
+      PCW_UIPARAM_DDR_ADV_ENABLE
+      PCW UIPARAM DDR ADV ENABLE
+      0
+    
+    
+      PCW_UIPARAM_DDR_MEMORY_TYPE
+      PCW UIPARAM DDR MEMORY TYPE
+      DDR 3
+    
+    
+      PCW_UIPARAM_DDR_ECC
+      PCW UIPARAM DDR ECC
+      Disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_BUS_WIDTH
+      PCW UIPARAM DDR BUS WIDTH
+      32 Bit
+    
+    
+      PCW_UIPARAM_DDR_BL
+      PCW UIPARAM DDR BL
+      8
+    
+    
+      PCW_UIPARAM_DDR_HIGH_TEMP
+      PCW UIPARAM DDR HIGH TEMP
+      Normal (0-85)
+    
+    
+      PCW_UIPARAM_DDR_PARTNO
+      PCW UIPARAM DDR PARTNO
+      MT41K256M16 RE-125
+    
+    
+      PCW_UIPARAM_DDR_DRAM_WIDTH
+      PCW UIPARAM DDR DRAM WIDTH
+      16 Bits
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_DEVICE_CAPACITY
+      PCW UIPARAM DDR DEVICE CAPACITY
+      4096 MBits
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_SPEED_BIN
+      PCW UIPARAM DDR SPEED BIN
+      DDR3_1066F
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL
+      PCW UIPARAM DDR TRAIN WRITE LEVEL
+      1
+    
+    
+      PCW_UIPARAM_DDR_TRAIN_READ_GATE
+      PCW UIPARAM DDR TRAIN READ GATE
+      1
+    
+    
+      PCW_UIPARAM_DDR_TRAIN_DATA_EYE
+      PCW UIPARAM DDR TRAIN DATA EYE
+      1
+    
+    
+      PCW_UIPARAM_DDR_CLOCK_STOP_EN
+      PCW UIPARAM DDR CLOCK STOP EN
+      0
+    
+    
+      PCW_UIPARAM_DDR_USE_INTERNAL_VREF
+      PCW UIPARAM DDR USE INTERNAL VREF
+      0
+    
+    
+      PCW_DDR_PRIORITY_WRITEPORT_0
+      PCW DDR PRIORITY WRITEPORT 0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_WRITEPORT_1
+      PCW DDR PRIORITY WRITEPORT 0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_WRITEPORT_2
+      PCW DDR PRIORITY WRITEPORT 0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_WRITEPORT_3
+      PCW DDR PRIORITY WRITEPORT 0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_READPORT_0
+      PCW DDR PRIORITY READPORT 0
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_READPORT_1
+      PCW DDR PRIORITY READPORT 1
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_READPORT_2
+      PCW DDR PRIORITY READPORT 2
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PRIORITY_READPORT_3
+      PCW DDR PRIORITY READPORT 3
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PORT0_HPR_ENABLE
+      PCW DDR PORT0 ENABLE HPR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PORT1_HPR_ENABLE
+      PCW DDR PORT1 ENABLE HPR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PORT2_HPR_ENABLE
+      PCW DDR PORT2 ENABLE HPR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_PORT3_HPR_ENABLE
+      PCW DDR PORT3 ENABLE HPR
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_HPRLPR_QUEUE_PARTITION
+      PCW DDR HPRLPR QUEUE PARTITION
+      HPR(0)/LPR(32)
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL
+      PCW DDR LPR TO CRITICAL PRIORITY LEVEL
+      2
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL
+      PCW DDR HPR TO CRITICAL PRIORITY LEVEL
+      15
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL
+      PCW DDR WRITE TO CRITICAL PRIORITY LEVEL
+      2
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NAND_PERIPHERAL_ENABLE
+      PCW NAND PERIPHERAL ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NAND_NAND_IO
+      PCW NAND NAND IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NAND_GRP_D8_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NAND_GRP_D8_IO
+      PCW NAND GRP D8 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_PERIPHERAL_ENABLE
+      PCW NOR PERIPHERAL ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_NOR_IO
+      PCW NOR NOR IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_A25_ENABLE
+      PCW NOR GRP A25 IO
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_A25_IO
+      PCW NOR GRP CS0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_CS0_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_CS0_IO
+      PCW NOR GRP CS1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_CS0_ENABLE
+      PCW NOR GRP SRAM CS0 ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_CS0_IO
+      PCW NOR GRP SRAM CS1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_CS1_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_CS1_IO
+      PCW NOR GRP SRAM CS0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_CS1_ENABLE
+      PCW NOR GRP SRAM CS1 ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_CS1_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_INT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_GRP_SRAM_INT_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_QSPI_PERIPHERAL_ENABLE
+      PCW QSPI PERIPHERAL ENABLE
+      1
+    
+    
+      PCW_QSPI_QSPI_IO
+      PCW QSPI QSPI IO
+      MIO 1 .. 6
+    
+    
+      PCW_QSPI_GRP_SINGLE_SS_ENABLE
+      PCW QSPI GRP SINGLE SS ENABLE
+      1
+    
+    
+      PCW_QSPI_GRP_SINGLE_SS_IO
+      PCW QSPI GRP SINGLE SS IO
+      MIO 1 .. 6
+    
+    
+      PCW_QSPI_GRP_SS1_ENABLE
+      0
+    
+    
+      PCW_QSPI_GRP_SS1_IO
+      PCW QSPI GRP SS1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SINGLE_QSPI_DATA_MODE
+      Single QSPI Data Mode
+      x4
+    
+    
+      PCW_DUAL_STACK_QSPI_DATA_MODE
+      Dual Stack QSPI Data Mode
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_DUAL_PARALLEL_QSPI_DATA_MODE
+      Dual Parallel QSPI Data Mode
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_QSPI_GRP_IO1_ENABLE
+      0
+    
+    
+      PCW_QSPI_GRP_IO1_IO
+      PCW QSPI GRP IO1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_QSPI_GRP_FBCLK_ENABLE
+      1
+    
+    
+      PCW_QSPI_GRP_FBCLK_IO
+      PCW QSPI GRP FBCLK IO
+      MIO 8
+    
+    
+      PCW_QSPI_INTERNAL_HIGHADDRESS
+      PCW QSPI INTERNAL HIGHADDRESS
+      0xFCFFFFFF
+    
+    
+      PCW_ENET0_PERIPHERAL_ENABLE
+      PCW ENET0 PERIPHERAL ENABLE
+      1
+    
+    
+      PCW_ENET0_ENET0_IO
+      PCW ENET0 ENET0 IO
+      MIO 16 .. 27
+    
+    
+      PCW_ENET0_GRP_MDIO_ENABLE
+      1
+    
+    
+      PCW_ENET0_GRP_MDIO_IO
+      PCW ENET0 GRP MDIO IO
+      MIO 52 .. 53
+    
+    
+      PCW_ENET_RESET_ENABLE
+      1
+    
+    
+      PCW_ENET_RESET_SELECT
+      Share reset pin
+    
+    
+      PCW_ENET0_RESET_ENABLE
+      0
+    
+    
+      PCW_ENET0_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_PERIPHERAL_ENABLE
+      PCW ENET1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_ENET1_ENET1_IO
+      PCW ENET1 ENET1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_GRP_MDIO_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_GRP_MDIO_IO
+      PCW ENET1 GRP MDIO IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_RESET_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_ENET1_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD0_PERIPHERAL_ENABLE
+      PCW SD0 PERIPHERAL ENABLE
+      1
+    
+    
+      PCW_SD0_SD0_IO
+      PCW SD0 SD0 IO
+      MIO 40 .. 45
+    
+    
+      PCW_SD0_GRP_CD_ENABLE
+      1
+    
+    
+      PCW_SD0_GRP_CD_IO
+      PCW SD0 GRP CD IO
+      MIO 47
+    
+    
+      PCW_SD0_GRP_WP_ENABLE
+      0
+    
+    
+      PCW_SD0_GRP_WP_IO
+      PCW SD0 GRP WP IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD0_GRP_POW_ENABLE
+      0
+    
+    
+      PCW_SD0_GRP_POW_IO
+      PCW SD0 GRP POW IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_PERIPHERAL_ENABLE
+      PCW SD1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_SD1_SD1_IO
+      PCW SD1 SD1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_CD_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_CD_IO
+      PCW SD1 GRP CD IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_WP_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_WP_IO
+      PCW SD1 GRP WP IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_POW_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SD1_GRP_POW_IO
+      PCW SD1 GRP POW IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART0_PERIPHERAL_ENABLE
+      PCW UART0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_UART0_UART0_IO
+      PCW UART0 UART0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART0_GRP_FULL_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART0_GRP_FULL_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_UART1_PERIPHERAL_ENABLE
+      PCW UART1 PERIPHERAL ENABLE
+      1
+    
+    
+      PCW_UART1_UART1_IO
+      PCW UART1 UART1 IO
+      MIO 48 .. 49
+    
+    
+      PCW_UART1_GRP_FULL_ENABLE
+      0
+    
+    
+      PCW_UART1_GRP_FULL_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_PERIPHERAL_ENABLE
+      PCW SPI0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_SPI0_SPI0_IO
+      PCW SPI0 SPI0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS0_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS0_IO
+      PCW SPI0 GRP SS0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS1_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS1_IO
+      PCW SPI0 GRP SS1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS2_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI0_GRP_SS2_IO
+      PCW SPI0 GRP SS2 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_PERIPHERAL_ENABLE
+      PCW SPI1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_SPI1_SPI1_IO
+      PCW SPI1 SPI1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS0_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS0_IO
+      PCW SPI1 GRP SS0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS1_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS1_IO
+      PCW SPI1 GRP SS1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS2_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_SPI1_GRP_SS2_IO
+      PCW SPI1 GRP SS2 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_PERIPHERAL_ENABLE
+      PCW CAN0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_CAN0_CAN0_IO
+      PCW CAN0 CAN0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_GRP_CLK_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN0_GRP_CLK_IO
+      PCW CAN0 GRP CLK IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_PERIPHERAL_ENABLE
+      PCW CAN1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_CAN1_CAN1_IO
+      PCW CAN1 CAN1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_GRP_CLK_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CAN1_GRP_CLK_IO
+      PCW CAN1 GRP CLK IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_PERIPHERAL_ENABLE
+      PCW TRACE PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_TRACE_TRACE_IO
+      PCW TRACE TRACE IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_2BIT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_2BIT_IO
+      PCW TRACE GRP 2BIT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_4BIT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_4BIT_IO
+      PCW TRACE GRP 4BIT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_8BIT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_8BIT_IO
+      PCW TRACE GRP 8BIT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_16BIT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_16BIT_IO
+      PCW TRACE GRP 16BIT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_32BIT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_GRP_32BIT_IO
+      PCW TRACE GRP 32BIT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TRACE_INTERNAL_WIDTH
+      PCW TRACE INTERNAL WIDTH
+      2
+    
+    
+      PCW_WDT_PERIPHERAL_ENABLE
+      PCW WDT PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_WDT_WDT_IO
+      PCW WDT WDT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC0_PERIPHERAL_ENABLE
+      PCW TTC0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_TTC0_TTC0_IO
+      PCW TTC0 TTC0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_TTC1_PERIPHERAL_ENABLE
+      PCW TTC1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_TTC1_TTC1_IO
+      PCW TTC1 TTC1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_PJTAG_PERIPHERAL_ENABLE
+      PCW PJTAG PERIPHERAL ENABLE 
+      0
+    
+    
+      PCW_PJTAG_PJTAG_IO
+      PCW PJTAG PJTAG IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_PERIPHERAL_ENABLE
+      PCW USB0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_USB0_USB0_IO
+      PCW USB0 USB0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB_RESET_ENABLE
+      1
+    
+    
+      PCW_USB_RESET_SELECT
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_RESET_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB0_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_PERIPHERAL_ENABLE
+      PCW USB1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_USB1_USB1_IO
+      PCW USB1 USB1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_RESET_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_USB1_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C0_PERIPHERAL_ENABLE
+      PCW I2C0 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_I2C0_I2C0_IO
+      PCW I2C0 I2C0 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C0_GRP_INT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C0_GRP_INT_IO
+      PCW I2C0 GRP INT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C0_RESET_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C0_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_PERIPHERAL_ENABLE
+      PCW I2C1 PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_I2C1_I2C1_IO
+      PCW I2C1 I2C1 IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_GRP_INT_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_GRP_INT_IO
+      PCW I2C1 GRP INT IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C_RESET_ENABLE
+      1
+    
+    
+      PCW_I2C_RESET_SELECT
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_RESET_ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_I2C1_RESET_IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_GPIO_PERIPHERAL_ENABLE
+      PCW GPIO PERIPHERAL ENABLE
+      0
+    
+    
+      PCW_GPIO_MIO_GPIO_ENABLE
+      1
+    
+    
+      PCW_GPIO_MIO_GPIO_IO
+      PCW GPIO MIO GPIO IO
+      MIO
+    
+    
+      PCW_GPIO_EMIO_GPIO_ENABLE
+      PCW GPIO EMIO GPIO ENABLE
+      0
+    
+    
+      PCW_GPIO_EMIO_GPIO_IO
+      PCW GPIO EMIO GPIO IO
+      <Select>
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_APU_CLK_RATIO_ENABLE
+      PCW APU CLK RATIO ENABLE
+      6:2:1
+    
+    
+      PCW_ENET0_PERIPHERAL_FREQMHZ
+      PCW ENET0 PERIPHERAL FREQMHZ
+      1000 Mbps
+    
+    
+      PCW_ENET1_PERIPHERAL_FREQMHZ
+      PCW ENET1 PERIPHERAL FREQMHZ
+      1000 Mbps
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_CPU_PERIPHERAL_CLKSRC
+      PCW CPU PERIPHERAL CLKSRC
+      ARM PLL
+    
+    
+      PCW_DDR_PERIPHERAL_CLKSRC
+      PCW DDR PERIPHERAL CLKSRC
+      DDR PLL
+    
+    
+      PCW_SMC_PERIPHERAL_CLKSRC
+      PCW SMC PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_QSPI_PERIPHERAL_CLKSRC
+      PCW QSPI PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_SDIO_PERIPHERAL_CLKSRC
+      PCW SDIO PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_UART_PERIPHERAL_CLKSRC
+      PCW UART PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_SPI_PERIPHERAL_CLKSRC
+      PCW SPI PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_CAN_PERIPHERAL_CLKSRC
+      PCW CAN PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_FCLK0_PERIPHERAL_CLKSRC
+      PCW FCLK0 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_FCLK1_PERIPHERAL_CLKSRC
+      PCW FCLK1 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_FCLK2_PERIPHERAL_CLKSRC
+      PCW FCLK2 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_FCLK3_PERIPHERAL_CLKSRC
+      PCW FCLK3 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_ENET0_PERIPHERAL_CLKSRC
+      PCW ENET0 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_ENET1_PERIPHERAL_CLKSRC
+      PCW ENET1 PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_CAN0_PERIPHERAL_CLKSRC
+      PCW CAN0 PERIPHERAL CLKSRC
+      External
+    
+    
+      PCW_CAN1_PERIPHERAL_CLKSRC
+      PCW CAN1 PERIPHERAL CLKSRC
+      External
+    
+    
+      PCW_TPIU_PERIPHERAL_CLKSRC
+      PCW TPIU PERIPHERAL CLKSRC
+      External
+    
+    
+      PCW_TTC0_CLK0_PERIPHERAL_CLKSRC
+      PCW TTC0 CLK0 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_TTC0_CLK1_PERIPHERAL_CLKSRC
+      PCW TTC0 CLK1 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_TTC0_CLK2_PERIPHERAL_CLKSRC
+      PCW TTC0 CLK2 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_TTC1_CLK0_PERIPHERAL_CLKSRC
+      PCW TTC1 CLK0 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_TTC1_CLK1_PERIPHERAL_CLKSRC
+      PCW TTC1 CLK1 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_TTC1_CLK2_PERIPHERAL_CLKSRC
+      PCW TTC1 CLK2 PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_WDT_PERIPHERAL_CLKSRC
+      PCW WDT PERIPHERAL CLKSRC
+      CPU_1X
+    
+    
+      PCW_DCI_PERIPHERAL_CLKSRC
+      PCW DCI PERIPHERAL CLKSRC
+      DDR PLL
+    
+    
+      PCW_PCAP_PERIPHERAL_CLKSRC
+      PCW PCAP PERIPHERAL CLKSRC
+      IO PLL
+    
+    
+      PCW_USB_RESET_POLARITY
+      PCW USB RESET POLARITY
+      Active Low
+    
+    
+      PCW_ENET_RESET_POLARITY
+      PCW USB RESET POLARITY
+      Active Low
+    
+    
+      PCW_I2C_RESET_POLARITY
+      PCW USB RESET POLARITY
+      Active Low
+    
+    
+      PCW_MIO_0_PULLUP
+      PCW MIO 0 PULLUP
+      enabled
+    
+    
+      PCW_MIO_0_IOTYPE
+      PCW MIO 0 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_0_DIRECTION
+      PCW MIO 0 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_0_SLEW
+      PCW MIO 0 SLEW
+      slow
+    
+    
+      PCW_MIO_1_PULLUP
+      PCW MIO 1 PULLUP
+      enabled
+    
+    
+      PCW_MIO_1_IOTYPE
+      PCW MIO 1 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_1_DIRECTION
+      PCW MIO 1 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_1_SLEW
+      PCW MIO 1 SLEW
+      slow
+    
+    
+      PCW_MIO_2_PULLUP
+      PCW MIO 2 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_2_IOTYPE
+      PCW MIO 2 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_2_DIRECTION
+      PCW MIO 2 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_2_SLEW
+      PCW MIO 2 SLEW
+      slow
+    
+    
+      PCW_MIO_3_PULLUP
+      PCW MIO 3 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_3_IOTYPE
+      PCW MIO 3 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_3_DIRECTION
+      PCW MIO 3 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_3_SLEW
+      PCW MIO 3 SLEW
+      slow
+    
+    
+      PCW_MIO_4_PULLUP
+      PCW MIO 4 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_4_IOTYPE
+      PCW MIO 4 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_4_DIRECTION
+      PCW MIO 4 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_4_SLEW
+      PCW MIO 4 SLEW
+      slow
+    
+    
+      PCW_MIO_5_PULLUP
+      PCW MIO 5 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_5_IOTYPE
+      PCW MIO 5 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_5_DIRECTION
+      PCW MIO 5 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_5_SLEW
+      PCW MIO 5 SLEW
+      slow
+    
+    
+      PCW_MIO_6_PULLUP
+      PCW MIO 6 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_6_IOTYPE
+      PCW MIO 6 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_6_DIRECTION
+      PCW MIO 6 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_6_SLEW
+      PCW MIO 6 SLEW
+      slow
+    
+    
+      PCW_MIO_7_PULLUP
+      PCW MIO 7 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_7_IOTYPE
+      PCW MIO 7 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_7_DIRECTION
+      PCW MIO 7 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_7_SLEW
+      PCW MIO 7 SLEW
+      slow
+    
+    
+      PCW_MIO_8_PULLUP
+      PCW MIO 8 PULLUP
+      disabled
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_8_IOTYPE
+      PCW MIO 8 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_8_DIRECTION
+      PCW MIO 8 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_8_SLEW
+      PCW MIO 8 SLEW
+      slow
+    
+    
+      PCW_MIO_9_PULLUP
+      PCW MIO 9 PULLUP
+      enabled
+    
+    
+      PCW_MIO_9_IOTYPE
+      PCW MIO 9 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_9_DIRECTION
+      PCW MIO 9 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_9_SLEW
+      PCW MIO 9 SLEW
+      slow
+    
+    
+      PCW_MIO_10_PULLUP
+      PCW MIO 10 PULLUP
+      enabled
+    
+    
+      PCW_MIO_10_IOTYPE
+      PCW MIO 10 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_10_DIRECTION
+      PCW MIO 10 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_10_SLEW
+      PCW MIO 10 SLEW
+      slow
+    
+    
+      PCW_MIO_11_PULLUP
+      PCW MIO 11 PULLUP
+      enabled
+    
+    
+      PCW_MIO_11_IOTYPE
+      PCW MIO 11 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_11_DIRECTION
+      PCW MIO 11 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_11_SLEW
+      PCW MIO 11 SLEW
+      slow
+    
+    
+      PCW_MIO_12_PULLUP
+      PCW MIO 12 PULLUP
+      enabled
+    
+    
+      PCW_MIO_12_IOTYPE
+      PCW MIO 12 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_12_DIRECTION
+      PCW MIO 12 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_12_SLEW
+      PCW MIO 12 SLEW
+      slow
+    
+    
+      PCW_MIO_13_PULLUP
+      PCW MIO 13 PULLUP
+      enabled
+    
+    
+      PCW_MIO_13_IOTYPE
+      PCW MIO 13 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_13_DIRECTION
+      PCW MIO 13 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_13_SLEW
+      PCW MIO 13 SLEW
+      slow
+    
+    
+      PCW_MIO_14_PULLUP
+      PCW MIO 14 PULLUP
+      enabled
+    
+    
+      PCW_MIO_14_IOTYPE
+      PCW MIO 14 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_14_DIRECTION
+      PCW MIO 14 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_14_SLEW
+      PCW MIO 14 SLEW
+      slow
+    
+    
+      PCW_MIO_15_PULLUP
+      PCW MIO 15 PULLUP
+      enabled
+    
+    
+      PCW_MIO_15_IOTYPE
+      PCW MIO 15 IOTYPE
+      LVCMOS 3.3V
+    
+    
+      PCW_MIO_15_DIRECTION
+      PCW MIO 15 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_15_SLEW
+      PCW MIO 15 SLEW
+      slow
+    
+    
+      PCW_MIO_16_PULLUP
+      PCW MIO 16 PULLUP
+      enabled
+    
+    
+      PCW_MIO_16_IOTYPE
+      PCW MIO 16 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_16_DIRECTION
+      PCW MIO 16 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_16_SLEW
+      PCW MIO 16 SLEW
+      slow
+    
+    
+      PCW_MIO_17_PULLUP
+      PCW MIO 17 PULLUP
+      enabled
+    
+    
+      PCW_MIO_17_IOTYPE
+      PCW MIO 17 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_17_DIRECTION
+      PCW MIO 17 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_17_SLEW
+      PCW MIO 17 SLEW
+      slow
+    
+    
+      PCW_MIO_18_PULLUP
+      PCW MIO 18 PULLUP
+      enabled
+    
+    
+      PCW_MIO_18_IOTYPE
+      PCW MIO 18 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_18_DIRECTION
+      PCW MIO 18 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_18_SLEW
+      PCW MIO 18 SLEW
+      slow
+    
+    
+      PCW_MIO_19_PULLUP
+      PCW MIO 19 PULLUP
+      enabled
+    
+    
+      PCW_MIO_19_IOTYPE
+      PCW MIO 19 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_19_DIRECTION
+      PCW MIO 19 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_19_SLEW
+      PCW MIO 19 SLEW
+      slow
+    
+    
+      PCW_MIO_20_PULLUP
+      PCW MIO 20 PULLUP
+      enabled
+    
+    
+      PCW_MIO_20_IOTYPE
+      PCW MIO 20 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_20_DIRECTION
+      PCW MIO 20 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_20_SLEW
+      PCW MIO 20 SLEW
+      slow
+    
+    
+      PCW_MIO_21_PULLUP
+      PCW MIO 21 PULLUP
+      enabled
+    
+    
+      PCW_MIO_21_IOTYPE
+      PCW MIO 21 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_21_DIRECTION
+      PCW MIO 21 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_21_SLEW
+      PCW MIO 21 SLEW
+      slow
+    
+    
+      PCW_MIO_22_PULLUP
+      PCW MIO 22 PULLUP
+      enabled
+    
+    
+      PCW_MIO_22_IOTYPE
+      PCW MIO 22 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_22_DIRECTION
+      PCW MIO 22 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_22_SLEW
+      PCW MIO 22 SLEW
+      slow
+    
+    
+      PCW_MIO_23_PULLUP
+      PCW MIO 23 PULLUP
+      enabled
+    
+    
+      PCW_MIO_23_IOTYPE
+      PCW MIO 23 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_23_DIRECTION
+      PCW MIO 23 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_23_SLEW
+      PCW MIO 23 SLEW
+      slow
+    
+    
+      PCW_MIO_24_PULLUP
+      PCW MIO 24 PULLUP
+      enabled
+    
+    
+      PCW_MIO_24_IOTYPE
+      PCW MIO 24 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_24_DIRECTION
+      PCW MIO 24 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_24_SLEW
+      PCW MIO 24 SLEW
+      slow
+    
+    
+      PCW_MIO_25_PULLUP
+      PCW MIO 25 PULLUP
+      enabled
+    
+    
+      PCW_MIO_25_IOTYPE
+      PCW MIO 25 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_25_DIRECTION
+      PCW MIO 25 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_25_SLEW
+      PCW MIO 25 SLEW
+      slow
+    
+    
+      PCW_MIO_26_PULLUP
+      PCW MIO 26 PULLUP
+      enabled
+    
+    
+      PCW_MIO_26_IOTYPE
+      PCW MIO 26 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_26_DIRECTION
+      PCW MIO 26 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_26_SLEW
+      PCW MIO 26 SLEW
+      slow
+    
+    
+      PCW_MIO_27_PULLUP
+      PCW MIO 27 PULLUP
+      enabled
+    
+    
+      PCW_MIO_27_IOTYPE
+      PCW MIO 27 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_27_DIRECTION
+      PCW MIO 27 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_27_SLEW
+      PCW MIO 27 SLEW
+      slow
+    
+    
+      PCW_MIO_28_PULLUP
+      PCW MIO 28 PULLUP
+      enabled
+    
+    
+      PCW_MIO_28_IOTYPE
+      PCW MIO 28 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_28_DIRECTION
+      PCW MIO 28 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_28_SLEW
+      PCW MIO 28 SLEW
+      slow
+    
+    
+      PCW_MIO_29_PULLUP
+      PCW MIO 29 PULLUP
+      enabled
+    
+    
+      PCW_MIO_29_IOTYPE
+      PCW MIO 29 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_29_DIRECTION
+      PCW MIO 29 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_29_SLEW
+      PCW MIO 29 SLEW
+      slow
+    
+    
+      PCW_MIO_30_PULLUP
+      PCW MIO 30 PULLUP
+      enabled
+    
+    
+      PCW_MIO_30_IOTYPE
+      PCW MIO 30 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_30_DIRECTION
+      PCW MIO 30 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_30_SLEW
+      PCW MIO 30 SLEW
+      slow
+    
+    
+      PCW_MIO_31_PULLUP
+      PCW MIO 31 PULLUP
+      enabled
+    
+    
+      PCW_MIO_31_IOTYPE
+      PCW MIO 31 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_31_DIRECTION
+      PCW MIO 31 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_31_SLEW
+      PCW MIO 31 SLEW
+      slow
+    
+    
+      PCW_MIO_32_PULLUP
+      PCW MIO 32 PULLUP
+      enabled
+    
+    
+      PCW_MIO_32_IOTYPE
+      PCW MIO 32 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_32_DIRECTION
+      PCW MIO 32 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_32_SLEW
+      PCW MIO 32 SLEW
+      slow
+    
+    
+      PCW_MIO_33_PULLUP
+      PCW MIO 33 PULLUP
+      enabled
+    
+    
+      PCW_MIO_33_IOTYPE
+      PCW MIO 33 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_33_DIRECTION
+      PCW MIO 33 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_33_SLEW
+      PCW MIO 33 SLEW
+      slow
+    
+    
+      PCW_MIO_34_PULLUP
+      PCW MIO 34 PULLUP
+      enabled
+    
+    
+      PCW_MIO_34_IOTYPE
+      PCW MIO 34 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_34_DIRECTION
+      PCW MIO 34 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_34_SLEW
+      PCW MIO 34 SLEW
+      slow
+    
+    
+      PCW_MIO_35_PULLUP
+      PCW MIO 35 PULLUP
+      enabled
+    
+    
+      PCW_MIO_35_IOTYPE
+      PCW MIO 35 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_35_DIRECTION
+      PCW MIO 35 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_35_SLEW
+      PCW MIO 35 SLEW
+      slow
+    
+    
+      PCW_MIO_36_PULLUP
+      PCW MIO 36 PULLUP
+      enabled
+    
+    
+      PCW_MIO_36_IOTYPE
+      PCW MIO 36 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_36_DIRECTION
+      PCW MIO 36 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_36_SLEW
+      PCW MIO 36 SLEW
+      slow
+    
+    
+      PCW_MIO_37_PULLUP
+      PCW MIO 37 PULLUP
+      enabled
+    
+    
+      PCW_MIO_37_IOTYPE
+      PCW MIO 37 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_37_DIRECTION
+      PCW MIO 37 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_37_SLEW
+      PCW MIO 37 SLEW
+      slow
+    
+    
+      PCW_MIO_38_PULLUP
+      PCW MIO 38 PULLUP
+      enabled
+    
+    
+      PCW_MIO_38_IOTYPE
+      PCW MIO 38 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_38_DIRECTION
+      PCW MIO 38 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_38_SLEW
+      PCW MIO 38 SLEW
+      slow
+    
+    
+      PCW_MIO_39_PULLUP
+      PCW MIO 39 PULLUP
+      enabled
+    
+    
+      PCW_MIO_39_IOTYPE
+      PCW MIO 39 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_39_DIRECTION
+      PCW MIO 39 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_39_SLEW
+      PCW MIO 39 SLEW
+      slow
+    
+    
+      PCW_MIO_40_PULLUP
+      PCW MIO 40 PULLUP
+      enabled
+    
+    
+      PCW_MIO_40_IOTYPE
+      PCW MIO 40 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_40_DIRECTION
+      PCW MIO 40 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_40_SLEW
+      PCW MIO 40 SLEW
+      slow
+    
+    
+      PCW_MIO_41_PULLUP
+      PCW MIO 41 PULLUP
+      enabled
+    
+    
+      PCW_MIO_41_IOTYPE
+      PCW MIO 41 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_41_DIRECTION
+      PCW MIO 41 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_41_SLEW
+      PCW MIO 41 SLEW
+      slow
+    
+    
+      PCW_MIO_42_PULLUP
+      PCW MIO 42 PULLUP
+      enabled
+    
+    
+      PCW_MIO_42_IOTYPE
+      PCW MIO 42 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_42_DIRECTION
+      PCW MIO 42 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_42_SLEW
+      PCW MIO 42 SLEW
+      slow
+    
+    
+      PCW_MIO_43_PULLUP
+      PCW MIO 43 PULLUP
+      enabled
+    
+    
+      PCW_MIO_43_IOTYPE
+      PCW MIO 43 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_43_DIRECTION
+      PCW MIO 43 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_43_SLEW
+      PCW MIO 43 SLEW
+      slow
+    
+    
+      PCW_MIO_44_PULLUP
+      PCW MIO 44 PULLUP
+      enabled
+    
+    
+      PCW_MIO_44_IOTYPE
+      PCW MIO 44 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_44_DIRECTION
+      PCW MIO 44 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_44_SLEW
+      PCW MIO 44 SLEW
+      slow
+    
+    
+      PCW_MIO_45_PULLUP
+      PCW MIO 45 PULLUP
+      enabled
+    
+    
+      PCW_MIO_45_IOTYPE
+      PCW MIO 45 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_45_DIRECTION
+      PCW MIO 45 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_45_SLEW
+      PCW MIO 45 SLEW
+      slow
+    
+    
+      PCW_MIO_46_PULLUP
+      PCW MIO 46 PULLUP
+      enabled
+    
+    
+      PCW_MIO_46_IOTYPE
+      PCW MIO 46 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_46_DIRECTION
+      PCW MIO 46 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_46_SLEW
+      PCW MIO 46 SLEW
+      slow
+    
+    
+      PCW_MIO_47_PULLUP
+      PCW MIO 47 PULLUP
+      enabled
+    
+    
+      PCW_MIO_47_IOTYPE
+      PCW MIO 47 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_47_DIRECTION
+      PCW MIO 47 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_47_SLEW
+      PCW MIO 47 SLEW
+      slow
+    
+    
+      PCW_MIO_48_PULLUP
+      PCW MIO 48 PULLUP
+      enabled
+    
+    
+      PCW_MIO_48_IOTYPE
+      PCW MIO 48 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_48_DIRECTION
+      PCW MIO 48 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_48_SLEW
+      PCW MIO 48 SLEW
+      slow
+    
+    
+      PCW_MIO_49_PULLUP
+      PCW MIO 49 PULLUP
+      enabled
+    
+    
+      PCW_MIO_49_IOTYPE
+      PCW MIO 49 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_49_DIRECTION
+      PCW MIO 49 DIRECTION
+      in
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_49_SLEW
+      PCW MIO 49 SLEW
+      slow
+    
+    
+      PCW_MIO_50_PULLUP
+      PCW MIO 50 PULLUP
+      enabled
+    
+    
+      PCW_MIO_50_IOTYPE
+      PCW MIO 50 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_50_DIRECTION
+      PCW MIO 50 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_50_SLEW
+      PCW MIO 50 SLEW
+      slow
+    
+    
+      PCW_MIO_51_PULLUP
+      PCW MIO 51 PULLUP
+      enabled
+    
+    
+      PCW_MIO_51_IOTYPE
+      PCW MIO 51 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_51_DIRECTION
+      PCW MIO 51 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_51_SLEW
+      PCW MIO 51 SLEW
+      slow
+    
+    
+      PCW_MIO_52_PULLUP
+      PCW MIO 52 PULLUP
+      enabled
+    
+    
+      PCW_MIO_52_IOTYPE
+      PCW MIO 52 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_52_DIRECTION
+      PCW MIO 52 DIRECTION
+      out
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_52_SLEW
+      PCW MIO 52 SLEW
+      slow
+    
+    
+      PCW_MIO_53_PULLUP
+      PCW MIO 53 PULLUP
+      enabled
+    
+    
+      PCW_MIO_53_IOTYPE
+      PCW MIO 53 IOTYPE
+      LVCMOS 1.8V
+    
+    
+      PCW_MIO_53_DIRECTION
+      PCW MIO 53 DIRECTION
+      inout
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_MIO_53_SLEW
+      PCW MIO 53 SLEW
+      slow
+    
+    
+      preset
+      preset
+      None
+    
+    
+      PCW_UIPARAM_GENERATE_SUMMARY
+      PCW UIPARAM GENERATE SUMMARY
+      NA
+    
+    
+      PCW_MIO_TREE_PERIPHERALS
+      PCW MIO TREE PERIPHERALS
+      GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0
+    
+    
+      PCW_MIO_TREE_SIGNALS
+      PCW MIO TREE SIGNALS
+      gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio
+    
+    
+      PCW_PS7_SI_REV
+      PCW PS7 SI REV
+      PRODUCTION
+    
+    
+      PCW_FPGA_FCLK0_ENABLE
+      PCW FPGA FCLK0 ENABLE
+      1
+      
+        
+          
+            true
+          
+        
+      
+    
+    
+      PCW_FPGA_FCLK1_ENABLE
+      PCW FPGA FCLK1 ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FPGA_FCLK2_ENABLE
+      PCW FPGA FCLK2 ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_FPGA_FCLK3_ENABLE
+      PCW FPGA FCLK3 ENABLE
+      0
+      
+        
+          
+            false
+          
+        
+      
+    
+    
+      PCW_NOR_SRAM_CS0_T_TR
+      PCW NOR SRAM CS0 T TR
+      1
+    
+    
+      PCW_NOR_SRAM_CS0_T_PC
+      PCW NOR SRAM CS0 T PC
+      1
+    
+    
+      PCW_NOR_SRAM_CS0_T_WP
+      PCW NOR SRAM CS0 T WP
+      1
+    
+    
+      PCW_NOR_SRAM_CS0_T_CEOE
+      PCW NOR SRAM CS0 T CEOE
+      1
+    
+    
+      PCW_NOR_SRAM_CS0_T_WC
+      PCW NOR SRAM CS0 T WC
+      11
+    
+    
+      PCW_NOR_SRAM_CS0_T_RC
+      PCW NOR SRAM CS0 T RC
+      11
+    
+    
+      PCW_NOR_SRAM_CS0_WE_TIME
+      PCW NOR SRAM CS0 WE TIME
+      0
+    
+    
+      PCW_NOR_SRAM_CS1_T_TR
+      PCW NOR SRAM CS1 T TR
+      1
+    
+    
+      PCW_NOR_SRAM_CS1_T_PC
+      PCW NOR SRAM CS1 T PC
+      1
+    
+    
+      PCW_NOR_SRAM_CS1_T_WP
+      PCW NOR SRAM CS1 T WP
+      1
+    
+    
+      PCW_NOR_SRAM_CS1_T_CEOE
+      PCW NOR SRAM CS1 T CEOE
+      1
+    
+    
+      PCW_NOR_SRAM_CS1_T_WC
+      PCW NOR SRAM CS1 T WC
+      11
+    
+    
+      PCW_NOR_SRAM_CS1_T_RC
+      PCW NOR SRAM CS1 T RC
+      11
+    
+    
+      PCW_NOR_SRAM_CS1_WE_TIME
+      PCW NOR SRAM CS1 WE TIME
+      0
+    
+    
+      PCW_NOR_CS0_T_TR
+      PCW NOR CS0 T TR
+      1
+    
+    
+      PCW_NOR_CS0_T_PC
+      PCW NOR CS0 T PC
+      1
+    
+    
+      PCW_NOR_CS0_T_WP
+      PCW NOR CS0 T WP
+      1
+    
+    
+      PCW_NOR_CS0_T_CEOE
+      PCW NOR CS0 T CEOE
+      1
+    
+    
+      PCW_NOR_CS0_T_WC
+      PCW NOR CS0 T WC
+      11
+    
+    
+      PCW_NOR_CS0_T_RC
+      PCW NOR CS0 T RC
+      11
+    
+    
+      PCW_NOR_CS0_WE_TIME
+      PCW NOR CS0 WE TIME
+      0
+    
+    
+      PCW_NOR_CS1_T_TR
+      PCW NOR CS1 T TR
+      1
+    
+    
+      PCW_NOR_CS1_T_PC
+      PCW NOR CS1 T PC
+      1
+    
+    
+      PCW_NOR_CS1_T_WP
+      PCW NOR CS1 T WP
+      1
+    
+    
+      PCW_NOR_CS1_T_CEOE
+      PCW NOR CS1 T CEOE
+      1
+    
+    
+      PCW_NOR_CS1_T_WC
+      PCW NOR CS1 T WC
+      11
+    
+    
+      PCW_NOR_CS1_T_RC
+      PCW NOR CS1 T RC
+      11
+    
+    
+      PCW_NOR_CS1_WE_TIME
+      PCW NOR CS1 WE TIME
+      0
+    
+    
+      PCW_NAND_CYCLES_T_RR
+      PCW NAND CYCLES T RR
+      1
+    
+    
+      PCW_NAND_CYCLES_T_AR
+      PCW NAND CYCLES T AR
+      1
+    
+    
+      PCW_NAND_CYCLES_T_CLR
+      PCW NAND CYCLES T CLR
+      1
+    
+    
+      PCW_NAND_CYCLES_T_WP
+      PCW NAND CYCLES T WP
+      1
+    
+    
+      PCW_NAND_CYCLES_T_REA
+      PCW NAND CYCLES T REA
+      1
+    
+    
+      PCW_NAND_CYCLES_T_WC
+      PCW NAND CYCLES T WC
+      11
+    
+    
+      PCW_NAND_CYCLES_T_RC
+      PCW NAND CYCLES T RC
+      11
+    
+    
+      PCW_SMC_CYCLE_T0
+      PCW SMC CYCLE T0
+      NA
+    
+    
+      PCW_SMC_CYCLE_T1
+      PCW SMC CYCLE T1
+      NA
+    
+    
+      PCW_SMC_CYCLE_T2
+      PCW SMC CYCLE T2
+      NA
+    
+    
+      PCW_SMC_CYCLE_T3
+      PCW SMC CYCLE T3
+      NA
+    
+    
+      PCW_SMC_CYCLE_T4
+      PCW SMC CYCLE T4
+      NA
+    
+    
+      PCW_SMC_CYCLE_T5
+      PCW SMC CYCLE T5
+      NA
+    
+    
+      PCW_SMC_CYCLE_T6
+      PCW SMC CYCLE T6
+      NA
+    
+    
+      PCW_PACKAGE_NAME
+      PCW PACKAGE NAME
+      clg400
+    
+    
+      PCW_PLL_BYPASSMODE_ENABLE
+      PCW PLL BYPASSMODE ENABLE
+      0
+    
+    
+      Component_Name
+      system_processing_system7_0_0
+    
+  
+  
+    
+      ZYNQ7 Processing System
+      
+        XPM_MEMORY
+        XPM_FIFO
+      
+      6
+      true
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+        
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+        
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+      
+    
+    
+      2017.4
+    
+  
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv
new file mode 100644
index 0000000..c4f6a03
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/sc_util_v1_0_vl_rfs.sv
@@ -0,0 +1,3149 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+qfeu25494ppdCU98NUgmFPEhtRj48vLWJqcD6r1LZUng496iG9QUQ6TAmFCGtVrRWrV4fsQhoFp8
+dqkjFpsMRA==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+SqpStMU1LlEXp6Q6Twls/fbdc/3UM9cSA5nqOh6nAl7cWsescojs+WMSspwqnaDbWuAmvzoKR5jj
+ovNIJbaAPUuc+5hsxLL+fs16H++Y8AMVU2T2bv3LrYNWV0RdMM3mhFiZodw57w0NBMDpw/XrfVR/
+BkxN7Ubb40GIwfRGDsY=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+L/guAEqGM8e7/XkiNC6v2kIvxayF9plLRYEJ7tvfyt0Rp+ZqMCdRxQucseCasvzT/07Yr6M4eg2k
+QuoddAUHtQQggWjc5nmNifZ5Dl1jQBrW78wRRoBapoXSUBA0UKus0fQ/n7+G3ZTKZrxlEfADRQzj
+cCkjKefnRood+1xdd+RkA65VlObmfjSYvjva97LMGQaECk6oxaEUqIvqsohVfms6vCHeyV4TPHyR
+JCAdlBoDKEz/NAkC5Kwp97IdlkFUAwtZVrRftkpso0w0iPSuZClwuQa5hlu84Is+BPtm9mgNXgTZ
+vO5lj0aM15baVa25alk/drKlfSerKP5bLub4EQ==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+RdoLJv2WzJsOrLH241pHkp5fDkkyjE0RNRxpqSW39lKmW7clm6rVEJp3lweCC5cyNH5W3mMA2KJU
+DHjRg4SBKoCif5/OQ8GMY9br1Po0yi2DlXFbPj5cPOsMzTKYENMR4JnWoQfA3+n09l4ezFVOjndI
+A69CB+g0T0ncYi6UoN5UL2BgE0xODCEp3Zd46XBiuiVyGHNeLhinIzBpo6mSUse8xyF2JwnxL0jq
+a++l7cdV2uNooTW/JiauLsQXUSV9kqOvnUJlu6LV3pJlywwIMqZ//qXNbsaknCnrs4U8Wt4X1b/k
+lURWRUswplCD5ioU+A4gbsrrnTek45oiNcxINA==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+VL44youutw9qAVs2WoG+JqsVomR4bk6EL/UiXJq8Qr/m+ICoCniLc1JonUol4lnTlswd/kuoO9sA
+zXh82WfOlHC3d00IIl9mavmV7HTUcSKvgV8wQQXERmwGa5XWSqV3V6r+x3zyDN6KiY9A2nZYaxCi
+SDA/ZwKxuIddou1bvcxRbCdt7uWya8mHAAKZ9V10FVSwNbKcC8Qn/51fq4PQ9V8yezrLtsdVxOrw
+1rEgrkFP8o9ancOuujuk3Zz81tz1c79wevYi+RofAX6Ku2Bh5S82OGqsSq9tdMhwaYztnXs87k+B
+7i79UD/+xD13w2CBl7+i0lN/iU+tBkNaahu8kw==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+DaWChNdp2AsxOo2yiu7RDN1IT6jX9wWZMdHnayD9h+VgYa0Lfr2Ty1yHSb6hkQDBvTI7S/w1nwNq
+gx+gRINcWEmEl8OsE0I2QPFiseQkIGmeQDxGyvU2fmHzegwfX8G70QpTxw933vWWboO5L/UO1vso
+mJbm2xD+5sWFmZxEZjY=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+Rsl5zJdgD+izHjfaOpTWzozNVGsTmrbuMxwUC36U8/avueS4/KlRFVr48aV+R+czUsIddlzAW9mQ
+IbPppRKkam+EXz5OXEGRQ3HiIpuGdKVcEgxZEel84mN4ZqysQFIWDI+WfvjTeZ8lAzCOFyllLEfi
+DHPLbql0ZYtsnJo18JX0KKNsHRExTRDtjwAmt6+juYDP8SloX51n9lunlZIaEtf43LOKqAvMd6HS
+xmSdoNvLWqUK3YrjX4GmqA23paD8GgtMZQnqUGhFo/QZhpgCI11mBZ8uFtHCf9Ns8EOPWdpGq9Xu
+CBczEVc9knQF0MAdUIuEPmlb36P0rTqYgojWmQ==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 175840)
+`pragma protect data_block
+YDJlLY5xw9OZyHyzGfSN8MhejjziI31tK7ObAWpXXuDR318g/WEEw1pfyStFhA7+lquP0adjh0gF
+nqfwwsnSQbforaTDFO3mCVPe+3ptzbuPfwRFY9wnKqfpOmEbePanFcEO889SbLDF/I0TsMzbvyvK
+F5v581DPrcosBTTsx84NmB45z4NSurhv7FkxAwbSqofKDNpKXaKQFu3DDWnYpNWdZl6iIw+BIY75
+iyeISaoed6hM8HWPzKpptkNlJAWaCluAHxMxq4k0jIRtrMIkBKkSgNa6Wcwf7aWFIlWXqhdjd0Co
+MJJbCRxJE5Ik9M0dLzR7ek7Z/Cqan7Ob8v7WZwMl9IjTHUB8+2CtTgt1nVzIomFInMWPMPnhOLFP
+ReaTyzzeMr0uhizODBLtEahenjEMSvfFBchdZShnB1nveZ3iDS0TinB9HYqkDBhje0ktiWPEHzna
+/JR6lg+W8ToIuqdAaQc0m5b8tKjoPOkNOQndWpQHC6faGg4VpQ/J1RmaIc8YZ0u3fTVERuQ9WOrX
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+`pragma protect end_protected
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_constants.vh b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_constants.vh
new file mode 100644
index 0000000..5eb1281
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_constants.vh
@@ -0,0 +1,123 @@
+`ifndef sc_util_v1_0_2_constants_GLOBAL_CONSTANTS
+`define sc_util_v1_0_2_constants_GLOBAL_CONSTANTS
+parameter integer K_MAX_NUM_BYTES =         128;
+parameter integer K_MAX_BYTE_SIZE =           7;
+parameter integer K_MAX_DATA_WIDTH =        1024;
+parameter integer K_MAX_DATA_SIZE =          10;
+parameter integer K_MIN_NUM_BYTES =           4;
+parameter integer K_MIN_BYTE_SIZE =           2;
+parameter integer K_MIN_DATA_WIDTH =          32;
+parameter integer K_MIN_DATA_SIZE =           5;
+parameter integer K_MAX_NUM_AXI4LITE_BYTES =           8;
+parameter integer K_MAX_AXI4LITE_BYTE_SIZE =           3;
+parameter integer K_MAX_AXI4LITE_DATA_WIDTH =          64;
+parameter integer K_MAX_AXI4LITE_DATA_SIZE =           6;
+parameter integer K_DATA_BITS_PER_BYTE =           9;
+parameter integer K_MAX_BYTE_FACTOR =          16;
+parameter integer K_MAX_BYTE_MAGNITUDE =           5;
+parameter integer K_MAX_ADDR_WIDTH =          64;
+parameter integer K_MAX_ID_WIDTH =          32;
+parameter integer K_MAX_MEP_IDENTIFIER_WIDTH =           8;
+parameter integer K_MAX_USER_WIDTH =        1024;
+parameter integer K_MAX_USER_PAYLD =         512;
+parameter integer K_MAX_NUM_SSC =          16;
+parameter integer K_MAX_SSC_SIZE =           4;
+parameter integer K_MAX_NUM_MSC =          64;
+parameter integer K_MAX_MSC_SIZE =           6;
+parameter integer K_MAX_SWBD_PORTS =          16;
+parameter integer K_MAX_SWBD_SIZE =           4;
+parameter integer K_MAX_CASCADES =          16;
+parameter integer K_MAX_TIERS =           4;
+parameter integer K_MAX_THREADS =          16;
+parameter integer K_MAX_THREAD_SIZE =           4;
+parameter integer K_MAX_NUM_SEG =         256;
+parameter integer K_MAX_SEG_WIDTH =           8;
+parameter integer K_MAX_EP_ROUTE_WIDTH =          64;
+parameter integer K_MAX_SC_ROUTE_WIDTH =          64;
+parameter integer K_MAX_CMD_PTR =           5;
+parameter integer K_MAX_LUTRAM_PTR =           8;
+parameter integer K_MAX_BRAM_PTR =          12;
+parameter integer K_MIN_BRAM_PTR =           9;
+parameter integer K_MAX_SYNC_RATIO =           8;
+parameter integer K_MAX_PIPELINES =           8;
+parameter integer K_LOG_MAX_PIPELINES =           3;
+parameter integer K_MAX_LATENCY =          15;
+parameter integer K_LOG_MAX_LATENCY =           4;
+parameter integer K_AXIS_ARB_TDATA_NUM_BYTES =           2;
+parameter integer K_MAX_USER_BITS_PER_BYTE =           4;
+parameter integer K_MAX_INFO_WIDTH =           1;
+parameter integer K_MAX_OUTSTANDING_REQ =           3;
+parameter integer K_AXI_SIZE_WIDTH =           3;
+parameter integer K_AXI_BURST_WIDTH =           2;
+parameter integer K_AXI_RESP_WIDTH =           2;
+parameter integer K_AXI_LAST_WIDTH =           1;
+parameter integer K_AXI_LEN_WIDTH =           8;
+parameter integer K_AXI_EXCL_LEN_WIDTH =           4;
+parameter integer K_AXI_LOCK_WIDTH =           1;
+parameter integer K_AXI3_LEN_WIDTH =           4;
+parameter integer K_AXI3_LOCK_WIDTH =           2;
+parameter integer K_AXI_PROT_WIDTH =           3;
+parameter integer K_AXI_QOS_WIDTH =           4;
+parameter integer K_AXI_CACHE_WIDTH =           4;
+parameter integer K_MAX_ACCEPTANCE =          32;
+parameter integer K_MAX_FANOUT =         200;
+parameter integer K_MAX_READ_WATERMARK =        4096;
+parameter integer K_MAX_BURST_LENGTH =         256;
+parameter integer CH_R =           0;
+parameter integer CH_W =           1;
+parameter integer CH_AR =           2;
+parameter integer CH_AW =           3;
+parameter integer CH_B =           4;
+parameter integer CLK_DOWN =          -2;
+parameter integer CLK_SYNC_ALIAS =          -1;
+parameter integer CLK_ASYNC =           0;
+parameter integer CLK_SYNC =           1;
+parameter integer CLK_UP =           2;
+parameter integer CLKEN_NONE =           0;
+parameter integer CLKEN_S =           1;
+parameter integer CLKEN_M =           2;
+parameter integer CLKEN_S_AND_M =           3;
+parameter integer ARB_BYPASS =           0;
+parameter integer ARB_ROUNDROBIN =           1;
+parameter integer ARB_SLAVE =           2;
+parameter integer FIFO_LUTRAM =           0;
+parameter integer FIFO_BRAM =           1;
+parameter integer FIFO_NONE =           2;
+parameter integer FIFO_IP_XPM_MEMORY =           0;
+parameter integer FIFO_IP_FG =           1;
+parameter integer FIFO_IP_XPM_FIFO =           2;
+parameter integer K_T_STRUCT_EXCLUSIVE_WIDTH =          11;
+parameter integer K_T_STATIC_ADDR_PAYLD_WIDTH =         102;
+parameter integer K_T_STATIC_RDATA_PAYLD_WIDTH =          17;
+parameter integer K_T_STATIC_WDATA_PAYLD_WIDTH =          15;
+parameter integer K_T_STATIC_BRSP_PAYLD_WIDTH =           2;
+parameter integer K_T_EXCLUSIVE_WIDTH =          43;
+parameter integer K_T_ADDR_AUGMENT_WIDTH =         114;
+parameter integer K_T_DATA_AUGMENT_WIDTH =          14;
+parameter integer K_T_BRSP_AUGMENT_WIDTH =           0;
+parameter integer K_USABLE_T_ADDR_CASCADE_WIDTH =         626;
+parameter integer K_USABLE_T_DATA_CASCADE_WIDTH =         526;
+parameter integer K_USABLE_T_BRSP_CASCADE_WIDTH =         512;
+parameter integer K_T_CASCADE_WIDTH =         627;
+parameter integer K_T_SEG_LEN_WIDTH =           8;
+parameter integer K_USABLE_T_ADDR_SIDEBAND_WIDTH =         699;
+parameter integer K_USABLE_T_DATA_SIDEBAND_WIDTH =         691;
+parameter integer K_USABLE_T_BRSP_SIDEBAND_WIDTH =         691;
+parameter integer K_T_SIDEBAND_WIDTH =         700;
+parameter integer K_USABLE_T_AXPAYLD_WIDTH =         808;
+parameter integer K_USABLE_T_WPAYLD_WIDTH =        1853;
+parameter integer K_USABLE_T_RPAYLD_WIDTH =        1759;
+parameter integer K_USABLE_T_BPAYLD_WIDTH =         734;
+parameter integer K_T_PAYLD_WIDTH =        1854;
+parameter integer K_MAX_PAYLD_WIDTH =        1854;
+parameter integer K_USABLE_T_AXVECTOR_WIDTH =        1145;
+parameter integer K_USABLE_T_WVECTOR_WIDTH =        2177;
+parameter integer K_USABLE_T_RVECTOR_WIDTH =        2083;
+parameter integer K_USABLE_T_BVECTOR_WIDTH =        1058;
+parameter integer K_STATIC_AXVECTOR_WIDTH =          25;
+parameter integer K_STATIC_WVECTOR_WIDTH =           1;
+parameter integer K_STATIC_RVECTOR_WIDTH =           3;
+parameter integer K_STATIC_BVECTOR_WIDTH =           2;
+parameter integer K_T_VECTOR_WIDTH =        2178;
+parameter integer K_MAX_VECTOR_WIDTH =        2178;
+`endif
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_structs.svh b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_structs.svh
new file mode 100644
index 0000000..7a8610f
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/02c8/hdl/verilog/sc_util_v1_0_2_structs.svh
@@ -0,0 +1,297 @@
+//  (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // cascade parameters and typedefs
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  typedef logic [((T_SC_AWUSER_WIDTH == 0) ? 1 : T_SC_AWUSER_WIDTH)-1:0]    t_sc_awuser;
+  typedef logic [((T_SC_ARUSER_WIDTH == 0) ? 1 : T_SC_ARUSER_WIDTH)-1:0]    t_sc_aruser;
+  typedef logic [((T_SC_BUSER_WIDTH ==  0) ? 1 : T_SC_BUSER_WIDTH )-1:0]    t_sc_buser;
+  typedef logic [((T_SC_RUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_RUSER_BITS_PER_BYTE*(T_SC_RDATA_WIDTH/8)))-1:0] t_sc_ruser;
+  typedef logic [((T_SC_WUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_WUSER_BITS_PER_BYTE*(T_SC_WDATA_WIDTH/8)))-1:0] t_sc_wuser;
+  typedef logic [T_SC_ADDR_WIDTH-1:0]                     t_sc_addr;
+  typedef logic [T_SC_MSC_ROUTE_WIDTH-1:0]                t_sc_msc_route;
+  typedef logic [T_SC_SSC_ROUTE_WIDTH-1:0]                t_sc_ssc_route;
+  typedef logic [(T_SC_ID_WIDTH==0?1:T_SC_ID_WIDTH)-1:0]  t_sc_id;
+  typedef logic [(T_SC_WUSER_BITS_PER_BYTE+8)-1:0]        t_sc_wuserdata_unit;
+  typedef logic [(T_SC_RUSER_BITS_PER_BYTE+8)-1:0]        t_sc_ruserdata_unit;
+  typedef logic [T_SC_RDATA_WIDTH -1:0]                   t_sc_rdata;
+  typedef logic [T_SC_WDATA_WIDTH-1:0]                    t_sc_wdata;
+  typedef logic [(T_SC_WDATA_WIDTH/8)-1:0]                t_sc_wstrb;
+
+  typedef struct packed {
+    t_sc_wuserdata_unit   userdata;
+    logic                 strb;
+  } t_sc_wdata_unit;
+
+  typedef struct packed {
+    t_sc_ruserdata_unit   userdata;
+  } t_sc_rdata_unit;
+
+  typedef struct packed {
+    t_sc_id                 id;
+    t_axi_len               len;
+    t_axi_size              size;
+  } t_sc_addr_exclusive;
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // payld parameters and typedefs
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  typedef struct packed {
+    t_axi_cache             cache;
+    t_axi_qos               qos;
+    t_axi_prot              prot;
+    t_axi_lock              lock;
+    t_sc_addr               addr;
+    t_sc_id                 id;
+    t_sc_aruser             user;
+    t_max_byte_size         last_offset;
+    t_sc_addr_exclusive     exclusive;
+    t_max_ep_route          ep_route;
+    t_axi_len               seg_len;
+    t_sc_msc_route          sc_route;
+  } t_sc_arpayld;
+
+  typedef struct packed {
+    t_axi_cache             cache;
+    t_axi_qos               qos;
+    t_axi_prot              prot;
+    t_axi_lock              lock;
+    t_sc_addr               addr;
+    t_sc_id                 id;
+    t_sc_awuser             user;
+    t_max_byte_size         last_offset;
+    t_sc_addr_exclusive     exclusive;
+    t_max_ep_route          ep_route;
+    t_axi_len               seg_len;
+    t_sc_msc_route          sc_route;
+  } t_sc_awpayld;
+
+  typedef struct packed {
+    t_sc_wdata_unit[(T_SC_WDATA_WIDTH/8)-1:0] bytes;
+    t_axi_last              last;
+    t_max_byte_size         last_offset;
+    t_max_byte_size         first_offset;
+    t_sc_msc_route          sc_route;
+  } t_sc_wpayld;
+
+  typedef struct packed {
+    t_sc_rdata_unit[(T_SC_RDATA_WIDTH/8)-1:0] bytes;
+    t_axi_last              last;
+    t_axi_resp              resp;
+    t_sc_id                 id;
+    t_max_byte_size         last_offset;
+    t_max_byte_size         first_offset;
+    t_sc_ssc_route          sc_route;
+  } t_sc_rpayld;
+
+  typedef struct packed {
+    t_axi_resp              resp;
+    t_sc_id                 id;
+    t_sc_buser              user;
+    t_sc_ssc_route          sc_route;
+  } t_sc_bpayld;
+
+//synthesis translate_off
+`ifdef MODEL_TECH
+
+  function string sprint_sc_addr_exclusive(
+    input t_sc_addr_exclusive  excl
+  );
+    string str;
+    str = "";
+    str = $sformatf("exclusive.id           = 0x%0x\n%s", excl.id,str);
+    str = $sformatf("exclusive.len          = 0x%0x\n%s", excl.len,str);
+    str = $sformatf("exclusive.size         = 0x%0x\n%s", excl.size,str);
+    return (str);
+  endfunction
+
+  function string sprint_sc_awpayld(
+    input t_sc_awpayld  pay
+  );
+    string str;
+    str = "";
+    str = sprint_sc_addr_exclusive(pay.exclusive);
+    str = $sformatf("ep_route   = 0x%0x\n%s", pay.ep_route,str);
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("seg_len    = 0x%0x\n%s", pay.seg_len,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("addr       = 0x%0x\n%s", pay.addr,str);
+    str = $sformatf("lock       = 0x%0x\n%s", pay.lock,str);
+    str = $sformatf("prot       = 0x%0x\n%s", pay.prot,str);
+    str = $sformatf("qos        = 0x%0x\n%s", pay.qos,str);
+    str = $sformatf("cache      = 0x%0x\n%s", pay.cache,str);
+    str = $sformatf("AWPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_awpayld
+
+  function string sprint_sc_arpayld(
+    input t_sc_arpayld  pay
+  );
+    string str;
+    str = "";
+    str = sprint_sc_addr_exclusive(pay.exclusive);
+    str = $sformatf("ep_route   = 0x%0x\n%s", pay.ep_route,str);
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("seg_len    = 0x%0x\n%s", pay.seg_len,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("addr       = 0x%0x\n%s", pay.addr,str);
+    str = $sformatf("lock       = 0x%0x\n%s", pay.lock,str);
+    str = $sformatf("prot       = 0x%0x\n%s", pay.prot,str);
+    str = $sformatf("qos        = 0x%0x\n%s", pay.qos,str);
+    str = $sformatf("cache      = 0x%0x\n%s", pay.cache,str);
+    str = $sformatf("ARPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_arpayld
+
+  function string sprint_sc_wpayld(
+    input t_sc_wpayld  pay
+  );
+    string str;
+    string strb;
+    string data;
+    str = "";
+    strb = "";
+    data = "";
+    str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
+    str = $sformatf("last_offset  = 0x%0x\n%s", pay.last_offset,str);
+    str = $sformatf("sc_route     = 0x%0x\n%S", pay.sc_route,str);
+    str = $sformatf("last         = 0x%0x\n%s", pay.last,str);
+    for (int i = 0; i < T_SC_WDATA_WIDTH/8;i++) begin
+      data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
+      strb = $sformatf("%0x%s", pay.bytes[i].strb, strb);
+    end
+    str = $sformatf("WPAYLD\n%sdata:%s\nstrb:%d\n",str,data,strb);
+    return (str);
+  endfunction : sprint_sc_wpayld
+
+  function string sprint_sc_rpayld(
+    input t_sc_rpayld  pay
+  );
+    string str;
+    string data;
+    str = "";
+    data = "";
+    str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
+    str = $sformatf("last_offset  = 0x%0x\n%s", pay.last_offset,str);
+    str = $sformatf("sc_route     = 0x%0x\n%S", pay.sc_route,str);
+    str = $sformatf("id           = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("resp         = 0x%0x\n%s", pay.resp,str);
+    str = $sformatf("last         = 0x%0x\n%s", pay.last,str);
+    for (int i = 0; i < T_SC_RDATA_WIDTH/8;i++) begin
+      data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
+    end
+    str = $sformatf("RPAYLD\n%sdata:%s\n",str,data);
+    return (str);
+  endfunction : sprint_sc_rpayld
+
+  function string sprint_sc_bpayld(
+    input t_sc_bpayld  pay
+  );
+    string str;
+    str = "";
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("resp       = 0x%0x\n%s", pay.resp,str);
+    str = $sformatf("BPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_bpayld
+`endif
+//synthesis translate_on
+
+
+typedef struct packed {
+  t_axi_cache       cache;
+  t_axi_qos         qos;
+  t_axi_prot        prot;
+  t_axi_lock        lock;
+  t_axi_len         len;
+  t_sc_addr         addr;
+  t_sc_id           id;
+  t_axi_size        size;
+  t_axi_burst       burst;
+  t_sc_awuser       user;
+} t_sc_awvector;
+
+typedef struct packed {
+  t_axi_cache       cache;
+  t_axi_qos         qos;
+  t_axi_prot        prot;
+  t_axi_lock        lock;
+  t_axi_len         len;
+  t_sc_addr         addr;
+  t_sc_id           id;
+  t_axi_size        size;
+  t_axi_burst       burst;
+  t_sc_aruser       user;
+} t_sc_arvector;
+
+typedef struct packed {
+  t_sc_wstrb        strb;
+  t_sc_wdata        data;
+  t_axi_last        last;
+  t_sc_wuser        user;
+} t_sc_wvector;
+
+typedef struct packed {
+  t_sc_rdata        data;
+  t_axi_last        last;
+  t_axi_resp        resp;
+  t_sc_id           id;
+  t_sc_ruser        user;
+} t_sc_rvector;
+
+
+typedef struct packed {
+  t_axi_resp        resp;
+  t_sc_id           id;
+  t_sc_buser        user;
+} t_sc_bvector;
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_apis.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_apis.v
new file mode 100644
index 0000000..5f91467
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_apis.v
@@ -0,0 +1,825 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_apis.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Set of Zynq VIP APIs that are used for writing tests.
+ *                
+ *****************************************************************************/
+
+  /* API for setting the STOP_ON_ERROR*/  
+  task automatic set_stop_on_error;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
+      STOP_ON_ERROR = LEVEL;
+//    M_AXI_GP0.master.set_stop_on_error(LEVEL);
+//    M_AXI_GP1.master.set_stop_on_error(LEVEL);
+//    S_AXI_GP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_GP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP2.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP3.slave.set_stop_on_error(LEVEL);
+//    S_AXI_ACP.slave.set_stop_on_error(LEVEL);
+      M_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      M_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP2.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP3.STOP_ON_ERROR = LEVEL;
+      S_AXI_ACP.STOP_ON_ERROR = LEVEL;
+
+    end
+  endtask 
+
+  /* API for setting the verbosity for channel level info*/  
+  task automatic set_channel_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the verbosity for function level info*/  
+  task automatic set_function_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_function_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_function_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_function_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the Message verbosity */  
+  task automatic set_debug_level_info;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO,  LEVEL);
+      DEBUG_INFO = LEVEL;
+      M_AXI_GP0.DEBUG_INFO = LEVEL;
+      M_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_GP0.DEBUG_INFO = LEVEL;
+      S_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP0.DEBUG_INFO = LEVEL;
+      S_AXI_HP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP2.DEBUG_INFO = LEVEL;
+      S_AXI_HP3.DEBUG_INFO = LEVEL;
+      S_AXI_ACP.DEBUG_INFO = LEVEL; 
+    end
+  endtask
+
+  /* API for setting ARQos Values */  
+  task automatic set_arqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting AWQos Values */  
+  task automatic set_awqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for soft reset control */
+  task automatic fpga_soft_reset;
+    input[data_width-1:0] reset_ctrl;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO,  reset_ctrl); 
+      gen_rst.fpga_soft_reset(reset_ctrl);  
+    end
+  endtask
+
+  /* API for pre-loading memories from (DDR/OCM model) */
+  task automatic pre_load_mem_from_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+ 
+  /* API for pre-loading memories (DDR/OCM) */
+  task automatic pre_load_mem;
+    input [1:0] data_type;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR) $stop; 
+      end
+    end
+  endtask
+
+  /* API for backdoor write to memories (DDR/OCM) */
+  task automatic write_mem;
+    input [max_burst_bits-1 :0] data;
+    input [addr_width-1:0] start_addr;
+    input [max_burst_bytes_width:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.write_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.write_mem(data,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+    /* read_memory */
+    task automatic read_mem;
+      input [addr_width-1:0] start_addr;
+      input [max_burst_bytes_width :0] no_of_bytes;
+      output[max_burst_bits-1 :0] data;
+      reg [1:0] mem_type;
+      integer succ;
+      begin
+        mem_type = decode_address(start_addr);
+        if(check_addr_aligned(start_addr)) begin    
+          case(mem_type)
+          OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.read_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          DDR_MEM : begin
+                    ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          default : begin
+                    $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                    if(STOP_ON_ERROR) $stop; 
+                    end 
+          endcase
+        end else begin 
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
+          if(STOP_ON_ERROR)
+            $stop; 
+        end
+      end
+  endtask
+
+  /* API for backdoor read to memories (DDR/OCM) */
+  task automatic peek_mem_to_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+  /* API to read interrupt status */
+  task automatic read_interrupt;
+    output[irq_width-1:0] irq_status;
+    begin
+      irq_status = IRQ_F2P;
+      if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO,  irq_status);
+    end
+  endtask
+
+  /* API to wait on interrup */
+  task automatic wait_interrupt;
+    input [3:0] irq;
+    output[irq_width-1:0] irq_status;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+
+      case(irq) 
+      0 :  wait(IRQ_F2P[0] === 1'b1);
+      1 :  wait(IRQ_F2P[1] === 1'b1);
+      2 :  wait(IRQ_F2P[2] === 1'b1);
+      3 :  wait(IRQ_F2P[3] === 1'b1);
+      4 :  wait(IRQ_F2P[4] === 1'b1);
+      5 :  wait(IRQ_F2P[5] === 1'b1);
+      6 :  wait(IRQ_F2P[6] === 1'b1);
+      7 :  wait(IRQ_F2P[7] === 1'b1);
+      8 :  wait(IRQ_F2P[8] === 1'b1);
+      8 :  wait(IRQ_F2P[9] === 1'b1);
+      10:  wait(IRQ_F2P[10] === 1'b1);
+      11:  wait(IRQ_F2P[11] === 1'b1);
+      12:  wait(IRQ_F2P[12] === 1'b1);
+      13:  wait(IRQ_F2P[13] === 1'b1);
+      14:  wait(IRQ_F2P[14] === 1'b1);
+      15:  wait(IRQ_F2P[15] === 1'b1);
+      default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
+      endcase
+      if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+      irq_status = IRQ_F2P;
+    end
+  endtask
+
+  /* API to wait for a certain match pattern*/ 
+  task automatic wait_mem_update;
+    input[addr_width-1:0] address;
+    input[data_width-1:0] data_in;
+    output[data_width-1:0] data_out;
+    reg[data_width-1:0] datao;
+    begin
+      if(mem_update_key) begin
+        mem_update_key = 0;
+        if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); 
+        if(check_addr_aligned(address)) begin
+         ddrc.ddr.wait_mem_update(address, datao);
+         if(datao != data_in)begin 
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
+           $stop;
+         end else
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO,  address, data_in);
+         data_out = datao;
+        end else begin
+           $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR,  address); 
+           if(STOP_ON_ERROR) $stop;
+        end
+        mem_update_key = 1;
+      end else 
+        $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end
+  endtask
+
+
+ /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ 
+ task automatic write_from_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] wr_size;
+   output [axi_rsp_width-1:0] response;
+   integer succ;
+   begin
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         $fclose(succ);
+         case(start_addr[31:30])
+          GP_M0 : begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end
+          GP_M1 : begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end 
+          default : begin
+           $display("[%0d] : %0s : Invalid Address(0x%0h)  'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+          end
+         endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a READ transaction on one of the AXI-Master ports*/ 
+ task automatic read_to_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] rd_size;
+   output [axi_rsp_width-1:0] response;
+   begin
+      if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR ,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         case(start_addr[31:30])
+          GP_M0 : begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end
+          GP_M1 : begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end
+          default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+         endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic write_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] wr_size;
+   input [(max_transfer_bytes*8)-1:0] w_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(wr_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+   end
+ endtask
+
+ /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic read_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] rd_size;
+   output[(max_transfer_bytes*8)-1:0] rd_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(rd_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+    end
+ endtask
+
+/* Hooks to call to VIP APIs */
+ task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp; /// string for response
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic read_burst;
+   input [addr_width-1:0] start_addr;
+   input [axi_len_width-1:0] len;
+   input [axi_size_width-1:0] siz;
+   input [axi_brst_type_width-1:0] burst;
+   input [axi_lock_width-1:0] lck;
+   input [axi_cache_width-1:0] cache;
+   input [axi_prot_width-1:0] prot;
+   output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
+   output [(axi_rsp_width*axi_burst_len)-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+    end
+ endtask 
+
+ task automatic wait_reg_update;
+   input [addr_width-1:0] addr;
+   input [data_width-1:0] data_i;
+   input [data_width-1:0] mask_i;
+   input [int_width-1:0] time_interval;
+   input [int_width-1:0] time_out;
+   output [data_width-1:0] data_o;
+
+   reg upd_done0;
+   reg upd_done1;
+   begin
+    if(!check_master_address(addr)) begin
+       $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR,  addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(addr[31:30] === GP_M0) begin
+     if(reg_update_key_0) begin
+       reg_update_key_0 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
+       if(DEBUG_INFO && upd_done0)
+         $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); 
+       reg_update_key_0 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else if(addr[31:30] === GP_M1) begin
+     if(reg_update_key_1) begin
+       reg_update_key_1 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
+       if(DEBUG_INFO && upd_done1)
+         $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO,  addr); 
+       reg_update_key_1 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); 
+   end
+ endtask 
+
+/* API to read register map */
+ task read_register_map;
+   input [addr_width-1:0] start_addr;
+   input [max_regs_width:0] no_of_registers;
+   output[max_burst_bits-1 :0] data;
+   reg [max_regs_width:0] no_of_regs;
+   begin
+    no_of_regs = no_of_registers;
+    if(no_of_registers > 32) begin
+      $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
+      no_of_regs = 32;
+    end
+    if(check_addr_aligned(start_addr)) begin
+      if(decode_address(start_addr) == REG_MEM) begin
+        if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO,  start_addr,no_of_regs ); 
+        regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
+        if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  start_addr, data ); 
+      end else begin
+       $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+      end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+    end
+   end
+ endtask
+
+/* API to read single register */
+ task read_register;
+   input [addr_width-1:0] addr;
+   output[data_width-1:0] data;
+   begin
+    if(check_addr_aligned(addr)) begin
+       if(decode_address(addr) == REG_MEM) begin
+         if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO,  addr ); 
+         regc.regm.get_data(addr >> 2, data);
+         if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  addr, data ); 
+       end else begin
+         $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
+       end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
+    end
+
+   end
+ endtask
+
+  /* API to set the AXI-Slave profile*/ 
+ task automatic set_slave_profile;
+    input[1023:0] name;
+    input[1:0] latency ;
+    begin 
+     if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO,  name);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
+      "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
+      "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
+      "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
+      "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
+      "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
+      "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
+      "ALL"       : begin
+                     S_AXI_GP0.set_latency_type(latency);
+                     S_AXI_GP1.set_latency_type(latency);
+                     S_AXI_HP0.set_latency_type(latency);
+                     S_AXI_HP1.set_latency_type(latency);
+                     S_AXI_HP2.set_latency_type(latency);
+                     S_AXI_HP3.set_latency_type(latency);
+                     S_AXI_ACP.set_latency_type(latency);
+                    end  
+     endcase
+    end
+ endtask
+
+
+/*------------------------------ LOCAL APIs ------------------------------------------------ */
+
+  /* local API for address decoding*/
+  function automatic [1:0] decode_address;
+    input [addr_width-1:0] address;
+    begin
+      if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) 
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= ddr_start_addr && address <= ddr_end_addr)
+        decode_address = DDR_MEM; /// DDR 
+      else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
+        decode_address = REG_MEM; /// Register Map
+      else
+        decode_address = INVALID_MEM_TYPE; /// ERROR in Address 
+    end
+  endfunction 
+
+  /* local API for checking address is 32-bit (4-byte) aligned */
+  function automatic check_addr_aligned;
+    input [addr_width-1:0] address;
+    begin 
+      if((address%4) !=0 ) begin // 
+        check_addr_aligned = 0; ///not_aligned
+      end else
+        check_addr_aligned = 1;
+    end
+  endfunction
+
+ /* local API to check address for GP Masters */
+ function check_master_address; 
+   input [addr_width-1:0] address;
+   begin
+     if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) 
+       check_master_address = 1'b1; 
+     else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) 
+       check_master_address = 1'b1; 
+     else
+       check_master_address = 1'b0; /// ERROR in Address 
+   end
+ endfunction
+
+ /* Response decode */
+ function automatic [511:0] get_resp;
+   input[axi_rsp_width-1:0] response;
+   begin 
+    case(response)
+     2'b00 : get_resp = "OKAY";
+     2'b01 : get_resp = "EXOKAY";
+     2'b10 : get_resp = "SLVERR";
+     2'b11 : get_resp = "DECERR";
+    endcase
+   end
+ endfunction 
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_acp.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_acp.v
new file mode 100644
index 0000000..891f5a9
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_acp.v
@@ -0,0 +1,93 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_axi_acp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for ACP port
+ *
+ *****************************************************************************/
+
+/* AXI Slave ACP */
+  processing_system7_vip_v1_0_3_axi_slave #( C_USE_S_AXI_ACP, // enable
+               axi_acp_name, // name
+               axi_acp_data_width, // data width
+               addr_width, /// address width
+               axi_acp_id_width, // ID width
+               C_S_AXI_ACP_BASEADDR, // slave base address
+               C_S_AXI_ACP_HIGHADDR,// slave size
+               axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 
+               axi_slv_excl_support, // Exclusive access support
+               axi_acp_wr_outstanding,
+               axi_acp_rd_outstanding)
+  S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
+            .S_ACLK   (S_AXI_ACP_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_ACP_AWID),
+            .S_AWADDR  (S_AXI_ACP_AWADDR),
+            .S_AWLEN   (S_AXI_ACP_AWLEN),
+            .S_AWSIZE  (S_AXI_ACP_AWSIZE),
+            .S_AWBURST (S_AXI_ACP_AWBURST),
+            .S_AWLOCK  (S_AXI_ACP_AWLOCK),
+            .S_AWCACHE (S_AXI_ACP_AWCACHE),
+            .S_AWPROT  (S_AXI_ACP_AWPROT),
+            .S_AWVALID (S_AXI_ACP_AWVALID),
+            .S_AWREADY (S_AXI_ACP_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_ACP_WID),
+            .S_WDATA  (S_AXI_ACP_WDATA),
+            .S_WSTRB  (S_AXI_ACP_WSTRB), 
+            .S_WLAST  (S_AXI_ACP_WLAST), 
+            .S_WVALID (S_AXI_ACP_WVALID),
+            .S_WREADY (S_AXI_ACP_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_ACP_BID),
+            .S_BRESP  (S_AXI_ACP_BRESP),
+            .S_BVALID (S_AXI_ACP_BVALID),
+            .S_BREADY (S_AXI_ACP_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_ACP_ARID),
+            .S_ARADDR  (S_AXI_ACP_ARADDR),
+            .S_ARLEN   (S_AXI_ACP_ARLEN),
+            .S_ARSIZE  (S_AXI_ACP_ARSIZE),
+            .S_ARBURST (S_AXI_ACP_ARBURST),
+            .S_ARLOCK  (S_AXI_ACP_ARLOCK),
+            .S_ARCACHE (S_AXI_ACP_ARCACHE),
+            .S_ARPROT  (S_AXI_ACP_ARPROT),
+            .S_ARVALID (S_AXI_ACP_ARVALID),
+            .S_ARREADY (S_AXI_ACP_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_ACP_RID),
+            .S_RDATA  (S_AXI_ACP_RDATA),
+            .S_RRESP  (S_AXI_ACP_RRESP),
+            .S_RLAST  (S_AXI_ACP_RLAST),
+            .S_RVALID (S_AXI_ACP_RVALID),
+            .S_RREADY (S_AXI_ACP_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_ACP_AWQOS),
+            .S_ARQOS  (S_AXI_ACP_ARQOS),            // Side band signals 
+
+            .SW_CLK   (net_sw_clk),
+/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
+            .WR_DATA_ACK_DDR (ddr_wr_ack_port0),
+            .WR_DATA_ACK_OCM (ocm_wr_ack_port0),
+            .WR_DATA  (net_wr_data_acp), 
+            .WR_ADDR  (net_wr_addr_acp), 
+            .WR_BYTES  (net_wr_bytes_acp), 
+            .WR_DATA_VALID_DDR  (ddr_wr_dv_port0), 
+            .WR_DATA_VALID_OCM  (ocm_wr_dv_port0), 
+            .WR_QOS (net_wr_qos_acp),
+
+            .RD_REQ_DDR (ddr_rd_req_port0),
+            .RD_REQ_OCM (ocm_rd_req_port0),
+            .RD_REQ_REG (reg_rd_req_port0),
+            .RD_ADDR (net_rd_addr_acp),
+            .RD_DATA_DDR (ddr_rd_data_port0),
+            .RD_DATA_OCM (ocm_rd_data_port0),
+            .RD_DATA_REG (reg_rd_data_port0),
+            .RD_BYTES (net_rd_bytes_acp),
+            .RD_DATA_VALID_DDR (ddr_rd_dv_port0),
+            .RD_DATA_VALID_OCM (ocm_rd_dv_port0),
+            .RD_DATA_VALID_REG (reg_rd_dv_port0),
+            .RD_QOS (net_rd_qos_acp)
+
+);
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_gp.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_gp.v
new file mode 100644
index 0000000..9594716
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_gp.v
@@ -0,0 +1,309 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_axi_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI GP ports
+ *
+ *****************************************************************************/
+
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12'b11_000_000_00_00    
+       12'b11_010_000_00_00     
+       12'b11_011_000_00_00   
+       12'b11_100_000_00_00   
+       12'b11_101_000_00_00   
+       12'b11_110_000_00_00     
+       12'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12'b11_000_001_00_00    
+       12'b11_010_001_00_00     
+       12'b11_011_001_00_00    
+       12'b11_100_001_00_00    
+       12'b11_101_001_00_00    
+       12'b11_110_001_00_00     
+       12'b11_111_001_00_00    
+   */
+ 
+/* AXI -Master GP0 */
+  processing_system7_vip_v1_0_3_axi_master #(C_USE_M_AXI_GP0, // enable
+               axi_mgp0_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
+            .M_ACLK   (M_AXI_GP0_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP0_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP0_AWADDR),
+            .M_AWLEN   (M_AXI_GP0_AWLEN),
+            .M_AWSIZE  (M_AXI_GP0_AWSIZE),
+            .M_AWBURST (M_AXI_GP0_AWBURST),
+            .M_AWLOCK  (M_AXI_GP0_AWLOCK),
+            .M_AWCACHE (M_AXI_GP0_AWCACHE),
+            .M_AWPROT  (M_AXI_GP0_AWPROT),
+            .M_AWVALID (M_AXI_GP0_AWVALID),
+            .M_AWREADY (M_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP0_WID_FULL),
+            .M_WDATA  (M_AXI_GP0_WDATA),
+            .M_WSTRB  (M_AXI_GP0_WSTRB), 
+            .M_WLAST  (M_AXI_GP0_WLAST), 
+            .M_WVALID (M_AXI_GP0_WVALID),
+            .M_WREADY (M_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP0_BID_FULL),
+            .M_BRESP  (M_AXI_GP0_BRESP),
+            .M_BVALID (M_AXI_GP0_BVALID),
+            .M_BREADY (M_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP0_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP0_ARADDR),
+            .M_ARLEN   (M_AXI_GP0_ARLEN),
+            .M_ARSIZE  (M_AXI_GP0_ARSIZE),
+            .M_ARBURST (M_AXI_GP0_ARBURST),
+            .M_ARLOCK  (M_AXI_GP0_ARLOCK),
+            .M_ARCACHE (M_AXI_GP0_ARCACHE),
+            .M_ARPROT  (M_AXI_GP0_ARPROT),
+            .M_ARVALID (M_AXI_GP0_ARVALID),
+            .M_ARREADY (M_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP0_RID_FULL),
+            .M_RDATA  (M_AXI_GP0_RDATA),
+            .M_RRESP  (M_AXI_GP0_RRESP),
+            .M_RLAST  (M_AXI_GP0_RLAST),
+            .M_RVALID (M_AXI_GP0_RVALID),
+            .M_RREADY (M_AXI_GP0_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP0_AWQOS),
+            .M_ARQOS  (M_AXI_GP0_ARQOS)
+            ); 
+ 
+ /* AXI Master GP1 */
+  processing_system7_vip_v1_0_3_axi_master #(C_USE_M_AXI_GP1, // enable
+               axi_mgp1_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
+            .M_ACLK   (M_AXI_GP1_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP1_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP1_AWADDR),
+            .M_AWLEN   (M_AXI_GP1_AWLEN),
+            .M_AWSIZE  (M_AXI_GP1_AWSIZE),
+            .M_AWBURST (M_AXI_GP1_AWBURST),
+            .M_AWLOCK  (M_AXI_GP1_AWLOCK),
+            .M_AWCACHE (M_AXI_GP1_AWCACHE),
+            .M_AWPROT  (M_AXI_GP1_AWPROT),
+            .M_AWVALID (M_AXI_GP1_AWVALID),
+            .M_AWREADY (M_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP1_WID_FULL),
+            .M_WDATA  (M_AXI_GP1_WDATA),
+            .M_WSTRB  (M_AXI_GP1_WSTRB), 
+            .M_WLAST  (M_AXI_GP1_WLAST), 
+            .M_WVALID (M_AXI_GP1_WVALID),
+            .M_WREADY (M_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP1_BID_FULL),
+            .M_BRESP  (M_AXI_GP1_BRESP),
+            .M_BVALID (M_AXI_GP1_BVALID),
+            .M_BREADY (M_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP1_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP1_ARADDR),
+            .M_ARLEN   (M_AXI_GP1_ARLEN),
+            .M_ARSIZE  (M_AXI_GP1_ARSIZE),
+            .M_ARBURST (M_AXI_GP1_ARBURST),
+            .M_ARLOCK  (M_AXI_GP1_ARLOCK),
+            .M_ARCACHE (M_AXI_GP1_ARCACHE),
+            .M_ARPROT  (M_AXI_GP1_ARPROT),
+            .M_ARVALID (M_AXI_GP1_ARVALID),
+            .M_ARREADY (M_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP1_RID_FULL),
+            .M_RDATA  (M_AXI_GP1_RDATA),
+            .M_RRESP  (M_AXI_GP1_RRESP),
+            .M_RLAST  (M_AXI_GP1_RLAST),
+            .M_RVALID (M_AXI_GP1_RVALID),
+            .M_RREADY (M_AXI_GP1_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP1_AWQOS),
+            .M_ARQOS  (M_AXI_GP1_ARQOS)
+           );
+
+/* AXI Slave GP0 */
+  processing_system7_vip_v1_0_3_axi_slave #(C_USE_S_AXI_GP0, /// enable
+              axi_sgp0_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP0_BASEADDR,//// base address
+              C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access not supported
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
+            .S_ACLK   (S_AXI_GP0_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP0_AWID),
+            .S_AWADDR  (S_AXI_GP0_AWADDR),
+            .S_AWLEN   (S_AXI_GP0_AWLEN),
+            .S_AWSIZE  (S_AXI_GP0_AWSIZE),
+            .S_AWBURST (S_AXI_GP0_AWBURST),
+            .S_AWLOCK  (S_AXI_GP0_AWLOCK),
+            .S_AWCACHE (S_AXI_GP0_AWCACHE),
+            .S_AWPROT  (S_AXI_GP0_AWPROT),
+            .S_AWVALID (S_AXI_GP0_AWVALID),
+            .S_AWREADY (S_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP0_WID),
+            .S_WDATA  (S_AXI_GP0_WDATA),
+            .S_WSTRB  (S_AXI_GP0_WSTRB), 
+            .S_WLAST  (S_AXI_GP0_WLAST), 
+            .S_WVALID (S_AXI_GP0_WVALID),
+            .S_WREADY (S_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP0_BID),
+            .S_BRESP  (S_AXI_GP0_BRESP),
+            .S_BVALID (S_AXI_GP0_BVALID),
+            .S_BREADY (S_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP0_ARID),
+            .S_ARADDR  (S_AXI_GP0_ARADDR),
+            .S_ARLEN   (S_AXI_GP0_ARLEN),
+            .S_ARSIZE  (S_AXI_GP0_ARSIZE),
+            .S_ARBURST (S_AXI_GP0_ARBURST),
+            .S_ARLOCK  (S_AXI_GP0_ARLOCK),
+            .S_ARCACHE (S_AXI_GP0_ARCACHE),
+            .S_ARPROT  (S_AXI_GP0_ARPROT),
+            .S_ARVALID (S_AXI_GP0_ARVALID),
+            .S_ARREADY (S_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP0_RID),
+            .S_RDATA  (S_AXI_GP0_RDATA),
+            .S_RRESP  (S_AXI_GP0_RRESP),
+            .S_RLAST  (S_AXI_GP0_RLAST),
+            .S_RVALID (S_AXI_GP0_RVALID),
+            .S_RREADY (S_AXI_GP0_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP0_AWQOS),
+            .S_ARQOS  (S_AXI_GP0_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
+            .WR_DATA  (net_wr_data_gp0), 
+            .WR_ADDR  (net_wr_addr_gp0), 
+            .WR_BYTES  (net_wr_bytes_gp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp0), 
+            .WR_QOS (net_wr_qos_gp0),
+            .RD_REQ_DDR (net_rd_req_ddr_gp0),
+            .RD_REQ_OCM (net_rd_req_ocm_gp0),
+            .RD_REQ_REG (net_rd_req_reg_gp0),
+            .RD_ADDR (net_rd_addr_gp0),
+            .RD_DATA_DDR (net_rd_data_ddr_gp0),
+            .RD_DATA_OCM (net_rd_data_ocm_gp0),
+            .RD_DATA_REG (net_rd_data_reg_gp0),
+            .RD_BYTES (net_rd_bytes_gp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
+            .RD_QOS (net_rd_qos_gp0)
+
+);
+
+/* AXI Slave GP1 */
+  processing_system7_vip_v1_0_3_axi_slave #(C_USE_S_AXI_GP1, /// enable
+              axi_sgp1_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP1_BASEADDR,//// base address
+              C_S_AXI_GP1_HIGHADDR,/// HIGh_addr 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP1(.S_RESETN  (net_axi_gp1_rstn),
+            .S_ACLK    (S_AXI_GP1_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP1_AWID),
+            .S_AWADDR  (S_AXI_GP1_AWADDR),
+            .S_AWLEN   (S_AXI_GP1_AWLEN),
+            .S_AWSIZE  (S_AXI_GP1_AWSIZE),
+            .S_AWBURST (S_AXI_GP1_AWBURST),
+            .S_AWLOCK  (S_AXI_GP1_AWLOCK),
+            .S_AWCACHE (S_AXI_GP1_AWCACHE),
+            .S_AWPROT  (S_AXI_GP1_AWPROT),
+            .S_AWVALID (S_AXI_GP1_AWVALID),
+            .S_AWREADY (S_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP1_WID),
+            .S_WDATA  (S_AXI_GP1_WDATA),
+            .S_WSTRB  (S_AXI_GP1_WSTRB), 
+            .S_WLAST  (S_AXI_GP1_WLAST), 
+            .S_WVALID (S_AXI_GP1_WVALID),
+            .S_WREADY (S_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP1_BID),
+            .S_BRESP  (S_AXI_GP1_BRESP),
+            .S_BVALID (S_AXI_GP1_BVALID),
+            .S_BREADY (S_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP1_ARID),
+            .S_ARADDR  (S_AXI_GP1_ARADDR),
+            .S_ARLEN   (S_AXI_GP1_ARLEN),
+            .S_ARSIZE  (S_AXI_GP1_ARSIZE),
+            .S_ARBURST (S_AXI_GP1_ARBURST),
+            .S_ARLOCK  (S_AXI_GP1_ARLOCK),
+            .S_ARCACHE (S_AXI_GP1_ARCACHE),
+            .S_ARPROT  (S_AXI_GP1_ARPROT),
+            .S_ARVALID (S_AXI_GP1_ARVALID),
+            .S_ARREADY (S_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP1_RID),
+            .S_RDATA  (S_AXI_GP1_RDATA),
+            .S_RRESP  (S_AXI_GP1_RRESP),
+            .S_RLAST  (S_AXI_GP1_RLAST),
+            .S_RVALID (S_AXI_GP1_RVALID),
+            .S_RREADY (S_AXI_GP1_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP1_AWQOS),
+            .S_ARQOS  (S_AXI_GP1_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
+            .WR_DATA  (net_wr_data_gp1), 
+            .WR_ADDR  (net_wr_addr_gp1), 
+            .WR_BYTES  (net_wr_bytes_gp1), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp1), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp1), 
+            .WR_QOS (net_wr_qos_gp1),
+            .RD_REQ_OCM (net_rd_req_ocm_gp1),
+            .RD_REQ_DDR (net_rd_req_ddr_gp1),
+            .RD_REQ_REG (net_rd_req_reg_gp1),
+            .RD_ADDR (net_rd_addr_gp1),
+            .RD_DATA_DDR (net_rd_data_ddr_gp1),
+            .RD_DATA_OCM (net_rd_data_ocm_gp1),
+            .RD_DATA_REG (net_rd_data_reg_gp1),
+            .RD_BYTES (net_rd_bytes_gp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
+            .RD_QOS (net_rd_qos_gp1)
+
+);
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_hp.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_hp.v
new file mode 100644
index 0000000..7d7b090
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_axi_hp.v
@@ -0,0 +1,346 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_axi_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI HP ports
+ *
+ *****************************************************************************/
+
+/* AXI Slave HP0 */  
+ processing_system7_vip_v1_0_3_afi_slave #(  C_USE_S_AXI_HP0, // enable
+               axi_hp0_name, // name
+               C_S_AXI_HP0_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP0_BASEADDR, // slave base address
+               C_S_AXI_HP0_HIGHADDR, // slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+  S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
+            .S_ACLK   (S_AXI_HP0_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP0_AWID),
+            .S_AWADDR  (S_AXI_HP0_AWADDR),
+            .S_AWLEN   (S_AXI_HP0_AWLEN),
+            .S_AWSIZE  (S_AXI_HP0_AWSIZE),
+            .S_AWBURST (S_AXI_HP0_AWBURST),
+            .S_AWLOCK  (S_AXI_HP0_AWLOCK),
+            .S_AWCACHE (S_AXI_HP0_AWCACHE),
+            .S_AWPROT  (S_AXI_HP0_AWPROT),
+            .S_AWVALID (S_AXI_HP0_AWVALID),
+            .S_AWREADY (S_AXI_HP0_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP0_WID),
+            .S_WDATA  (S_AXI_HP0_WDATA),
+            .S_WSTRB  (S_AXI_HP0_WSTRB), 
+            .S_WLAST  (S_AXI_HP0_WLAST), 
+            .S_WVALID (S_AXI_HP0_WVALID),
+            .S_WREADY (S_AXI_HP0_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP0_BID),
+            .S_BRESP  (S_AXI_HP0_BRESP),
+            .S_BVALID (S_AXI_HP0_BVALID),
+            .S_BREADY (S_AXI_HP0_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP0_ARID),
+            .S_ARADDR  (S_AXI_HP0_ARADDR),
+            .S_ARLEN   (S_AXI_HP0_ARLEN),
+            .S_ARSIZE  (S_AXI_HP0_ARSIZE),
+            .S_ARBURST (S_AXI_HP0_ARBURST),
+            .S_ARLOCK  (S_AXI_HP0_ARLOCK),
+            .S_ARCACHE (S_AXI_HP0_ARCACHE),
+            .S_ARPROT  (S_AXI_HP0_ARPROT),
+            .S_ARVALID (S_AXI_HP0_ARVALID),
+            .S_ARREADY (S_AXI_HP0_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP0_RID),
+            .S_RDATA  (S_AXI_HP0_RDATA),
+            .S_RRESP  (S_AXI_HP0_RRESP),
+            .S_RLAST  (S_AXI_HP0_RLAST),
+            .S_RVALID (S_AXI_HP0_RVALID),
+            .S_RREADY (S_AXI_HP0_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP0_AWQOS), 
+            .S_ARQOS  (S_AXI_HP0_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP0_RCOUNT),
+            .S_WCOUNT (S_AXI_HP0_WCOUNT),
+            .S_RACOUNT (S_AXI_HP0_RACOUNT),
+            .S_WACOUNT (S_AXI_HP0_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
+            .WR_DATA  (net_wr_data_hp0), 
+            .WR_ADDR  (net_wr_addr_hp0), 
+            .WR_BYTES (net_wr_bytes_hp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp0), 
+            .WR_QOS (net_wr_qos_hp0),
+            .RD_REQ_DDR (net_rd_req_ddr_hp0),
+            .RD_REQ_OCM (net_rd_req_ocm_hp0),
+            .RD_ADDR (net_rd_addr_hp0),
+            .RD_DATA_DDR (net_rd_data_ddr_hp0),
+            .RD_DATA_OCM (net_rd_data_ocm_hp0),
+            .RD_BYTES (net_rd_bytes_hp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
+            .RD_QOS (net_rd_qos_hp0)
+ );
+
+/* AXI Slave HP1 */  
+ processing_system7_vip_v1_0_3_afi_slave #( C_USE_S_AXI_HP1, // enable
+               axi_hp1_name, // name
+               C_S_AXI_HP1_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP1_BASEADDR, // slave base address
+               C_S_AXI_HP1_HIGHADDR, // Slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
+            .S_ACLK   (S_AXI_HP1_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP1_AWID),
+            .S_AWADDR  (S_AXI_HP1_AWADDR),
+            .S_AWLEN   (S_AXI_HP1_AWLEN),
+            .S_AWSIZE  (S_AXI_HP1_AWSIZE),
+            .S_AWBURST (S_AXI_HP1_AWBURST),
+            .S_AWLOCK  (S_AXI_HP1_AWLOCK),
+            .S_AWCACHE (S_AXI_HP1_AWCACHE),
+            .S_AWPROT  (S_AXI_HP1_AWPROT),
+            .S_AWVALID (S_AXI_HP1_AWVALID),
+            .S_AWREADY (S_AXI_HP1_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP1_WID),
+            .S_WDATA  (S_AXI_HP1_WDATA),
+            .S_WSTRB  (S_AXI_HP1_WSTRB), 
+            .S_WLAST  (S_AXI_HP1_WLAST), 
+            .S_WVALID (S_AXI_HP1_WVALID),
+            .S_WREADY (S_AXI_HP1_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP1_BID),
+            .S_BRESP  (S_AXI_HP1_BRESP),
+            .S_BVALID (S_AXI_HP1_BVALID),
+            .S_BREADY (S_AXI_HP1_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP1_ARID),
+            .S_ARADDR  (S_AXI_HP1_ARADDR),
+            .S_ARLEN   (S_AXI_HP1_ARLEN),
+            .S_ARSIZE  (S_AXI_HP1_ARSIZE),
+            .S_ARBURST (S_AXI_HP1_ARBURST),
+            .S_ARLOCK  (S_AXI_HP1_ARLOCK),
+            .S_ARCACHE (S_AXI_HP1_ARCACHE),
+            .S_ARPROT  (S_AXI_HP1_ARPROT),
+            .S_ARVALID (S_AXI_HP1_ARVALID),
+            .S_ARREADY (S_AXI_HP1_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP1_RID),
+            .S_RDATA  (S_AXI_HP1_RDATA),
+            .S_RRESP  (S_AXI_HP1_RRESP),
+            .S_RLAST  (S_AXI_HP1_RLAST),
+            .S_RVALID (S_AXI_HP1_RVALID),
+            .S_RREADY (S_AXI_HP1_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP1_AWQOS), 
+            .S_ARQOS  (S_AXI_HP1_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP1_RCOUNT),
+            .S_WCOUNT (S_AXI_HP1_WCOUNT),
+            .S_RACOUNT (S_AXI_HP1_RACOUNT),
+            .S_WACOUNT (S_AXI_HP1_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
+            .WR_DATA  (net_wr_data_hp1), 
+            .WR_ADDR  (net_wr_addr_hp1), 
+            .WR_BYTES (net_wr_bytes_hp1), 
+            .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), 
+            .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), 
+            .WR_QOS (net_wr_qos_hp1),
+            .RD_REQ_DDR (net_rd_req_ddr_hp1),
+            .RD_REQ_OCM (net_rd_req_ocm_hp1),
+            .RD_ADDR (net_rd_addr_hp1),
+            .RD_DATA_DDR (net_rd_data_ddr_hp1),
+            .RD_DATA_OCM (net_rd_data_ocm_hp1),
+            .RD_BYTES (net_rd_bytes_hp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
+            .RD_QOS (net_rd_qos_hp1)
+
+  );
+
+/* AXI Slave HP2 */  
+ processing_system7_vip_v1_0_3_afi_slave #( C_USE_S_AXI_HP2, // enable
+               axi_hp2_name, // name
+               C_S_AXI_HP2_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP2_BASEADDR, // slave base address
+               C_S_AXI_HP2_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
+            .S_ACLK    (S_AXI_HP2_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP2_AWID),
+            .S_AWADDR  (S_AXI_HP2_AWADDR),
+            .S_AWLEN   (S_AXI_HP2_AWLEN),
+            .S_AWSIZE  (S_AXI_HP2_AWSIZE),
+            .S_AWBURST (S_AXI_HP2_AWBURST),
+            .S_AWLOCK  (S_AXI_HP2_AWLOCK),
+            .S_AWCACHE (S_AXI_HP2_AWCACHE),
+            .S_AWPROT  (S_AXI_HP2_AWPROT),
+            .S_AWVALID (S_AXI_HP2_AWVALID),
+            .S_AWREADY (S_AXI_HP2_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP2_WID),
+            .S_WDATA  (S_AXI_HP2_WDATA),
+            .S_WSTRB  (S_AXI_HP2_WSTRB), 
+            .S_WLAST  (S_AXI_HP2_WLAST), 
+            .S_WVALID (S_AXI_HP2_WVALID),
+            .S_WREADY (S_AXI_HP2_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP2_BID),
+            .S_BRESP  (S_AXI_HP2_BRESP),
+            .S_BVALID (S_AXI_HP2_BVALID),
+            .S_BREADY (S_AXI_HP2_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP2_ARID),
+            .S_ARADDR  (S_AXI_HP2_ARADDR),
+            .S_ARLEN   (S_AXI_HP2_ARLEN),
+            .S_ARSIZE  (S_AXI_HP2_ARSIZE),
+            .S_ARBURST (S_AXI_HP2_ARBURST),
+            .S_ARLOCK  (S_AXI_HP2_ARLOCK),
+            .S_ARCACHE (S_AXI_HP2_ARCACHE),
+            .S_ARPROT  (S_AXI_HP2_ARPROT),
+            .S_ARVALID (S_AXI_HP2_ARVALID),
+            .S_ARREADY (S_AXI_HP2_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP2_RID),
+            .S_RDATA  (S_AXI_HP2_RDATA),
+            .S_RRESP  (S_AXI_HP2_RRESP),
+            .S_RLAST  (S_AXI_HP2_RLAST),
+            .S_RVALID (S_AXI_HP2_RVALID),
+            .S_RREADY (S_AXI_HP2_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP2_AWQOS), 
+            .S_ARQOS  (S_AXI_HP2_ARQOS), 
+             // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP2_RCOUNT),
+            .S_WCOUNT (S_AXI_HP2_WCOUNT),
+            .S_RACOUNT (S_AXI_HP2_RACOUNT),
+            .S_WACOUNT (S_AXI_HP2_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
+            .WR_DATA  (net_wr_data_hp2), 
+            .WR_ADDR  (net_wr_addr_hp2), 
+            .WR_BYTES (net_wr_bytes_hp2), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp2), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp2), 
+            .WR_QOS (net_wr_qos_hp2),
+            .RD_REQ_DDR (net_rd_req_ddr_hp2),
+            .RD_REQ_OCM (net_rd_req_ocm_hp2),
+            .RD_ADDR (net_rd_addr_hp2),
+            .RD_DATA_DDR (net_rd_data_ddr_hp2),
+            .RD_DATA_OCM (net_rd_data_ocm_hp2),
+            .RD_BYTES (net_rd_bytes_hp2),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
+            .RD_QOS (net_rd_qos_hp2)
+
+ );
+
+/* AXI Slave HP3 */  
+ processing_system7_vip_v1_0_3_afi_slave #( C_USE_S_AXI_HP3, // enable
+               axi_hp3_name, // name
+               C_S_AXI_HP3_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP3_BASEADDR, // slave base address
+               C_S_AXI_HP3_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
+            .S_ACLK   (S_AXI_HP3_ACLK),
+            // Write ADDRESS CHANNEL
+            .S_AWID    (S_AXI_HP3_AWID),
+            .S_AWADDR  (S_AXI_HP3_AWADDR),
+            .S_AWLEN   (S_AXI_HP3_AWLEN),
+            .S_AWSIZE  (S_AXI_HP3_AWSIZE),
+            .S_AWBURST (S_AXI_HP3_AWBURST),
+            .S_AWLOCK  (S_AXI_HP3_AWLOCK),
+            .S_AWCACHE (S_AXI_HP3_AWCACHE),
+            .S_AWPROT  (S_AXI_HP3_AWPROT),
+            .S_AWVALID (S_AXI_HP3_AWVALID),
+            .S_AWREADY (S_AXI_HP3_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP3_WID),
+            .S_WDATA  (S_AXI_HP3_WDATA),
+            .S_WSTRB  (S_AXI_HP3_WSTRB), 
+            .S_WLAST  (S_AXI_HP3_WLAST), 
+            .S_WVALID (S_AXI_HP3_WVALID),
+            .S_WREADY (S_AXI_HP3_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP3_BID),
+            .S_BRESP  (S_AXI_HP3_BRESP),
+            .S_BVALID (S_AXI_HP3_BVALID),
+            .S_BREADY (S_AXI_HP3_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP3_ARID),
+            .S_ARADDR  (S_AXI_HP3_ARADDR),
+            .S_ARLEN   (S_AXI_HP3_ARLEN),
+            .S_ARSIZE  (S_AXI_HP3_ARSIZE),
+            .S_ARBURST (S_AXI_HP3_ARBURST),
+            .S_ARLOCK  (S_AXI_HP3_ARLOCK),
+            .S_ARCACHE (S_AXI_HP3_ARCACHE),
+            .S_ARPROT  (S_AXI_HP3_ARPROT),
+            .S_ARVALID (S_AXI_HP3_ARVALID),
+            .S_ARREADY (S_AXI_HP3_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP3_RID),
+            .S_RDATA  (S_AXI_HP3_RDATA),
+            .S_RRESP  (S_AXI_HP3_RRESP),
+            .S_RLAST  (S_AXI_HP3_RLAST),
+            .S_RVALID (S_AXI_HP3_RVALID),
+            .S_RREADY (S_AXI_HP3_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP3_AWQOS), 
+            .S_ARQOS  (S_AXI_HP3_ARQOS),
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP3_RCOUNT),
+            .S_WCOUNT (S_AXI_HP3_WCOUNT),
+            .S_RACOUNT (S_AXI_HP3_RACOUNT),
+            .S_WACOUNT (S_AXI_HP3_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
+            .WR_DATA  (net_wr_data_hp3), 
+            .WR_ADDR  (net_wr_addr_hp3), 
+            .WR_BYTES (net_wr_bytes_hp3), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp3), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp3), 
+            .WR_QOS (net_wr_qos_hp3),
+            .RD_REQ_DDR (net_rd_req_ddr_hp3),
+            .RD_REQ_OCM (net_rd_req_ocm_hp3),
+            .RD_ADDR (net_rd_addr_hp3),
+            .RD_DATA_DDR (net_rd_data_ddr_hp3),
+            .RD_DATA_OCM (net_rd_data_ocm_hp3),
+            .RD_BYTES (net_rd_bytes_hp3),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
+            .RD_QOS (net_rd_qos_hp3)
+ );
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_local_params.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_local_params.v
new file mode 100644
index 0000000..b86583a
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_local_params.v
@@ -0,0 +1,239 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_local_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters used in Zynq VIP
+ *
+ *****************************************************************************/
+
+/* local */ 
+parameter m_axi_gp0_baseaddr = 32'h4000_0000;
+parameter m_axi_gp1_baseaddr = 32'h8000_0000;
+parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
+parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
+
+parameter addr_width = 32;   // maximum address width
+parameter data_width = 32;   // maximum data width.
+parameter max_chars  = 128;  // max characters for file name
+parameter mem_width  = data_width/8; /// memory width in bytes
+parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
+parameter int_width  = 32; //integre width
+
+/* for internal read/write APIs used for data transfers */
+parameter max_burst_len   = 16;  /// maximum brst length on axi 
+parameter max_data_width  = 64; // maximum data width for internal AXI bursts 
+parameter max_burst_bits  = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts 
+parameter max_burst_bytes = (max_burst_bits)/8;                // maximum data bytes in each transfer 
+parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts 
+
+parameter max_registers   = 32;
+parameter max_regs_width  = clogb2(max_registers);
+
+parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; 
+
+/* Interrupt bits supported */
+parameter irq_width = 16;
+
+/* GP Master0 & Master1 address decode */
+parameter GP_M0 = 2'b01;
+parameter GP_M1 = 2'b10;
+
+parameter ALL_RANDOM= 2'b00;
+parameter ALL_ZEROS = 2'b01;
+parameter ALL_ONES  = 2'b10;
+
+parameter ddr_start_addr = 32'h0008_0000;
+parameter ddr_end_addr   = 32'h3FFF_FFFF;
+
+parameter ocm_start_addr = 32'h0000_0000;
+parameter ocm_end_addr   = 32'h0003_FFFF;
+parameter high_ocm_start_addr = 32'hFFFC_0000;
+parameter high_ocm_end_addr   = 32'hFFFF_FFFF;
+parameter ocm_low_addr   = 32'hFFFF_0000;
+
+parameter reg_start_addr = 32'hE000_0000;
+parameter reg_end_addr   = 32'hF8F0_2F80;
+
+
+/* for Master port APIs and AXI protocol related signal widths*/
+parameter axi_burst_len  = 16;
+parameter axi_len_width  = clogb2(axi_burst_len);
+parameter axi_size_width = 3;
+parameter axi_brst_type_width = 2;
+parameter axi_lock_width = 2;
+parameter axi_cache_width = 4;
+parameter axi_prot_width = 3;
+parameter axi_rsp_width = 2;
+parameter axi_mgp_data_width = 32;
+parameter axi_mgp_id_width   = 12;
+parameter axi_mgp_outstanding = 8;
+parameter axi_mgp_wr_id = 12'hC00;
+parameter axi_mgp_rd_id = 12'hC0C;
+parameter axi_mgp0_name  = "M_AXI_GP0";
+parameter axi_mgp1_name  = "M_AXI_GP1";
+parameter axi_qos_width  = 4;
+parameter max_transfer_bytes = 128; // For Master APIs.
+parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
+
+
+/* for GP slave ports*/
+parameter axi_sgp_data_width = 32;
+parameter axi_sgp_id_width   = 6;
+parameter axi_sgp_rd_outstanding = 8;
+parameter axi_sgp_wr_outstanding = 8;
+parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
+parameter axi_sgp0_name  = "S_AXI_GP0";
+parameter axi_sgp1_name  = "S_AXI_GP1";
+
+/* for ACP slave ports*/
+parameter axi_acp_data_width = 64;
+parameter axi_acp_id_width   = 3;
+parameter axi_acp_rd_outstanding = 7;
+parameter axi_acp_wr_outstanding = 3;
+parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
+parameter axi_acp_name  = "S_AXI_ACP";
+
+/* for HP slave ports*/
+parameter axi_hp_id_width   = 6;
+parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
+parameter axi_hp0_name  = "S_AXI_HP0";
+parameter axi_hp1_name  = "S_AXI_HP1";
+parameter axi_hp2_name  = "S_AXI_HP2";
+parameter axi_hp3_name  = "S_AXI_HP3";
+
+
+parameter axi_slv_excl_support = 0; // For Slave  ports EXCL access is not supported
+parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
+
+/* AXI transfer types */
+parameter AXI_FIXED = 2'b00;
+parameter AXI_INCR  = 2'b01;
+parameter AXI_WRAP  = 2'b10;
+
+/* Exclusive Access */
+parameter AXI_NRML  = 2'b00;
+parameter AXI_EXCL  = 2'b01;
+parameter AXI_LOCK  = 2'b10;
+
+/* AXI Response types */
+parameter AXI_OK = 2'b00;
+parameter AXI_EXCL_OK  = 2'b01;
+parameter AXI_SLV_ERR  = 2'b10;
+parameter AXI_DEC_ERR  = 2'b11;
+
+function automatic integer clogb2;
+  input [31:0] value;
+  begin
+      value = value - 1;
+      for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
+          value = value >> 1;
+      end
+  end
+endfunction
+
+/* needed only for AFI modules  and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
+  /* WR FIFO data */
+  parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  parameter wr_bytes_lsb = 0;
+  parameter wr_bytes_msb = max_burst_bytes_width;
+  parameter wr_addr_lsb  = wr_bytes_msb + 1;
+  parameter wr_addr_msb  = wr_addr_lsb + addr_width-1;
+  parameter wr_data_lsb  = wr_addr_msb + 1;
+  parameter wr_data_msb  = wr_data_lsb + max_burst_bits-1;
+  parameter wr_qos_lsb   = wr_data_msb + 1;
+  parameter wr_qos_msb   = wr_qos_lsb + axi_qos_width-1;
+ 
+  /* WR AFI FIFO data */ 
+    /* ID -  1071:1066
+     Resp - 1065:1064
+     data - 1063:40   
+     address - 39:8
+     valid_bytes - 7:0
+    */
+  parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
+  parameter wr_afi_bytes_lsb = 0;
+  parameter wr_afi_bytes_msb = max_burst_bytes_width;
+  parameter wr_afi_addr_lsb  = wr_afi_bytes_msb + 1;
+  parameter wr_afi_addr_msb  = wr_afi_addr_lsb + addr_width-1;
+  parameter wr_afi_data_lsb  = wr_afi_addr_msb + 1;
+  parameter wr_afi_data_msb  = wr_afi_data_lsb + max_burst_bits-1; 
+  parameter wr_afi_rsp_lsb   = wr_afi_data_msb + 1; 
+  parameter wr_afi_rsp_msb   = wr_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter wr_afi_id_lsb    = wr_afi_rsp_msb + 1; 
+  parameter wr_afi_id_msb    = wr_afi_id_lsb + axi_hp_id_width-1; 
+  parameter wr_afi_ln_lsb    = wr_afi_id_msb + 1;
+  parameter wr_afi_ln_msb    = wr_afi_ln_lsb + axi_len_width-1;
+  parameter wr_afi_qos_lsb   = wr_afi_ln_msb + 1;
+  parameter wr_afi_qos_msb   = wr_afi_qos_lsb + axi_qos_width-1;
+
+
+  parameter afi_fifo_size    = 1024; /// AFI FIFO is stored as 1024-bytes 
+  parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
+  parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
+
+/* for interconnect fifo models */
+  parameter intr_max_outstanding = 8;
+  parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
+  parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width +  axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
+  parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
+
+  //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  parameter rd_afi_bytes_lsb = 0;
+  parameter rd_afi_bytes_msb = max_burst_bytes_width;
+  parameter rd_afi_rsp_lsb   = rd_afi_bytes_msb + 1; 
+  parameter rd_afi_rsp_msb   = rd_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter rd_afi_id_lsb    = rd_afi_rsp_msb + 1; 
+  parameter rd_afi_id_msb    = rd_afi_id_lsb + axi_hp_id_width-1; 
+  parameter rd_afi_ln_lsb    = rd_afi_id_msb + 1;
+  parameter rd_afi_ln_msb    = rd_afi_ln_lsb + axi_len_width-1;
+  parameter rd_afi_brst_lsb  = rd_afi_ln_msb + 1;
+  parameter rd_afi_brst_msb  = rd_afi_brst_lsb + axi_brst_type_width-1;
+  parameter rd_afi_siz_lsb   = rd_afi_brst_msb + 1;
+  parameter rd_afi_siz_msb   = rd_afi_siz_lsb + axi_size_width-1;
+  parameter rd_afi_addr_lsb  = rd_afi_siz_msb + 1;
+  parameter rd_afi_addr_msb  = rd_afi_addr_lsb + addr_width-1;
+  parameter rd_afi_data_lsb  = rd_afi_addr_msb + 1;
+  parameter rd_afi_data_msb  = rd_afi_data_lsb + max_burst_bits-1; 
+
+
+/* Latency types */
+ parameter BEST_CASE  = 0;
+ parameter AVG_CASE   = 1;
+ parameter WORST_CASE = 2;
+ parameter RANDOM_CASE  = 3;
+
+/* Latency Parameters ACP  */
+  parameter acp_wr_min   =  21;
+  parameter acp_wr_avg   =  16;
+  parameter acp_wr_max   =  27;
+  parameter acp_rd_min   =  34;
+  parameter acp_rd_avg   =  125;
+  parameter acp_rd_max   =  130; 
+
+/* Latency Parameters GP  */
+  parameter gp_wr_min   =  21;
+  parameter gp_wr_avg   =  16;
+  parameter gp_wr_max   =  46;
+  parameter gp_rd_min   =  38;
+  parameter gp_rd_avg   =  125;
+  parameter gp_rd_max   =  130; 
+
+/* Latency Parameters HP  */
+  parameter afi_wr_min  =  37;
+  parameter afi_wr_avg  =  41;
+  parameter afi_wr_max  =  42;
+  parameter afi_rd_min  =  41;
+  parameter afi_rd_avg  =  221;
+  parameter afi_rd_max  =  229; 
+
+/* ID VALID and INVALID */
+  parameter secure_access_enabled = 0;
+  parameter id_invalid = 0;
+  parameter id_valid = 1;
+
+/* Display */
+  parameter DISP_INFO = "*ZYNQ_VIP_INFO";
+  parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
+  parameter DISP_ERR  = "*ZYNQ_VIP_ERROR";
+  parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_init.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_init.v
new file mode 100644
index 0000000..1a43bbd
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_init.v
@@ -0,0 +1,2924 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_reg_init.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Initialize register default values.
+ *
+ *****************************************************************************/
+
+// Register default value info for chip pele_ps
+// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
+// 54 modules, 2532 registers.
+
+
+// ************************************************************
+//   Module afi0 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL);
+set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS);
+set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG);
+set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL);
+set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS);
+set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi1 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL);
+set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS);
+set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG);
+set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL);
+set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS);
+set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi2 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL);
+set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS);
+set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG);
+set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL);
+set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS);
+set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module afi3 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL);
+set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP);
+set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS);
+set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL);
+set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG);
+set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL);
+set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP);
+set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS);
+set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL);
+set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG);
+
+// ************************************************************
+//   Module can0 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( can0__SRR, val_can0__SRR);
+set_reset_data( can0__MSR, val_can0__MSR);
+set_reset_data( can0__BRPR, val_can0__BRPR);
+set_reset_data( can0__BTR, val_can0__BTR);
+set_reset_data( can0__ECR, val_can0__ECR);
+set_reset_data( can0__ESR, val_can0__ESR);
+set_reset_data( can0__SR, val_can0__SR);
+set_reset_data( can0__ISR, val_can0__ISR);
+set_reset_data( can0__IER, val_can0__IER);
+set_reset_data( can0__ICR, val_can0__ICR);
+set_reset_data( can0__TCR, val_can0__TCR);
+set_reset_data( can0__WIR, val_can0__WIR);
+set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID);
+set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC);
+set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1);
+set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2);
+set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID);
+set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC);
+set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1);
+set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2);
+set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID);
+set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC);
+set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1);
+set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2);
+set_reset_data( can0__AFR, val_can0__AFR);
+set_reset_data( can0__AFMR1, val_can0__AFMR1);
+set_reset_data( can0__AFIR1, val_can0__AFIR1);
+set_reset_data( can0__AFMR2, val_can0__AFMR2);
+set_reset_data( can0__AFIR2, val_can0__AFIR2);
+set_reset_data( can0__AFMR3, val_can0__AFMR3);
+set_reset_data( can0__AFIR3, val_can0__AFIR3);
+set_reset_data( can0__AFMR4, val_can0__AFMR4);
+set_reset_data( can0__AFIR4, val_can0__AFIR4);
+
+// ************************************************************
+//   Module can1 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( can1__SRR, val_can1__SRR);
+set_reset_data( can1__MSR, val_can1__MSR);
+set_reset_data( can1__BRPR, val_can1__BRPR);
+set_reset_data( can1__BTR, val_can1__BTR);
+set_reset_data( can1__ECR, val_can1__ECR);
+set_reset_data( can1__ESR, val_can1__ESR);
+set_reset_data( can1__SR, val_can1__SR);
+set_reset_data( can1__ISR, val_can1__ISR);
+set_reset_data( can1__IER, val_can1__IER);
+set_reset_data( can1__ICR, val_can1__ICR);
+set_reset_data( can1__TCR, val_can1__TCR);
+set_reset_data( can1__WIR, val_can1__WIR);
+set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID);
+set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC);
+set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1);
+set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2);
+set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID);
+set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC);
+set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1);
+set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2);
+set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID);
+set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC);
+set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1);
+set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2);
+set_reset_data( can1__AFR, val_can1__AFR);
+set_reset_data( can1__AFMR1, val_can1__AFMR1);
+set_reset_data( can1__AFIR1, val_can1__AFIR1);
+set_reset_data( can1__AFMR2, val_can1__AFMR2);
+set_reset_data( can1__AFIR2, val_can1__AFIR2);
+set_reset_data( can1__AFMR3, val_can1__AFMR3);
+set_reset_data( can1__AFIR3, val_can1__AFIR3);
+set_reset_data( can1__AFMR4, val_can1__AFMR4);
+set_reset_data( can1__AFIR4, val_can1__AFIR4);
+
+// ************************************************************
+//   Module ddrc ddrc
+//   doc version: 1.25
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl);
+set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg);
+set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg);
+set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg);
+set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg);
+set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0);
+set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1);
+set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2);
+set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3);
+set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4);
+set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param);
+set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg);
+set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg);
+set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr);
+set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ);
+set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank);
+set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col);
+set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row);
+set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg);
+set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg);
+set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt);
+set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg);
+set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib);
+set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold);
+set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1);
+set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2);
+set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3);
+set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4);
+set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5);
+set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6);
+set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01);
+set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ);
+set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg);
+set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg);
+set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c);
+set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d);
+set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing);
+set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2);
+set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing);
+set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET);
+set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET);
+set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET);
+set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET);
+set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub);
+set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET);
+set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET);
+set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable);
+set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0);
+set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1);
+set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2);
+set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3);
+set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0);
+set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1);
+set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2);
+set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3);
+set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0);
+set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1);
+set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2);
+set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3);
+set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0);
+set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1);
+set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2);
+set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3);
+set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0);
+set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1);
+set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2);
+set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3);
+set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0);
+set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1);
+set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2);
+set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3);
+set_reset_data( ddrc__reg_64, val_ddrc__reg_64);
+set_reset_data( ddrc__reg_65, val_ddrc__reg_65);
+set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0);
+set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1);
+set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2);
+set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3);
+set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710);
+set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711);
+set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712);
+set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713);
+set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0);
+set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1);
+set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2);
+set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3);
+set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts);
+set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts);
+set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2);
+set_reset_data( ddrc__axi_id, val_ddrc__axi_id);
+set_reset_data( ddrc__page_mask, val_ddrc__page_mask);
+set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0);
+set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1);
+set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2);
+set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3);
+set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0);
+set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1);
+set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2);
+set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3);
+set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0);
+set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1);
+set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2);
+set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3);
+set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0);
+set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1);
+set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2);
+set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3);
+set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20);
+set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21);
+set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22);
+set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23);
+set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30);
+set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31);
+set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32);
+set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33);
+set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg);
+set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0);
+set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1);
+set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2);
+set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3);
+set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read);
+set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0);
+set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1);
+set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2);
+set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3);
+set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm);
+set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm);
+set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm);
+
+// ************************************************************
+//   Module debug_axim axim
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL);
+set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS);
+set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL);
+set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL);
+set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS);
+set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL);
+set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL);
+set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH);
+set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT);
+set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER);
+set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT);
+set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD);
+set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT);
+set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK);
+set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER);
+set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER);
+set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC);
+set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK);
+set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER);
+set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER);
+set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC);
+set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK);
+set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER);
+set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER);
+set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC);
+set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK);
+set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER);
+set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER);
+set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC);
+set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK);
+set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER);
+set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER);
+set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC);
+set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK);
+set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER);
+set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER);
+set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC);
+set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK);
+set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER);
+set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER);
+set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC);
+set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK);
+set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER);
+set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER);
+set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC);
+set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL);
+set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT);
+set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK);
+set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN);
+set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK);
+set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA);
+set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS);
+set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1);
+set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0);
+set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL);
+set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET);
+set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR);
+set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS);
+set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS);
+set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS);
+set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID);
+set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE);
+set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4);
+set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5);
+set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6);
+set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7);
+set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0);
+set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1);
+set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2);
+set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3);
+set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0);
+set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1);
+set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2);
+set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_cti0 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL);
+set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK);
+set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET);
+set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR);
+set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE);
+set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0);
+set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1);
+set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2);
+set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3);
+set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4);
+set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5);
+set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6);
+set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7);
+set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0);
+set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1);
+set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2);
+set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3);
+set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4);
+set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5);
+set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6);
+set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7);
+set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS);
+set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS);
+set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS);
+set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS);
+set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE);
+set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL);
+set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK);
+set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK);
+set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT);
+set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT);
+set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK);
+set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK);
+set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN);
+set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN);
+set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL);
+set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR);
+set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR);
+set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR);
+set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR);
+set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR);
+set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID);
+set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR);
+set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4);
+set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5);
+set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6);
+set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7);
+set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0);
+set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1);
+set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2);
+set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3);
+set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0);
+set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1);
+set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2);
+set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_cti1 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL);
+set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK);
+set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET);
+set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR);
+set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE);
+set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0);
+set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1);
+set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2);
+set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3);
+set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4);
+set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5);
+set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6);
+set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7);
+set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0);
+set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1);
+set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2);
+set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3);
+set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4);
+set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5);
+set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6);
+set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7);
+set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS);
+set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS);
+set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS);
+set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS);
+set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE);
+set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL);
+set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK);
+set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK);
+set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT);
+set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT);
+set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK);
+set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK);
+set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN);
+set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN);
+set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL);
+set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR);
+set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR);
+set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR);
+set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR);
+set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR);
+set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID);
+set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR);
+set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4);
+set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5);
+set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6);
+set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7);
+set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0);
+set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1);
+set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2);
+set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3);
+set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0);
+set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1);
+set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2);
+set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_pmu0 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4);
+set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5);
+set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4);
+set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5);
+set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET);
+set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR);
+set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET);
+set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR);
+set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR);
+set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC);
+set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR);
+set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR);
+
+// ************************************************************
+//   Module debug_cpu_pmu1 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4);
+set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5);
+set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4);
+set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5);
+set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET);
+set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR);
+set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET);
+set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR);
+set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR);
+set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC);
+set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR);
+set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR);
+
+// ************************************************************
+//   Module debug_cpu_ptm0 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR);
+set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR);
+set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER);
+set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR);
+set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR);
+set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR);
+set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1);
+set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1);
+set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2);
+set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3);
+set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4);
+set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5);
+set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6);
+set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7);
+set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8);
+set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1);
+set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2);
+set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3);
+set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4);
+set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5);
+set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6);
+set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7);
+set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2);
+set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1);
+set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2);
+set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR);
+set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR);
+set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1);
+set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2);
+set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1);
+set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR);
+set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR);
+set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR);
+set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER);
+set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR);
+set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR);
+set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR);
+set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR);
+set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR);
+set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT);
+set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN);
+set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER);
+set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0);
+set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2);
+set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID);
+set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0);
+set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL);
+set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR);
+set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR);
+set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR);
+set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR);
+set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR);
+set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID);
+set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR);
+set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4);
+set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5);
+set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6);
+set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7);
+set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0);
+set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1);
+set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2);
+set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3);
+set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0);
+set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1);
+set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2);
+set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3);
+
+// ************************************************************
+//   Module debug_cpu_ptm1 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR);
+set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR);
+set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER);
+set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR);
+set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR);
+set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR);
+set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1);
+set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1);
+set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2);
+set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3);
+set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4);
+set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5);
+set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6);
+set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7);
+set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8);
+set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1);
+set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2);
+set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3);
+set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4);
+set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5);
+set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6);
+set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7);
+set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2);
+set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1);
+set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2);
+set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR);
+set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR);
+set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1);
+set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2);
+set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1);
+set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR);
+set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR);
+set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR);
+set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER);
+set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR);
+set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR);
+set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR);
+set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR);
+set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR);
+set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT);
+set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN);
+set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER);
+set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0);
+set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2);
+set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID);
+set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0);
+set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL);
+set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR);
+set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR);
+set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR);
+set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR);
+set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR);
+set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID);
+set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR);
+set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4);
+set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5);
+set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6);
+set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7);
+set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0);
+set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1);
+set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2);
+set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3);
+set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0);
+set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1);
+set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2);
+set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_axim cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL);
+set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK);
+set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET);
+set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR);
+set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE);
+set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0);
+set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1);
+set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2);
+set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3);
+set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4);
+set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5);
+set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6);
+set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7);
+set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0);
+set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1);
+set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2);
+set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3);
+set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4);
+set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5);
+set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6);
+set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7);
+set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS);
+set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS);
+set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS);
+set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE);
+set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL);
+set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK);
+set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK);
+set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT);
+set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT);
+set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK);
+set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK);
+set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN);
+set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN);
+set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL);
+set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR);
+set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR);
+set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR);
+set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR);
+set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR);
+set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID);
+set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR);
+set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4);
+set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5);
+set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6);
+set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7);
+set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0);
+set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1);
+set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2);
+set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3);
+set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0);
+set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1);
+set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2);
+set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_etb_tpiu cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL);
+set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR);
+set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6);
+set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6);
+set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7);
+set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS);
+set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE);
+set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL);
+set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK);
+set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT);
+set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK);
+set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN);
+set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN);
+set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL);
+set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR);
+set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR);
+set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR);
+set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR);
+set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR);
+set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID);
+set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2);
+set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3);
+set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0);
+set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1);
+set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2);
+set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3);
+
+// ************************************************************
+//   Module debug_cti_ftm cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL);
+set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK);
+set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET);
+set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR);
+set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE);
+set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0);
+set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1);
+set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2);
+set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3);
+set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4);
+set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5);
+set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6);
+set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7);
+set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0);
+set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1);
+set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2);
+set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3);
+set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4);
+set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5);
+set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6);
+set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7);
+set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS);
+set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS);
+set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS);
+set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS);
+set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE);
+set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL);
+set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK);
+set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK);
+set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT);
+set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT);
+set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK);
+set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK);
+set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN);
+set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN);
+set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL);
+set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR);
+set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR);
+set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR);
+set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR);
+set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR);
+set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID);
+set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR);
+set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4);
+set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5);
+set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6);
+set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7);
+set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0);
+set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1);
+set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2);
+set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3);
+set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0);
+set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1);
+set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2);
+set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3);
+
+// ************************************************************
+//   Module debug_dap_rom dap
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00);
+set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01);
+set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02);
+set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03);
+set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04);
+set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05);
+set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06);
+set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07);
+set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08);
+set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09);
+set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10);
+set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11);
+set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12);
+set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13);
+set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14);
+set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15);
+set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4);
+set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5);
+set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6);
+set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7);
+set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0);
+set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1);
+set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2);
+set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3);
+set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0);
+set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1);
+set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2);
+set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3);
+
+// ************************************************************
+//   Module debug_etb etb
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_etb__RDP, val_debug_etb__RDP);
+set_reset_data( debug_etb__STS, val_debug_etb__STS);
+set_reset_data( debug_etb__RRD, val_debug_etb__RRD);
+set_reset_data( debug_etb__RRP, val_debug_etb__RRP);
+set_reset_data( debug_etb__RWP, val_debug_etb__RWP);
+set_reset_data( debug_etb__TRG, val_debug_etb__TRG);
+set_reset_data( debug_etb__CTL, val_debug_etb__CTL);
+set_reset_data( debug_etb__RWD, val_debug_etb__RWD);
+set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR);
+set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR);
+set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0);
+set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK);
+set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN);
+set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0);
+set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2);
+set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1);
+set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0);
+set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR);
+set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR);
+set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR);
+set_reset_data( debug_etb__LAR, val_debug_etb__LAR);
+set_reset_data( debug_etb__LSR, val_debug_etb__LSR);
+set_reset_data( debug_etb__ASR, val_debug_etb__ASR);
+set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID);
+set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR);
+set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4);
+set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5);
+set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6);
+set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7);
+set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0);
+set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1);
+set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2);
+set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3);
+set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0);
+set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1);
+set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2);
+set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3);
+
+// ************************************************************
+//   Module debug_ftm ftm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL);
+set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS);
+set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL);
+set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0);
+set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1);
+set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2);
+set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3);
+set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0);
+set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1);
+set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2);
+set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3);
+set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE);
+set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD);
+set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT);
+set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID);
+set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK);
+set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER);
+set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS);
+set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT);
+set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0);
+set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2);
+set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1);
+set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0);
+set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR);
+set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET);
+set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR);
+set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS);
+set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS);
+set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS);
+set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID);
+set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE);
+set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4);
+set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5);
+set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6);
+set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7);
+set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0);
+set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1);
+set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2);
+set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3);
+set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0);
+set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1);
+set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2);
+set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3);
+
+// ************************************************************
+//   Module debug_funnel funnel
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_funnel__Control, val_debug_funnel__Control);
+set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl);
+set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0);
+set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2);
+set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1);
+set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0);
+set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR);
+set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR);
+set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR);
+set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR);
+set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR);
+set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR);
+set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID);
+set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR);
+set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4);
+set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5);
+set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6);
+set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7);
+set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0);
+set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1);
+set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2);
+set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3);
+set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0);
+set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1);
+set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2);
+set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3);
+
+// ************************************************************
+//   Module debug_itm itm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00);
+set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01);
+set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02);
+set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03);
+set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04);
+set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05);
+set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06);
+set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07);
+set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08);
+set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09);
+set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10);
+set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11);
+set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12);
+set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13);
+set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14);
+set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15);
+set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16);
+set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17);
+set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18);
+set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19);
+set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20);
+set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21);
+set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22);
+set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23);
+set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24);
+set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25);
+set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26);
+set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27);
+set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28);
+set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29);
+set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30);
+set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31);
+set_reset_data( debug_itm__TER, val_debug_itm__TER);
+set_reset_data( debug_itm__TTR, val_debug_itm__TTR);
+set_reset_data( debug_itm__CR, val_debug_itm__CR);
+set_reset_data( debug_itm__SCR, val_debug_itm__SCR);
+set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK);
+set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT);
+set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0);
+set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2);
+set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1);
+set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0);
+set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR);
+set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR);
+set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR);
+set_reset_data( debug_itm__LAR, val_debug_itm__LAR);
+set_reset_data( debug_itm__LSR, val_debug_itm__LSR);
+set_reset_data( debug_itm__ASR, val_debug_itm__ASR);
+set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID);
+set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR);
+set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4);
+set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5);
+set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6);
+set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7);
+set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0);
+set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1);
+set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2);
+set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3);
+set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0);
+set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1);
+set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2);
+set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3);
+
+// ************************************************************
+//   Module debug_tpiu tpiu
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize);
+set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize);
+set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode);
+set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount);
+set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult);
+set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest);
+set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest);
+set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount);
+set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR);
+set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR);
+set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount);
+set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn);
+set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut);
+set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK);
+set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN);
+set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0);
+set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2);
+set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1);
+set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0);
+set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR);
+set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR);
+set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR);
+set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR);
+set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR);
+set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR);
+set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID);
+set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR);
+set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4);
+set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5);
+set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6);
+set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7);
+set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0);
+set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1);
+set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2);
+set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3);
+set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0);
+set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1);
+set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2);
+set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3);
+
+// ************************************************************
+//   Module devcfg devcfg
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( devcfg__CTRL, val_devcfg__CTRL);
+set_reset_data( devcfg__LOCK, val_devcfg__LOCK);
+set_reset_data( devcfg__CFG, val_devcfg__CFG);
+set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS);
+set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK);
+set_reset_data( devcfg__STATUS, val_devcfg__STATUS);
+set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR);
+set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR);
+set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN);
+set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN);
+set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW);
+set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR);
+set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID);
+set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK);
+set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL);
+set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG);
+set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS);
+set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK);
+set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS);
+set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO);
+set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO);
+set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL);
+
+// ************************************************************
+//   Module dmac0_ns dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR);
+set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC);
+set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN);
+set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS);
+set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS);
+set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR);
+set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD);
+set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC);
+set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD);
+set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0);
+set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1);
+set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2);
+set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3);
+set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4);
+set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5);
+set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6);
+set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7);
+set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0);
+set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0);
+set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1);
+set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1);
+set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2);
+set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2);
+set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3);
+set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3);
+set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4);
+set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4);
+set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5);
+set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5);
+set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6);
+set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6);
+set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7);
+set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7);
+set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0);
+set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0);
+set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0);
+set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0);
+set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0);
+set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1);
+set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1);
+set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1);
+set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1);
+set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1);
+set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2);
+set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2);
+set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2);
+set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2);
+set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2);
+set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3);
+set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3);
+set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3);
+set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3);
+set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3);
+set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4);
+set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4);
+set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4);
+set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4);
+set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4);
+set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5);
+set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5);
+set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5);
+set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5);
+set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5);
+set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6);
+set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6);
+set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6);
+set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6);
+set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6);
+set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7);
+set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7);
+set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7);
+set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7);
+set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7);
+set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS);
+set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD);
+set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0);
+set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1);
+set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0);
+set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1);
+set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2);
+set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3);
+set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4);
+set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD);
+set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD);
+set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0);
+set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1);
+set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2);
+set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3);
+set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0);
+set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1);
+set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2);
+set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3);
+
+// ************************************************************
+//   Module dmac0_s dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR);
+set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC);
+set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN);
+set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS);
+set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS);
+set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR);
+set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD);
+set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC);
+set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD);
+set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0);
+set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1);
+set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2);
+set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3);
+set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4);
+set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5);
+set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6);
+set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7);
+set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0);
+set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0);
+set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1);
+set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1);
+set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2);
+set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2);
+set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3);
+set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3);
+set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4);
+set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4);
+set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5);
+set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5);
+set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6);
+set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6);
+set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7);
+set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7);
+set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0);
+set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0);
+set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0);
+set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0);
+set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0);
+set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1);
+set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1);
+set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1);
+set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1);
+set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1);
+set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2);
+set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2);
+set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2);
+set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2);
+set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2);
+set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3);
+set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3);
+set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3);
+set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3);
+set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3);
+set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4);
+set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4);
+set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4);
+set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4);
+set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4);
+set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5);
+set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5);
+set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5);
+set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5);
+set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5);
+set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6);
+set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6);
+set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6);
+set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6);
+set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6);
+set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7);
+set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7);
+set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7);
+set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7);
+set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7);
+set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS);
+set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD);
+set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0);
+set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1);
+set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0);
+set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1);
+set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2);
+set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3);
+set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4);
+set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD);
+set_reset_data( dmac0_s__WD, val_dmac0_s__WD);
+set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0);
+set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1);
+set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2);
+set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3);
+set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0);
+set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1);
+set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2);
+set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3);
+
+// ************************************************************
+//   Module efuse_ctrl efuse_ctrl
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK);
+set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK);
+set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA);
+set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG);
+set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS);
+set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL);
+set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW);
+set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW);
+
+// ************************************************************
+//   Module gem0 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl);
+set_reset_data( gem0__net_cfg, val_gem0__net_cfg);
+set_reset_data( gem0__net_status, val_gem0__net_status);
+set_reset_data( gem0__user_io, val_gem0__user_io);
+set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg);
+set_reset_data( gem0__tx_status, val_gem0__tx_status);
+set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar);
+set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar);
+set_reset_data( gem0__rx_status, val_gem0__rx_status);
+set_reset_data( gem0__intr_status, val_gem0__intr_status);
+set_reset_data( gem0__intr_en, val_gem0__intr_en);
+set_reset_data( gem0__intr_dis, val_gem0__intr_dis);
+set_reset_data( gem0__intr_mask, val_gem0__intr_mask);
+set_reset_data( gem0__phy_maint, val_gem0__phy_maint);
+set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq);
+set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq);
+set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd);
+set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd);
+set_reset_data( gem0__hash_bot, val_gem0__hash_bot);
+set_reset_data( gem0__hash_top, val_gem0__hash_top);
+set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot);
+set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top);
+set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot);
+set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top);
+set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot);
+set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top);
+set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot);
+set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top);
+set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1);
+set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2);
+set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3);
+set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4);
+set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan);
+set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch);
+set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan);
+set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause);
+set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot);
+set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top);
+set_reset_data( gem0__module_id, val_gem0__module_id);
+set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot);
+set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top);
+set_reset_data( gem0__frames_tx, val_gem0__frames_tx);
+set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx);
+set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx);
+set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx);
+set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx);
+set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx);
+set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx);
+set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx);
+set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx);
+set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx);
+set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx);
+set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs);
+set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames);
+set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames);
+set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns);
+set_reset_data( gem0__late_collisns, val_gem0__late_collisns);
+set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames);
+set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs);
+set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot);
+set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top);
+set_reset_data( gem0__frames_rx, val_gem0__frames_rx);
+set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx);
+set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx);
+set_reset_data( gem0__pause_rx, val_gem0__pause_rx);
+set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx);
+set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx);
+set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx);
+set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx);
+set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx);
+set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx);
+set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx);
+set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx);
+set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx);
+set_reset_data( gem0__jab_rx, val_gem0__jab_rx);
+set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors);
+set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors);
+set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors);
+set_reset_data( gem0__align_errors, val_gem0__align_errors);
+set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors);
+set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors);
+set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors);
+set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors);
+set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors);
+set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s);
+set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns);
+set_reset_data( gem0__timer_s, val_gem0__timer_s);
+set_reset_data( gem0__timer_ns, val_gem0__timer_ns);
+set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust);
+set_reset_data( gem0__timer_incr, val_gem0__timer_incr);
+set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s);
+set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns);
+set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s);
+set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns);
+set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s);
+set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns);
+set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s);
+set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns);
+set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl);
+set_reset_data( gem0__pcs_status, val_gem0__pcs_status);
+set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id);
+set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id);
+set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad);
+set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability);
+set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp);
+set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg);
+set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg);
+set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status);
+set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1);
+set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2);
+set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3);
+set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4);
+set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5);
+set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6);
+set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7);
+set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1);
+set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2);
+set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3);
+set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4);
+set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5);
+set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6);
+set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7);
+set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1);
+set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2);
+set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3);
+set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4);
+set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5);
+set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6);
+set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7);
+set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1);
+set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2);
+set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3);
+set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4);
+set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5);
+set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6);
+set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7);
+set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1);
+set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2);
+set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3);
+set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4);
+set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5);
+set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6);
+set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7);
+set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0);
+set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1);
+set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2);
+set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3);
+set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4);
+set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5);
+set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6);
+set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7);
+set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8);
+set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9);
+set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10);
+set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11);
+set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12);
+set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13);
+set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14);
+set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15);
+set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0);
+set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1);
+set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2);
+set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3);
+set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4);
+set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5);
+set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6);
+set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7);
+set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8);
+set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9);
+set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10);
+set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11);
+set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12);
+set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13);
+set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14);
+set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15);
+set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1);
+set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2);
+set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3);
+set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4);
+set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5);
+set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6);
+set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7);
+set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1);
+set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2);
+set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3);
+set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4);
+set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5);
+set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6);
+set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7);
+set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1);
+set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2);
+set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3);
+set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4);
+set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5);
+set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6);
+set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7);
+
+// ************************************************************
+//   Module gem1 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl);
+set_reset_data( gem1__net_cfg, val_gem1__net_cfg);
+set_reset_data( gem1__net_status, val_gem1__net_status);
+set_reset_data( gem1__user_io, val_gem1__user_io);
+set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg);
+set_reset_data( gem1__tx_status, val_gem1__tx_status);
+set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar);
+set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar);
+set_reset_data( gem1__rx_status, val_gem1__rx_status);
+set_reset_data( gem1__intr_status, val_gem1__intr_status);
+set_reset_data( gem1__intr_en, val_gem1__intr_en);
+set_reset_data( gem1__intr_dis, val_gem1__intr_dis);
+set_reset_data( gem1__intr_mask, val_gem1__intr_mask);
+set_reset_data( gem1__phy_maint, val_gem1__phy_maint);
+set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq);
+set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq);
+set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd);
+set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd);
+set_reset_data( gem1__hash_bot, val_gem1__hash_bot);
+set_reset_data( gem1__hash_top, val_gem1__hash_top);
+set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot);
+set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top);
+set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot);
+set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top);
+set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot);
+set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top);
+set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot);
+set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top);
+set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1);
+set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2);
+set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3);
+set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4);
+set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan);
+set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch);
+set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan);
+set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause);
+set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot);
+set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top);
+set_reset_data( gem1__module_id, val_gem1__module_id);
+set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot);
+set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top);
+set_reset_data( gem1__frames_tx, val_gem1__frames_tx);
+set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx);
+set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx);
+set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx);
+set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx);
+set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx);
+set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx);
+set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx);
+set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx);
+set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx);
+set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx);
+set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs);
+set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames);
+set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames);
+set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns);
+set_reset_data( gem1__late_collisns, val_gem1__late_collisns);
+set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames);
+set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs);
+set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot);
+set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top);
+set_reset_data( gem1__frames_rx, val_gem1__frames_rx);
+set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx);
+set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx);
+set_reset_data( gem1__pause_rx, val_gem1__pause_rx);
+set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx);
+set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx);
+set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx);
+set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx);
+set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx);
+set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx);
+set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx);
+set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx);
+set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx);
+set_reset_data( gem1__jab_rx, val_gem1__jab_rx);
+set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors);
+set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors);
+set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors);
+set_reset_data( gem1__align_errors, val_gem1__align_errors);
+set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors);
+set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors);
+set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors);
+set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors);
+set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors);
+set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s);
+set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns);
+set_reset_data( gem1__timer_s, val_gem1__timer_s);
+set_reset_data( gem1__timer_ns, val_gem1__timer_ns);
+set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust);
+set_reset_data( gem1__timer_incr, val_gem1__timer_incr);
+set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s);
+set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns);
+set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s);
+set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns);
+set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s);
+set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns);
+set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s);
+set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns);
+set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl);
+set_reset_data( gem1__pcs_status, val_gem1__pcs_status);
+set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id);
+set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id);
+set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad);
+set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability);
+set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp);
+set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg);
+set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg);
+set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status);
+set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1);
+set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2);
+set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3);
+set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4);
+set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5);
+set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6);
+set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7);
+set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1);
+set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2);
+set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3);
+set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4);
+set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5);
+set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6);
+set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7);
+set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1);
+set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2);
+set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3);
+set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4);
+set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5);
+set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6);
+set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7);
+set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1);
+set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2);
+set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3);
+set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4);
+set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5);
+set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6);
+set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7);
+set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1);
+set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2);
+set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3);
+set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4);
+set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5);
+set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6);
+set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7);
+set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0);
+set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1);
+set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2);
+set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3);
+set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4);
+set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5);
+set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6);
+set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7);
+set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8);
+set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9);
+set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10);
+set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11);
+set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12);
+set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13);
+set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14);
+set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15);
+set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0);
+set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1);
+set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2);
+set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3);
+set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4);
+set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5);
+set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6);
+set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7);
+set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8);
+set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9);
+set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10);
+set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11);
+set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12);
+set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13);
+set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14);
+set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15);
+set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1);
+set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2);
+set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3);
+set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4);
+set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5);
+set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6);
+set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7);
+set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1);
+set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2);
+set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3);
+set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4);
+set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5);
+set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6);
+set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7);
+set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1);
+set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2);
+set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3);
+set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4);
+set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5);
+set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6);
+set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7);
+
+// ************************************************************
+//   Module gpio gpio
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW);
+set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW);
+set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW);
+set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW);
+set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW);
+set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW);
+set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW);
+set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW);
+set_reset_data( gpio__DATA_0, val_gpio__DATA_0);
+set_reset_data( gpio__DATA_1, val_gpio__DATA_1);
+set_reset_data( gpio__DATA_2, val_gpio__DATA_2);
+set_reset_data( gpio__DATA_3, val_gpio__DATA_3);
+set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO);
+set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO);
+set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO);
+set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO);
+set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0);
+set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0);
+set_reset_data( gpio__OEN_0, val_gpio__OEN_0);
+set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0);
+set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0);
+set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0);
+set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0);
+set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0);
+set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0);
+set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0);
+set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1);
+set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1);
+set_reset_data( gpio__OEN_1, val_gpio__OEN_1);
+set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1);
+set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1);
+set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1);
+set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1);
+set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1);
+set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1);
+set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1);
+set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2);
+set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2);
+set_reset_data( gpio__OEN_2, val_gpio__OEN_2);
+set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2);
+set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2);
+set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2);
+set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2);
+set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2);
+set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2);
+set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2);
+set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3);
+set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3);
+set_reset_data( gpio__OEN_3, val_gpio__OEN_3);
+set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3);
+set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3);
+set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3);
+set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3);
+set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3);
+set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3);
+set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3);
+
+// ************************************************************
+//   Module gpv_iou_switch gpv_iou_switch
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap);
+set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0);
+set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1);
+set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi);
+set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou);
+set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves);
+set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc);
+set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4);
+set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5);
+set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6);
+set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7);
+set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0);
+set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1);
+set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2);
+set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3);
+set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0);
+set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1);
+set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2);
+set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0);
+set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1);
+set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou);
+set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0);
+set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0);
+set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1);
+set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1);
+set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0);
+set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0);
+set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1);
+set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1);
+set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0);
+set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0);
+set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0);
+set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1);
+set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1);
+set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1);
+set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou);
+
+// ************************************************************
+//   Module gpv_qos301_cpu qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl);
+set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot);
+set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot);
+set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p);
+set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b);
+set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r);
+set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p);
+set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b);
+set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r);
+
+// ************************************************************
+//   Module gpv_qos301_dmac qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl);
+set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot);
+set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot);
+set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p);
+set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b);
+set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r);
+set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p);
+set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b);
+set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r);
+
+// ************************************************************
+//   Module gpv_qos301_iou qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl);
+set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot);
+set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot);
+set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p);
+set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b);
+set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r);
+set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p);
+set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b);
+set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r);
+
+// ************************************************************
+//   Module gpv_trustzone nic301_addr_region_ctrl_registers
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap);
+set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0);
+set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1);
+set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb);
+
+// ************************************************************
+//   Module i2c0 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0);
+set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0);
+set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0);
+set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0);
+set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0);
+set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0);
+set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0);
+set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0);
+set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0);
+set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0);
+set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0);
+
+// ************************************************************
+//   Module i2c1 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0);
+set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0);
+set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0);
+set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0);
+set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0);
+set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0);
+set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0);
+set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0);
+set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0);
+set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0);
+set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0);
+
+// ************************************************************
+//   Module l2cache L2Cpl310
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id);
+set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type);
+set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control);
+set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control);
+set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control);
+set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control);
+set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl);
+set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg);
+set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg);
+set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1);
+set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0);
+set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask);
+set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status);
+set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status);
+set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear);
+set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync);
+set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa);
+set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way);
+set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa);
+set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index);
+set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way);
+set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa);
+set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index);
+set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way);
+set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0);
+set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0);
+set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1);
+set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1);
+set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2);
+set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2);
+set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3);
+set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3);
+set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4);
+set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4);
+set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5);
+set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5);
+set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6);
+set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6);
+set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7);
+set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7);
+set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en);
+set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way);
+set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start);
+set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end);
+set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl);
+set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl);
+set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl);
+
+// ************************************************************
+//   Module mpcore mpcore
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER);
+set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER);
+set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register);
+set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State);
+set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register);
+set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register);
+set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC);
+set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register);
+set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR);
+set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR);
+set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR);
+set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR);
+set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR);
+set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR);
+set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR);
+set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR);
+set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR);
+set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0);
+set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1);
+set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register);
+set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register);
+set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0);
+set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1);
+set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register);
+set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register);
+set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register);
+set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register);
+set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register);
+set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register);
+set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register);
+set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register);
+set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register);
+set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register);
+set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register);
+set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR);
+set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR);
+set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR);
+set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0);
+set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1);
+set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2);
+set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0);
+set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1);
+set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2);
+set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0);
+set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1);
+set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2);
+set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0);
+set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1);
+set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2);
+set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0);
+set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1);
+set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2);
+set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0);
+set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1);
+set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2);
+set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0);
+set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1);
+set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2);
+set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3);
+set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4);
+set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5);
+set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6);
+set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7);
+set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8);
+set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9);
+set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10);
+set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11);
+set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12);
+set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13);
+set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14);
+set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15);
+set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16);
+set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17);
+set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18);
+set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19);
+set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20);
+set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21);
+set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22);
+set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23);
+set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0);
+set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1);
+set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2);
+set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3);
+set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4);
+set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5);
+set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6);
+set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7);
+set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8);
+set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9);
+set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10);
+set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11);
+set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12);
+set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13);
+set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14);
+set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15);
+set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16);
+set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17);
+set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18);
+set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19);
+set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20);
+set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21);
+set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22);
+set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23);
+set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0);
+set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1);
+set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2);
+set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3);
+set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4);
+set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5);
+set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status);
+set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0);
+set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1);
+set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR);
+set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4);
+set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5);
+set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6);
+set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7);
+set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0);
+set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1);
+set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2);
+set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3);
+set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0);
+set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1);
+set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2);
+set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3);
+
+// ************************************************************
+//   Module ocm ocm
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL);
+set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS);
+set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS);
+set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL);
+
+// ************************************************************
+//   Module qspi qspi
+//   doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
+/// Design Specification document
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( qspi__Config_reg, val_qspi__Config_reg);
+set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG);
+set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG);
+set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG);
+set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG);
+set_reset_data( qspi__En_REG, val_qspi__En_REG);
+set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG);
+set_reset_data( qspi__TXD0, val_qspi__TXD0);
+set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG);
+set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG);
+set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG);
+set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG);
+set_reset_data( qspi__GPIO, val_qspi__GPIO);
+set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ);
+set_reset_data( qspi__TXD1, val_qspi__TXD1);
+set_reset_data( qspi__TXD2, val_qspi__TXD2);
+set_reset_data( qspi__TXD3, val_qspi__TXD3);
+set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG);
+set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS);
+set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID);
+
+// ************************************************************
+//   Module sd0 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register);
+set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count);
+set_reset_data( sd0__Argument, val_sd0__Argument);
+set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command);
+set_reset_data( sd0__Response0, val_sd0__Response0);
+set_reset_data( sd0__Response1, val_sd0__Response1);
+set_reset_data( sd0__Response2, val_sd0__Response2);
+set_reset_data( sd0__Response3, val_sd0__Response3);
+set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port);
+set_reset_data( sd0__Present_State, val_sd0__Present_State);
+set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
+set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset);
+set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status);
+set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable);
+set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
+set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status);
+set_reset_data( sd0__Capabilities, val_sd0__Capabilities);
+set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities);
+set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
+set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status);
+set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address);
+set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control);
+set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection);
+set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support);
+set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version);
+
+// ************************************************************
+//   Module sd1 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register);
+set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count);
+set_reset_data( sd1__Argument, val_sd1__Argument);
+set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command);
+set_reset_data( sd1__Response0, val_sd1__Response0);
+set_reset_data( sd1__Response1, val_sd1__Response1);
+set_reset_data( sd1__Response2, val_sd1__Response2);
+set_reset_data( sd1__Response3, val_sd1__Response3);
+set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port);
+set_reset_data( sd1__Present_State, val_sd1__Present_State);
+set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
+set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset);
+set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status);
+set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable);
+set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
+set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status);
+set_reset_data( sd1__Capabilities, val_sd1__Capabilities);
+set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities);
+set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
+set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status);
+set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address);
+set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control);
+set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection);
+set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support);
+set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version);
+
+// ************************************************************
+//   Module slcr slcr
+//   doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( slcr__SCL, val_slcr__SCL);
+set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK);
+set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK);
+set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA);
+set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL);
+set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL);
+set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL);
+set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS);
+set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG);
+set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG);
+set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG);
+set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL);
+set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL);
+set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL);
+set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL);
+set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL);
+set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL);
+set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL);
+set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL);
+set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL);
+set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL);
+set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL);
+set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL);
+set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL);
+set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL);
+set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL);
+set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL);
+set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL);
+set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL);
+set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL);
+set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL);
+set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL);
+set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL);
+set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL);
+set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT);
+set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA);
+set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL);
+set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL);
+set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT);
+set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA);
+set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL);
+set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL);
+set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT);
+set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA);
+set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL);
+set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL);
+set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT);
+set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA);
+set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL);
+set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM);
+set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST);
+set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR);
+set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE);
+set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG);
+set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT);
+set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT);
+set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL);
+set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL);
+set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL);
+set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL);
+set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL);
+set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL);
+set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL);
+set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL);
+set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL);
+set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL);
+set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL);
+set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL);
+set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL);
+set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL);
+set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL);
+set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL);
+set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL);
+set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL);
+set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL);
+set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON);
+set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR);
+set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS);
+set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE);
+set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL);
+set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL);
+set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0);
+set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1);
+set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM);
+set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM);
+set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS);
+set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS);
+set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS);
+set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM);
+set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO);
+set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB);
+set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M);
+set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI);
+set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL);
+set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE);
+set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT);
+set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START);
+set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START);
+set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA);
+set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL);
+set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS);
+set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00);
+set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01);
+set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02);
+set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03);
+set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04);
+set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05);
+set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06);
+set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07);
+set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08);
+set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09);
+set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10);
+set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11);
+set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12);
+set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13);
+set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14);
+set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15);
+set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16);
+set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17);
+set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18);
+set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19);
+set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20);
+set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21);
+set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22);
+set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23);
+set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24);
+set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25);
+set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26);
+set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27);
+set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28);
+set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29);
+set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30);
+set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31);
+set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32);
+set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33);
+set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34);
+set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35);
+set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36);
+set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37);
+set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38);
+set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39);
+set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40);
+set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41);
+set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42);
+set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43);
+set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44);
+set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45);
+set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46);
+set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47);
+set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48);
+set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49);
+set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50);
+set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51);
+set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52);
+set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53);
+set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL);
+set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK);
+set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0);
+set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1);
+set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL);
+set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL);
+set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN);
+set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG);
+set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0);
+set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1);
+set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2);
+set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0);
+set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1);
+set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2);
+set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM);
+set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM);
+set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01);
+set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01);
+set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0);
+set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1);
+set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0);
+set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1);
+set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI);
+set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM);
+set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0);
+set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1);
+set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2);
+set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0);
+set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1);
+set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2);
+set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0);
+set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1);
+set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2);
+set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0);
+set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1);
+set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2);
+set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM);
+set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0);
+set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1);
+set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM);
+set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM);
+set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL);
+set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18);
+set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25);
+set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33);
+set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL);
+set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL);
+set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL);
+set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0);
+set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1);
+set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0);
+set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1);
+set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0);
+set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1);
+set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF);
+set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK);
+set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL);
+set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL);
+set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS);
+
+// ************************************************************
+//   Module smcc pl353
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( smcc__memc_status, val_smcc__memc_status);
+set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg);
+set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set);
+set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr);
+set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd);
+set_reset_data( smcc__set_cycles, val_smcc__set_cycles);
+set_reset_data( smcc__set_opmode, val_smcc__set_opmode);
+set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0);
+set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1);
+set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0);
+set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0);
+set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1);
+set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1);
+set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0);
+set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0);
+set_reset_data( smcc__user_status, val_smcc__user_status);
+set_reset_data( smcc__user_config, val_smcc__user_config);
+set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0);
+set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0);
+set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0);
+set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0);
+set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0);
+set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0);
+set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0);
+set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0);
+set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0);
+set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0);
+set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1);
+set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1);
+set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1);
+set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1);
+set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1);
+set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1);
+set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1);
+set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1);
+set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1);
+set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1);
+set_reset_data( smcc__integration_test, val_smcc__integration_test);
+set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0);
+set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1);
+set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2);
+set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3);
+set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0);
+set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1);
+set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2);
+set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3);
+
+// ************************************************************
+//   Module spi0 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0);
+set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0);
+set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0);
+set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0);
+set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0);
+set_reset_data( spi0__En_reg0, val_spi0__En_reg0);
+set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0);
+set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0);
+set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0);
+set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0);
+set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0);
+set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0);
+set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0);
+
+// ************************************************************
+//   Module spi1 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0);
+set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0);
+set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0);
+set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0);
+set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0);
+set_reset_data( spi1__En_reg0, val_spi1__En_reg0);
+set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0);
+set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0);
+set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0);
+set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0);
+set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0);
+set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0);
+set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0);
+
+// ************************************************************
+//   Module swdt swdt
+//   doc version: 2.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( swdt__MODE, val_swdt__MODE);
+set_reset_data( swdt__CONTROL, val_swdt__CONTROL);
+set_reset_data( swdt__RESTART, val_swdt__RESTART);
+set_reset_data( swdt__STATUS, val_swdt__STATUS);
+
+// ************************************************************
+//   Module ttc0 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1);
+set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2);
+set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3);
+set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1);
+set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2);
+set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3);
+set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1);
+set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2);
+set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3);
+set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1);
+set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2);
+set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3);
+set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1);
+set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2);
+set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3);
+set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1);
+set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2);
+set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3);
+set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1);
+set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2);
+set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3);
+set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1);
+set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2);
+set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3);
+set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1);
+set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2);
+set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3);
+set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1);
+set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2);
+set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3);
+set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1);
+set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2);
+set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3);
+
+// ************************************************************
+//   Module ttc1 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1);
+set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2);
+set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3);
+set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1);
+set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2);
+set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3);
+set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1);
+set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2);
+set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3);
+set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1);
+set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2);
+set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3);
+set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1);
+set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2);
+set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3);
+set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1);
+set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2);
+set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3);
+set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1);
+set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2);
+set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3);
+set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1);
+set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2);
+set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3);
+set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1);
+set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2);
+set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3);
+set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1);
+set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2);
+set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3);
+set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1);
+set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2);
+set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3);
+
+// ************************************************************
+//   Module uart0 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0);
+set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0);
+set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0);
+set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0);
+set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0);
+set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0);
+set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0);
+set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0);
+set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0);
+set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0);
+set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0);
+set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0);
+set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0);
+set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0);
+set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0);
+set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0);
+set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0);
+set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0);
+
+// ************************************************************
+//   Module uart1 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0);
+set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0);
+set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0);
+set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0);
+set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0);
+set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0);
+set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0);
+set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0);
+set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0);
+set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0);
+set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0);
+set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0);
+set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0);
+set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0);
+set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0);
+set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0);
+set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0);
+set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0);
+
+// ************************************************************
+//   Module usb0 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( usb0__ID, val_usb0__ID);
+set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL);
+set_reset_data( usb0__HWHOST, val_usb0__HWHOST);
+set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE);
+set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF);
+set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF);
+set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD);
+set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL);
+set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD);
+set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL);
+set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG);
+set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION);
+set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS);
+set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS);
+set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION);
+set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS);
+set_reset_data( usb0__USBCMD, val_usb0__USBCMD);
+set_reset_data( usb0__USBSTS, val_usb0__USBSTS);
+set_reset_data( usb0__USBINTR, val_usb0__USBINTR);
+set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX);
+set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR);
+set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR);
+set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL);
+set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE);
+set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING);
+set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING);
+set_reset_data( usb0__IC_USB, val_usb0__IC_USB);
+set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT);
+set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK);
+set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN);
+set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG);
+set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1);
+set_reset_data( usb0__OTGSC, val_usb0__OTGSC);
+set_reset_data( usb0__USBMODE, val_usb0__USBMODE);
+set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT);
+set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME);
+set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH);
+set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT);
+set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE);
+set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0);
+set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1);
+set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2);
+set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3);
+set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4);
+set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5);
+set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6);
+set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7);
+set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8);
+set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9);
+set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10);
+set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11);
+set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12);
+
+// ************************************************************
+//   Module usb1 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+set_reset_data( usb1__ID, val_usb1__ID);
+set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL);
+set_reset_data( usb1__HWHOST, val_usb1__HWHOST);
+set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE);
+set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF);
+set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF);
+set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD);
+set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL);
+set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD);
+set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL);
+set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG);
+set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION);
+set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS);
+set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS);
+set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION);
+set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS);
+set_reset_data( usb1__USBCMD, val_usb1__USBCMD);
+set_reset_data( usb1__USBSTS, val_usb1__USBSTS);
+set_reset_data( usb1__USBINTR, val_usb1__USBINTR);
+set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX);
+set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR);
+set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR);
+set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL);
+set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE);
+set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING);
+set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING);
+set_reset_data( usb1__IC_USB, val_usb1__IC_USB);
+set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT);
+set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK);
+set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN);
+set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG);
+set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1);
+set_reset_data( usb1__OTGSC, val_usb1__OTGSC);
+set_reset_data( usb1__USBMODE, val_usb1__USBMODE);
+set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT);
+set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME);
+set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH);
+set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT);
+set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE);
+set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0);
+set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1);
+set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2);
+set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3);
+set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4);
+set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5);
+set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6);
+set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7);
+set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8);
+set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9);
+set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10);
+set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11);
+set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12);
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_params.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_params.v
new file mode 100644
index 0000000..fe18b65
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_reg_params.v
@@ -0,0 +1,10519 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_reg_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters for Register Address and Default values.
+ *
+ *****************************************************************************/
+
+// Register default value info for chip pele_ps
+// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
+// 54 modules, 2532 registers.
+
+
+// ************************************************************
+//   Module afi0 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000;
+parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004;
+parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDQOS = 32'hF8008008;
+parameter val_afi0__AFI_RDQOS = 32'h00000000;
+parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C;
+parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_RDDEBUG = 32'hF8008010;
+parameter val_afi0__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014;
+parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018;
+parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRQOS = 32'hF800801C;
+parameter val_afi0__AFI_WRQOS = 32'h00000000;
+parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020;
+parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi0__AFI_WRDEBUG = 32'hF8008024;
+parameter val_afi0__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi1 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000;
+parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004;
+parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDQOS = 32'hF8009008;
+parameter val_afi1__AFI_RDQOS = 32'h00000000;
+parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C;
+parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_RDDEBUG = 32'hF8009010;
+parameter val_afi1__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014;
+parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018;
+parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRQOS = 32'hF800901C;
+parameter val_afi1__AFI_WRQOS = 32'h00000000;
+parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020;
+parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi1__AFI_WRDEBUG = 32'hF8009024;
+parameter val_afi1__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi2 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000;
+parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004;
+parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDQOS = 32'hF800A008;
+parameter val_afi2__AFI_RDQOS = 32'h00000000;
+parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C;
+parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_RDDEBUG = 32'hF800A010;
+parameter val_afi2__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014;
+parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018;
+parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRQOS = 32'hF800A01C;
+parameter val_afi2__AFI_WRQOS = 32'h00000000;
+parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020;
+parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi2__AFI_WRDEBUG = 32'hF800A024;
+parameter val_afi2__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module afi3 AFI
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000;
+parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000;
+parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004;
+parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDQOS = 32'hF800B008;
+parameter val_afi3__AFI_RDQOS = 32'h00000000;
+parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C;
+parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_RDDEBUG = 32'hF800B010;
+parameter val_afi3__AFI_RDDEBUG = 32'h00000000;
+parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014;
+parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00;
+parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018;
+parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
+parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRQOS = 32'hF800B01C;
+parameter val_afi3__AFI_WRQOS = 32'h00000000;
+parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020;
+parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
+parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
+
+parameter afi3__AFI_WRDEBUG = 32'hF800B024;
+parameter val_afi3__AFI_WRDEBUG = 32'h00000000;
+parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module can0 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter can0__SRR = 32'hE0008000;
+parameter val_can0__SRR = 32'h00000000;
+parameter mask_can0__SRR = 32'hFFFFFFFF;
+
+parameter can0__MSR = 32'hE0008004;
+parameter val_can0__MSR = 32'h00000000;
+parameter mask_can0__MSR = 32'hFFFFFFFF;
+
+parameter can0__BRPR = 32'hE0008008;
+parameter val_can0__BRPR = 32'h00000000;
+parameter mask_can0__BRPR = 32'hFFFFFFFF;
+
+parameter can0__BTR = 32'hE000800C;
+parameter val_can0__BTR = 32'h00000000;
+parameter mask_can0__BTR = 32'hFFFFFFFF;
+
+parameter can0__ECR = 32'hE0008010;
+parameter val_can0__ECR = 32'h00000000;
+parameter mask_can0__ECR = 32'hFFFFFFFF;
+
+parameter can0__ESR = 32'hE0008014;
+parameter val_can0__ESR = 32'h00000000;
+parameter mask_can0__ESR = 32'hFFFFFFFF;
+
+parameter can0__SR = 32'hE0008018;
+parameter val_can0__SR = 32'h00000001;
+parameter mask_can0__SR = 32'hFFFFFFFF;
+
+parameter can0__ISR = 32'hE000801C;
+parameter val_can0__ISR = 32'h00006000;
+parameter mask_can0__ISR = 32'hFFFFFFFF;
+
+parameter can0__IER = 32'hE0008020;
+parameter val_can0__IER = 32'h00000000;
+parameter mask_can0__IER = 32'hFFFFFFFF;
+
+parameter can0__ICR = 32'hE0008024;
+parameter val_can0__ICR = 32'h00000000;
+parameter mask_can0__ICR = 32'hFFFFFFFF;
+
+parameter can0__TCR = 32'hE0008028;
+parameter val_can0__TCR = 32'h00000000;
+parameter mask_can0__TCR = 32'hFFFFFFFF;
+
+parameter can0__WIR = 32'hE000802C;
+parameter val_can0__WIR = 32'h00003F3F;
+parameter mask_can0__WIR = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_ID = 32'hE0008030;
+parameter val_can0__TXFIFO_ID = 32'h00000000;
+parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DLC = 32'hE0008034;
+parameter val_can0__TXFIFO_DLC = 32'h00000000;
+parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DATA1 = 32'hE0008038;
+parameter val_can0__TXFIFO_DATA1 = 32'h00000000;
+parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF;
+
+parameter can0__TXFIFO_DATA2 = 32'hE000803C;
+parameter val_can0__TXFIFO_DATA2 = 32'h00000000;
+parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_ID = 32'hE0008040;
+parameter val_can0__TXHPB_ID = 32'h00000000;
+parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DLC = 32'hE0008044;
+parameter val_can0__TXHPB_DLC = 32'h00000000;
+parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DATA1 = 32'hE0008048;
+parameter val_can0__TXHPB_DATA1 = 32'h00000000;
+parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF;
+
+parameter can0__TXHPB_DATA2 = 32'hE000804C;
+parameter val_can0__TXHPB_DATA2 = 32'h00000000;
+parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF;
+
+parameter can0__RXFIFO_ID = 32'hE0008050;
+parameter val_can0__RXFIFO_ID = 32'h00000000;
+parameter mask_can0__RXFIFO_ID = 32'h00000000;
+
+parameter can0__RXFIFO_DLC = 32'hE0008054;
+parameter val_can0__RXFIFO_DLC = 32'h00000000;
+parameter mask_can0__RXFIFO_DLC = 32'h00000000;
+
+parameter can0__RXFIFO_DATA1 = 32'hE0008058;
+parameter val_can0__RXFIFO_DATA1 = 32'h00000000;
+parameter mask_can0__RXFIFO_DATA1 = 32'h00000000;
+
+parameter can0__RXFIFO_DATA2 = 32'hE000805C;
+parameter val_can0__RXFIFO_DATA2 = 32'h00000000;
+parameter mask_can0__RXFIFO_DATA2 = 32'h00000000;
+
+parameter can0__AFR = 32'hE0008060;
+parameter val_can0__AFR = 32'h00000000;
+parameter mask_can0__AFR = 32'hFFFFFFFF;
+
+parameter can0__AFMR1 = 32'hE0008064;
+parameter val_can0__AFMR1 = 32'h00000000;
+parameter mask_can0__AFMR1 = 32'h00000000;
+
+parameter can0__AFIR1 = 32'hE0008068;
+parameter val_can0__AFIR1 = 32'h00000000;
+parameter mask_can0__AFIR1 = 32'h00000000;
+
+parameter can0__AFMR2 = 32'hE000806C;
+parameter val_can0__AFMR2 = 32'h00000000;
+parameter mask_can0__AFMR2 = 32'h00000000;
+
+parameter can0__AFIR2 = 32'hE0008070;
+parameter val_can0__AFIR2 = 32'h00000000;
+parameter mask_can0__AFIR2 = 32'h00000000;
+
+parameter can0__AFMR3 = 32'hE0008074;
+parameter val_can0__AFMR3 = 32'h00000000;
+parameter mask_can0__AFMR3 = 32'h00000000;
+
+parameter can0__AFIR3 = 32'hE0008078;
+parameter val_can0__AFIR3 = 32'h00000000;
+parameter mask_can0__AFIR3 = 32'h00000000;
+
+parameter can0__AFMR4 = 32'hE000807C;
+parameter val_can0__AFMR4 = 32'h00000000;
+parameter mask_can0__AFMR4 = 32'h00000000;
+
+parameter can0__AFIR4 = 32'hE0008080;
+parameter val_can0__AFIR4 = 32'h00000000;
+parameter mask_can0__AFIR4 = 32'h00000000;
+
+
+// ************************************************************
+//   Module can1 can
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter can1__SRR = 32'hE0009000;
+parameter val_can1__SRR = 32'h00000000;
+parameter mask_can1__SRR = 32'hFFFFFFFF;
+
+parameter can1__MSR = 32'hE0009004;
+parameter val_can1__MSR = 32'h00000000;
+parameter mask_can1__MSR = 32'hFFFFFFFF;
+
+parameter can1__BRPR = 32'hE0009008;
+parameter val_can1__BRPR = 32'h00000000;
+parameter mask_can1__BRPR = 32'hFFFFFFFF;
+
+parameter can1__BTR = 32'hE000900C;
+parameter val_can1__BTR = 32'h00000000;
+parameter mask_can1__BTR = 32'hFFFFFFFF;
+
+parameter can1__ECR = 32'hE0009010;
+parameter val_can1__ECR = 32'h00000000;
+parameter mask_can1__ECR = 32'hFFFFFFFF;
+
+parameter can1__ESR = 32'hE0009014;
+parameter val_can1__ESR = 32'h00000000;
+parameter mask_can1__ESR = 32'hFFFFFFFF;
+
+parameter can1__SR = 32'hE0009018;
+parameter val_can1__SR = 32'h00000001;
+parameter mask_can1__SR = 32'hFFFFFFFF;
+
+parameter can1__ISR = 32'hE000901C;
+parameter val_can1__ISR = 32'h00006000;
+parameter mask_can1__ISR = 32'hFFFFFFFF;
+
+parameter can1__IER = 32'hE0009020;
+parameter val_can1__IER = 32'h00000000;
+parameter mask_can1__IER = 32'hFFFFFFFF;
+
+parameter can1__ICR = 32'hE0009024;
+parameter val_can1__ICR = 32'h00000000;
+parameter mask_can1__ICR = 32'hFFFFFFFF;
+
+parameter can1__TCR = 32'hE0009028;
+parameter val_can1__TCR = 32'h00000000;
+parameter mask_can1__TCR = 32'hFFFFFFFF;
+
+parameter can1__WIR = 32'hE000902C;
+parameter val_can1__WIR = 32'h00003F3F;
+parameter mask_can1__WIR = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_ID = 32'hE0009030;
+parameter val_can1__TXFIFO_ID = 32'h00000000;
+parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DLC = 32'hE0009034;
+parameter val_can1__TXFIFO_DLC = 32'h00000000;
+parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DATA1 = 32'hE0009038;
+parameter val_can1__TXFIFO_DATA1 = 32'h00000000;
+parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF;
+
+parameter can1__TXFIFO_DATA2 = 32'hE000903C;
+parameter val_can1__TXFIFO_DATA2 = 32'h00000000;
+parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_ID = 32'hE0009040;
+parameter val_can1__TXHPB_ID = 32'h00000000;
+parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DLC = 32'hE0009044;
+parameter val_can1__TXHPB_DLC = 32'h00000000;
+parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DATA1 = 32'hE0009048;
+parameter val_can1__TXHPB_DATA1 = 32'h00000000;
+parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF;
+
+parameter can1__TXHPB_DATA2 = 32'hE000904C;
+parameter val_can1__TXHPB_DATA2 = 32'h00000000;
+parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF;
+
+parameter can1__RXFIFO_ID = 32'hE0009050;
+parameter val_can1__RXFIFO_ID = 32'h00000000;
+parameter mask_can1__RXFIFO_ID = 32'h00000000;
+
+parameter can1__RXFIFO_DLC = 32'hE0009054;
+parameter val_can1__RXFIFO_DLC = 32'h00000000;
+parameter mask_can1__RXFIFO_DLC = 32'h00000000;
+
+parameter can1__RXFIFO_DATA1 = 32'hE0009058;
+parameter val_can1__RXFIFO_DATA1 = 32'h00000000;
+parameter mask_can1__RXFIFO_DATA1 = 32'h00000000;
+
+parameter can1__RXFIFO_DATA2 = 32'hE000905C;
+parameter val_can1__RXFIFO_DATA2 = 32'h00000000;
+parameter mask_can1__RXFIFO_DATA2 = 32'h00000000;
+
+parameter can1__AFR = 32'hE0009060;
+parameter val_can1__AFR = 32'h00000000;
+parameter mask_can1__AFR = 32'hFFFFFFFF;
+
+parameter can1__AFMR1 = 32'hE0009064;
+parameter val_can1__AFMR1 = 32'h00000000;
+parameter mask_can1__AFMR1 = 32'h00000000;
+
+parameter can1__AFIR1 = 32'hE0009068;
+parameter val_can1__AFIR1 = 32'h00000000;
+parameter mask_can1__AFIR1 = 32'h00000000;
+
+parameter can1__AFMR2 = 32'hE000906C;
+parameter val_can1__AFMR2 = 32'h00000000;
+parameter mask_can1__AFMR2 = 32'h00000000;
+
+parameter can1__AFIR2 = 32'hE0009070;
+parameter val_can1__AFIR2 = 32'h00000000;
+parameter mask_can1__AFIR2 = 32'h00000000;
+
+parameter can1__AFMR3 = 32'hE0009074;
+parameter val_can1__AFMR3 = 32'h00000000;
+parameter mask_can1__AFMR3 = 32'h00000000;
+
+parameter can1__AFIR3 = 32'hE0009078;
+parameter val_can1__AFIR3 = 32'h00000000;
+parameter mask_can1__AFIR3 = 32'h00000000;
+
+parameter can1__AFMR4 = 32'hE000907C;
+parameter val_can1__AFMR4 = 32'h00000000;
+parameter mask_can1__AFMR4 = 32'h00000000;
+
+parameter can1__AFIR4 = 32'hE0009080;
+parameter val_can1__AFIR4 = 32'h00000000;
+parameter mask_can1__AFIR4 = 32'h00000000;
+
+
+// ************************************************************
+//   Module ddrc ddrc
+//   doc version: 1.25
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ddrc__ddrc_ctrl = 32'hF8006000;
+parameter val_ddrc__ddrc_ctrl = 32'h00000200;
+parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF;
+
+parameter ddrc__Two_rank_cfg = 32'hF8006004;
+parameter val_ddrc__Two_rank_cfg = 32'h000C1076;
+parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF;
+
+parameter ddrc__HPR_reg = 32'hF8006008;
+parameter val_ddrc__HPR_reg = 32'h03C0780F;
+parameter mask_ddrc__HPR_reg = 32'h03FFFFFF;
+
+parameter ddrc__LPR_reg = 32'hF800600C;
+parameter val_ddrc__LPR_reg = 32'h03C0780F;
+parameter mask_ddrc__LPR_reg = 32'h03FFFFFF;
+
+parameter ddrc__WR_reg = 32'hF8006010;
+parameter val_ddrc__WR_reg = 32'h0007F80F;
+parameter mask_ddrc__WR_reg = 32'h03FFFFFF;
+
+parameter ddrc__DRAM_param_reg0 = 32'hF8006014;
+parameter val_ddrc__DRAM_param_reg0 = 32'h00041016;
+parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF;
+
+parameter ddrc__DRAM_param_reg1 = 32'hF8006018;
+parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9;
+parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF;
+
+parameter ddrc__DRAM_param_reg2 = 32'hF800601C;
+parameter val_ddrc__DRAM_param_reg2 = 32'h83015904;
+parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_param_reg3 = 32'hF8006020;
+parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0;
+parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_param_reg4 = 32'hF8006024;
+parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C;
+parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF;
+
+parameter ddrc__DRAM_init_param = 32'hF8006028;
+parameter val_ddrc__DRAM_init_param = 32'h00002007;
+parameter mask_ddrc__DRAM_init_param = 32'h00003FFF;
+
+parameter ddrc__DRAM_EMR_reg = 32'hF800602C;
+parameter val_ddrc__DRAM_EMR_reg = 32'h00000008;
+parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030;
+parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940;
+parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034;
+parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034;
+parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF;
+
+parameter ddrc__DRAM_disable_DQ = 32'hF8006038;
+parameter val_ddrc__DRAM_disable_DQ = 32'h00000000;
+parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF;
+
+parameter ddrc__DRAM_addr_map_bank = 32'hF800603C;
+parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77;
+parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF;
+
+parameter ddrc__DRAM_addr_map_col = 32'hF8006040;
+parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000;
+parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF;
+
+parameter ddrc__DRAM_addr_map_row = 32'hF8006044;
+parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555;
+parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF;
+
+parameter ddrc__DRAM_ODT_reg = 32'hF8006048;
+parameter val_ddrc__DRAM_ODT_reg = 32'h00000249;
+parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF;
+
+parameter ddrc__phy_dbg_reg = 32'hF800604C;
+parameter val_ddrc__phy_dbg_reg = 32'h00000000;
+parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF;
+
+parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050;
+parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200;
+parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF;
+
+parameter ddrc__mode_sts_reg = 32'hF8006054;
+parameter val_ddrc__mode_sts_reg = 32'h00000000;
+parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF;
+
+parameter ddrc__DLL_calib = 32'hF8006058;
+parameter val_ddrc__DLL_calib = 32'h00000101;
+parameter mask_ddrc__DLL_calib = 32'h0001FFFF;
+
+parameter ddrc__ODT_delay_hold = 32'hF800605C;
+parameter val_ddrc__ODT_delay_hold = 32'h00000023;
+parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF;
+
+parameter ddrc__ctrl_reg1 = 32'hF8006060;
+parameter val_ddrc__ctrl_reg1 = 32'h0000003E;
+parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF;
+
+parameter ddrc__ctrl_reg2 = 32'hF8006064;
+parameter val_ddrc__ctrl_reg2 = 32'h00020000;
+parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF;
+
+parameter ddrc__ctrl_reg3 = 32'hF8006068;
+parameter val_ddrc__ctrl_reg3 = 32'h00284027;
+parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF;
+
+parameter ddrc__ctrl_reg4 = 32'hF800606C;
+parameter val_ddrc__ctrl_reg4 = 32'h00001610;
+parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF;
+
+parameter ddrc__ctrl_reg5 = 32'hF8006078;
+parameter val_ddrc__ctrl_reg5 = 32'h00455111;
+parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF;
+
+parameter ddrc__ctrl_reg6 = 32'hF800607C;
+parameter val_ddrc__ctrl_reg6 = 32'h00032222;
+parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0;
+parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000;
+parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF;
+
+parameter ddrc__CHE_T_ZQ = 32'hF80060A4;
+parameter val_ddrc__CHE_T_ZQ = 32'h10300802;
+parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8;
+parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A;
+parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF;
+
+parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC;
+parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000;
+parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF;
+
+parameter ddrc__reg_2c = 32'hF80060B0;
+parameter val_ddrc__reg_2c = 32'h00000000;
+parameter mask_ddrc__reg_2c = 32'h1FFFFFFF;
+
+parameter ddrc__reg_2d = 32'hF80060B4;
+parameter val_ddrc__reg_2d = 32'h00000200;
+parameter mask_ddrc__reg_2d = 32'h000007FF;
+
+parameter ddrc__dfi_timing = 32'hF80060B8;
+parameter val_ddrc__dfi_timing = 32'h00200067;
+parameter mask_ddrc__dfi_timing = 32'h01FFFFFF;
+
+parameter ddrc__refresh_timer_2 = 32'hF80060BC;
+parameter val_ddrc__refresh_timer_2 = 32'h00000000;
+parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF;
+
+parameter ddrc__nc_timing = 32'hF80060C0;
+parameter val_ddrc__nc_timing = 32'h00000000;
+parameter mask_ddrc__nc_timing = 32'h003FFFFF;
+
+parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4;
+parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003;
+
+parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8;
+parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC;
+parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0;
+parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4;
+parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8;
+parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC;
+parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001;
+
+parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0;
+parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC;
+parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
+
+parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0;
+parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF;
+
+parameter ddrc__ECC_scrub = 32'hF80060F4;
+parameter val_ddrc__ECC_scrub = 32'h00000008;
+parameter mask_ddrc__ECC_scrub = 32'h0000000F;
+
+parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8;
+parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC;
+parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000;
+parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF;
+
+parameter ddrc__phy_rcvr_enable = 32'hF8006114;
+parameter val_ddrc__phy_rcvr_enable = 32'h00000000;
+parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF;
+
+parameter ddrc__PHY_Config0 = 32'hF8006118;
+parameter val_ddrc__PHY_Config0 = 32'h40000001;
+parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config1 = 32'hF800611C;
+parameter val_ddrc__PHY_Config1 = 32'h40000001;
+parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config2 = 32'hF8006120;
+parameter val_ddrc__PHY_Config2 = 32'h40000001;
+parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF;
+
+parameter ddrc__PHY_Config3 = 32'hF8006124;
+parameter val_ddrc__PHY_Config3 = 32'h40000001;
+parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF;
+
+parameter ddrc__phy_init_ratio0 = 32'hF800612C;
+parameter val_ddrc__phy_init_ratio0 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio1 = 32'hF8006130;
+parameter val_ddrc__phy_init_ratio1 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio2 = 32'hF8006134;
+parameter val_ddrc__phy_init_ratio2 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF;
+
+parameter ddrc__phy_init_ratio3 = 32'hF8006138;
+parameter val_ddrc__phy_init_ratio3 = 32'h00000000;
+parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140;
+parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144;
+parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148;
+parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C;
+parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040;
+parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154;
+parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158;
+parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C;
+parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160;
+parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000;
+parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__phy_we_cfg0 = 32'hF8006168;
+parameter val_ddrc__phy_we_cfg0 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg1 = 32'hF800616C;
+parameter val_ddrc__phy_we_cfg1 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg2 = 32'hF8006170;
+parameter val_ddrc__phy_we_cfg2 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF;
+
+parameter ddrc__phy_we_cfg3 = 32'hF8006174;
+parameter val_ddrc__phy_we_cfg3 = 32'h00000040;
+parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF;
+
+parameter ddrc__wr_data_slv0 = 32'hF800617C;
+parameter val_ddrc__wr_data_slv0 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv1 = 32'hF8006180;
+parameter val_ddrc__wr_data_slv1 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv2 = 32'hF8006184;
+parameter val_ddrc__wr_data_slv2 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF;
+
+parameter ddrc__wr_data_slv3 = 32'hF8006188;
+parameter val_ddrc__wr_data_slv3 = 32'h00000080;
+parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF;
+
+parameter ddrc__reg_64 = 32'hF8006190;
+parameter val_ddrc__reg_64 = 32'h10020000;
+parameter mask_ddrc__reg_64 = 32'hFFFFFFFF;
+
+parameter ddrc__reg_65 = 32'hF8006194;
+parameter val_ddrc__reg_65 = 32'h00000000;
+parameter mask_ddrc__reg_65 = 32'h000FFFFF;
+
+parameter ddrc__reg69_6a0 = 32'hF80061A4;
+parameter val_ddrc__reg69_6a0 = 32'h000F0000;
+parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF;
+
+parameter ddrc__reg69_6a1 = 32'hF80061A8;
+parameter val_ddrc__reg69_6a1 = 32'h000F0000;
+parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6c_6d2 = 32'hF80061B0;
+parameter val_ddrc__reg6c_6d2 = 32'h000F0000;
+parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6c_6d3 = 32'hF80061B4;
+parameter val_ddrc__reg6c_6d3 = 32'h000F0000;
+parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF;
+
+parameter ddrc__reg6e_710 = 32'hF80061B8;
+parameter val_ddrc__reg6e_710 = 32'h00000000;
+parameter mask_ddrc__reg6e_710 = 32'h00000000;
+
+parameter ddrc__reg6e_711 = 32'hF80061BC;
+parameter val_ddrc__reg6e_711 = 32'h00000000;
+parameter mask_ddrc__reg6e_711 = 32'h00000000;
+
+parameter ddrc__reg6e_712 = 32'hF80061C0;
+parameter val_ddrc__reg6e_712 = 32'h00000000;
+parameter mask_ddrc__reg6e_712 = 32'h00000000;
+
+parameter ddrc__reg6e_713 = 32'hF80061C4;
+parameter val_ddrc__reg6e_713 = 32'h00000000;
+parameter mask_ddrc__reg6e_713 = 32'h00000000;
+
+parameter ddrc__phy_dll_sts0 = 32'hF80061CC;
+parameter val_ddrc__phy_dll_sts0 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts1 = 32'hF80061D0;
+parameter val_ddrc__phy_dll_sts1 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts2 = 32'hF80061D4;
+parameter val_ddrc__phy_dll_sts2 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF;
+
+parameter ddrc__phy_dll_sts3 = 32'hF80061D8;
+parameter val_ddrc__phy_dll_sts3 = 32'h00000000;
+parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF;
+
+parameter ddrc__dll_lock_sts = 32'hF80061E0;
+parameter val_ddrc__dll_lock_sts = 32'h00000000;
+parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF;
+
+parameter ddrc__phy_ctrl_sts = 32'hF80061E4;
+parameter val_ddrc__phy_ctrl_sts = 32'h00000000;
+parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000;
+
+parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8;
+parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000;
+parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF;
+
+parameter ddrc__axi_id = 32'hF8006200;
+parameter val_ddrc__axi_id = 32'h00153042;
+parameter mask_ddrc__axi_id = 32'h03FFFFFF;
+
+parameter ddrc__page_mask = 32'hF8006204;
+parameter val_ddrc__page_mask = 32'h00000000;
+parameter mask_ddrc__page_mask = 32'hFFFFFFFF;
+
+parameter ddrc__axi_priority_wr_port0 = 32'hF8006208;
+parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port1 = 32'hF800620C;
+parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port2 = 32'hF8006210;
+parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_wr_port3 = 32'hF8006214;
+parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF;
+parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port0 = 32'hF8006218;
+parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port1 = 32'hF800621C;
+parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port2 = 32'hF8006220;
+parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF;
+
+parameter ddrc__axi_priority_rd_port3 = 32'hF8006224;
+parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF;
+parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg0 = 32'hF8006248;
+parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg1 = 32'hF800624C;
+parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg2 = 32'hF8006250;
+parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF;
+
+parameter ddrc__AHB_priority_cfg3 = 32'hF8006254;
+parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF;
+parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF;
+
+parameter ddrc__perf_mon0 = 32'hF8006260;
+parameter val_ddrc__perf_mon0 = 32'h00000000;
+parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon1 = 32'hF8006264;
+parameter val_ddrc__perf_mon1 = 32'h00000000;
+parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon2 = 32'hF8006268;
+parameter val_ddrc__perf_mon2 = 32'h00000000;
+parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon3 = 32'hF800626C;
+parameter val_ddrc__perf_mon3 = 32'h00000000;
+parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF;
+
+parameter ddrc__perf_mon20 = 32'hF8006270;
+parameter val_ddrc__perf_mon20 = 32'h00000000;
+parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon21 = 32'hF8006274;
+parameter val_ddrc__perf_mon21 = 32'h00000000;
+parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon22 = 32'hF8006278;
+parameter val_ddrc__perf_mon22 = 32'h00000000;
+parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon23 = 32'hF800627C;
+parameter val_ddrc__perf_mon23 = 32'h00000000;
+parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF;
+
+parameter ddrc__perf_mon30 = 32'hF8006280;
+parameter val_ddrc__perf_mon30 = 32'h00000000;
+parameter mask_ddrc__perf_mon30 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon31 = 32'hF8006284;
+parameter val_ddrc__perf_mon31 = 32'h00000000;
+parameter mask_ddrc__perf_mon31 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon32 = 32'hF8006288;
+parameter val_ddrc__perf_mon32 = 32'h00000000;
+parameter mask_ddrc__perf_mon32 = 32'h0000FFFF;
+
+parameter ddrc__perf_mon33 = 32'hF800628C;
+parameter val_ddrc__perf_mon33 = 32'h00000000;
+parameter mask_ddrc__perf_mon33 = 32'h0000FFFF;
+
+parameter ddrc__trusted_mem_cfg = 32'hF8006290;
+parameter val_ddrc__trusted_mem_cfg = 32'h00000000;
+parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF;
+
+parameter ddrc__excl_access_cfg0 = 32'hF8006294;
+parameter val_ddrc__excl_access_cfg0 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg1 = 32'hF8006298;
+parameter val_ddrc__excl_access_cfg1 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg2 = 32'hF800629C;
+parameter val_ddrc__excl_access_cfg2 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF;
+
+parameter ddrc__excl_access_cfg3 = 32'hF80062A0;
+parameter val_ddrc__excl_access_cfg3 = 32'h00000000;
+parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF;
+
+parameter ddrc__mode_reg_read = 32'hF80062A4;
+parameter val_ddrc__mode_reg_read = 32'h00000000;
+parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF;
+
+parameter ddrc__lpddr_ctrl0 = 32'hF80062A8;
+parameter val_ddrc__lpddr_ctrl0 = 32'h00000000;
+parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF;
+
+parameter ddrc__lpddr_ctrl1 = 32'hF80062AC;
+parameter val_ddrc__lpddr_ctrl1 = 32'h00000000;
+parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF;
+
+parameter ddrc__lpddr_ctrl2 = 32'hF80062B0;
+parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015;
+parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF;
+
+parameter ddrc__lpddr_ctrl3 = 32'hF80062B4;
+parameter val_ddrc__lpddr_ctrl3 = 32'h00000601;
+parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF;
+
+parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8;
+parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444;
+parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF;
+
+parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC;
+parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888;
+parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF;
+
+parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0;
+parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444;
+parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF;
+
+
+// ************************************************************
+//   Module debug_axim axim
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_axim__GLOBAL_CTRL = 32'hF880C000;
+parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002;
+parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003;
+
+parameter debug_axim__GLOBAL_STATUS = 32'hF880C004;
+parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000;
+parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3;
+
+parameter debug_axim__FILTER_CTRL = 32'hF880C010;
+parameter val_debug_axim__FILTER_CTRL = 32'h00000000;
+parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F;
+
+parameter debug_axim__TRIGGER_CTRL = 32'hF880C020;
+parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000;
+parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF;
+
+parameter debug_axim__TRIGGER_STATUS = 32'hF880C024;
+parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000;
+parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003;
+
+parameter debug_axim__PACKET_CTRL = 32'hF880C030;
+parameter val_debug_axim__PACKET_CTRL = 32'h00070000;
+parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF;
+
+parameter debug_axim__TOUT_CTRL = 32'hF880C040;
+parameter val_debug_axim__TOUT_CTRL = 32'h00000000;
+parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F;
+
+parameter debug_axim__TOUT_THRESH = 32'hF880C044;
+parameter val_debug_axim__TOUT_THRESH = 32'h00008000;
+parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF;
+
+parameter debug_axim__FIFO_CURRENT = 32'hF880C050;
+parameter val_debug_axim__FIFO_CURRENT = 32'h80000000;
+parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF;
+
+parameter debug_axim__FIFO_HYSTER = 32'hF880C054;
+parameter val_debug_axim__FIFO_HYSTER = 32'h00000100;
+parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF;
+
+parameter debug_axim__SYNC_CURRENT = 32'hF880C060;
+parameter val_debug_axim__SYNC_CURRENT = 32'h00000000;
+parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF;
+
+parameter debug_axim__SYNC_RELOAD = 32'hF880C064;
+parameter val_debug_axim__SYNC_RELOAD = 32'h00000800;
+parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF;
+
+parameter debug_axim__TSTMP_CURRENT = 32'hF880C070;
+parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000;
+parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000;
+
+parameter debug_axim__ADDR0_MASK = 32'hF880C200;
+parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_LOWER = 32'hF880C204;
+parameter val_debug_axim__ADDR0_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_UPPER = 32'hF880C208;
+parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR0_MISC = 32'hF880C20C;
+parameter val_debug_axim__ADDR0_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR1_MASK = 32'hF880C210;
+parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_LOWER = 32'hF880C214;
+parameter val_debug_axim__ADDR1_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_UPPER = 32'hF880C218;
+parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR1_MISC = 32'hF880C21C;
+parameter val_debug_axim__ADDR1_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR2_MASK = 32'hF880C220;
+parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_LOWER = 32'hF880C224;
+parameter val_debug_axim__ADDR2_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_UPPER = 32'hF880C228;
+parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR2_MISC = 32'hF880C22C;
+parameter val_debug_axim__ADDR2_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF;
+
+parameter debug_axim__ADDR3_MASK = 32'hF880C230;
+parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_LOWER = 32'hF880C234;
+parameter val_debug_axim__ADDR3_LOWER = 32'h00000000;
+parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_UPPER = 32'hF880C238;
+parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC;
+parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF;
+
+parameter debug_axim__ADDR3_MISC = 32'hF880C23C;
+parameter val_debug_axim__ADDR3_MISC = 32'h00000000;
+parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF;
+
+parameter debug_axim__ID0_MASK = 32'hF880C300;
+parameter val_debug_axim__ID0_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID0_MASK = 32'h000003FF;
+
+parameter debug_axim__ID0_LOWER = 32'hF880C304;
+parameter val_debug_axim__ID0_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID0_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID0_UPPER = 32'hF880C308;
+parameter val_debug_axim__ID0_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID0_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID0_MISC = 32'hF880C30C;
+parameter val_debug_axim__ID0_MISC = 32'h00000000;
+parameter mask_debug_axim__ID0_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID1_MASK = 32'hF880C310;
+parameter val_debug_axim__ID1_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID1_MASK = 32'h000003FF;
+
+parameter debug_axim__ID1_LOWER = 32'hF880C314;
+parameter val_debug_axim__ID1_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID1_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID1_UPPER = 32'hF880C318;
+parameter val_debug_axim__ID1_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID1_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID1_MISC = 32'hF880C31C;
+parameter val_debug_axim__ID1_MISC = 32'h00000000;
+parameter mask_debug_axim__ID1_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID2_MASK = 32'hF880C320;
+parameter val_debug_axim__ID2_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID2_MASK = 32'h000003FF;
+
+parameter debug_axim__ID2_LOWER = 32'hF880C324;
+parameter val_debug_axim__ID2_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID2_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID2_UPPER = 32'hF880C328;
+parameter val_debug_axim__ID2_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID2_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID2_MISC = 32'hF880C32C;
+parameter val_debug_axim__ID2_MISC = 32'h00000000;
+parameter mask_debug_axim__ID2_MISC = 32'h00003FFF;
+
+parameter debug_axim__ID3_MASK = 32'hF880C330;
+parameter val_debug_axim__ID3_MASK = 32'h000003FF;
+parameter mask_debug_axim__ID3_MASK = 32'h000003FF;
+
+parameter debug_axim__ID3_LOWER = 32'hF880C334;
+parameter val_debug_axim__ID3_LOWER = 32'h00000000;
+parameter mask_debug_axim__ID3_LOWER = 32'h000003FF;
+
+parameter debug_axim__ID3_UPPER = 32'hF880C338;
+parameter val_debug_axim__ID3_UPPER = 32'h000003FF;
+parameter mask_debug_axim__ID3_UPPER = 32'h000003FF;
+
+parameter debug_axim__ID3_MISC = 32'hF880C33C;
+parameter val_debug_axim__ID3_MISC = 32'h00000000;
+parameter mask_debug_axim__ID3_MISC = 32'h00003FFF;
+
+parameter debug_axim__AXI_SEL = 32'hF880C800;
+parameter val_debug_axim__AXI_SEL = 32'h00000000;
+parameter mask_debug_axim__AXI_SEL = 32'h00000007;
+
+parameter debug_axim__IT_TRIGOUT = 32'hF880CED0;
+parameter val_debug_axim__IT_TRIGOUT = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001;
+
+parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4;
+parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000;
+
+parameter debug_axim__IT_TRIGIN = 32'hF880CED8;
+parameter val_debug_axim__IT_TRIGIN = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGIN = 32'h00000000;
+
+parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC;
+parameter val_debug_axim__IT_TRIGINACK = 32'h00000000;
+parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001;
+
+parameter debug_axim__IT_ATBDATA = 32'hF880CEEC;
+parameter val_debug_axim__IT_ATBDATA = 32'h00000000;
+parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F;
+
+parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0;
+parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000;
+parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000;
+
+parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4;
+parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000;
+parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F;
+
+parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8;
+parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000;
+parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF;
+
+parameter debug_axim__IT_CTRL = 32'hF880CF00;
+parameter val_debug_axim__IT_CTRL = 32'h00000000;
+parameter mask_debug_axim__IT_CTRL = 32'h00000001;
+
+parameter debug_axim__CLAIM_SET = 32'hF880CFA0;
+parameter val_debug_axim__CLAIM_SET = 32'h00000001;
+parameter mask_debug_axim__CLAIM_SET = 32'h0000000F;
+
+parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4;
+parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000;
+parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F;
+
+parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0;
+parameter val_debug_axim__LOCK_ACCESS = 32'h00000000;
+parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF;
+
+parameter debug_axim__LOCK_STATUS = 32'hF880CFB4;
+parameter val_debug_axim__LOCK_STATUS = 32'h00000003;
+parameter mask_debug_axim__LOCK_STATUS = 32'h00000007;
+
+parameter debug_axim__AUTH_STATUS = 32'hF880CFB8;
+parameter val_debug_axim__AUTH_STATUS = 32'h00000000;
+parameter mask_debug_axim__AUTH_STATUS = 32'h00000033;
+
+parameter debug_axim__DEV_ID = 32'hF880CFC8;
+parameter val_debug_axim__DEV_ID = 32'h00000000;
+parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF;
+
+parameter debug_axim__DEV_TYPE = 32'hF880CFCC;
+parameter val_debug_axim__DEV_TYPE = 32'h00000043;
+parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID4 = 32'hF880CFD0;
+parameter val_debug_axim__PERIPHID4 = 32'h00000003;
+parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID5 = 32'hF880CFD4;
+parameter val_debug_axim__PERIPHID5 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID6 = 32'hF880CFD8;
+parameter val_debug_axim__PERIPHID6 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID7 = 32'hF880CFDC;
+parameter val_debug_axim__PERIPHID7 = 32'h00000000;
+parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID0 = 32'hF880CFE0;
+parameter val_debug_axim__PERIPHID0 = 32'h000000B2;
+parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID1 = 32'hF880CFE4;
+parameter val_debug_axim__PERIPHID1 = 32'h00000093;
+parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID2 = 32'hF880CFE8;
+parameter val_debug_axim__PERIPHID2 = 32'h00000008;
+parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF;
+
+parameter debug_axim__PERIPHID3 = 32'hF880CFEC;
+parameter val_debug_axim__PERIPHID3 = 32'h00000002;
+parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID0 = 32'hF880CFF0;
+parameter val_debug_axim__COMPID0 = 32'h0000000D;
+parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID1 = 32'hF880CFF4;
+parameter val_debug_axim__COMPID1 = 32'h00000090;
+parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID2 = 32'hF880CFF8;
+parameter val_debug_axim__COMPID2 = 32'h00000005;
+parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF;
+
+parameter debug_axim__COMPID3 = 32'hF880CFFC;
+parameter val_debug_axim__COMPID3 = 32'h000000B1;
+parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_cti0 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000;
+parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001;
+
+parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010;
+parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014;
+parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018;
+parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C;
+parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020;
+parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024;
+parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028;
+parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C;
+parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030;
+parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034;
+parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038;
+parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C;
+parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0;
+parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4;
+parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8;
+parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC;
+parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0;
+parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4;
+parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8;
+parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC;
+parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130;
+parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134;
+parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138;
+parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C;
+parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTIGATE = 32'hF8898140;
+parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F;
+parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F;
+
+parameter debug_cpu_cti0__ASICCTL = 32'hF8898144;
+parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000;
+parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC;
+parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0;
+parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4;
+parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8;
+parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC;
+parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0;
+parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4;
+parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F;
+
+parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8;
+parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00;
+parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000;
+parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001;
+
+parameter debug_cpu_cti0__CTSR = 32'hF8898FA0;
+parameter val_debug_cpu_cti0__CTSR = 32'h0000000F;
+parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F;
+
+parameter debug_cpu_cti0__CTCR = 32'hF8898FA4;
+parameter val_debug_cpu_cti0__CTCR = 32'h00000000;
+parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F;
+
+parameter debug_cpu_cti0__LAR = 32'hF8898FB0;
+parameter val_debug_cpu_cti0__LAR = 32'h00000000;
+parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_cti0__LSR = 32'hF8898FB4;
+parameter val_debug_cpu_cti0__LSR = 32'h00000003;
+parameter mask_debug_cpu_cti0__LSR = 32'h00000007;
+
+parameter debug_cpu_cti0__ASR = 32'hF8898FB8;
+parameter val_debug_cpu_cti0__ASR = 32'h00000005;
+parameter mask_debug_cpu_cti0__ASR = 32'h00000005;
+
+parameter debug_cpu_cti0__DEVID = 32'hF8898FC8;
+parameter val_debug_cpu_cti0__DEVID = 32'h00040800;
+parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF;
+
+parameter debug_cpu_cti0__DTIR = 32'hF8898FCC;
+parameter val_debug_cpu_cti0__DTIR = 32'h00000014;
+parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0;
+parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4;
+parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8;
+parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC;
+parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0;
+parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4;
+parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8;
+parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC;
+parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0;
+parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4;
+parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8;
+parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC;
+parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_cti1 cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000;
+parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001;
+
+parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010;
+parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014;
+parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018;
+parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C;
+parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020;
+parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024;
+parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028;
+parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C;
+parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030;
+parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034;
+parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038;
+parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C;
+parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0;
+parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4;
+parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8;
+parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC;
+parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0;
+parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4;
+parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8;
+parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC;
+parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130;
+parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134;
+parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138;
+parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C;
+parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTIGATE = 32'hF8899140;
+parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F;
+parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F;
+
+parameter debug_cpu_cti1__ASICCTL = 32'hF8899144;
+parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000;
+parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC;
+parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0;
+parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4;
+parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8;
+parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC;
+parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0;
+parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4;
+parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F;
+
+parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8;
+parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00;
+parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000;
+parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001;
+
+parameter debug_cpu_cti1__CTSR = 32'hF8899FA0;
+parameter val_debug_cpu_cti1__CTSR = 32'h0000000F;
+parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F;
+
+parameter debug_cpu_cti1__CTCR = 32'hF8899FA4;
+parameter val_debug_cpu_cti1__CTCR = 32'h00000000;
+parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F;
+
+parameter debug_cpu_cti1__LAR = 32'hF8899FB0;
+parameter val_debug_cpu_cti1__LAR = 32'h00000000;
+parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_cti1__LSR = 32'hF8899FB4;
+parameter val_debug_cpu_cti1__LSR = 32'h00000003;
+parameter mask_debug_cpu_cti1__LSR = 32'h00000007;
+
+parameter debug_cpu_cti1__ASR = 32'hF8899FB8;
+parameter val_debug_cpu_cti1__ASR = 32'h00000005;
+parameter mask_debug_cpu_cti1__ASR = 32'h00000005;
+
+parameter debug_cpu_cti1__DEVID = 32'hF8899FC8;
+parameter val_debug_cpu_cti1__DEVID = 32'h00040800;
+parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF;
+
+parameter debug_cpu_cti1__DTIR = 32'hF8899FCC;
+parameter val_debug_cpu_cti1__DTIR = 32'h00000014;
+parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0;
+parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4;
+parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8;
+parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC;
+parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0;
+parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4;
+parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8;
+parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC;
+parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0;
+parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4;
+parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8;
+parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC;
+parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_pmu0 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000;
+parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004;
+parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008;
+parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C;
+parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010;
+parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014;
+parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C;
+parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400;
+parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404;
+parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408;
+parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C;
+parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410;
+parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414;
+parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00;
+parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20;
+parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40;
+parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60;
+parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80;
+parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0;
+parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000;
+
+parameter debug_cpu_pmu0__PMCR = 32'hF8891E04;
+parameter val_debug_cpu_pmu0__PMCR = 32'h41093000;
+parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08;
+parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000;
+parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_pmu1 cortexa9_pmu
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000;
+parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004;
+parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008;
+parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C;
+parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010;
+parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014;
+parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C;
+parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400;
+parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404;
+parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408;
+parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C;
+parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410;
+parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414;
+parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00;
+parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20;
+parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40;
+parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60;
+parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80;
+parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0;
+parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000;
+
+parameter debug_cpu_pmu1__PMCR = 32'hF8893E04;
+parameter val_debug_cpu_pmu1__PMCR = 32'h41093000;
+parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08;
+parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000;
+parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module debug_cpu_ptm0 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_ptm0__ETMCR = 32'hF889C000;
+parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400;
+parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004;
+parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004;
+parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008;
+parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSR = 32'hF889C010;
+parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F;
+
+parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014;
+parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF;
+
+parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018;
+parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF;
+
+parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024;
+parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040;
+parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044;
+parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048;
+parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C;
+parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050;
+parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054;
+parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058;
+parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C;
+parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080;
+parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084;
+parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088;
+parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C;
+parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090;
+parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094;
+parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098;
+parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C;
+parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140;
+parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144;
+parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150;
+parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000;
+parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154;
+parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000;
+parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160;
+parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164;
+parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170;
+parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174;
+parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180;
+parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184;
+parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188;
+parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C;
+parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190;
+parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194;
+parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C;
+parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003;
+
+parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0;
+parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4;
+parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0;
+parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC;
+parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0;
+parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400;
+parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF;
+
+parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4;
+parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300;
+parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8;
+parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2;
+parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC;
+parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF;
+
+parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC;
+parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F;
+
+parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200;
+parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F;
+
+parameter debug_cpu_ptm0__OSLSR = 32'hF889C304;
+parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314;
+parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001;
+parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC;
+parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF;
+
+parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0;
+parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020;
+
+parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8;
+parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001;
+
+parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC;
+parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0;
+parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
+
+parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4;
+parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F;
+
+parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8;
+parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00;
+parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001;
+
+parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0;
+parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF;
+parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4;
+parameter val_debug_cpu_ptm0__CTCR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__LAR = 32'hF889CFB0;
+parameter val_debug_cpu_ptm0__LAR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__LSR = 32'hF889CFB4;
+parameter val_debug_cpu_ptm0__LSR = 32'h00000003;
+parameter mask_debug_cpu_ptm0__LSR = 32'h00000007;
+
+parameter debug_cpu_ptm0__ASR = 32'hF889CFB8;
+parameter val_debug_cpu_ptm0__ASR = 32'h00000000;
+parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3;
+
+parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8;
+parameter val_debug_cpu_ptm0__DEVID = 32'h00000000;
+parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC;
+parameter val_debug_cpu_ptm0__DTIR = 32'h00000013;
+parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0;
+parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4;
+parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8;
+parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC;
+parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0;
+parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050;
+parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4;
+parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8;
+parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC;
+parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0;
+parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4;
+parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8;
+parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC;
+parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cpu_ptm1 ptm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cpu_ptm1__ETMCR = 32'hF889D000;
+parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400;
+parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004;
+parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004;
+parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008;
+parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSR = 32'hF889D010;
+parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F;
+
+parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014;
+parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF;
+
+parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018;
+parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF;
+
+parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024;
+parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040;
+parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044;
+parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048;
+parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C;
+parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050;
+parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054;
+parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058;
+parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C;
+parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080;
+parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084;
+parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088;
+parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C;
+parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090;
+parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094;
+parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098;
+parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C;
+parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140;
+parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144;
+parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150;
+parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000;
+parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154;
+parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000;
+parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160;
+parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164;
+parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170;
+parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174;
+parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180;
+parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184;
+parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188;
+parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C;
+parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190;
+parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194;
+parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C;
+parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003;
+
+parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0;
+parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4;
+parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF;
+
+parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0;
+parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC;
+parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0;
+parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400;
+parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF;
+
+parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4;
+parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300;
+parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8;
+parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2;
+parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF;
+
+parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC;
+parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF;
+
+parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC;
+parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F;
+
+parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200;
+parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F;
+
+parameter debug_cpu_ptm1__OSLSR = 32'hF889D304;
+parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314;
+parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001;
+parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC;
+parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF;
+
+parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0;
+parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020;
+
+parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8;
+parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001;
+
+parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC;
+parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0;
+parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
+
+parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4;
+parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F;
+
+parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8;
+parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00;
+parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001;
+
+parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0;
+parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF;
+parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4;
+parameter val_debug_cpu_ptm1__CTCR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__LAR = 32'hF889DFB0;
+parameter val_debug_cpu_ptm1__LAR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__LSR = 32'hF889DFB4;
+parameter val_debug_cpu_ptm1__LSR = 32'h00000003;
+parameter mask_debug_cpu_ptm1__LSR = 32'h00000007;
+
+parameter debug_cpu_ptm1__ASR = 32'hF889DFB8;
+parameter val_debug_cpu_ptm1__ASR = 32'h00000000;
+parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3;
+
+parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8;
+parameter val_debug_cpu_ptm1__DEVID = 32'h00000000;
+parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF;
+
+parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC;
+parameter val_debug_cpu_ptm1__DTIR = 32'h00000013;
+parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0;
+parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4;
+parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8;
+parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC;
+parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0;
+parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050;
+parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4;
+parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8;
+parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC;
+parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0;
+parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D;
+parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4;
+parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090;
+parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8;
+parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005;
+parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF;
+
+parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC;
+parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1;
+parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_axim cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_axim__CTICONTROL = 32'hF880A000;
+parameter val_debug_cti_axim__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_axim__CTIINTACK = 32'hF880A010;
+parameter val_debug_cti_axim__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_axim__CTIAPPSET = 32'hF880A014;
+parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018;
+parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C;
+parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN0 = 32'hF880A020;
+parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN1 = 32'hF880A024;
+parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN2 = 32'hF880A028;
+parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C;
+parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN4 = 32'hF880A030;
+parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN5 = 32'hF880A034;
+parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN6 = 32'hF880A038;
+parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C;
+parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0;
+parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4;
+parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8;
+parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC;
+parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0;
+parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4;
+parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8;
+parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC;
+parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130;
+parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134;
+parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138;
+parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C;
+parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_axim__CTIGATE = 32'hF880A140;
+parameter val_debug_cti_axim__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_axim__ASICCTL = 32'hF880A144;
+parameter val_debug_cti_axim__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC;
+parameter val_debug_cti_axim__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0;
+parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4;
+parameter val_debug_cti_axim__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8;
+parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC;
+parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0;
+parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_axim__ITCHIN = 32'hF880AEF4;
+parameter val_debug_cti_axim__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8;
+parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_axim__ITCTRL = 32'hF880AF00;
+parameter val_debug_cti_axim__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_axim__ITCTRL = 32'h00000001;
+
+parameter debug_cti_axim__CTSR = 32'hF880AFA0;
+parameter val_debug_cti_axim__CTSR = 32'h0000000F;
+parameter mask_debug_cti_axim__CTSR = 32'h0000000F;
+
+parameter debug_cti_axim__CTCR = 32'hF880AFA4;
+parameter val_debug_cti_axim__CTCR = 32'h00000000;
+parameter mask_debug_cti_axim__CTCR = 32'h0000000F;
+
+parameter debug_cti_axim__LAR = 32'hF880AFB0;
+parameter val_debug_cti_axim__LAR = 32'h00000000;
+parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_axim__LSR = 32'hF880AFB4;
+parameter val_debug_cti_axim__LSR = 32'h00000003;
+parameter mask_debug_cti_axim__LSR = 32'h00000007;
+
+parameter debug_cti_axim__ASR = 32'hF880AFB8;
+parameter val_debug_cti_axim__ASR = 32'h00000005;
+parameter mask_debug_cti_axim__ASR = 32'h00000005;
+
+parameter debug_cti_axim__DEVID = 32'hF880AFC8;
+parameter val_debug_cti_axim__DEVID = 32'h00040800;
+parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_axim__DTIR = 32'hF880AFCC;
+parameter val_debug_cti_axim__DTIR = 32'h00000014;
+parameter mask_debug_cti_axim__DTIR = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0;
+parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4;
+parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8;
+parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC;
+parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0;
+parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4;
+parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8;
+parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC;
+parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID0 = 32'hF880AFF0;
+parameter val_debug_cti_axim__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID1 = 32'hF880AFF4;
+parameter val_debug_cti_axim__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID2 = 32'hF880AFF8;
+parameter val_debug_cti_axim__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_axim__COMPID3 = 32'hF880AFFC;
+parameter val_debug_cti_axim__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_etb_tpiu cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000;
+parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010;
+parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014;
+parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018;
+parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C;
+parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020;
+parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024;
+parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028;
+parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C;
+parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030;
+parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034;
+parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038;
+parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C;
+parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC;
+parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130;
+parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134;
+parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138;
+parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C;
+parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140;
+parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144;
+parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC;
+parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0;
+parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4;
+parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8;
+parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC;
+parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0;
+parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4;
+parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8;
+parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00;
+parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001;
+
+parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0;
+parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
+parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4;
+parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F;
+
+parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0;
+parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4;
+parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003;
+parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007;
+
+parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8;
+parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005;
+parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005;
+
+parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8;
+parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800;
+parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC;
+parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014;
+parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0;
+parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4;
+parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8;
+parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC;
+parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0;
+parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4;
+parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8;
+parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC;
+parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0;
+parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4;
+parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8;
+parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC;
+parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_cti_ftm cti
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_cti_ftm__CTICONTROL = 32'hF8809000;
+parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001;
+
+parameter debug_cti_ftm__CTIINTACK = 32'hF8809010;
+parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF;
+
+parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014;
+parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018;
+parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C;
+parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020;
+parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024;
+parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028;
+parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C;
+parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030;
+parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034;
+parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038;
+parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C;
+parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0;
+parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4;
+parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8;
+parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC;
+parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0;
+parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4;
+parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8;
+parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC;
+parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000;
+parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F;
+
+parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130;
+parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
+
+parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134;
+parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF;
+
+parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138;
+parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
+
+parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C;
+parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000;
+parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F;
+
+parameter debug_cti_ftm__CTIGATE = 32'hF8809140;
+parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F;
+parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F;
+
+parameter debug_cti_ftm__ASICCTL = 32'hF8809144;
+parameter val_debug_cti_ftm__ASICCTL = 32'h00000000;
+parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC;
+parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0;
+parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4;
+parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8;
+parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC;
+parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0;
+parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4;
+parameter val_debug_cti_ftm__ITCHIN = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F;
+
+parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8;
+parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000;
+parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF;
+
+parameter debug_cti_ftm__ITCTRL = 32'hF8809F00;
+parameter val_debug_cti_ftm__ITCTRL = 32'h00000000;
+parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001;
+
+parameter debug_cti_ftm__CTSR = 32'hF8809FA0;
+parameter val_debug_cti_ftm__CTSR = 32'h0000000F;
+parameter mask_debug_cti_ftm__CTSR = 32'h0000000F;
+
+parameter debug_cti_ftm__CTCR = 32'hF8809FA4;
+parameter val_debug_cti_ftm__CTCR = 32'h00000000;
+parameter mask_debug_cti_ftm__CTCR = 32'h0000000F;
+
+parameter debug_cti_ftm__LAR = 32'hF8809FB0;
+parameter val_debug_cti_ftm__LAR = 32'h00000000;
+parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF;
+
+parameter debug_cti_ftm__LSR = 32'hF8809FB4;
+parameter val_debug_cti_ftm__LSR = 32'h00000003;
+parameter mask_debug_cti_ftm__LSR = 32'h00000007;
+
+parameter debug_cti_ftm__ASR = 32'hF8809FB8;
+parameter val_debug_cti_ftm__ASR = 32'h00000005;
+parameter mask_debug_cti_ftm__ASR = 32'h00000005;
+
+parameter debug_cti_ftm__DEVID = 32'hF8809FC8;
+parameter val_debug_cti_ftm__DEVID = 32'h00040800;
+parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF;
+
+parameter debug_cti_ftm__DTIR = 32'hF8809FCC;
+parameter val_debug_cti_ftm__DTIR = 32'h00000014;
+parameter mask_debug_cti_ftm__DTIR = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0;
+parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004;
+parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4;
+parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8;
+parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC;
+parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0;
+parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006;
+parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4;
+parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8;
+parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF;
+
+parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC;
+parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000;
+parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0;
+parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D;
+parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4;
+parameter val_debug_cti_ftm__COMPID1 = 32'h00000090;
+parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8;
+parameter val_debug_cti_ftm__COMPID2 = 32'h00000005;
+parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF;
+
+parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC;
+parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1;
+parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_dap_rom dap
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000;
+parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003;
+parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004;
+parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003;
+parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008;
+parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003;
+parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C;
+parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003;
+parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010;
+parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003;
+parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014;
+parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003;
+parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018;
+parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003;
+parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C;
+parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003;
+parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020;
+parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003;
+parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024;
+parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003;
+parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028;
+parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C;
+parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030;
+parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034;
+parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038;
+parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C;
+parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000;
+parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF;
+
+parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0;
+parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003;
+parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4;
+parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8;
+parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC;
+parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0;
+parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2;
+parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4;
+parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093;
+parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8;
+parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008;
+parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF;
+
+parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC;
+parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000;
+parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID0 = 32'hF8800FF0;
+parameter val_debug_dap_rom__COMPID0 = 32'h0000000D;
+parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID1 = 32'hF8800FF4;
+parameter val_debug_dap_rom__COMPID1 = 32'h00000010;
+parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID2 = 32'hF8800FF8;
+parameter val_debug_dap_rom__COMPID2 = 32'h00000005;
+parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF;
+
+parameter debug_dap_rom__COMPID3 = 32'hF8800FFC;
+parameter val_debug_dap_rom__COMPID3 = 32'h000000B1;
+parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_etb etb
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_etb__RDP = 32'hF8801004;
+parameter val_debug_etb__RDP = 32'h00000400;
+parameter mask_debug_etb__RDP = 32'hFFFFFFFF;
+
+parameter debug_etb__STS = 32'hF880100C;
+parameter val_debug_etb__STS = 32'h00000000;
+parameter mask_debug_etb__STS = 32'h0000000F;
+
+parameter debug_etb__RRD = 32'hF8801010;
+parameter val_debug_etb__RRD = 32'h00000000;
+parameter mask_debug_etb__RRD = 32'hFFFFFFFF;
+
+parameter debug_etb__RRP = 32'hF8801014;
+parameter val_debug_etb__RRP = 32'h00000000;
+parameter mask_debug_etb__RRP = 32'h000003FF;
+
+parameter debug_etb__RWP = 32'hF8801018;
+parameter val_debug_etb__RWP = 32'h00000000;
+parameter mask_debug_etb__RWP = 32'h000003FF;
+
+parameter debug_etb__TRG = 32'hF880101C;
+parameter val_debug_etb__TRG = 32'h00000000;
+parameter mask_debug_etb__TRG = 32'h000003FF;
+
+parameter debug_etb__CTL = 32'hF8801020;
+parameter val_debug_etb__CTL = 32'h00000000;
+parameter mask_debug_etb__CTL = 32'h00000001;
+
+parameter debug_etb__RWD = 32'hF8801024;
+parameter val_debug_etb__RWD = 32'h00000000;
+parameter mask_debug_etb__RWD = 32'hFFFFFFFF;
+
+parameter debug_etb__FFSR = 32'hF8801300;
+parameter val_debug_etb__FFSR = 32'h00000000;
+parameter mask_debug_etb__FFSR = 32'h00000003;
+
+parameter debug_etb__FFCR = 32'hF8801304;
+parameter val_debug_etb__FFCR = 32'h00000200;
+parameter mask_debug_etb__FFCR = 32'h00003FFF;
+
+parameter debug_etb__ITMISCOP0 = 32'hF8801EE0;
+parameter val_debug_etb__ITMISCOP0 = 32'h00000000;
+parameter mask_debug_etb__ITMISCOP0 = 32'h00000003;
+
+parameter debug_etb__ITTRFLINACK = 32'hF8801EE4;
+parameter val_debug_etb__ITTRFLINACK = 32'h00000000;
+parameter mask_debug_etb__ITTRFLINACK = 32'h00000003;
+
+parameter debug_etb__ITTRFLIN = 32'hF8801EE8;
+parameter val_debug_etb__ITTRFLIN = 32'h00000000;
+parameter mask_debug_etb__ITTRFLIN = 32'h00000003;
+
+parameter debug_etb__ITATBDATA0 = 32'hF8801EEC;
+parameter val_debug_etb__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_etb__ITATBCTR2 = 32'hF8801EF0;
+parameter val_debug_etb__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR2 = 32'h00000003;
+
+parameter debug_etb__ITATBCTR1 = 32'hF8801EF4;
+parameter val_debug_etb__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F;
+
+parameter debug_etb__ITATBCTR0 = 32'hF8801EF8;
+parameter val_debug_etb__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_etb__IMCR = 32'hF8801F00;
+parameter val_debug_etb__IMCR = 32'h00000000;
+parameter mask_debug_etb__IMCR = 32'h00000001;
+
+parameter debug_etb__CTSR = 32'hF8801FA0;
+parameter val_debug_etb__CTSR = 32'h0000000F;
+parameter mask_debug_etb__CTSR = 32'h0000000F;
+
+parameter debug_etb__CTCR = 32'hF8801FA4;
+parameter val_debug_etb__CTCR = 32'h00000000;
+parameter mask_debug_etb__CTCR = 32'h0000000F;
+
+parameter debug_etb__LAR = 32'hF8801FB0;
+parameter val_debug_etb__LAR = 32'h00000000;
+parameter mask_debug_etb__LAR = 32'hFFFFFFFF;
+
+parameter debug_etb__LSR = 32'hF8801FB4;
+parameter val_debug_etb__LSR = 32'h00000003;
+parameter mask_debug_etb__LSR = 32'h00000007;
+
+parameter debug_etb__ASR = 32'hF8801FB8;
+parameter val_debug_etb__ASR = 32'h00000000;
+parameter mask_debug_etb__ASR = 32'h000000FF;
+
+parameter debug_etb__DEVID = 32'hF8801FC8;
+parameter val_debug_etb__DEVID = 32'h00000000;
+parameter mask_debug_etb__DEVID = 32'h0000003F;
+
+parameter debug_etb__DTIR = 32'hF8801FCC;
+parameter val_debug_etb__DTIR = 32'h00000021;
+parameter mask_debug_etb__DTIR = 32'h000000FF;
+
+parameter debug_etb__PERIPHID4 = 32'hF8801FD0;
+parameter val_debug_etb__PERIPHID4 = 32'h00000004;
+parameter mask_debug_etb__PERIPHID4 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID5 = 32'hF8801FD4;
+parameter val_debug_etb__PERIPHID5 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID5 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID6 = 32'hF8801FD8;
+parameter val_debug_etb__PERIPHID6 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID6 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID7 = 32'hF8801FDC;
+parameter val_debug_etb__PERIPHID7 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID7 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID0 = 32'hF8801FE0;
+parameter val_debug_etb__PERIPHID0 = 32'h00000007;
+parameter mask_debug_etb__PERIPHID0 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID1 = 32'hF8801FE4;
+parameter val_debug_etb__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_etb__PERIPHID1 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID2 = 32'hF8801FE8;
+parameter val_debug_etb__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_etb__PERIPHID2 = 32'h000000FF;
+
+parameter debug_etb__PERIPHID3 = 32'hF8801FEC;
+parameter val_debug_etb__PERIPHID3 = 32'h00000000;
+parameter mask_debug_etb__PERIPHID3 = 32'h000000FF;
+
+parameter debug_etb__COMPID0 = 32'hF8801FF0;
+parameter val_debug_etb__COMPID0 = 32'h0000000D;
+parameter mask_debug_etb__COMPID0 = 32'h000000FF;
+
+parameter debug_etb__COMPID1 = 32'hF8801FF4;
+parameter val_debug_etb__COMPID1 = 32'h00000090;
+parameter mask_debug_etb__COMPID1 = 32'h000000FF;
+
+parameter debug_etb__COMPID2 = 32'hF8801FF8;
+parameter val_debug_etb__COMPID2 = 32'h00000005;
+parameter mask_debug_etb__COMPID2 = 32'h000000FF;
+
+parameter debug_etb__COMPID3 = 32'hF8801FFC;
+parameter val_debug_etb__COMPID3 = 32'h000000B1;
+parameter mask_debug_etb__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_ftm ftm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_ftm__FTMGLBCTRL = 32'hF880B000;
+parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000;
+parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001;
+
+parameter debug_ftm__FTMSTATUS = 32'hF880B004;
+parameter val_debug_ftm__FTMSTATUS = 32'h00000082;
+parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF;
+
+parameter debug_ftm__FTMCONTROL = 32'hF880B008;
+parameter val_debug_ftm__FTMCONTROL = 32'h00000000;
+parameter mask_debug_ftm__FTMCONTROL = 32'h00000007;
+
+parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C;
+parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010;
+parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014;
+parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF;
+
+parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018;
+parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000;
+parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C;
+parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020;
+parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024;
+parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF;
+
+parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028;
+parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000;
+parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF;
+
+parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C;
+parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000;
+parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F;
+
+parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030;
+parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000;
+parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF;
+
+parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034;
+parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000;
+parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF;
+
+parameter debug_ftm__FTMATID = 32'hF880B400;
+parameter val_debug_ftm__FTMATID = 32'h00000000;
+parameter mask_debug_ftm__FTMATID = 32'h0000007F;
+
+parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0;
+parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F;
+
+parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4;
+parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F;
+
+parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8;
+parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000;
+parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001;
+
+parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC;
+parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001;
+parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF;
+
+parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC;
+parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F;
+
+parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0;
+parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001;
+parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003;
+
+parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4;
+parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F;
+
+parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8;
+parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000;
+parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF;
+
+parameter debug_ftm__FTMITCR = 32'hF880BF00;
+parameter val_debug_ftm__FTMITCR = 32'h00000000;
+parameter mask_debug_ftm__FTMITCR = 32'h00000001;
+
+parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0;
+parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF;
+parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF;
+
+parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4;
+parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
+parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
+
+parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0;
+parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000;
+parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF;
+
+parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4;
+parameter val_debug_ftm__LOCK_STATUS = 32'h00000003;
+parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007;
+
+parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8;
+parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088;
+parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF;
+
+parameter debug_ftm__FTMDEVID = 32'hF880BFC8;
+parameter val_debug_ftm__FTMDEVID = 32'h00000000;
+parameter mask_debug_ftm__FTMDEVID = 32'h00000001;
+
+parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC;
+parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033;
+parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0;
+parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4;
+parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8;
+parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC;
+parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0;
+parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001;
+parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4;
+parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090;
+parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8;
+parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C;
+parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF;
+
+parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC;
+parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000;
+parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0;
+parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D;
+parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4;
+parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090;
+parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8;
+parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005;
+parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF;
+
+parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC;
+parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1;
+parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_funnel funnel
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_funnel__Control = 32'hF8804000;
+parameter val_debug_funnel__Control = 32'h00000300;
+parameter mask_debug_funnel__Control = 32'h00000FFF;
+
+parameter debug_funnel__PriControl = 32'hF8804004;
+parameter val_debug_funnel__PriControl = 32'h00FAC688;
+parameter mask_debug_funnel__PriControl = 32'h00FFFFFF;
+
+parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC;
+parameter val_debug_funnel__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F;
+
+parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0;
+parameter val_debug_funnel__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003;
+
+parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4;
+parameter val_debug_funnel__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F;
+
+parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8;
+parameter val_debug_funnel__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF;
+
+parameter debug_funnel__IMCR = 32'hF8804F00;
+parameter val_debug_funnel__IMCR = 32'h00000000;
+parameter mask_debug_funnel__IMCR = 32'h00000001;
+
+parameter debug_funnel__CTSR = 32'hF8804FA0;
+parameter val_debug_funnel__CTSR = 32'h0000000F;
+parameter mask_debug_funnel__CTSR = 32'h0000000F;
+
+parameter debug_funnel__CTCR = 32'hF8804FA4;
+parameter val_debug_funnel__CTCR = 32'h00000000;
+parameter mask_debug_funnel__CTCR = 32'h0000000F;
+
+parameter debug_funnel__LAR = 32'hF8804FB0;
+parameter val_debug_funnel__LAR = 32'h00000000;
+parameter mask_debug_funnel__LAR = 32'hFFFFFFFF;
+
+parameter debug_funnel__LSR = 32'hF8804FB4;
+parameter val_debug_funnel__LSR = 32'h00000003;
+parameter mask_debug_funnel__LSR = 32'h00000007;
+
+parameter debug_funnel__ASR = 32'hF8804FB8;
+parameter val_debug_funnel__ASR = 32'h00000000;
+parameter mask_debug_funnel__ASR = 32'h000000FF;
+
+parameter debug_funnel__DEVID = 32'hF8804FC8;
+parameter val_debug_funnel__DEVID = 32'h00000028;
+parameter mask_debug_funnel__DEVID = 32'h000000FF;
+
+parameter debug_funnel__DTIR = 32'hF8804FCC;
+parameter val_debug_funnel__DTIR = 32'h00000012;
+parameter mask_debug_funnel__DTIR = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID4 = 32'hF8804FD0;
+parameter val_debug_funnel__PERIPHID4 = 32'h00000004;
+parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID5 = 32'hF8804FD4;
+parameter val_debug_funnel__PERIPHID5 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID6 = 32'hF8804FD8;
+parameter val_debug_funnel__PERIPHID6 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID7 = 32'hF8804FDC;
+parameter val_debug_funnel__PERIPHID7 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID0 = 32'hF8804FE0;
+parameter val_debug_funnel__PERIPHID0 = 32'h00000008;
+parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID1 = 32'hF8804FE4;
+parameter val_debug_funnel__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID2 = 32'hF8804FE8;
+parameter val_debug_funnel__PERIPHID2 = 32'h0000001B;
+parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF;
+
+parameter debug_funnel__PERIPHID3 = 32'hF8804FEC;
+parameter val_debug_funnel__PERIPHID3 = 32'h00000000;
+parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF;
+
+parameter debug_funnel__COMPID0 = 32'hF8804FF0;
+parameter val_debug_funnel__COMPID0 = 32'h0000000D;
+parameter mask_debug_funnel__COMPID0 = 32'h000000FF;
+
+parameter debug_funnel__COMPID1 = 32'hF8804FF4;
+parameter val_debug_funnel__COMPID1 = 32'h00000090;
+parameter mask_debug_funnel__COMPID1 = 32'h000000FF;
+
+parameter debug_funnel__COMPID2 = 32'hF8804FF8;
+parameter val_debug_funnel__COMPID2 = 32'h00000005;
+parameter mask_debug_funnel__COMPID2 = 32'h000000FF;
+
+parameter debug_funnel__COMPID3 = 32'hF8804FFC;
+parameter val_debug_funnel__COMPID3 = 32'h000000B1;
+parameter mask_debug_funnel__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_itm itm
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_itm__StimPort00 = 32'hF8805000;
+parameter val_debug_itm__StimPort00 = 32'h00000000;
+parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort01 = 32'hF8805004;
+parameter val_debug_itm__StimPort01 = 32'h00000000;
+parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort02 = 32'hF8805008;
+parameter val_debug_itm__StimPort02 = 32'h00000000;
+parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort03 = 32'hF880500C;
+parameter val_debug_itm__StimPort03 = 32'h00000000;
+parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort04 = 32'hF8805010;
+parameter val_debug_itm__StimPort04 = 32'h00000000;
+parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort05 = 32'hF8805014;
+parameter val_debug_itm__StimPort05 = 32'h00000000;
+parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort06 = 32'hF8805018;
+parameter val_debug_itm__StimPort06 = 32'h00000000;
+parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort07 = 32'hF880501C;
+parameter val_debug_itm__StimPort07 = 32'h00000000;
+parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort08 = 32'hF8805020;
+parameter val_debug_itm__StimPort08 = 32'h00000000;
+parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort09 = 32'hF8805024;
+parameter val_debug_itm__StimPort09 = 32'h00000000;
+parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort10 = 32'hF8805028;
+parameter val_debug_itm__StimPort10 = 32'h00000000;
+parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort11 = 32'hF880502C;
+parameter val_debug_itm__StimPort11 = 32'h00000000;
+parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort12 = 32'hF8805030;
+parameter val_debug_itm__StimPort12 = 32'h00000000;
+parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort13 = 32'hF8805034;
+parameter val_debug_itm__StimPort13 = 32'h00000000;
+parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort14 = 32'hF8805038;
+parameter val_debug_itm__StimPort14 = 32'h00000000;
+parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort15 = 32'hF880503C;
+parameter val_debug_itm__StimPort15 = 32'h00000000;
+parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort16 = 32'hF8805040;
+parameter val_debug_itm__StimPort16 = 32'h00000000;
+parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort17 = 32'hF8805044;
+parameter val_debug_itm__StimPort17 = 32'h00000000;
+parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort18 = 32'hF8805048;
+parameter val_debug_itm__StimPort18 = 32'h00000000;
+parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort19 = 32'hF880504C;
+parameter val_debug_itm__StimPort19 = 32'h00000000;
+parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort20 = 32'hF8805050;
+parameter val_debug_itm__StimPort20 = 32'h00000000;
+parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort21 = 32'hF8805054;
+parameter val_debug_itm__StimPort21 = 32'h00000000;
+parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort22 = 32'hF8805058;
+parameter val_debug_itm__StimPort22 = 32'h00000000;
+parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort23 = 32'hF880505C;
+parameter val_debug_itm__StimPort23 = 32'h00000000;
+parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort24 = 32'hF8805060;
+parameter val_debug_itm__StimPort24 = 32'h00000000;
+parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort25 = 32'hF8805064;
+parameter val_debug_itm__StimPort25 = 32'h00000000;
+parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort26 = 32'hF8805068;
+parameter val_debug_itm__StimPort26 = 32'h00000000;
+parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort27 = 32'hF880506C;
+parameter val_debug_itm__StimPort27 = 32'h00000000;
+parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort28 = 32'hF8805070;
+parameter val_debug_itm__StimPort28 = 32'h00000000;
+parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort29 = 32'hF8805074;
+parameter val_debug_itm__StimPort29 = 32'h00000000;
+parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort30 = 32'hF8805078;
+parameter val_debug_itm__StimPort30 = 32'h00000000;
+parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF;
+
+parameter debug_itm__StimPort31 = 32'hF880507C;
+parameter val_debug_itm__StimPort31 = 32'h00000000;
+parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF;
+
+parameter debug_itm__TER = 32'hF8805E00;
+parameter val_debug_itm__TER = 32'h00000000;
+parameter mask_debug_itm__TER = 32'hFFFFFFFF;
+
+parameter debug_itm__TTR = 32'hF8805E20;
+parameter val_debug_itm__TTR = 32'h00000000;
+parameter mask_debug_itm__TTR = 32'hFFFFFFFF;
+
+parameter debug_itm__CR = 32'hF8805E80;
+parameter val_debug_itm__CR = 32'h00000004;
+parameter mask_debug_itm__CR = 32'h00FFFFFF;
+
+parameter debug_itm__SCR = 32'hF8805E90;
+parameter val_debug_itm__SCR = 32'h00000400;
+parameter mask_debug_itm__SCR = 32'h00000FFF;
+
+parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4;
+parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000;
+parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001;
+
+parameter debug_itm__ITTRIGOUT = 32'hF8805EE8;
+parameter val_debug_itm__ITTRIGOUT = 32'h00000000;
+parameter mask_debug_itm__ITTRIGOUT = 32'h00000001;
+
+parameter debug_itm__ITATBDATA0 = 32'hF8805EEC;
+parameter val_debug_itm__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_itm__ITATBDATA0 = 32'h00000003;
+
+parameter debug_itm__ITATBCTR2 = 32'hF8805EF0;
+parameter val_debug_itm__ITATBCTR2 = 32'h00000001;
+parameter mask_debug_itm__ITATBCTR2 = 32'h00000001;
+
+parameter debug_itm__ITATABCTR1 = 32'hF8805EF4;
+parameter val_debug_itm__ITATABCTR1 = 32'h00000000;
+parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F;
+
+parameter debug_itm__ITATBCTR0 = 32'hF8805EF8;
+parameter val_debug_itm__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_itm__ITATBCTR0 = 32'h00000003;
+
+parameter debug_itm__IMCR = 32'hF8805F00;
+parameter val_debug_itm__IMCR = 32'h00000000;
+parameter mask_debug_itm__IMCR = 32'h00000001;
+
+parameter debug_itm__CTSR = 32'hF8805FA0;
+parameter val_debug_itm__CTSR = 32'h000000FF;
+parameter mask_debug_itm__CTSR = 32'h000000FF;
+
+parameter debug_itm__CTCR = 32'hF8805FA4;
+parameter val_debug_itm__CTCR = 32'h00000000;
+parameter mask_debug_itm__CTCR = 32'h000000FF;
+
+parameter debug_itm__LAR = 32'hF8805FB0;
+parameter val_debug_itm__LAR = 32'h00000000;
+parameter mask_debug_itm__LAR = 32'hFFFFFFFF;
+
+parameter debug_itm__LSR = 32'hF8805FB4;
+parameter val_debug_itm__LSR = 32'h00000003;
+parameter mask_debug_itm__LSR = 32'h00000007;
+
+parameter debug_itm__ASR = 32'hF8805FB8;
+parameter val_debug_itm__ASR = 32'h00000088;
+parameter mask_debug_itm__ASR = 32'h000000FF;
+
+parameter debug_itm__DEVID = 32'hF8805FC8;
+parameter val_debug_itm__DEVID = 32'h00000020;
+parameter mask_debug_itm__DEVID = 32'h00001FFF;
+
+parameter debug_itm__DTIR = 32'hF8805FCC;
+parameter val_debug_itm__DTIR = 32'h00000043;
+parameter mask_debug_itm__DTIR = 32'h000000FF;
+
+parameter debug_itm__PERIPHID4 = 32'hF8805FD0;
+parameter val_debug_itm__PERIPHID4 = 32'h00000004;
+parameter mask_debug_itm__PERIPHID4 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID5 = 32'hF8805FD4;
+parameter val_debug_itm__PERIPHID5 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID5 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID6 = 32'hF8805FD8;
+parameter val_debug_itm__PERIPHID6 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID6 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID7 = 32'hF8805FDC;
+parameter val_debug_itm__PERIPHID7 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID7 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID0 = 32'hF8805FE0;
+parameter val_debug_itm__PERIPHID0 = 32'h00000013;
+parameter mask_debug_itm__PERIPHID0 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID1 = 32'hF8805FE4;
+parameter val_debug_itm__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_itm__PERIPHID1 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID2 = 32'hF8805FE8;
+parameter val_debug_itm__PERIPHID2 = 32'h0000002B;
+parameter mask_debug_itm__PERIPHID2 = 32'h000000FF;
+
+parameter debug_itm__PERIPHID3 = 32'hF8805FEC;
+parameter val_debug_itm__PERIPHID3 = 32'h00000000;
+parameter mask_debug_itm__PERIPHID3 = 32'h000000FF;
+
+parameter debug_itm__COMPID0 = 32'hF8805FF0;
+parameter val_debug_itm__COMPID0 = 32'h0000000D;
+parameter mask_debug_itm__COMPID0 = 32'h000000FF;
+
+parameter debug_itm__COMPID1 = 32'hF8805FF4;
+parameter val_debug_itm__COMPID1 = 32'h00000090;
+parameter mask_debug_itm__COMPID1 = 32'h000000FF;
+
+parameter debug_itm__COMPID2 = 32'hF8805FF8;
+parameter val_debug_itm__COMPID2 = 32'h00000005;
+parameter mask_debug_itm__COMPID2 = 32'h000000FF;
+
+parameter debug_itm__COMPID3 = 32'hF8805FFC;
+parameter val_debug_itm__COMPID3 = 32'h000000B1;
+parameter mask_debug_itm__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module debug_tpiu tpiu
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter debug_tpiu__SuppSize = 32'hF8803000;
+parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF;
+parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF;
+
+parameter debug_tpiu__CurrentSize = 32'hF8803004;
+parameter val_debug_tpiu__CurrentSize = 32'h00000001;
+parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF;
+
+parameter debug_tpiu__SuppTrigMode = 32'hF8803100;
+parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F;
+parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF;
+
+parameter debug_tpiu__TrigCount = 32'hF8803104;
+parameter val_debug_tpiu__TrigCount = 32'h00000000;
+parameter mask_debug_tpiu__TrigCount = 32'h000000FF;
+
+parameter debug_tpiu__TrigMult = 32'hF8803108;
+parameter val_debug_tpiu__TrigMult = 32'h00000000;
+parameter mask_debug_tpiu__TrigMult = 32'h0000001F;
+
+parameter debug_tpiu__SuppTest = 32'hF8803200;
+parameter val_debug_tpiu__SuppTest = 32'h0003000F;
+parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF;
+
+parameter debug_tpiu__CurrentTest = 32'hF8803204;
+parameter val_debug_tpiu__CurrentTest = 32'h00000000;
+parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF;
+
+parameter debug_tpiu__TestRepeatCount = 32'hF8803208;
+parameter val_debug_tpiu__TestRepeatCount = 32'h00000000;
+parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF;
+
+parameter debug_tpiu__FFSR = 32'hF8803300;
+parameter val_debug_tpiu__FFSR = 32'h00000006;
+parameter mask_debug_tpiu__FFSR = 32'h00000007;
+
+parameter debug_tpiu__FFCR = 32'hF8803304;
+parameter val_debug_tpiu__FFCR = 32'h00000000;
+parameter mask_debug_tpiu__FFCR = 32'h00003FFF;
+
+parameter debug_tpiu__FormatSyncCount = 32'hF8803308;
+parameter val_debug_tpiu__FormatSyncCount = 32'h00000040;
+parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF;
+
+parameter debug_tpiu__EXTCTLIn = 32'hF8803400;
+parameter val_debug_tpiu__EXTCTLIn = 32'h00000000;
+parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF;
+
+parameter debug_tpiu__EXTCTLOut = 32'hF8803404;
+parameter val_debug_tpiu__EXTCTLOut = 32'h00000000;
+parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF;
+
+parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4;
+parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000;
+parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003;
+
+parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8;
+parameter val_debug_tpiu__ITTRFLIN = 32'h00000000;
+parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000;
+
+parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC;
+parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000;
+
+parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0;
+parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003;
+
+parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4;
+parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000;
+
+parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8;
+parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000;
+parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000;
+
+parameter debug_tpiu__IMCR = 32'hF8803F00;
+parameter val_debug_tpiu__IMCR = 32'h00000000;
+parameter mask_debug_tpiu__IMCR = 32'h00000001;
+
+parameter debug_tpiu__CTSR = 32'hF8803FA0;
+parameter val_debug_tpiu__CTSR = 32'h0000000F;
+parameter mask_debug_tpiu__CTSR = 32'h0000000F;
+
+parameter debug_tpiu__CTCR = 32'hF8803FA4;
+parameter val_debug_tpiu__CTCR = 32'h00000000;
+parameter mask_debug_tpiu__CTCR = 32'h0000000F;
+
+parameter debug_tpiu__LAR = 32'hF8803FB0;
+parameter val_debug_tpiu__LAR = 32'h00000000;
+parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF;
+
+parameter debug_tpiu__LSR = 32'hF8803FB4;
+parameter val_debug_tpiu__LSR = 32'h00000003;
+parameter mask_debug_tpiu__LSR = 32'h00000007;
+
+parameter debug_tpiu__ASR = 32'hF8803FB8;
+parameter val_debug_tpiu__ASR = 32'h00000000;
+parameter mask_debug_tpiu__ASR = 32'h000000FF;
+
+parameter debug_tpiu__DEVID = 32'hF8803FC8;
+parameter val_debug_tpiu__DEVID = 32'h000000A0;
+parameter mask_debug_tpiu__DEVID = 32'h00000FFF;
+
+parameter debug_tpiu__DTIR = 32'hF8803FCC;
+parameter val_debug_tpiu__DTIR = 32'h00000011;
+parameter mask_debug_tpiu__DTIR = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0;
+parameter val_debug_tpiu__PERIPHID4 = 32'h00000004;
+parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4;
+parameter val_debug_tpiu__PERIPHID5 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8;
+parameter val_debug_tpiu__PERIPHID6 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC;
+parameter val_debug_tpiu__PERIPHID7 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0;
+parameter val_debug_tpiu__PERIPHID0 = 32'h00000012;
+parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4;
+parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9;
+parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8;
+parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B;
+parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF;
+
+parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC;
+parameter val_debug_tpiu__PERIPHID3 = 32'h00000000;
+parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID0 = 32'hF8803FF0;
+parameter val_debug_tpiu__COMPID0 = 32'h0000000D;
+parameter mask_debug_tpiu__COMPID0 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID1 = 32'hF8803FF4;
+parameter val_debug_tpiu__COMPID1 = 32'h00000090;
+parameter mask_debug_tpiu__COMPID1 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID2 = 32'hF8803FF8;
+parameter val_debug_tpiu__COMPID2 = 32'h00000005;
+parameter mask_debug_tpiu__COMPID2 = 32'h000000FF;
+
+parameter debug_tpiu__COMPID3 = 32'hF8803FFC;
+parameter val_debug_tpiu__COMPID3 = 32'h000000B1;
+parameter mask_debug_tpiu__COMPID3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module devcfg devcfg
+//   doc version: 1.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter devcfg__CTRL = 32'hF8007000;
+parameter val_devcfg__CTRL = 32'h0C000000;
+parameter mask_devcfg__CTRL = 32'hFFFFFFFF;
+
+parameter devcfg__LOCK = 32'hF8007004;
+parameter val_devcfg__LOCK = 32'h00000000;
+parameter mask_devcfg__LOCK = 32'hFFFFFFFF;
+
+parameter devcfg__CFG = 32'hF8007008;
+parameter val_devcfg__CFG = 32'h0000050B;
+parameter mask_devcfg__CFG = 32'hFFFFFFFF;
+
+parameter devcfg__INT_STS = 32'hF800700C;
+parameter val_devcfg__INT_STS = 32'h00000000;
+parameter mask_devcfg__INT_STS = 32'hFFFFFFFF;
+
+parameter devcfg__INT_MASK = 32'hF8007010;
+parameter val_devcfg__INT_MASK = 32'hFFFFFFFF;
+parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF;
+
+parameter devcfg__STATUS = 32'hF8007014;
+parameter val_devcfg__STATUS = 32'h40000820;
+parameter mask_devcfg__STATUS = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_SRC_ADDR = 32'hF8007018;
+parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000;
+parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_DST_ADDR = 32'hF800701C;
+parameter val_devcfg__DMA_DST_ADDR = 32'h00000000;
+parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_SRC_LEN = 32'hF8007020;
+parameter val_devcfg__DMA_SRC_LEN = 32'h00000000;
+parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF;
+
+parameter devcfg__DMA_DEST_LEN = 32'hF8007024;
+parameter val_devcfg__DMA_DEST_LEN = 32'h00000000;
+parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF;
+
+parameter devcfg__ROM_SHADOW = 32'hF8007028;
+parameter val_devcfg__ROM_SHADOW = 32'h00000000;
+parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF;
+
+parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C;
+parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000;
+parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF;
+
+parameter devcfg__SW_ID = 32'hF8007030;
+parameter val_devcfg__SW_ID = 32'h00000000;
+parameter mask_devcfg__SW_ID = 32'hFFFFFFFF;
+
+parameter devcfg__UNLOCK = 32'hF8007034;
+parameter val_devcfg__UNLOCK = 32'h00000000;
+parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF;
+
+parameter devcfg__MCTRL = 32'hF8007080;
+parameter val_devcfg__MCTRL = 32'h00800000;
+parameter mask_devcfg__MCTRL = 32'h0FFFFFFF;
+
+parameter devcfg__XADCIF_CFG = 32'hF8007100;
+parameter val_devcfg__XADCIF_CFG = 32'h00001114;
+parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_INT_STS = 32'hF8007104;
+parameter val_devcfg__XADCIF_INT_STS = 32'h00000200;
+parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_INT_MASK = 32'hF8007108;
+parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
+parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_MSTS = 32'hF800710C;
+parameter val_devcfg__XADCIF_MSTS = 32'h00000500;
+parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110;
+parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000;
+parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_RDFIFO = 32'hF8007114;
+parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000;
+parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF;
+
+parameter devcfg__XADCIF_MCTL = 32'hF8007118;
+parameter val_devcfg__XADCIF_MCTL = 32'h00000010;
+parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module dmac0_ns dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter dmac0_ns__DSR = 32'hF8004000;
+parameter val_dmac0_ns__DSR = 32'h00000000;
+parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DPC = 32'hF8004004;
+parameter val_dmac0_ns__DPC = 32'h00000000;
+parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTEN = 32'hF8004020;
+parameter val_dmac0_ns__INTEN = 32'h00000000;
+parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024;
+parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000;
+parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTMIS = 32'hF8004028;
+parameter val_dmac0_ns__INTMIS = 32'h00000000;
+parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__INTCLR = 32'hF800402C;
+parameter val_dmac0_ns__INTCLR = 32'h00000000;
+parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FSRD = 32'hF8004030;
+parameter val_dmac0_ns__FSRD = 32'h00000000;
+parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FSRC = 32'hF8004034;
+parameter val_dmac0_ns__FSRC = 32'h00000000;
+parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTRD = 32'hF8004038;
+parameter val_dmac0_ns__FTRD = 32'h00000000;
+parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR0 = 32'hF8004040;
+parameter val_dmac0_ns__FTR0 = 32'h00000000;
+parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR1 = 32'hF8004044;
+parameter val_dmac0_ns__FTR1 = 32'h00000000;
+parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR2 = 32'hF8004048;
+parameter val_dmac0_ns__FTR2 = 32'h00000000;
+parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR3 = 32'hF800404C;
+parameter val_dmac0_ns__FTR3 = 32'h00000000;
+parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR4 = 32'hF8004050;
+parameter val_dmac0_ns__FTR4 = 32'h00000000;
+parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR5 = 32'hF8004054;
+parameter val_dmac0_ns__FTR5 = 32'h00000000;
+parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR6 = 32'hF8004058;
+parameter val_dmac0_ns__FTR6 = 32'h00000000;
+parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__FTR7 = 32'hF800405C;
+parameter val_dmac0_ns__FTR7 = 32'h00000000;
+parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR0 = 32'hF8004100;
+parameter val_dmac0_ns__CSR0 = 32'h00000000;
+parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC0 = 32'hF8004104;
+parameter val_dmac0_ns__CPC0 = 32'h00000000;
+parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR1 = 32'hF8004108;
+parameter val_dmac0_ns__CSR1 = 32'h00000000;
+parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC1 = 32'hF800410C;
+parameter val_dmac0_ns__CPC1 = 32'h00000000;
+parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR2 = 32'hF8004110;
+parameter val_dmac0_ns__CSR2 = 32'h00000000;
+parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC2 = 32'hF8004114;
+parameter val_dmac0_ns__CPC2 = 32'h00000000;
+parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR3 = 32'hF8004118;
+parameter val_dmac0_ns__CSR3 = 32'h00000000;
+parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC3 = 32'hF800411C;
+parameter val_dmac0_ns__CPC3 = 32'h00000000;
+parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR4 = 32'hF8004120;
+parameter val_dmac0_ns__CSR4 = 32'h00000000;
+parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC4 = 32'hF8004124;
+parameter val_dmac0_ns__CPC4 = 32'h00000000;
+parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR5 = 32'hF8004128;
+parameter val_dmac0_ns__CSR5 = 32'h00000000;
+parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC5 = 32'hF800412C;
+parameter val_dmac0_ns__CPC5 = 32'h00000000;
+parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR6 = 32'hF8004130;
+parameter val_dmac0_ns__CSR6 = 32'h00000000;
+parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC6 = 32'hF8004134;
+parameter val_dmac0_ns__CPC6 = 32'h00000000;
+parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CSR7 = 32'hF8004138;
+parameter val_dmac0_ns__CSR7 = 32'h00000000;
+parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CPC7 = 32'hF800413C;
+parameter val_dmac0_ns__CPC7 = 32'h00000000;
+parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR0 = 32'hF8004400;
+parameter val_dmac0_ns__SAR0 = 32'h00000000;
+parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR0 = 32'hF8004404;
+parameter val_dmac0_ns__DAR0 = 32'h00000000;
+parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR0 = 32'hF8004408;
+parameter val_dmac0_ns__CCR0 = 32'h00000000;
+parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_0 = 32'hF800440C;
+parameter val_dmac0_ns__LC0_0 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_0 = 32'hF8004410;
+parameter val_dmac0_ns__LC1_0 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR1 = 32'hF8004420;
+parameter val_dmac0_ns__SAR1 = 32'h00000000;
+parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR1 = 32'hF8004424;
+parameter val_dmac0_ns__DAR1 = 32'h00000000;
+parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR1 = 32'hF8004428;
+parameter val_dmac0_ns__CCR1 = 32'h00000000;
+parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_1 = 32'hF800442C;
+parameter val_dmac0_ns__LC0_1 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_1 = 32'hF8004430;
+parameter val_dmac0_ns__LC1_1 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR2 = 32'hF8004440;
+parameter val_dmac0_ns__SAR2 = 32'h00000000;
+parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR2 = 32'hF8004444;
+parameter val_dmac0_ns__DAR2 = 32'h00000000;
+parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR2 = 32'hF8004448;
+parameter val_dmac0_ns__CCR2 = 32'h00000000;
+parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_2 = 32'hF800444C;
+parameter val_dmac0_ns__LC0_2 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_2 = 32'hF8004450;
+parameter val_dmac0_ns__LC1_2 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR3 = 32'hF8004460;
+parameter val_dmac0_ns__SAR3 = 32'h00000000;
+parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR3 = 32'hF8004464;
+parameter val_dmac0_ns__DAR3 = 32'h00000000;
+parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR3 = 32'hF8004468;
+parameter val_dmac0_ns__CCR3 = 32'h00000000;
+parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_3 = 32'hF800446C;
+parameter val_dmac0_ns__LC0_3 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_3 = 32'hF8004470;
+parameter val_dmac0_ns__LC1_3 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR4 = 32'hF8004480;
+parameter val_dmac0_ns__SAR4 = 32'h00000000;
+parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR4 = 32'hF8004484;
+parameter val_dmac0_ns__DAR4 = 32'h00000000;
+parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR4 = 32'hF8004488;
+parameter val_dmac0_ns__CCR4 = 32'h00000000;
+parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_4 = 32'hF800448C;
+parameter val_dmac0_ns__LC0_4 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_4 = 32'hF8004490;
+parameter val_dmac0_ns__LC1_4 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR5 = 32'hF80044A0;
+parameter val_dmac0_ns__SAR5 = 32'h00000000;
+parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR5 = 32'hF80044A4;
+parameter val_dmac0_ns__DAR5 = 32'h00000000;
+parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR5 = 32'hF80044A8;
+parameter val_dmac0_ns__CCR5 = 32'h00000000;
+parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_5 = 32'hF80044AC;
+parameter val_dmac0_ns__LC0_5 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_5 = 32'hF80044B0;
+parameter val_dmac0_ns__LC1_5 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR6 = 32'hF80044C0;
+parameter val_dmac0_ns__SAR6 = 32'h00000000;
+parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR6 = 32'hF80044C4;
+parameter val_dmac0_ns__DAR6 = 32'h00000000;
+parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR6 = 32'hF80044C8;
+parameter val_dmac0_ns__CCR6 = 32'h00000000;
+parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_6 = 32'hF80044CC;
+parameter val_dmac0_ns__LC0_6 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_6 = 32'hF80044D0;
+parameter val_dmac0_ns__LC1_6 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__SAR7 = 32'hF80044E0;
+parameter val_dmac0_ns__SAR7 = 32'h00000000;
+parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DAR7 = 32'hF80044E4;
+parameter val_dmac0_ns__DAR7 = 32'h00000000;
+parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CCR7 = 32'hF80044E8;
+parameter val_dmac0_ns__CCR7 = 32'h00000000;
+parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC0_7 = 32'hF80044EC;
+parameter val_dmac0_ns__LC0_7 = 32'h00000000;
+parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__LC1_7 = 32'hF80044F0;
+parameter val_dmac0_ns__LC1_7 = 32'h00000000;
+parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGSTATUS = 32'hF8004D00;
+parameter val_dmac0_ns__DBGSTATUS = 32'h00000000;
+parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGCMD = 32'hF8004D04;
+parameter val_dmac0_ns__DBGCMD = 32'h00000000;
+parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGINST0 = 32'hF8004D08;
+parameter val_dmac0_ns__DBGINST0 = 32'h00000000;
+parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__DBGINST1 = 32'hF8004D0C;
+parameter val_dmac0_ns__DBGINST1 = 32'h00000000;
+parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR0 = 32'hF8004E00;
+parameter val_dmac0_ns__CR0 = 32'h00000000;
+parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR1 = 32'hF8004E04;
+parameter val_dmac0_ns__CR1 = 32'h00000000;
+parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR2 = 32'hF8004E08;
+parameter val_dmac0_ns__CR2 = 32'h00000000;
+parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR3 = 32'hF8004E0C;
+parameter val_dmac0_ns__CR3 = 32'h00000000;
+parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CR4 = 32'hF8004E10;
+parameter val_dmac0_ns__CR4 = 32'h00000000;
+parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__CRD = 32'hF8004E14;
+parameter val_dmac0_ns__CRD = 32'h00000000;
+parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__WD = 32'hF8004E80;
+parameter val_dmac0_ns__WD = 32'h00000000;
+parameter mask_dmac0_ns__WD = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_0 = 32'hF8004FE0;
+parameter val_dmac0_ns__periph_id_0 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_1 = 32'hF8004FE4;
+parameter val_dmac0_ns__periph_id_1 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_2 = 32'hF8004FE8;
+parameter val_dmac0_ns__periph_id_2 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__periph_id_3 = 32'hF8004FEC;
+parameter val_dmac0_ns__periph_id_3 = 32'h00000000;
+parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0;
+parameter val_dmac0_ns__pcell_id_0 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4;
+parameter val_dmac0_ns__pcell_id_1 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8;
+parameter val_dmac0_ns__pcell_id_2 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC;
+parameter val_dmac0_ns__pcell_id_3 = 32'h00000000;
+parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module dmac0_s dmac
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter dmac0_s__DSR = 32'hF8003000;
+parameter val_dmac0_s__DSR = 32'h00000000;
+parameter mask_dmac0_s__DSR = 32'hFFFFFFFF;
+
+parameter dmac0_s__DPC = 32'hF8003004;
+parameter val_dmac0_s__DPC = 32'h00000000;
+parameter mask_dmac0_s__DPC = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTEN = 32'hF8003020;
+parameter val_dmac0_s__INTEN = 32'h00000000;
+parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF;
+
+parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024;
+parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000;
+parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTMIS = 32'hF8003028;
+parameter val_dmac0_s__INTMIS = 32'h00000000;
+parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF;
+
+parameter dmac0_s__INTCLR = 32'hF800302C;
+parameter val_dmac0_s__INTCLR = 32'h00000000;
+parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF;
+
+parameter dmac0_s__FSRD = 32'hF8003030;
+parameter val_dmac0_s__FSRD = 32'h00000000;
+parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__FSRC = 32'hF8003034;
+parameter val_dmac0_s__FSRC = 32'h00000000;
+parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTRD = 32'hF8003038;
+parameter val_dmac0_s__FTRD = 32'h00000000;
+parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR0 = 32'hF8003040;
+parameter val_dmac0_s__FTR0 = 32'h00000000;
+parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR1 = 32'hF8003044;
+parameter val_dmac0_s__FTR1 = 32'h00000000;
+parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR2 = 32'hF8003048;
+parameter val_dmac0_s__FTR2 = 32'h00000000;
+parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR3 = 32'hF800304C;
+parameter val_dmac0_s__FTR3 = 32'h00000000;
+parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR4 = 32'hF8003050;
+parameter val_dmac0_s__FTR4 = 32'h00000000;
+parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR5 = 32'hF8003054;
+parameter val_dmac0_s__FTR5 = 32'h00000000;
+parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR6 = 32'hF8003058;
+parameter val_dmac0_s__FTR6 = 32'h00000000;
+parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__FTR7 = 32'hF800305C;
+parameter val_dmac0_s__FTR7 = 32'h00000000;
+parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR0 = 32'hF8003100;
+parameter val_dmac0_s__CSR0 = 32'h00000000;
+parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC0 = 32'hF8003104;
+parameter val_dmac0_s__CPC0 = 32'h00000000;
+parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR1 = 32'hF8003108;
+parameter val_dmac0_s__CSR1 = 32'h00000000;
+parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC1 = 32'hF800310C;
+parameter val_dmac0_s__CPC1 = 32'h00000000;
+parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR2 = 32'hF8003110;
+parameter val_dmac0_s__CSR2 = 32'h00000000;
+parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC2 = 32'hF8003114;
+parameter val_dmac0_s__CPC2 = 32'h00000000;
+parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR3 = 32'hF8003118;
+parameter val_dmac0_s__CSR3 = 32'h00000000;
+parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC3 = 32'hF800311C;
+parameter val_dmac0_s__CPC3 = 32'h00000000;
+parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR4 = 32'hF8003120;
+parameter val_dmac0_s__CSR4 = 32'h00000000;
+parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC4 = 32'hF8003124;
+parameter val_dmac0_s__CPC4 = 32'h00000000;
+parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR5 = 32'hF8003128;
+parameter val_dmac0_s__CSR5 = 32'h00000000;
+parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC5 = 32'hF800312C;
+parameter val_dmac0_s__CPC5 = 32'h00000000;
+parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR6 = 32'hF8003130;
+parameter val_dmac0_s__CSR6 = 32'h00000000;
+parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC6 = 32'hF8003134;
+parameter val_dmac0_s__CPC6 = 32'h00000000;
+parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CSR7 = 32'hF8003138;
+parameter val_dmac0_s__CSR7 = 32'h00000000;
+parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CPC7 = 32'hF800313C;
+parameter val_dmac0_s__CPC7 = 32'h00000000;
+parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR0 = 32'hF8003400;
+parameter val_dmac0_s__SAR0 = 32'h00000000;
+parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR0 = 32'hF8003404;
+parameter val_dmac0_s__DAR0 = 32'h00000000;
+parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR0 = 32'hF8003408;
+parameter val_dmac0_s__CCR0 = 32'h00800200;
+parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_0 = 32'hF800340C;
+parameter val_dmac0_s__LC0_0 = 32'h00000000;
+parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_0 = 32'hF8003410;
+parameter val_dmac0_s__LC1_0 = 32'h00000000;
+parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR1 = 32'hF8003420;
+parameter val_dmac0_s__SAR1 = 32'h00000000;
+parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR1 = 32'hF8003424;
+parameter val_dmac0_s__DAR1 = 32'h00000000;
+parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR1 = 32'hF8003428;
+parameter val_dmac0_s__CCR1 = 32'h00800200;
+parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_1 = 32'hF800342C;
+parameter val_dmac0_s__LC0_1 = 32'h00000000;
+parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_1 = 32'hF8003430;
+parameter val_dmac0_s__LC1_1 = 32'h00000000;
+parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR2 = 32'hF8003440;
+parameter val_dmac0_s__SAR2 = 32'h00000000;
+parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR2 = 32'hF8003444;
+parameter val_dmac0_s__DAR2 = 32'h00000000;
+parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR2 = 32'hF8003448;
+parameter val_dmac0_s__CCR2 = 32'h00800200;
+parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_2 = 32'hF800344C;
+parameter val_dmac0_s__LC0_2 = 32'h00000000;
+parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_2 = 32'hF8003450;
+parameter val_dmac0_s__LC1_2 = 32'h00000000;
+parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR3 = 32'hF8003460;
+parameter val_dmac0_s__SAR3 = 32'h00000000;
+parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR3 = 32'hF8003464;
+parameter val_dmac0_s__DAR3 = 32'h00000000;
+parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR3 = 32'hF8003468;
+parameter val_dmac0_s__CCR3 = 32'h00800200;
+parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_3 = 32'hF800346C;
+parameter val_dmac0_s__LC0_3 = 32'h00000000;
+parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_3 = 32'hF8003470;
+parameter val_dmac0_s__LC1_3 = 32'h00000000;
+parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR4 = 32'hF8003480;
+parameter val_dmac0_s__SAR4 = 32'h00000000;
+parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR4 = 32'hF8003484;
+parameter val_dmac0_s__DAR4 = 32'h00000000;
+parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR4 = 32'hF8003488;
+parameter val_dmac0_s__CCR4 = 32'h00800200;
+parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_4 = 32'hF800348C;
+parameter val_dmac0_s__LC0_4 = 32'h00000000;
+parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_4 = 32'hF8003490;
+parameter val_dmac0_s__LC1_4 = 32'h00000000;
+parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR5 = 32'hF80034A0;
+parameter val_dmac0_s__SAR5 = 32'h00000000;
+parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR5 = 32'hF80034A4;
+parameter val_dmac0_s__DAR5 = 32'h00000000;
+parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR5 = 32'hF80034A8;
+parameter val_dmac0_s__CCR5 = 32'h00800200;
+parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_5 = 32'hF80034AC;
+parameter val_dmac0_s__LC0_5 = 32'h00000000;
+parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_5 = 32'hF80034B0;
+parameter val_dmac0_s__LC1_5 = 32'h00000000;
+parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR6 = 32'hF80034C0;
+parameter val_dmac0_s__SAR6 = 32'h00000000;
+parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR6 = 32'hF80034C4;
+parameter val_dmac0_s__DAR6 = 32'h00000000;
+parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR6 = 32'hF80034C8;
+parameter val_dmac0_s__CCR6 = 32'h00800200;
+parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_6 = 32'hF80034CC;
+parameter val_dmac0_s__LC0_6 = 32'h00000000;
+parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_6 = 32'hF80034D0;
+parameter val_dmac0_s__LC1_6 = 32'h00000000;
+parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF;
+
+parameter dmac0_s__SAR7 = 32'hF80034E0;
+parameter val_dmac0_s__SAR7 = 32'h00000000;
+parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DAR7 = 32'hF80034E4;
+parameter val_dmac0_s__DAR7 = 32'h00000000;
+parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CCR7 = 32'hF80034E8;
+parameter val_dmac0_s__CCR7 = 32'h00800200;
+parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC0_7 = 32'hF80034EC;
+parameter val_dmac0_s__LC0_7 = 32'h00000000;
+parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__LC1_7 = 32'hF80034F0;
+parameter val_dmac0_s__LC1_7 = 32'h00000000;
+parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGSTATUS = 32'hF8003D00;
+parameter val_dmac0_s__DBGSTATUS = 32'h00000000;
+parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGCMD = 32'hF8003D04;
+parameter val_dmac0_s__DBGCMD = 32'h00000000;
+parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGINST0 = 32'hF8003D08;
+parameter val_dmac0_s__DBGINST0 = 32'h00000000;
+parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__DBGINST1 = 32'hF8003D0C;
+parameter val_dmac0_s__DBGINST1 = 32'h00000000;
+parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR0 = 32'hF8003E00;
+parameter val_dmac0_s__CR0 = 32'h001E3071;
+parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR1 = 32'hF8003E04;
+parameter val_dmac0_s__CR1 = 32'h00000074;
+parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR2 = 32'hF8003E08;
+parameter val_dmac0_s__CR2 = 32'h00000000;
+parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR3 = 32'hF8003E0C;
+parameter val_dmac0_s__CR3 = 32'h00000000;
+parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CR4 = 32'hF8003E10;
+parameter val_dmac0_s__CR4 = 32'h00000000;
+parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF;
+
+parameter dmac0_s__CRD = 32'hF8003E14;
+parameter val_dmac0_s__CRD = 32'h07FF7F73;
+parameter mask_dmac0_s__CRD = 32'hFFFFFFFF;
+
+parameter dmac0_s__WD = 32'hF8003E80;
+parameter val_dmac0_s__WD = 32'h00000000;
+parameter mask_dmac0_s__WD = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_0 = 32'hF8003FE0;
+parameter val_dmac0_s__periph_id_0 = 32'h00000030;
+parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_1 = 32'hF8003FE4;
+parameter val_dmac0_s__periph_id_1 = 32'h00000013;
+parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_2 = 32'hF8003FE8;
+parameter val_dmac0_s__periph_id_2 = 32'h00000024;
+parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__periph_id_3 = 32'hF8003FEC;
+parameter val_dmac0_s__periph_id_3 = 32'h00000000;
+parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_0 = 32'hF8003FF0;
+parameter val_dmac0_s__pcell_id_0 = 32'h0000000D;
+parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_1 = 32'hF8003FF4;
+parameter val_dmac0_s__pcell_id_1 = 32'h000000F0;
+parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_2 = 32'hF8003FF8;
+parameter val_dmac0_s__pcell_id_2 = 32'h00000005;
+parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF;
+
+parameter dmac0_s__pcell_id_3 = 32'hF8003FFC;
+parameter val_dmac0_s__pcell_id_3 = 32'h000000B1;
+parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module efuse_ctrl efuse_ctrl
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter efuse_ctrl__WR_LOCK = 32'hF800D000;
+parameter val_efuse_ctrl__WR_LOCK = 32'h00000000;
+parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004;
+parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000;
+parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008;
+parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001;
+parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__CFG = 32'hF800D00C;
+parameter val_efuse_ctrl__CFG = 32'h00010F00;
+parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__STATUS = 32'hF800D010;
+parameter val_efuse_ctrl__STATUS = 32'h00100000;
+parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__CONTROL = 32'hF800D014;
+parameter val_efuse_ctrl__CONTROL = 32'h00000003;
+parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__PGM_STBW = 32'hF800D018;
+parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0;
+parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF;
+
+parameter efuse_ctrl__RD_STBW = 32'hF800D01C;
+parameter val_efuse_ctrl__RD_STBW = 32'h0000000B;
+parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module gem0 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gem0__net_ctrl = 32'hE000B000;
+parameter val_gem0__net_ctrl = 32'h00000000;
+parameter mask_gem0__net_ctrl = 32'hFFFFFFFF;
+
+parameter gem0__net_cfg = 32'hE000B004;
+parameter val_gem0__net_cfg = 32'h00080000;
+parameter mask_gem0__net_cfg = 32'hFFFFFFFF;
+
+parameter gem0__net_status = 32'hE000B008;
+parameter val_gem0__net_status = 32'h00000004;
+parameter mask_gem0__net_status = 32'hFFFFFFFD;
+
+parameter gem0__user_io = 32'hE000B00C;
+parameter val_gem0__user_io = 32'h00000000;
+parameter mask_gem0__user_io = 32'h0000FFFF;
+
+parameter gem0__dma_cfg = 32'hE000B010;
+parameter val_gem0__dma_cfg = 32'h00020784;
+parameter mask_gem0__dma_cfg = 32'hFFFFFFFF;
+
+parameter gem0__tx_status = 32'hE000B014;
+parameter val_gem0__tx_status = 32'h00000000;
+parameter mask_gem0__tx_status = 32'hFFFFFFFF;
+
+parameter gem0__rx_qbar = 32'hE000B018;
+parameter val_gem0__rx_qbar = 32'h00000000;
+parameter mask_gem0__rx_qbar = 32'hFFFFFFFF;
+
+parameter gem0__tx_qbar = 32'hE000B01C;
+parameter val_gem0__tx_qbar = 32'h00000000;
+parameter mask_gem0__tx_qbar = 32'hFFFFFFFF;
+
+parameter gem0__rx_status = 32'hE000B020;
+parameter val_gem0__rx_status = 32'h00000000;
+parameter mask_gem0__rx_status = 32'hFFFFFFFF;
+
+parameter gem0__intr_status = 32'hE000B024;
+parameter val_gem0__intr_status = 32'h00000000;
+parameter mask_gem0__intr_status = 32'hFFFFFFFF;
+
+parameter gem0__intr_en = 32'hE000B028;
+parameter val_gem0__intr_en = 32'h00000000;
+parameter mask_gem0__intr_en = 32'h00000000;
+
+parameter gem0__intr_dis = 32'hE000B02C;
+parameter val_gem0__intr_dis = 32'h00000000;
+parameter mask_gem0__intr_dis = 32'h00000000;
+
+parameter gem0__intr_mask = 32'hE000B030;
+parameter val_gem0__intr_mask = 32'h0001FFFF;
+parameter mask_gem0__intr_mask = 32'hFC01FFFF;
+
+parameter gem0__phy_maint = 32'hE000B034;
+parameter val_gem0__phy_maint = 32'h00000000;
+parameter mask_gem0__phy_maint = 32'hFFFFFFFF;
+
+parameter gem0__rx_pauseq = 32'hE000B038;
+parameter val_gem0__rx_pauseq = 32'h00000000;
+parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF;
+
+parameter gem0__tx_pauseq = 32'hE000B03C;
+parameter val_gem0__tx_pauseq = 32'h0000FFFF;
+parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF;
+
+parameter gem0__tx_partial_st_fwd = 32'hE000B040;
+parameter val_gem0__tx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem0__rx_partial_st_fwd = 32'hE000B044;
+parameter val_gem0__rx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem0__hash_bot = 32'hE000B080;
+parameter val_gem0__hash_bot = 32'h00000000;
+parameter mask_gem0__hash_bot = 32'hFFFFFFFF;
+
+parameter gem0__hash_top = 32'hE000B084;
+parameter val_gem0__hash_top = 32'h00000000;
+parameter mask_gem0__hash_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_bot = 32'hE000B088;
+parameter val_gem0__spec_addr1_bot = 32'h00000000;
+parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_top = 32'hE000B08C;
+parameter val_gem0__spec_addr1_top = 32'h00000000;
+parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr2_bot = 32'hE000B090;
+parameter val_gem0__spec_addr2_bot = 32'h00000000;
+parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr2_top = 32'hE000B094;
+parameter val_gem0__spec_addr2_top = 32'h00000000;
+parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr3_bot = 32'hE000B098;
+parameter val_gem0__spec_addr3_bot = 32'h00000000;
+parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr3_top = 32'hE000B09C;
+parameter val_gem0__spec_addr3_top = 32'h00000000;
+parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr4_bot = 32'hE000B0A0;
+parameter val_gem0__spec_addr4_bot = 32'h00000000;
+parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr4_top = 32'hE000B0A4;
+parameter val_gem0__spec_addr4_top = 32'h00000000;
+parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match1 = 32'hE000B0A8;
+parameter val_gem0__type_id_match1 = 32'h00000000;
+parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match2 = 32'hE000B0AC;
+parameter val_gem0__type_id_match2 = 32'h00000000;
+parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match3 = 32'hE000B0B0;
+parameter val_gem0__type_id_match3 = 32'h00000000;
+parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF;
+
+parameter gem0__type_id_match4 = 32'hE000B0B4;
+parameter val_gem0__type_id_match4 = 32'h00000000;
+parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF;
+
+parameter gem0__wake_on_lan = 32'hE000B0B8;
+parameter val_gem0__wake_on_lan = 32'h00000000;
+parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF;
+
+parameter gem0__ipg_stretch = 32'hE000B0BC;
+parameter val_gem0__ipg_stretch = 32'h00000000;
+parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF;
+
+parameter gem0__stacked_vlan = 32'hE000B0C0;
+parameter val_gem0__stacked_vlan = 32'h00000000;
+parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF;
+
+parameter gem0__tx_pfc_pause = 32'hE000B0C4;
+parameter val_gem0__tx_pfc_pause = 32'h00000000;
+parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8;
+parameter val_gem0__spec_addr1_mask_bot = 32'h00000000;
+parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF;
+
+parameter gem0__spec_addr1_mask_top = 32'hE000B0CC;
+parameter val_gem0__spec_addr1_mask_top = 32'h00000000;
+parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF;
+
+parameter gem0__module_id = 32'hE000B0FC;
+parameter val_gem0__module_id = 32'h00020118;
+parameter mask_gem0__module_id = 32'hFFFFFFFF;
+
+parameter gem0__octets_tx_bot = 32'hE000B100;
+parameter val_gem0__octets_tx_bot = 32'h00000000;
+parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF;
+
+parameter gem0__octets_tx_top = 32'hE000B104;
+parameter val_gem0__octets_tx_top = 32'h00000000;
+parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF;
+
+parameter gem0__frames_tx = 32'hE000B108;
+parameter val_gem0__frames_tx = 32'h00000000;
+parameter mask_gem0__frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__broadcast_frames_tx = 32'hE000B10C;
+parameter val_gem0__broadcast_frames_tx = 32'h00000000;
+parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__multi_frames_tx = 32'hE000B110;
+parameter val_gem0__multi_frames_tx = 32'h00000000;
+parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__pause_frames_tx = 32'hE000B114;
+parameter val_gem0__pause_frames_tx = 32'h00000000;
+parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_64b_tx = 32'hE000B118;
+parameter val_gem0__frames_64b_tx = 32'h00000000;
+parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_65to127b_tx = 32'hE000B11C;
+parameter val_gem0__frames_65to127b_tx = 32'h00000000;
+parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_128to255b_tx = 32'hE000B120;
+parameter val_gem0__frames_128to255b_tx = 32'h00000000;
+parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_256to511b_tx = 32'hE000B124;
+parameter val_gem0__frames_256to511b_tx = 32'h00000000;
+parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_512to1023b_tx = 32'hE000B128;
+parameter val_gem0__frames_512to1023b_tx = 32'h00000000;
+parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_1024to1518b_tx = 32'hE000B12C;
+parameter val_gem0__frames_1024to1518b_tx = 32'h00000000;
+parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF;
+
+parameter gem0__frames_gt1518b_tx = 32'hE000B130;
+parameter val_gem0__frames_gt1518b_tx = 32'h00000000;
+parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF;
+
+parameter gem0__tx_under_runs = 32'hE000B134;
+parameter val_gem0__tx_under_runs = 32'h00000000;
+parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF;
+
+parameter gem0__single_collisn_frames = 32'hE000B138;
+parameter val_gem0__single_collisn_frames = 32'h00000000;
+parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem0__multi_collisn_frames = 32'hE000B13C;
+parameter val_gem0__multi_collisn_frames = 32'h00000000;
+parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem0__excessive_collisns = 32'hE000B140;
+parameter val_gem0__excessive_collisns = 32'h00000000;
+parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF;
+
+parameter gem0__late_collisns = 32'hE000B144;
+parameter val_gem0__late_collisns = 32'h00000000;
+parameter mask_gem0__late_collisns = 32'hFFFFFFFF;
+
+parameter gem0__deferred_tx_frames = 32'hE000B148;
+parameter val_gem0__deferred_tx_frames = 32'h00000000;
+parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF;
+
+parameter gem0__carrier_sense_errs = 32'hE000B14C;
+parameter val_gem0__carrier_sense_errs = 32'h00000000;
+parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF;
+
+parameter gem0__octets_rx_bot = 32'hE000B150;
+parameter val_gem0__octets_rx_bot = 32'h00000000;
+parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF;
+
+parameter gem0__octets_rx_top = 32'hE000B154;
+parameter val_gem0__octets_rx_top = 32'h00000000;
+parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF;
+
+parameter gem0__frames_rx = 32'hE000B158;
+parameter val_gem0__frames_rx = 32'h00000000;
+parameter mask_gem0__frames_rx = 32'hFFFFFFFF;
+
+parameter gem0__bdcast_fames_rx = 32'hE000B15C;
+parameter val_gem0__bdcast_fames_rx = 32'h00000000;
+parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF;
+
+parameter gem0__multi_frames_rx = 32'hE000B160;
+parameter val_gem0__multi_frames_rx = 32'h00000000;
+parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF;
+
+parameter gem0__pause_rx = 32'hE000B164;
+parameter val_gem0__pause_rx = 32'h00000000;
+parameter mask_gem0__pause_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_64b_rx = 32'hE000B168;
+parameter val_gem0__frames_64b_rx = 32'h00000000;
+parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_65to127b_rx = 32'hE000B16C;
+parameter val_gem0__frames_65to127b_rx = 32'h00000000;
+parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_128to255b_rx = 32'hE000B170;
+parameter val_gem0__frames_128to255b_rx = 32'h00000000;
+parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_256to511b_rx = 32'hE000B174;
+parameter val_gem0__frames_256to511b_rx = 32'h00000000;
+parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_512to1023b_rx = 32'hE000B178;
+parameter val_gem0__frames_512to1023b_rx = 32'h00000000;
+parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_1024to1518b_rx = 32'hE000B17C;
+parameter val_gem0__frames_1024to1518b_rx = 32'h00000000;
+parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF;
+
+parameter gem0__frames_gt1518b_rx = 32'hE000B180;
+parameter val_gem0__frames_gt1518b_rx = 32'h00000000;
+parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF;
+
+parameter gem0__undersz_rx = 32'hE000B184;
+parameter val_gem0__undersz_rx = 32'h00000000;
+parameter mask_gem0__undersz_rx = 32'hFFFFFFFF;
+
+parameter gem0__oversz_rx = 32'hE000B188;
+parameter val_gem0__oversz_rx = 32'h00000000;
+parameter mask_gem0__oversz_rx = 32'hFFFFFFFF;
+
+parameter gem0__jab_rx = 32'hE000B18C;
+parameter val_gem0__jab_rx = 32'h00000000;
+parameter mask_gem0__jab_rx = 32'hFFFFFFFF;
+
+parameter gem0__fcs_errors = 32'hE000B190;
+parameter val_gem0__fcs_errors = 32'h00000000;
+parameter mask_gem0__fcs_errors = 32'hFFFFFFFF;
+
+parameter gem0__length_field_errors = 32'hE000B194;
+parameter val_gem0__length_field_errors = 32'h00000000;
+parameter mask_gem0__length_field_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_symbol_errors = 32'hE000B198;
+parameter val_gem0__rx_symbol_errors = 32'h00000000;
+parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF;
+
+parameter gem0__align_errors = 32'hE000B19C;
+parameter val_gem0__align_errors = 32'h00000000;
+parameter mask_gem0__align_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_resource_errors = 32'hE000B1A0;
+parameter val_gem0__rx_resource_errors = 32'h00000000;
+parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF;
+
+parameter gem0__rx_overrun_errors = 32'hE000B1A4;
+parameter val_gem0__rx_overrun_errors = 32'h00000000;
+parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF;
+
+parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8;
+parameter val_gem0__ip_hdr_csum_errors = 32'h00000000;
+parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__tcp_csum_errors = 32'hE000B1AC;
+parameter val_gem0__tcp_csum_errors = 32'h00000000;
+parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__udp_csum_errors = 32'hE000B1B0;
+parameter val_gem0__udp_csum_errors = 32'h00000000;
+parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem0__timer_strobe_s = 32'hE000B1C8;
+parameter val_gem0__timer_strobe_s = 32'h00000000;
+parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF;
+
+parameter gem0__timer_strobe_ns = 32'hE000B1CC;
+parameter val_gem0__timer_strobe_ns = 32'h00000000;
+parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF;
+
+parameter gem0__timer_s = 32'hE000B1D0;
+parameter val_gem0__timer_s = 32'h00000000;
+parameter mask_gem0__timer_s = 32'hFFFFFFFF;
+
+parameter gem0__timer_ns = 32'hE000B1D4;
+parameter val_gem0__timer_ns = 32'h00000000;
+parameter mask_gem0__timer_ns = 32'hFFFFFFFF;
+
+parameter gem0__timer_adjust = 32'hE000B1D8;
+parameter val_gem0__timer_adjust = 32'h00000000;
+parameter mask_gem0__timer_adjust = 32'hFFFFFFFF;
+
+parameter gem0__timer_incr = 32'hE000B1DC;
+parameter val_gem0__timer_incr = 32'h00000000;
+parameter mask_gem0__timer_incr = 32'hFFFFFFFF;
+
+parameter gem0__ptp_tx_s = 32'hE000B1E0;
+parameter val_gem0__ptp_tx_s = 32'h00000000;
+parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_tx_ns = 32'hE000B1E4;
+parameter val_gem0__ptp_tx_ns = 32'h00000000;
+parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_rx_s = 32'hE000B1E8;
+parameter val_gem0__ptp_rx_s = 32'h00000000;
+parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_rx_ns = 32'hE000B1EC;
+parameter val_gem0__ptp_rx_ns = 32'h00000000;
+parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_tx_s = 32'hE000B1F0;
+parameter val_gem0__ptp_peer_tx_s = 32'h00000000;
+parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4;
+parameter val_gem0__ptp_peer_tx_ns = 32'h00000000;
+parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_rx_s = 32'hE000B1F8;
+parameter val_gem0__ptp_peer_rx_s = 32'h00000000;
+parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF;
+
+parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC;
+parameter val_gem0__ptp_peer_rx_ns = 32'h00000000;
+parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF;
+
+parameter gem0__pcs_ctrl = 32'hE000B200;
+parameter val_gem0__pcs_ctrl = 32'h00000000;
+parameter mask_gem0__pcs_ctrl = 32'h00000000;
+
+parameter gem0__pcs_status = 32'hE000B204;
+parameter val_gem0__pcs_status = 32'h00000000;
+parameter mask_gem0__pcs_status = 32'h00000000;
+
+parameter gem0__pcs_upper_phy_id = 32'hE000B208;
+parameter val_gem0__pcs_upper_phy_id = 32'h00000000;
+parameter mask_gem0__pcs_upper_phy_id = 32'h00000000;
+
+parameter gem0__pcs_lower_phy_id = 32'hE000B20C;
+parameter val_gem0__pcs_lower_phy_id = 32'h00000000;
+parameter mask_gem0__pcs_lower_phy_id = 32'h00000000;
+
+parameter gem0__pcs_autoneg_ad = 32'hE000B210;
+parameter val_gem0__pcs_autoneg_ad = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_ad = 32'h00000000;
+
+parameter gem0__pcs_autoneg_ability = 32'hE000B214;
+parameter val_gem0__pcs_autoneg_ability = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_ability = 32'h00000000;
+
+parameter gem0__pcs_autonec_exp = 32'hE000B218;
+parameter val_gem0__pcs_autonec_exp = 32'h00000000;
+parameter mask_gem0__pcs_autonec_exp = 32'h00000000;
+
+parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C;
+parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000;
+
+parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220;
+parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
+parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
+
+parameter gem0__pcs_extended_status = 32'hE000B23C;
+parameter val_gem0__pcs_extended_status = 32'h00000000;
+parameter mask_gem0__pcs_extended_status = 32'h00000000;
+
+parameter gem0__design_cfg1 = 32'hE000B280;
+parameter val_gem0__design_cfg1 = 32'h02000000;
+parameter mask_gem0__design_cfg1 = 32'h0E000000;
+
+parameter gem0__design_cfg2 = 32'hE000B284;
+parameter val_gem0__design_cfg2 = 32'h2A813FFF;
+parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF;
+
+parameter gem0__design_cfg3 = 32'hE000B288;
+parameter val_gem0__design_cfg3 = 32'h00000000;
+parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF;
+
+parameter gem0__design_cfg4 = 32'hE000B28C;
+parameter val_gem0__design_cfg4 = 32'h00000000;
+parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF;
+
+parameter gem0__design_cfg5 = 32'hE000B290;
+parameter val_gem0__design_cfg5 = 32'h002F2045;
+parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF;
+
+parameter gem0__design_cfg6 = 32'hE000B294;
+parameter val_gem0__design_cfg6 = 32'h00000000;
+parameter mask_gem0__design_cfg6 = 32'h00000000;
+
+parameter gem0__design_cfg7 = 32'hE000B298;
+parameter val_gem0__design_cfg7 = 32'h00000000;
+parameter mask_gem0__design_cfg7 = 32'h00000000;
+
+parameter gem0__isr_pq1 = 32'hE000B400;
+parameter val_gem0__isr_pq1 = 32'h00000000;
+parameter mask_gem0__isr_pq1 = 32'h00000000;
+
+parameter gem0__isr_pq2 = 32'hE000B404;
+parameter val_gem0__isr_pq2 = 32'h00000000;
+parameter mask_gem0__isr_pq2 = 32'h00000000;
+
+parameter gem0__isr_pq3 = 32'hE000B408;
+parameter val_gem0__isr_pq3 = 32'h00000000;
+parameter mask_gem0__isr_pq3 = 32'h00000000;
+
+parameter gem0__isr_pq4 = 32'hE000B40C;
+parameter val_gem0__isr_pq4 = 32'h00000000;
+parameter mask_gem0__isr_pq4 = 32'h00000000;
+
+parameter gem0__isr_pq5 = 32'hE000B410;
+parameter val_gem0__isr_pq5 = 32'h00000000;
+parameter mask_gem0__isr_pq5 = 32'h00000000;
+
+parameter gem0__isr_pq6 = 32'hE000B414;
+parameter val_gem0__isr_pq6 = 32'h00000000;
+parameter mask_gem0__isr_pq6 = 32'h00000000;
+
+parameter gem0__isr_pq7 = 32'hE000B418;
+parameter val_gem0__isr_pq7 = 32'h00000000;
+parameter mask_gem0__isr_pq7 = 32'h00000000;
+
+parameter gem0__tx_qbar_q1 = 32'hE000B440;
+parameter val_gem0__tx_qbar_q1 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q1 = 32'h00000000;
+
+parameter gem0__tx_qbar_q2 = 32'hE000B444;
+parameter val_gem0__tx_qbar_q2 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q2 = 32'h00000000;
+
+parameter gem0__tx_qbar_q3 = 32'hE000B448;
+parameter val_gem0__tx_qbar_q3 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q3 = 32'h00000000;
+
+parameter gem0__tx_qbar_q4 = 32'hE000B44C;
+parameter val_gem0__tx_qbar_q4 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q4 = 32'h00000000;
+
+parameter gem0__tx_qbar_q5 = 32'hE000B450;
+parameter val_gem0__tx_qbar_q5 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q5 = 32'h00000000;
+
+parameter gem0__tx_qbar_q6 = 32'hE000B454;
+parameter val_gem0__tx_qbar_q6 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q6 = 32'h00000000;
+
+parameter gem0__tx_qbar_q7 = 32'hE000B458;
+parameter val_gem0__tx_qbar_q7 = 32'h00000000;
+parameter mask_gem0__tx_qbar_q7 = 32'h00000000;
+
+parameter gem0__rx_qbar_q1 = 32'hE000B480;
+parameter val_gem0__rx_qbar_q1 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q1 = 32'h00000000;
+
+parameter gem0__rx_qbar_q2 = 32'hE000B484;
+parameter val_gem0__rx_qbar_q2 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q2 = 32'h00000000;
+
+parameter gem0__rx_qbar_q3 = 32'hE000B488;
+parameter val_gem0__rx_qbar_q3 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q3 = 32'h00000000;
+
+parameter gem0__rx_qbar_q4 = 32'hE000B48C;
+parameter val_gem0__rx_qbar_q4 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q4 = 32'h00000000;
+
+parameter gem0__rx_qbar_q5 = 32'hE000B490;
+parameter val_gem0__rx_qbar_q5 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q5 = 32'h00000000;
+
+parameter gem0__rx_qbar_q6 = 32'hE000B494;
+parameter val_gem0__rx_qbar_q6 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q6 = 32'h00000000;
+
+parameter gem0__rx_qbar_q7 = 32'hE000B498;
+parameter val_gem0__rx_qbar_q7 = 32'h00000000;
+parameter mask_gem0__rx_qbar_q7 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q1 = 32'hE000B4A0;
+parameter val_gem0__rx_bufsz_q1 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q1 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q2 = 32'hE000B4A4;
+parameter val_gem0__rx_bufsz_q2 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q2 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q3 = 32'hE000B4A8;
+parameter val_gem0__rx_bufsz_q3 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q3 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q4 = 32'hE000B4AC;
+parameter val_gem0__rx_bufsz_q4 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q4 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q5 = 32'hE000B4B0;
+parameter val_gem0__rx_bufsz_q5 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q5 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q6 = 32'hE000B4B4;
+parameter val_gem0__rx_bufsz_q6 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q6 = 32'h00000000;
+
+parameter gem0__rx_bufsz_q7 = 32'hE000B4B8;
+parameter val_gem0__rx_bufsz_q7 = 32'h00000000;
+parameter mask_gem0__rx_bufsz_q7 = 32'h00000000;
+
+parameter gem0__screen_t1_r0 = 32'hE000B500;
+parameter val_gem0__screen_t1_r0 = 32'h00000000;
+parameter mask_gem0__screen_t1_r0 = 32'h00000000;
+
+parameter gem0__screen_t1_r1 = 32'hE000B504;
+parameter val_gem0__screen_t1_r1 = 32'h00000000;
+parameter mask_gem0__screen_t1_r1 = 32'h00000000;
+
+parameter gem0__screen_t1_r2 = 32'hE000B508;
+parameter val_gem0__screen_t1_r2 = 32'h00000000;
+parameter mask_gem0__screen_t1_r2 = 32'h00000000;
+
+parameter gem0__screen_t1_r3 = 32'hE000B50C;
+parameter val_gem0__screen_t1_r3 = 32'h00000000;
+parameter mask_gem0__screen_t1_r3 = 32'h00000000;
+
+parameter gem0__screen_t1_r4 = 32'hE000B510;
+parameter val_gem0__screen_t1_r4 = 32'h00000000;
+parameter mask_gem0__screen_t1_r4 = 32'h00000000;
+
+parameter gem0__screen_t1_r5 = 32'hE000B514;
+parameter val_gem0__screen_t1_r5 = 32'h00000000;
+parameter mask_gem0__screen_t1_r5 = 32'h00000000;
+
+parameter gem0__screen_t1_r6 = 32'hE000B518;
+parameter val_gem0__screen_t1_r6 = 32'h00000000;
+parameter mask_gem0__screen_t1_r6 = 32'h00000000;
+
+parameter gem0__screen_t1_r7 = 32'hE000B51C;
+parameter val_gem0__screen_t1_r7 = 32'h00000000;
+parameter mask_gem0__screen_t1_r7 = 32'h00000000;
+
+parameter gem0__screen_t1_r8 = 32'hE000B520;
+parameter val_gem0__screen_t1_r8 = 32'h00000000;
+parameter mask_gem0__screen_t1_r8 = 32'h00000000;
+
+parameter gem0__screen_t1_r9 = 32'hE000B524;
+parameter val_gem0__screen_t1_r9 = 32'h00000000;
+parameter mask_gem0__screen_t1_r9 = 32'h00000000;
+
+parameter gem0__screen_t1_r10 = 32'hE000B528;
+parameter val_gem0__screen_t1_r10 = 32'h00000000;
+parameter mask_gem0__screen_t1_r10 = 32'h00000000;
+
+parameter gem0__screen_t1_r11 = 32'hE000B52C;
+parameter val_gem0__screen_t1_r11 = 32'h00000000;
+parameter mask_gem0__screen_t1_r11 = 32'h00000000;
+
+parameter gem0__screen_t1_r12 = 32'hE000B530;
+parameter val_gem0__screen_t1_r12 = 32'h00000000;
+parameter mask_gem0__screen_t1_r12 = 32'h00000000;
+
+parameter gem0__screen_t1_r13 = 32'hE000B534;
+parameter val_gem0__screen_t1_r13 = 32'h00000000;
+parameter mask_gem0__screen_t1_r13 = 32'h00000000;
+
+parameter gem0__screen_t1_r14 = 32'hE000B538;
+parameter val_gem0__screen_t1_r14 = 32'h00000000;
+parameter mask_gem0__screen_t1_r14 = 32'h00000000;
+
+parameter gem0__screen_t1_r15 = 32'hE000B53C;
+parameter val_gem0__screen_t1_r15 = 32'h00000000;
+parameter mask_gem0__screen_t1_r15 = 32'h00000000;
+
+parameter gem0__screen_t2_r0 = 32'hE000B540;
+parameter val_gem0__screen_t2_r0 = 32'h00000000;
+parameter mask_gem0__screen_t2_r0 = 32'h00000000;
+
+parameter gem0__screen_t2_r1 = 32'hE000B544;
+parameter val_gem0__screen_t2_r1 = 32'h00000000;
+parameter mask_gem0__screen_t2_r1 = 32'h00000000;
+
+parameter gem0__screen_t2_r2 = 32'hE000B548;
+parameter val_gem0__screen_t2_r2 = 32'h00000000;
+parameter mask_gem0__screen_t2_r2 = 32'h00000000;
+
+parameter gem0__screen_t2_r3 = 32'hE000B54C;
+parameter val_gem0__screen_t2_r3 = 32'h00000000;
+parameter mask_gem0__screen_t2_r3 = 32'h00000000;
+
+parameter gem0__screen_t2_r4 = 32'hE000B550;
+parameter val_gem0__screen_t2_r4 = 32'h00000000;
+parameter mask_gem0__screen_t2_r4 = 32'h00000000;
+
+parameter gem0__screen_t2_r5 = 32'hE000B554;
+parameter val_gem0__screen_t2_r5 = 32'h00000000;
+parameter mask_gem0__screen_t2_r5 = 32'h00000000;
+
+parameter gem0__screen_t2_r6 = 32'hE000B558;
+parameter val_gem0__screen_t2_r6 = 32'h00000000;
+parameter mask_gem0__screen_t2_r6 = 32'h00000000;
+
+parameter gem0__screen_t2_r7 = 32'hE000B55C;
+parameter val_gem0__screen_t2_r7 = 32'h00000000;
+parameter mask_gem0__screen_t2_r7 = 32'h00000000;
+
+parameter gem0__screen_t2_r8 = 32'hE000B560;
+parameter val_gem0__screen_t2_r8 = 32'h00000000;
+parameter mask_gem0__screen_t2_r8 = 32'h00000000;
+
+parameter gem0__screen_t2_r9 = 32'hE000B564;
+parameter val_gem0__screen_t2_r9 = 32'h00000000;
+parameter mask_gem0__screen_t2_r9 = 32'h00000000;
+
+parameter gem0__screen_t2_r10 = 32'hE000B568;
+parameter val_gem0__screen_t2_r10 = 32'h00000000;
+parameter mask_gem0__screen_t2_r10 = 32'h00000000;
+
+parameter gem0__screen_t2_r11 = 32'hE000B56C;
+parameter val_gem0__screen_t2_r11 = 32'h00000000;
+parameter mask_gem0__screen_t2_r11 = 32'h00000000;
+
+parameter gem0__screen_t2_r12 = 32'hE000B570;
+parameter val_gem0__screen_t2_r12 = 32'h00000000;
+parameter mask_gem0__screen_t2_r12 = 32'h00000000;
+
+parameter gem0__screen_t2_r13 = 32'hE000B574;
+parameter val_gem0__screen_t2_r13 = 32'h00000000;
+parameter mask_gem0__screen_t2_r13 = 32'h00000000;
+
+parameter gem0__screen_t2_r14 = 32'hE000B578;
+parameter val_gem0__screen_t2_r14 = 32'h00000000;
+parameter mask_gem0__screen_t2_r14 = 32'h00000000;
+
+parameter gem0__screen_t2_r15 = 32'hE000B57C;
+parameter val_gem0__screen_t2_r15 = 32'h00000000;
+parameter mask_gem0__screen_t2_r15 = 32'h00000000;
+
+parameter gem0__intr_en_pq1 = 32'hE000B600;
+parameter val_gem0__intr_en_pq1 = 32'h00000000;
+parameter mask_gem0__intr_en_pq1 = 32'h00000000;
+
+parameter gem0__intr_en_pq2 = 32'hE000B604;
+parameter val_gem0__intr_en_pq2 = 32'h00000000;
+parameter mask_gem0__intr_en_pq2 = 32'h00000000;
+
+parameter gem0__intr_en_pq3 = 32'hE000B608;
+parameter val_gem0__intr_en_pq3 = 32'h00000000;
+parameter mask_gem0__intr_en_pq3 = 32'h00000000;
+
+parameter gem0__intr_en_pq4 = 32'hE000B60C;
+parameter val_gem0__intr_en_pq4 = 32'h00000000;
+parameter mask_gem0__intr_en_pq4 = 32'h00000000;
+
+parameter gem0__intr_en_pq5 = 32'hE000B610;
+parameter val_gem0__intr_en_pq5 = 32'h00000000;
+parameter mask_gem0__intr_en_pq5 = 32'h00000000;
+
+parameter gem0__intr_en_pq6 = 32'hE000B614;
+parameter val_gem0__intr_en_pq6 = 32'h00000000;
+parameter mask_gem0__intr_en_pq6 = 32'h00000000;
+
+parameter gem0__intr_en_pq7 = 32'hE000B618;
+parameter val_gem0__intr_en_pq7 = 32'h00000000;
+parameter mask_gem0__intr_en_pq7 = 32'h00000000;
+
+parameter gem0__intr_dis_pq1 = 32'hE000B620;
+parameter val_gem0__intr_dis_pq1 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq1 = 32'h00000000;
+
+parameter gem0__intr_dis_pq2 = 32'hE000B624;
+parameter val_gem0__intr_dis_pq2 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq2 = 32'h00000000;
+
+parameter gem0__intr_dis_pq3 = 32'hE000B628;
+parameter val_gem0__intr_dis_pq3 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq3 = 32'h00000000;
+
+parameter gem0__intr_dis_pq4 = 32'hE000B62C;
+parameter val_gem0__intr_dis_pq4 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq4 = 32'h00000000;
+
+parameter gem0__intr_dis_pq5 = 32'hE000B630;
+parameter val_gem0__intr_dis_pq5 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq5 = 32'h00000000;
+
+parameter gem0__intr_dis_pq6 = 32'hE000B634;
+parameter val_gem0__intr_dis_pq6 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq6 = 32'h00000000;
+
+parameter gem0__intr_dis_pq7 = 32'hE000B638;
+parameter val_gem0__intr_dis_pq7 = 32'h00000000;
+parameter mask_gem0__intr_dis_pq7 = 32'h00000000;
+
+parameter gem0__intr_mask_pq1 = 32'hE000B640;
+parameter val_gem0__intr_mask_pq1 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq1 = 32'h00000000;
+
+parameter gem0__intr_mask_pq2 = 32'hE000B644;
+parameter val_gem0__intr_mask_pq2 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq2 = 32'h00000000;
+
+parameter gem0__intr_mask_pq3 = 32'hE000B648;
+parameter val_gem0__intr_mask_pq3 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq3 = 32'h00000000;
+
+parameter gem0__intr_mask_pq4 = 32'hE000B64C;
+parameter val_gem0__intr_mask_pq4 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq4 = 32'h00000000;
+
+parameter gem0__intr_mask_pq5 = 32'hE000B650;
+parameter val_gem0__intr_mask_pq5 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq5 = 32'h00000000;
+
+parameter gem0__intr_mask_pq6 = 32'hE000B654;
+parameter val_gem0__intr_mask_pq6 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq6 = 32'h00000000;
+
+parameter gem0__intr_mask_pq7 = 32'hE000B658;
+parameter val_gem0__intr_mask_pq7 = 32'h00000000;
+parameter mask_gem0__intr_mask_pq7 = 32'h00000000;
+
+
+// ************************************************************
+//   Module gem1 GEM
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gem1__net_ctrl = 32'hE000C000;
+parameter val_gem1__net_ctrl = 32'h00000000;
+parameter mask_gem1__net_ctrl = 32'hFFFFFFFF;
+
+parameter gem1__net_cfg = 32'hE000C004;
+parameter val_gem1__net_cfg = 32'h00080000;
+parameter mask_gem1__net_cfg = 32'hFFFFFFFF;
+
+parameter gem1__net_status = 32'hE000C008;
+parameter val_gem1__net_status = 32'h00000004;
+parameter mask_gem1__net_status = 32'hFFFFFFFD;
+
+parameter gem1__user_io = 32'hE000C00C;
+parameter val_gem1__user_io = 32'h00000000;
+parameter mask_gem1__user_io = 32'h0000FFFF;
+
+parameter gem1__dma_cfg = 32'hE000C010;
+parameter val_gem1__dma_cfg = 32'h00020784;
+parameter mask_gem1__dma_cfg = 32'hFFFFFFFF;
+
+parameter gem1__tx_status = 32'hE000C014;
+parameter val_gem1__tx_status = 32'h00000000;
+parameter mask_gem1__tx_status = 32'hFFFFFFFF;
+
+parameter gem1__rx_qbar = 32'hE000C018;
+parameter val_gem1__rx_qbar = 32'h00000000;
+parameter mask_gem1__rx_qbar = 32'hFFFFFFFF;
+
+parameter gem1__tx_qbar = 32'hE000C01C;
+parameter val_gem1__tx_qbar = 32'h00000000;
+parameter mask_gem1__tx_qbar = 32'hFFFFFFFF;
+
+parameter gem1__rx_status = 32'hE000C020;
+parameter val_gem1__rx_status = 32'h00000000;
+parameter mask_gem1__rx_status = 32'hFFFFFFFF;
+
+parameter gem1__intr_status = 32'hE000C024;
+parameter val_gem1__intr_status = 32'h00000000;
+parameter mask_gem1__intr_status = 32'hFFFFFFFF;
+
+parameter gem1__intr_en = 32'hE000C028;
+parameter val_gem1__intr_en = 32'h00000000;
+parameter mask_gem1__intr_en = 32'h00000000;
+
+parameter gem1__intr_dis = 32'hE000C02C;
+parameter val_gem1__intr_dis = 32'h00000000;
+parameter mask_gem1__intr_dis = 32'h00000000;
+
+parameter gem1__intr_mask = 32'hE000C030;
+parameter val_gem1__intr_mask = 32'h0001FFFF;
+parameter mask_gem1__intr_mask = 32'hFC01FFFF;
+
+parameter gem1__phy_maint = 32'hE000C034;
+parameter val_gem1__phy_maint = 32'h00000000;
+parameter mask_gem1__phy_maint = 32'hFFFFFFFF;
+
+parameter gem1__rx_pauseq = 32'hE000C038;
+parameter val_gem1__rx_pauseq = 32'h00000000;
+parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF;
+
+parameter gem1__tx_pauseq = 32'hE000C03C;
+parameter val_gem1__tx_pauseq = 32'h0000FFFF;
+parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF;
+
+parameter gem1__tx_partial_st_fwd = 32'hE000C040;
+parameter val_gem1__tx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem1__rx_partial_st_fwd = 32'hE000C044;
+parameter val_gem1__rx_partial_st_fwd = 32'h000003FF;
+parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF;
+
+parameter gem1__hash_bot = 32'hE000C080;
+parameter val_gem1__hash_bot = 32'h00000000;
+parameter mask_gem1__hash_bot = 32'hFFFFFFFF;
+
+parameter gem1__hash_top = 32'hE000C084;
+parameter val_gem1__hash_top = 32'h00000000;
+parameter mask_gem1__hash_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_bot = 32'hE000C088;
+parameter val_gem1__spec_addr1_bot = 32'h00000000;
+parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_top = 32'hE000C08C;
+parameter val_gem1__spec_addr1_top = 32'h00000000;
+parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr2_bot = 32'hE000C090;
+parameter val_gem1__spec_addr2_bot = 32'h00000000;
+parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr2_top = 32'hE000C094;
+parameter val_gem1__spec_addr2_top = 32'h00000000;
+parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr3_bot = 32'hE000C098;
+parameter val_gem1__spec_addr3_bot = 32'h00000000;
+parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr3_top = 32'hE000C09C;
+parameter val_gem1__spec_addr3_top = 32'h00000000;
+parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr4_bot = 32'hE000C0A0;
+parameter val_gem1__spec_addr4_bot = 32'h00000000;
+parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr4_top = 32'hE000C0A4;
+parameter val_gem1__spec_addr4_top = 32'h00000000;
+parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match1 = 32'hE000C0A8;
+parameter val_gem1__type_id_match1 = 32'h00000000;
+parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match2 = 32'hE000C0AC;
+parameter val_gem1__type_id_match2 = 32'h00000000;
+parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match3 = 32'hE000C0B0;
+parameter val_gem1__type_id_match3 = 32'h00000000;
+parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF;
+
+parameter gem1__type_id_match4 = 32'hE000C0B4;
+parameter val_gem1__type_id_match4 = 32'h00000000;
+parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF;
+
+parameter gem1__wake_on_lan = 32'hE000C0B8;
+parameter val_gem1__wake_on_lan = 32'h00000000;
+parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF;
+
+parameter gem1__ipg_stretch = 32'hE000C0BC;
+parameter val_gem1__ipg_stretch = 32'h00000000;
+parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF;
+
+parameter gem1__stacked_vlan = 32'hE000C0C0;
+parameter val_gem1__stacked_vlan = 32'h00000000;
+parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF;
+
+parameter gem1__tx_pfc_pause = 32'hE000C0C4;
+parameter val_gem1__tx_pfc_pause = 32'h00000000;
+parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8;
+parameter val_gem1__spec_addr1_mask_bot = 32'h00000000;
+parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF;
+
+parameter gem1__spec_addr1_mask_top = 32'hE000C0CC;
+parameter val_gem1__spec_addr1_mask_top = 32'h00000000;
+parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF;
+
+parameter gem1__module_id = 32'hE000C0FC;
+parameter val_gem1__module_id = 32'h00020118;
+parameter mask_gem1__module_id = 32'hFFFFFFFF;
+
+parameter gem1__octets_tx_bot = 32'hE000C100;
+parameter val_gem1__octets_tx_bot = 32'h00000000;
+parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF;
+
+parameter gem1__octets_tx_top = 32'hE000C104;
+parameter val_gem1__octets_tx_top = 32'h00000000;
+parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF;
+
+parameter gem1__frames_tx = 32'hE000C108;
+parameter val_gem1__frames_tx = 32'h00000000;
+parameter mask_gem1__frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__broadcast_frames_tx = 32'hE000C10C;
+parameter val_gem1__broadcast_frames_tx = 32'h00000000;
+parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__multi_frames_tx = 32'hE000C110;
+parameter val_gem1__multi_frames_tx = 32'h00000000;
+parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__pause_frames_tx = 32'hE000C114;
+parameter val_gem1__pause_frames_tx = 32'h00000000;
+parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_64b_tx = 32'hE000C118;
+parameter val_gem1__frames_64b_tx = 32'h00000000;
+parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_65to127b_tx = 32'hE000C11C;
+parameter val_gem1__frames_65to127b_tx = 32'h00000000;
+parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_128to255b_tx = 32'hE000C120;
+parameter val_gem1__frames_128to255b_tx = 32'h00000000;
+parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_256to511b_tx = 32'hE000C124;
+parameter val_gem1__frames_256to511b_tx = 32'h00000000;
+parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_512to1023b_tx = 32'hE000C128;
+parameter val_gem1__frames_512to1023b_tx = 32'h00000000;
+parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_1024to1518b_tx = 32'hE000C12C;
+parameter val_gem1__frames_1024to1518b_tx = 32'h00000000;
+parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF;
+
+parameter gem1__frames_gt1518b_tx = 32'hE000C130;
+parameter val_gem1__frames_gt1518b_tx = 32'h00000000;
+parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF;
+
+parameter gem1__tx_under_runs = 32'hE000C134;
+parameter val_gem1__tx_under_runs = 32'h00000000;
+parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF;
+
+parameter gem1__single_collisn_frames = 32'hE000C138;
+parameter val_gem1__single_collisn_frames = 32'h00000000;
+parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem1__multi_collisn_frames = 32'hE000C13C;
+parameter val_gem1__multi_collisn_frames = 32'h00000000;
+parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF;
+
+parameter gem1__excessive_collisns = 32'hE000C140;
+parameter val_gem1__excessive_collisns = 32'h00000000;
+parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF;
+
+parameter gem1__late_collisns = 32'hE000C144;
+parameter val_gem1__late_collisns = 32'h00000000;
+parameter mask_gem1__late_collisns = 32'hFFFFFFFF;
+
+parameter gem1__deferred_tx_frames = 32'hE000C148;
+parameter val_gem1__deferred_tx_frames = 32'h00000000;
+parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF;
+
+parameter gem1__carrier_sense_errs = 32'hE000C14C;
+parameter val_gem1__carrier_sense_errs = 32'h00000000;
+parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF;
+
+parameter gem1__octets_rx_bot = 32'hE000C150;
+parameter val_gem1__octets_rx_bot = 32'h00000000;
+parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF;
+
+parameter gem1__octets_rx_top = 32'hE000C154;
+parameter val_gem1__octets_rx_top = 32'h00000000;
+parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF;
+
+parameter gem1__frames_rx = 32'hE000C158;
+parameter val_gem1__frames_rx = 32'h00000000;
+parameter mask_gem1__frames_rx = 32'hFFFFFFFF;
+
+parameter gem1__bdcast_fames_rx = 32'hE000C15C;
+parameter val_gem1__bdcast_fames_rx = 32'h00000000;
+parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF;
+
+parameter gem1__multi_frames_rx = 32'hE000C160;
+parameter val_gem1__multi_frames_rx = 32'h00000000;
+parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF;
+
+parameter gem1__pause_rx = 32'hE000C164;
+parameter val_gem1__pause_rx = 32'h00000000;
+parameter mask_gem1__pause_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_64b_rx = 32'hE000C168;
+parameter val_gem1__frames_64b_rx = 32'h00000000;
+parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_65to127b_rx = 32'hE000C16C;
+parameter val_gem1__frames_65to127b_rx = 32'h00000000;
+parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_128to255b_rx = 32'hE000C170;
+parameter val_gem1__frames_128to255b_rx = 32'h00000000;
+parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_256to511b_rx = 32'hE000C174;
+parameter val_gem1__frames_256to511b_rx = 32'h00000000;
+parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_512to1023b_rx = 32'hE000C178;
+parameter val_gem1__frames_512to1023b_rx = 32'h00000000;
+parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_1024to1518b_rx = 32'hE000C17C;
+parameter val_gem1__frames_1024to1518b_rx = 32'h00000000;
+parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF;
+
+parameter gem1__frames_gt1518b_rx = 32'hE000C180;
+parameter val_gem1__frames_gt1518b_rx = 32'h00000000;
+parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF;
+
+parameter gem1__undersz_rx = 32'hE000C184;
+parameter val_gem1__undersz_rx = 32'h00000000;
+parameter mask_gem1__undersz_rx = 32'hFFFFFFFF;
+
+parameter gem1__oversz_rx = 32'hE000C188;
+parameter val_gem1__oversz_rx = 32'h00000000;
+parameter mask_gem1__oversz_rx = 32'hFFFFFFFF;
+
+parameter gem1__jab_rx = 32'hE000C18C;
+parameter val_gem1__jab_rx = 32'h00000000;
+parameter mask_gem1__jab_rx = 32'hFFFFFFFF;
+
+parameter gem1__fcs_errors = 32'hE000C190;
+parameter val_gem1__fcs_errors = 32'h00000000;
+parameter mask_gem1__fcs_errors = 32'hFFFFFFFF;
+
+parameter gem1__length_field_errors = 32'hE000C194;
+parameter val_gem1__length_field_errors = 32'h00000000;
+parameter mask_gem1__length_field_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_symbol_errors = 32'hE000C198;
+parameter val_gem1__rx_symbol_errors = 32'h00000000;
+parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF;
+
+parameter gem1__align_errors = 32'hE000C19C;
+parameter val_gem1__align_errors = 32'h00000000;
+parameter mask_gem1__align_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_resource_errors = 32'hE000C1A0;
+parameter val_gem1__rx_resource_errors = 32'h00000000;
+parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF;
+
+parameter gem1__rx_overrun_errors = 32'hE000C1A4;
+parameter val_gem1__rx_overrun_errors = 32'h00000000;
+parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF;
+
+parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8;
+parameter val_gem1__ip_hdr_csum_errors = 32'h00000000;
+parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__tcp_csum_errors = 32'hE000C1AC;
+parameter val_gem1__tcp_csum_errors = 32'h00000000;
+parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__udp_csum_errors = 32'hE000C1B0;
+parameter val_gem1__udp_csum_errors = 32'h00000000;
+parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF;
+
+parameter gem1__timer_strobe_s = 32'hE000C1C8;
+parameter val_gem1__timer_strobe_s = 32'h00000000;
+parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF;
+
+parameter gem1__timer_strobe_ns = 32'hE000C1CC;
+parameter val_gem1__timer_strobe_ns = 32'h00000000;
+parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF;
+
+parameter gem1__timer_s = 32'hE000C1D0;
+parameter val_gem1__timer_s = 32'h00000000;
+parameter mask_gem1__timer_s = 32'hFFFFFFFF;
+
+parameter gem1__timer_ns = 32'hE000C1D4;
+parameter val_gem1__timer_ns = 32'h00000000;
+parameter mask_gem1__timer_ns = 32'hFFFFFFFF;
+
+parameter gem1__timer_adjust = 32'hE000C1D8;
+parameter val_gem1__timer_adjust = 32'h00000000;
+parameter mask_gem1__timer_adjust = 32'hFFFFFFFF;
+
+parameter gem1__timer_incr = 32'hE000C1DC;
+parameter val_gem1__timer_incr = 32'h00000000;
+parameter mask_gem1__timer_incr = 32'hFFFFFFFF;
+
+parameter gem1__ptp_tx_s = 32'hE000C1E0;
+parameter val_gem1__ptp_tx_s = 32'h00000000;
+parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_tx_ns = 32'hE000C1E4;
+parameter val_gem1__ptp_tx_ns = 32'h00000000;
+parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_rx_s = 32'hE000C1E8;
+parameter val_gem1__ptp_rx_s = 32'h00000000;
+parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_rx_ns = 32'hE000C1EC;
+parameter val_gem1__ptp_rx_ns = 32'h00000000;
+parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_tx_s = 32'hE000C1F0;
+parameter val_gem1__ptp_peer_tx_s = 32'h00000000;
+parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4;
+parameter val_gem1__ptp_peer_tx_ns = 32'h00000000;
+parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_rx_s = 32'hE000C1F8;
+parameter val_gem1__ptp_peer_rx_s = 32'h00000000;
+parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF;
+
+parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC;
+parameter val_gem1__ptp_peer_rx_ns = 32'h00000000;
+parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF;
+
+parameter gem1__pcs_ctrl = 32'hE000C200;
+parameter val_gem1__pcs_ctrl = 32'h00000000;
+parameter mask_gem1__pcs_ctrl = 32'h00000000;
+
+parameter gem1__pcs_status = 32'hE000C204;
+parameter val_gem1__pcs_status = 32'h00000000;
+parameter mask_gem1__pcs_status = 32'h00000000;
+
+parameter gem1__pcs_upper_phy_id = 32'hE000C208;
+parameter val_gem1__pcs_upper_phy_id = 32'h00000000;
+parameter mask_gem1__pcs_upper_phy_id = 32'h00000000;
+
+parameter gem1__pcs_lower_phy_id = 32'hE000C20C;
+parameter val_gem1__pcs_lower_phy_id = 32'h00000000;
+parameter mask_gem1__pcs_lower_phy_id = 32'h00000000;
+
+parameter gem1__pcs_autoneg_ad = 32'hE000C210;
+parameter val_gem1__pcs_autoneg_ad = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_ad = 32'h00000000;
+
+parameter gem1__pcs_autoneg_ability = 32'hE000C214;
+parameter val_gem1__pcs_autoneg_ability = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_ability = 32'h00000000;
+
+parameter gem1__pcs_autonec_exp = 32'hE000C218;
+parameter val_gem1__pcs_autonec_exp = 32'h00000000;
+parameter mask_gem1__pcs_autonec_exp = 32'h00000000;
+
+parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C;
+parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000;
+
+parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220;
+parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
+parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
+
+parameter gem1__pcs_extended_status = 32'hE000C23C;
+parameter val_gem1__pcs_extended_status = 32'h00000000;
+parameter mask_gem1__pcs_extended_status = 32'h00000000;
+
+parameter gem1__design_cfg1 = 32'hE000C280;
+parameter val_gem1__design_cfg1 = 32'h02000000;
+parameter mask_gem1__design_cfg1 = 32'h0E000000;
+
+parameter gem1__design_cfg2 = 32'hE000C284;
+parameter val_gem1__design_cfg2 = 32'h2A813FFF;
+parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF;
+
+parameter gem1__design_cfg3 = 32'hE000C288;
+parameter val_gem1__design_cfg3 = 32'h00000000;
+parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF;
+
+parameter gem1__design_cfg4 = 32'hE000C28C;
+parameter val_gem1__design_cfg4 = 32'h00000000;
+parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF;
+
+parameter gem1__design_cfg5 = 32'hE000C290;
+parameter val_gem1__design_cfg5 = 32'h002F2045;
+parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF;
+
+parameter gem1__design_cfg6 = 32'hE000C294;
+parameter val_gem1__design_cfg6 = 32'h00000000;
+parameter mask_gem1__design_cfg6 = 32'h00000000;
+
+parameter gem1__design_cfg7 = 32'hE000C298;
+parameter val_gem1__design_cfg7 = 32'h00000000;
+parameter mask_gem1__design_cfg7 = 32'h00000000;
+
+parameter gem1__isr_pq1 = 32'hE000C400;
+parameter val_gem1__isr_pq1 = 32'h00000000;
+parameter mask_gem1__isr_pq1 = 32'h00000000;
+
+parameter gem1__isr_pq2 = 32'hE000C404;
+parameter val_gem1__isr_pq2 = 32'h00000000;
+parameter mask_gem1__isr_pq2 = 32'h00000000;
+
+parameter gem1__isr_pq3 = 32'hE000C408;
+parameter val_gem1__isr_pq3 = 32'h00000000;
+parameter mask_gem1__isr_pq3 = 32'h00000000;
+
+parameter gem1__isr_pq4 = 32'hE000C40C;
+parameter val_gem1__isr_pq4 = 32'h00000000;
+parameter mask_gem1__isr_pq4 = 32'h00000000;
+
+parameter gem1__isr_pq5 = 32'hE000C410;
+parameter val_gem1__isr_pq5 = 32'h00000000;
+parameter mask_gem1__isr_pq5 = 32'h00000000;
+
+parameter gem1__isr_pq6 = 32'hE000C414;
+parameter val_gem1__isr_pq6 = 32'h00000000;
+parameter mask_gem1__isr_pq6 = 32'h00000000;
+
+parameter gem1__isr_pq7 = 32'hE000C418;
+parameter val_gem1__isr_pq7 = 32'h00000000;
+parameter mask_gem1__isr_pq7 = 32'h00000000;
+
+parameter gem1__tx_qbar_q1 = 32'hE000C440;
+parameter val_gem1__tx_qbar_q1 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q1 = 32'h00000000;
+
+parameter gem1__tx_qbar_q2 = 32'hE000C444;
+parameter val_gem1__tx_qbar_q2 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q2 = 32'h00000000;
+
+parameter gem1__tx_qbar_q3 = 32'hE000C448;
+parameter val_gem1__tx_qbar_q3 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q3 = 32'h00000000;
+
+parameter gem1__tx_qbar_q4 = 32'hE000C44C;
+parameter val_gem1__tx_qbar_q4 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q4 = 32'h00000000;
+
+parameter gem1__tx_qbar_q5 = 32'hE000C450;
+parameter val_gem1__tx_qbar_q5 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q5 = 32'h00000000;
+
+parameter gem1__tx_qbar_q6 = 32'hE000C454;
+parameter val_gem1__tx_qbar_q6 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q6 = 32'h00000000;
+
+parameter gem1__tx_qbar_q7 = 32'hE000C458;
+parameter val_gem1__tx_qbar_q7 = 32'h00000000;
+parameter mask_gem1__tx_qbar_q7 = 32'h00000000;
+
+parameter gem1__rx_qbar_q1 = 32'hE000C480;
+parameter val_gem1__rx_qbar_q1 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q1 = 32'h00000000;
+
+parameter gem1__rx_qbar_q2 = 32'hE000C484;
+parameter val_gem1__rx_qbar_q2 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q2 = 32'h00000000;
+
+parameter gem1__rx_qbar_q3 = 32'hE000C488;
+parameter val_gem1__rx_qbar_q3 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q3 = 32'h00000000;
+
+parameter gem1__rx_qbar_q4 = 32'hE000C48C;
+parameter val_gem1__rx_qbar_q4 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q4 = 32'h00000000;
+
+parameter gem1__rx_qbar_q5 = 32'hE000C490;
+parameter val_gem1__rx_qbar_q5 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q5 = 32'h00000000;
+
+parameter gem1__rx_qbar_q6 = 32'hE000C494;
+parameter val_gem1__rx_qbar_q6 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q6 = 32'h00000000;
+
+parameter gem1__rx_qbar_q7 = 32'hE000C498;
+parameter val_gem1__rx_qbar_q7 = 32'h00000000;
+parameter mask_gem1__rx_qbar_q7 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q1 = 32'hE000C4A0;
+parameter val_gem1__rx_bufsz_q1 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q1 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q2 = 32'hE000C4A4;
+parameter val_gem1__rx_bufsz_q2 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q2 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q3 = 32'hE000C4A8;
+parameter val_gem1__rx_bufsz_q3 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q3 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q4 = 32'hE000C4AC;
+parameter val_gem1__rx_bufsz_q4 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q4 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q5 = 32'hE000C4B0;
+parameter val_gem1__rx_bufsz_q5 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q5 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q6 = 32'hE000C4B4;
+parameter val_gem1__rx_bufsz_q6 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q6 = 32'h00000000;
+
+parameter gem1__rx_bufsz_q7 = 32'hE000C4B8;
+parameter val_gem1__rx_bufsz_q7 = 32'h00000000;
+parameter mask_gem1__rx_bufsz_q7 = 32'h00000000;
+
+parameter gem1__screen_t1_r0 = 32'hE000C500;
+parameter val_gem1__screen_t1_r0 = 32'h00000000;
+parameter mask_gem1__screen_t1_r0 = 32'h00000000;
+
+parameter gem1__screen_t1_r1 = 32'hE000C504;
+parameter val_gem1__screen_t1_r1 = 32'h00000000;
+parameter mask_gem1__screen_t1_r1 = 32'h00000000;
+
+parameter gem1__screen_t1_r2 = 32'hE000C508;
+parameter val_gem1__screen_t1_r2 = 32'h00000000;
+parameter mask_gem1__screen_t1_r2 = 32'h00000000;
+
+parameter gem1__screen_t1_r3 = 32'hE000C50C;
+parameter val_gem1__screen_t1_r3 = 32'h00000000;
+parameter mask_gem1__screen_t1_r3 = 32'h00000000;
+
+parameter gem1__screen_t1_r4 = 32'hE000C510;
+parameter val_gem1__screen_t1_r4 = 32'h00000000;
+parameter mask_gem1__screen_t1_r4 = 32'h00000000;
+
+parameter gem1__screen_t1_r5 = 32'hE000C514;
+parameter val_gem1__screen_t1_r5 = 32'h00000000;
+parameter mask_gem1__screen_t1_r5 = 32'h00000000;
+
+parameter gem1__screen_t1_r6 = 32'hE000C518;
+parameter val_gem1__screen_t1_r6 = 32'h00000000;
+parameter mask_gem1__screen_t1_r6 = 32'h00000000;
+
+parameter gem1__screen_t1_r7 = 32'hE000C51C;
+parameter val_gem1__screen_t1_r7 = 32'h00000000;
+parameter mask_gem1__screen_t1_r7 = 32'h00000000;
+
+parameter gem1__screen_t1_r8 = 32'hE000C520;
+parameter val_gem1__screen_t1_r8 = 32'h00000000;
+parameter mask_gem1__screen_t1_r8 = 32'h00000000;
+
+parameter gem1__screen_t1_r9 = 32'hE000C524;
+parameter val_gem1__screen_t1_r9 = 32'h00000000;
+parameter mask_gem1__screen_t1_r9 = 32'h00000000;
+
+parameter gem1__screen_t1_r10 = 32'hE000C528;
+parameter val_gem1__screen_t1_r10 = 32'h00000000;
+parameter mask_gem1__screen_t1_r10 = 32'h00000000;
+
+parameter gem1__screen_t1_r11 = 32'hE000C52C;
+parameter val_gem1__screen_t1_r11 = 32'h00000000;
+parameter mask_gem1__screen_t1_r11 = 32'h00000000;
+
+parameter gem1__screen_t1_r12 = 32'hE000C530;
+parameter val_gem1__screen_t1_r12 = 32'h00000000;
+parameter mask_gem1__screen_t1_r12 = 32'h00000000;
+
+parameter gem1__screen_t1_r13 = 32'hE000C534;
+parameter val_gem1__screen_t1_r13 = 32'h00000000;
+parameter mask_gem1__screen_t1_r13 = 32'h00000000;
+
+parameter gem1__screen_t1_r14 = 32'hE000C538;
+parameter val_gem1__screen_t1_r14 = 32'h00000000;
+parameter mask_gem1__screen_t1_r14 = 32'h00000000;
+
+parameter gem1__screen_t1_r15 = 32'hE000C53C;
+parameter val_gem1__screen_t1_r15 = 32'h00000000;
+parameter mask_gem1__screen_t1_r15 = 32'h00000000;
+
+parameter gem1__screen_t2_r0 = 32'hE000C540;
+parameter val_gem1__screen_t2_r0 = 32'h00000000;
+parameter mask_gem1__screen_t2_r0 = 32'h00000000;
+
+parameter gem1__screen_t2_r1 = 32'hE000C544;
+parameter val_gem1__screen_t2_r1 = 32'h00000000;
+parameter mask_gem1__screen_t2_r1 = 32'h00000000;
+
+parameter gem1__screen_t2_r2 = 32'hE000C548;
+parameter val_gem1__screen_t2_r2 = 32'h00000000;
+parameter mask_gem1__screen_t2_r2 = 32'h00000000;
+
+parameter gem1__screen_t2_r3 = 32'hE000C54C;
+parameter val_gem1__screen_t2_r3 = 32'h00000000;
+parameter mask_gem1__screen_t2_r3 = 32'h00000000;
+
+parameter gem1__screen_t2_r4 = 32'hE000C550;
+parameter val_gem1__screen_t2_r4 = 32'h00000000;
+parameter mask_gem1__screen_t2_r4 = 32'h00000000;
+
+parameter gem1__screen_t2_r5 = 32'hE000C554;
+parameter val_gem1__screen_t2_r5 = 32'h00000000;
+parameter mask_gem1__screen_t2_r5 = 32'h00000000;
+
+parameter gem1__screen_t2_r6 = 32'hE000C558;
+parameter val_gem1__screen_t2_r6 = 32'h00000000;
+parameter mask_gem1__screen_t2_r6 = 32'h00000000;
+
+parameter gem1__screen_t2_r7 = 32'hE000C55C;
+parameter val_gem1__screen_t2_r7 = 32'h00000000;
+parameter mask_gem1__screen_t2_r7 = 32'h00000000;
+
+parameter gem1__screen_t2_r8 = 32'hE000C560;
+parameter val_gem1__screen_t2_r8 = 32'h00000000;
+parameter mask_gem1__screen_t2_r8 = 32'h00000000;
+
+parameter gem1__screen_t2_r9 = 32'hE000C564;
+parameter val_gem1__screen_t2_r9 = 32'h00000000;
+parameter mask_gem1__screen_t2_r9 = 32'h00000000;
+
+parameter gem1__screen_t2_r10 = 32'hE000C568;
+parameter val_gem1__screen_t2_r10 = 32'h00000000;
+parameter mask_gem1__screen_t2_r10 = 32'h00000000;
+
+parameter gem1__screen_t2_r11 = 32'hE000C56C;
+parameter val_gem1__screen_t2_r11 = 32'h00000000;
+parameter mask_gem1__screen_t2_r11 = 32'h00000000;
+
+parameter gem1__screen_t2_r12 = 32'hE000C570;
+parameter val_gem1__screen_t2_r12 = 32'h00000000;
+parameter mask_gem1__screen_t2_r12 = 32'h00000000;
+
+parameter gem1__screen_t2_r13 = 32'hE000C574;
+parameter val_gem1__screen_t2_r13 = 32'h00000000;
+parameter mask_gem1__screen_t2_r13 = 32'h00000000;
+
+parameter gem1__screen_t2_r14 = 32'hE000C578;
+parameter val_gem1__screen_t2_r14 = 32'h00000000;
+parameter mask_gem1__screen_t2_r14 = 32'h00000000;
+
+parameter gem1__screen_t2_r15 = 32'hE000C57C;
+parameter val_gem1__screen_t2_r15 = 32'h00000000;
+parameter mask_gem1__screen_t2_r15 = 32'h00000000;
+
+parameter gem1__intr_en_pq1 = 32'hE000C600;
+parameter val_gem1__intr_en_pq1 = 32'h00000000;
+parameter mask_gem1__intr_en_pq1 = 32'h00000000;
+
+parameter gem1__intr_en_pq2 = 32'hE000C604;
+parameter val_gem1__intr_en_pq2 = 32'h00000000;
+parameter mask_gem1__intr_en_pq2 = 32'h00000000;
+
+parameter gem1__intr_en_pq3 = 32'hE000C608;
+parameter val_gem1__intr_en_pq3 = 32'h00000000;
+parameter mask_gem1__intr_en_pq3 = 32'h00000000;
+
+parameter gem1__intr_en_pq4 = 32'hE000C60C;
+parameter val_gem1__intr_en_pq4 = 32'h00000000;
+parameter mask_gem1__intr_en_pq4 = 32'h00000000;
+
+parameter gem1__intr_en_pq5 = 32'hE000C610;
+parameter val_gem1__intr_en_pq5 = 32'h00000000;
+parameter mask_gem1__intr_en_pq5 = 32'h00000000;
+
+parameter gem1__intr_en_pq6 = 32'hE000C614;
+parameter val_gem1__intr_en_pq6 = 32'h00000000;
+parameter mask_gem1__intr_en_pq6 = 32'h00000000;
+
+parameter gem1__intr_en_pq7 = 32'hE000C618;
+parameter val_gem1__intr_en_pq7 = 32'h00000000;
+parameter mask_gem1__intr_en_pq7 = 32'h00000000;
+
+parameter gem1__intr_dis_pq1 = 32'hE000C620;
+parameter val_gem1__intr_dis_pq1 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq1 = 32'h00000000;
+
+parameter gem1__intr_dis_pq2 = 32'hE000C624;
+parameter val_gem1__intr_dis_pq2 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq2 = 32'h00000000;
+
+parameter gem1__intr_dis_pq3 = 32'hE000C628;
+parameter val_gem1__intr_dis_pq3 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq3 = 32'h00000000;
+
+parameter gem1__intr_dis_pq4 = 32'hE000C62C;
+parameter val_gem1__intr_dis_pq4 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq4 = 32'h00000000;
+
+parameter gem1__intr_dis_pq5 = 32'hE000C630;
+parameter val_gem1__intr_dis_pq5 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq5 = 32'h00000000;
+
+parameter gem1__intr_dis_pq6 = 32'hE000C634;
+parameter val_gem1__intr_dis_pq6 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq6 = 32'h00000000;
+
+parameter gem1__intr_dis_pq7 = 32'hE000C638;
+parameter val_gem1__intr_dis_pq7 = 32'h00000000;
+parameter mask_gem1__intr_dis_pq7 = 32'h00000000;
+
+parameter gem1__intr_mask_pq1 = 32'hE000C640;
+parameter val_gem1__intr_mask_pq1 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq1 = 32'h00000000;
+
+parameter gem1__intr_mask_pq2 = 32'hE000C644;
+parameter val_gem1__intr_mask_pq2 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq2 = 32'h00000000;
+
+parameter gem1__intr_mask_pq3 = 32'hE000C648;
+parameter val_gem1__intr_mask_pq3 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq3 = 32'h00000000;
+
+parameter gem1__intr_mask_pq4 = 32'hE000C64C;
+parameter val_gem1__intr_mask_pq4 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq4 = 32'h00000000;
+
+parameter gem1__intr_mask_pq5 = 32'hE000C650;
+parameter val_gem1__intr_mask_pq5 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq5 = 32'h00000000;
+
+parameter gem1__intr_mask_pq6 = 32'hE000C654;
+parameter val_gem1__intr_mask_pq6 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq6 = 32'h00000000;
+
+parameter gem1__intr_mask_pq7 = 32'hE000C658;
+parameter val_gem1__intr_mask_pq7 = 32'h00000000;
+parameter mask_gem1__intr_mask_pq7 = 32'h00000000;
+
+
+// ************************************************************
+//   Module gpio gpio
+//   doc version: 
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpio__MASK_DATA_0_LSW = 32'hE000A000;
+parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_0_MSW = 32'hE000A004;
+parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_1_LSW = 32'hE000A008;
+parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000;
+
+parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C;
+parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0;
+
+parameter gpio__MASK_DATA_2_LSW = 32'hE000A010;
+parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_2_MSW = 32'hE000A014;
+parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_3_LSW = 32'hE000A018;
+parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF;
+
+parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C;
+parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000;
+parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF;
+
+parameter gpio__DATA_0 = 32'hE000A040;
+parameter val_gpio__DATA_0 = 32'h00000000;
+parameter mask_gpio__DATA_0 = 32'h00000000;
+
+parameter gpio__DATA_1 = 32'hE000A044;
+parameter val_gpio__DATA_1 = 32'h00000000;
+parameter mask_gpio__DATA_1 = 32'h00000000;
+
+parameter gpio__DATA_2 = 32'hE000A048;
+parameter val_gpio__DATA_2 = 32'h00000000;
+parameter mask_gpio__DATA_2 = 32'hFFFFFFFF;
+
+parameter gpio__DATA_3 = 32'hE000A04C;
+parameter val_gpio__DATA_3 = 32'h00000000;
+parameter mask_gpio__DATA_3 = 32'hFFFFFFFF;
+
+parameter gpio__DATA_0_RO = 32'hE000A060;
+parameter val_gpio__DATA_0_RO = 32'h00000000;
+parameter mask_gpio__DATA_0_RO = 32'h00000000;
+
+parameter gpio__DATA_1_RO = 32'hE000A064;
+parameter val_gpio__DATA_1_RO = 32'h00000000;
+parameter mask_gpio__DATA_1_RO = 32'h00000000;
+
+parameter gpio__DATA_2_RO = 32'hE000A068;
+parameter val_gpio__DATA_2_RO = 32'h00000000;
+parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF;
+
+parameter gpio__DATA_3_RO = 32'hE000A06C;
+parameter val_gpio__DATA_3_RO = 32'h00000000;
+parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_0 = 32'hE000A200;
+parameter val_gpio__BYPM_0 = 32'h00000000;
+parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_0 = 32'hE000A204;
+parameter val_gpio__DIRM_0 = 32'h00000000;
+parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_0 = 32'hE000A208;
+parameter val_gpio__OEN_0 = 32'h00000000;
+parameter mask_gpio__OEN_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_0 = 32'hE000A20C;
+parameter val_gpio__INT_MASK_0 = 32'h00000000;
+parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_0 = 32'hE000A210;
+parameter val_gpio__INT_EN_0 = 32'h00000000;
+parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_0 = 32'hE000A214;
+parameter val_gpio__INT_DIS_0 = 32'h00000000;
+parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_0 = 32'hE000A218;
+parameter val_gpio__INT_STAT_0 = 32'h00000000;
+parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_0 = 32'hE000A21C;
+parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_0 = 32'hE000A220;
+parameter val_gpio__INT_POLARITY_0 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_0 = 32'hE000A224;
+parameter val_gpio__INT_ANY_0 = 32'h00000000;
+parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_1 = 32'hE000A240;
+parameter val_gpio__BYPM_1 = 32'h00000000;
+parameter mask_gpio__BYPM_1 = 32'h003FFFFF;
+
+parameter gpio__DIRM_1 = 32'hE000A244;
+parameter val_gpio__DIRM_1 = 32'h00000000;
+parameter mask_gpio__DIRM_1 = 32'h003FFFFF;
+
+parameter gpio__OEN_1 = 32'hE000A248;
+parameter val_gpio__OEN_1 = 32'h00000000;
+parameter mask_gpio__OEN_1 = 32'h003FFFFF;
+
+parameter gpio__INT_MASK_1 = 32'hE000A24C;
+parameter val_gpio__INT_MASK_1 = 32'h00000000;
+parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF;
+
+parameter gpio__INT_EN_1 = 32'hE000A250;
+parameter val_gpio__INT_EN_1 = 32'h00000000;
+parameter mask_gpio__INT_EN_1 = 32'h003FFFFF;
+
+parameter gpio__INT_DIS_1 = 32'hE000A254;
+parameter val_gpio__INT_DIS_1 = 32'h00000000;
+parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF;
+
+parameter gpio__INT_STAT_1 = 32'hE000A258;
+parameter val_gpio__INT_STAT_1 = 32'h00000000;
+parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF;
+
+parameter gpio__INT_TYPE_1 = 32'hE000A25C;
+parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF;
+parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF;
+
+parameter gpio__INT_POLARITY_1 = 32'hE000A260;
+parameter val_gpio__INT_POLARITY_1 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF;
+
+parameter gpio__INT_ANY_1 = 32'hE000A264;
+parameter val_gpio__INT_ANY_1 = 32'h00000000;
+parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF;
+
+parameter gpio__BYPM_2 = 32'hE000A280;
+parameter val_gpio__BYPM_2 = 32'h00000000;
+parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_2 = 32'hE000A284;
+parameter val_gpio__DIRM_2 = 32'h00000000;
+parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_2 = 32'hE000A288;
+parameter val_gpio__OEN_2 = 32'h00000000;
+parameter mask_gpio__OEN_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_2 = 32'hE000A28C;
+parameter val_gpio__INT_MASK_2 = 32'h00000000;
+parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_2 = 32'hE000A290;
+parameter val_gpio__INT_EN_2 = 32'h00000000;
+parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_2 = 32'hE000A294;
+parameter val_gpio__INT_DIS_2 = 32'h00000000;
+parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_2 = 32'hE000A298;
+parameter val_gpio__INT_STAT_2 = 32'h00000000;
+parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_2 = 32'hE000A29C;
+parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_2 = 32'hE000A2A0;
+parameter val_gpio__INT_POLARITY_2 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_2 = 32'hE000A2A4;
+parameter val_gpio__INT_ANY_2 = 32'h00000000;
+parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF;
+
+parameter gpio__BYPM_3 = 32'hE000A2C0;
+parameter val_gpio__BYPM_3 = 32'h00000000;
+parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF;
+
+parameter gpio__DIRM_3 = 32'hE000A2C4;
+parameter val_gpio__DIRM_3 = 32'h00000000;
+parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF;
+
+parameter gpio__OEN_3 = 32'hE000A2C8;
+parameter val_gpio__OEN_3 = 32'h00000000;
+parameter mask_gpio__OEN_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_MASK_3 = 32'hE000A2CC;
+parameter val_gpio__INT_MASK_3 = 32'h00000000;
+parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_EN_3 = 32'hE000A2D0;
+parameter val_gpio__INT_EN_3 = 32'h00000000;
+parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_DIS_3 = 32'hE000A2D4;
+parameter val_gpio__INT_DIS_3 = 32'h00000000;
+parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_STAT_3 = 32'hE000A2D8;
+parameter val_gpio__INT_STAT_3 = 32'h00000000;
+parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_TYPE_3 = 32'hE000A2DC;
+parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
+parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_POLARITY_3 = 32'hE000A2E0;
+parameter val_gpio__INT_POLARITY_3 = 32'h00000000;
+parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF;
+
+parameter gpio__INT_ANY_3 = 32'hE000A2E4;
+parameter val_gpio__INT_ANY_3 = 32'h00000000;
+parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module gpv_iou_switch gpv_iou_switch
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_iou_switch__Remap = 32'hE0200000;
+parameter val_gpv_iou_switch__Remap = 32'h00000000;
+parameter mask_gpv_iou_switch__Remap = 32'h000000FF;
+
+parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008;
+parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001;
+
+parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C;
+parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001;
+
+parameter gpv_iou_switch__security4_qspi = 32'hE0200010;
+parameter val_gpv_iou_switch__security4_qspi = 32'h00000000;
+parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001;
+
+parameter gpv_iou_switch__security5_miou = 32'hE0200014;
+parameter val_gpv_iou_switch__security5_miou = 32'h00000000;
+parameter mask_gpv_iou_switch__security5_miou = 32'h00000001;
+
+parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018;
+parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000;
+parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF;
+
+parameter gpv_iou_switch__security7_smc = 32'hE020001C;
+parameter val_gpv_iou_switch__security7_smc = 32'h00000000;
+parameter mask_gpv_iou_switch__security7_smc = 32'h00000001;
+
+parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0;
+parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004;
+parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4;
+parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8;
+parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC;
+parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0;
+parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001;
+parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4;
+parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3;
+parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8;
+parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B;
+parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF;
+
+parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC;
+parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000;
+parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id0 = 32'hE0201FF0;
+parameter val_gpv_iou_switch__component_id0 = 32'h0000000D;
+parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id1 = 32'hE0201FF4;
+parameter val_gpv_iou_switch__component_id1 = 32'h000000F0;
+parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id2 = 32'hE0201FF8;
+parameter val_gpv_iou_switch__component_id2 = 32'h00000005;
+parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF;
+
+parameter gpv_iou_switch__component_id3 = 32'hE0201FFC;
+parameter val_gpv_iou_switch__component_id3 = 32'h000000B1;
+parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003;
+
+parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044;
+parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003;
+
+parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044;
+parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008;
+parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028;
+parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100;
+parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104;
+parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108;
+parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028;
+parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100;
+parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104;
+parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108;
+parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028;
+parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100;
+parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104;
+parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108;
+parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028;
+parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100;
+parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104;
+parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108;
+parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028;
+parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100;
+parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104;
+parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108;
+parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028;
+parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007;
+
+parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100;
+parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F;
+
+parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104;
+parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F;
+
+parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108;
+parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003;
+
+parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108;
+parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000;
+parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003;
+
+
+// ************************************************************
+//   Module gpv_qos301_cpu qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C;
+parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_cpu__max_ot = 32'hF8946110;
+parameter val_gpv_qos301_cpu__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114;
+parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_cpu__aw_p = 32'hF8946118;
+parameter val_gpv_qos301_cpu__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_cpu__aw_b = 32'hF894611C;
+parameter val_gpv_qos301_cpu__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_cpu__aw_r = 32'hF8946120;
+parameter val_gpv_qos301_cpu__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_cpu__ar_p = 32'hF8946124;
+parameter val_gpv_qos301_cpu__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_cpu__ar_b = 32'hF8946128;
+parameter val_gpv_qos301_cpu__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_cpu__ar_r = 32'hF894612C;
+parameter val_gpv_qos301_cpu__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_qos301_dmac qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C;
+parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_dmac__max_ot = 32'hF8947110;
+parameter val_gpv_qos301_dmac__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114;
+parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_dmac__aw_p = 32'hF8947118;
+parameter val_gpv_qos301_dmac__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_dmac__aw_b = 32'hF894711C;
+parameter val_gpv_qos301_dmac__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_dmac__aw_r = 32'hF8947120;
+parameter val_gpv_qos301_dmac__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_dmac__ar_p = 32'hF8947124;
+parameter val_gpv_qos301_dmac__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_dmac__ar_b = 32'hF8947128;
+parameter val_gpv_qos301_dmac__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_dmac__ar_r = 32'hF894712C;
+parameter val_gpv_qos301_dmac__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_qos301_iou qos301
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_qos301_iou__qos_cntl = 32'hF894810C;
+parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000;
+parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF;
+
+parameter gpv_qos301_iou__max_ot = 32'hF8948110;
+parameter val_gpv_qos301_iou__max_ot = 32'h00000000;
+parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF;
+
+parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114;
+parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000;
+parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF;
+
+parameter gpv_qos301_iou__aw_p = 32'hF8948118;
+parameter val_gpv_qos301_iou__aw_p = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000;
+
+parameter gpv_qos301_iou__aw_b = 32'hF894811C;
+parameter val_gpv_qos301_iou__aw_b = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF;
+
+parameter gpv_qos301_iou__aw_r = 32'hF8948120;
+parameter val_gpv_qos301_iou__aw_r = 32'h00000000;
+parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000;
+
+parameter gpv_qos301_iou__ar_p = 32'hF8948124;
+parameter val_gpv_qos301_iou__ar_p = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000;
+
+parameter gpv_qos301_iou__ar_b = 32'hF8948128;
+parameter val_gpv_qos301_iou__ar_b = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF;
+
+parameter gpv_qos301_iou__ar_r = 32'hF894812C;
+parameter val_gpv_qos301_iou__ar_r = 32'h00000000;
+parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000;
+
+
+// ************************************************************
+//   Module gpv_trustzone nic301_addr_region_ctrl_registers
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter gpv_trustzone__Remap = 32'hF8900000;
+parameter val_gpv_trustzone__Remap = 32'h00000000;
+parameter mask_gpv_trustzone__Remap = 32'h000000C0;
+
+parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C;
+parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000;
+parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001;
+
+parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020;
+parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000;
+parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001;
+
+parameter gpv_trustzone__security_apb = 32'hF8900028;
+parameter val_gpv_trustzone__security_apb = 32'h00000000;
+parameter mask_gpv_trustzone__security_apb = 32'h0000003F;
+
+
+// ************************************************************
+//   Module i2c0 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter i2c0__Control_reg0 = 32'hE0004000;
+parameter val_i2c0__Control_reg0 = 32'h00000000;
+parameter mask_i2c0__Control_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Status_reg0 = 32'hE0004004;
+parameter val_i2c0__Status_reg0 = 32'h00000000;
+parameter mask_i2c0__Status_reg0 = 32'h0000FFFF;
+
+parameter i2c0__I2C_address_reg0 = 32'hE0004008;
+parameter val_i2c0__I2C_address_reg0 = 32'h00000000;
+parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF;
+
+parameter i2c0__I2C_data_reg0 = 32'hE000400C;
+parameter val_i2c0__I2C_data_reg0 = 32'h00000000;
+parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Interrupt_status_reg0 = 32'hE0004010;
+parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000;
+parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Transfer_size_reg0 = 32'hE0004014;
+parameter val_i2c0__Transfer_size_reg0 = 32'h00000000;
+parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF;
+
+parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018;
+parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000;
+parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF;
+
+parameter i2c0__Time_out_reg0 = 32'hE000401C;
+parameter val_i2c0__Time_out_reg0 = 32'h0000001F;
+parameter mask_i2c0__Time_out_reg0 = 32'h000000FF;
+
+parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020;
+parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF;
+parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024;
+parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000;
+parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF;
+
+parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028;
+parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000;
+parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module i2c1 IIC
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter i2c1__Control_reg0 = 32'hE0005000;
+parameter val_i2c1__Control_reg0 = 32'h00000000;
+parameter mask_i2c1__Control_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Status_reg0 = 32'hE0005004;
+parameter val_i2c1__Status_reg0 = 32'h00000000;
+parameter mask_i2c1__Status_reg0 = 32'h0000FFFF;
+
+parameter i2c1__I2C_address_reg0 = 32'hE0005008;
+parameter val_i2c1__I2C_address_reg0 = 32'h00000000;
+parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF;
+
+parameter i2c1__I2C_data_reg0 = 32'hE000500C;
+parameter val_i2c1__I2C_data_reg0 = 32'h00000000;
+parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Interrupt_status_reg0 = 32'hE0005010;
+parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000;
+parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Transfer_size_reg0 = 32'hE0005014;
+parameter val_i2c1__Transfer_size_reg0 = 32'h00000000;
+parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF;
+
+parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018;
+parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000;
+parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF;
+
+parameter i2c1__Time_out_reg0 = 32'hE000501C;
+parameter val_i2c1__Time_out_reg0 = 32'h0000001F;
+parameter mask_i2c1__Time_out_reg0 = 32'h000000FF;
+
+parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020;
+parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF;
+parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024;
+parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000;
+parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF;
+
+parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028;
+parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000;
+parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module l2cache L2Cpl310
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter l2cache__reg0_cache_id = 32'hF8F02000;
+parameter val_l2cache__reg0_cache_id = 32'h410000C8;
+parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF;
+
+parameter l2cache__reg0_cache_type = 32'hF8F02004;
+parameter val_l2cache__reg0_cache_type = 32'h9E300300;
+parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_control = 32'hF8F02100;
+parameter val_l2cache__reg1_control = 32'h00000000;
+parameter mask_l2cache__reg1_control = 32'h7FFFFFFF;
+
+parameter l2cache__reg1_aux_control = 32'hF8F02104;
+parameter val_l2cache__reg1_aux_control = 32'h02050000;
+parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_tag_ram_control = 32'hF8F02108;
+parameter val_l2cache__reg1_tag_ram_control = 32'h00000777;
+parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg1_data_ram_control = 32'hF8F0210C;
+parameter val_l2cache__reg1_data_ram_control = 32'h00000777;
+parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200;
+parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204;
+parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208;
+parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C;
+parameter val_l2cache__reg2_ev_counter1 = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_ev_counter0 = 32'hF8F02210;
+parameter val_l2cache__reg2_ev_counter0 = 32'h00000000;
+parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_mask = 32'hF8F02214;
+parameter val_l2cache__reg2_int_mask = 32'h00000000;
+parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_mask_status = 32'hF8F02218;
+parameter val_l2cache__reg2_int_mask_status = 32'h00000000;
+parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_raw_status = 32'hF8F0221C;
+parameter val_l2cache__reg2_int_raw_status = 32'h00000000;
+parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF;
+
+parameter l2cache__reg2_int_clear = 32'hF8F02220;
+parameter val_l2cache__reg2_int_clear = 32'h00000000;
+parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_cache_sync = 32'hF8F02730;
+parameter val_l2cache__reg7_cache_sync = 32'h00000000;
+parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_inv_pa = 32'hF8F02770;
+parameter val_l2cache__reg7_inv_pa = 32'h00000000;
+parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_inv_way = 32'hF8F0277C;
+parameter val_l2cache__reg7_inv_way = 32'h00000000;
+parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_pa = 32'hF8F027B0;
+parameter val_l2cache__reg7_clean_pa = 32'h00000000;
+parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_index = 32'hF8F027B8;
+parameter val_l2cache__reg7_clean_index = 32'h00000000;
+parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_way = 32'hF8F027BC;
+parameter val_l2cache__reg7_clean_way = 32'h00000000;
+parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0;
+parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8;
+parameter val_l2cache__reg7_clean_inv_index = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF;
+
+parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC;
+parameter val_l2cache__reg7_clean_inv_way = 32'h00000000;
+parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900;
+parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904;
+parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908;
+parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C;
+parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910;
+parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914;
+parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918;
+parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C;
+parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920;
+parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924;
+parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928;
+parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C;
+parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930;
+parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934;
+parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938;
+parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000;
+parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C;
+parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000;
+parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_lock_line_en = 32'hF8F02950;
+parameter val_l2cache__reg9_lock_line_en = 32'h00000000;
+parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF;
+
+parameter l2cache__reg9_unlock_way = 32'hF8F02954;
+parameter val_l2cache__reg9_unlock_way = 32'h00000000;
+parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF;
+
+parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00;
+parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001;
+parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF;
+
+parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04;
+parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000;
+parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40;
+parameter val_l2cache__reg15_debug_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60;
+parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF;
+
+parameter l2cache__reg15_power_ctrl = 32'hF8F02F80;
+parameter val_l2cache__reg15_power_ctrl = 32'h00000000;
+parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module mpcore mpcore
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000;
+parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002;
+parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004;
+parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501;
+parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008;
+parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000;
+parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C;
+parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000;
+parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF;
+
+parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040;
+parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000;
+parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044;
+parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000;
+parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050;
+parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F;
+parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF;
+
+parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054;
+parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000;
+parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__ICCICR = 32'hF8F00100;
+parameter val_mpcore__ICCICR = 32'h00000000;
+parameter mask_mpcore__ICCICR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCPMR = 32'hF8F00104;
+parameter val_mpcore__ICCPMR = 32'h00000000;
+parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCBPR = 32'hF8F00108;
+parameter val_mpcore__ICCBPR = 32'h00000002;
+parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIAR = 32'hF8F0010C;
+parameter val_mpcore__ICCIAR = 32'h000003FF;
+parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCEOIR = 32'hF8F00110;
+parameter val_mpcore__ICCEOIR = 32'h00000000;
+parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCRPR = 32'hF8F00114;
+parameter val_mpcore__ICCRPR = 32'h000000FF;
+parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCHPIR = 32'hF8F00118;
+parameter val_mpcore__ICCHPIR = 32'h000003FF;
+parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCABPR = 32'hF8F0011C;
+parameter val_mpcore__ICCABPR = 32'h00000003;
+parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR = 32'hF8F001FC;
+parameter val_mpcore__ICCIDR = 32'h3901243B;
+parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200;
+parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204;
+parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208;
+parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C;
+parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210;
+parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000;
+parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF;
+
+parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214;
+parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000;
+parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF;
+
+parameter mpcore__Auto_increment_Register = 32'hF8F00218;
+parameter val_mpcore__Auto_increment_Register = 32'h00000000;
+parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600;
+parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604;
+parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608;
+parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C;
+parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Load_Register = 32'hF8F00620;
+parameter val_mpcore__Watchdog_Load_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624;
+parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Control_Register = 32'hF8F00628;
+parameter val_mpcore__Watchdog_Control_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C;
+parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630;
+parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF;
+
+parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634;
+parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000;
+parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF;
+
+parameter mpcore__ICDDCR = 32'hF8F01000;
+parameter val_mpcore__ICDDCR = 32'h00000000;
+parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICTR = 32'hF8F01004;
+parameter val_mpcore__ICDICTR = 32'h00000C22;
+parameter mask_mpcore__ICDICTR = 32'hE000FFFF;
+
+parameter mpcore__ICDIIDR = 32'hF8F01008;
+parameter val_mpcore__ICDIIDR = 32'h0102043B;
+parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR0 = 32'hF8F01080;
+parameter val_mpcore__ICDISR0 = 32'h00000000;
+parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR1 = 32'hF8F01084;
+parameter val_mpcore__ICDISR1 = 32'h00000000;
+parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISR2 = 32'hF8F01088;
+parameter val_mpcore__ICDISR2 = 32'h00000000;
+parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER0 = 32'hF8F01100;
+parameter val_mpcore__ICDISER0 = 32'h0000FFFF;
+parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER1 = 32'hF8F01104;
+parameter val_mpcore__ICDISER1 = 32'h00000000;
+parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISER2 = 32'hF8F01108;
+parameter val_mpcore__ICDISER2 = 32'h00000000;
+parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER0 = 32'hF8F01180;
+parameter val_mpcore__ICDICER0 = 32'h0000FFFF;
+parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER1 = 32'hF8F01184;
+parameter val_mpcore__ICDICER1 = 32'h00000000;
+parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICER2 = 32'hF8F01188;
+parameter val_mpcore__ICDICER2 = 32'h00000000;
+parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR0 = 32'hF8F01200;
+parameter val_mpcore__ICDISPR0 = 32'h00000000;
+parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR1 = 32'hF8F01204;
+parameter val_mpcore__ICDISPR1 = 32'h00000000;
+parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDISPR2 = 32'hF8F01208;
+parameter val_mpcore__ICDISPR2 = 32'h00000000;
+parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR0 = 32'hF8F01280;
+parameter val_mpcore__ICDICPR0 = 32'h00000000;
+parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR1 = 32'hF8F01284;
+parameter val_mpcore__ICDICPR1 = 32'h00000000;
+parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICPR2 = 32'hF8F01288;
+parameter val_mpcore__ICDICPR2 = 32'h00000000;
+parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR0 = 32'hF8F01300;
+parameter val_mpcore__ICDABR0 = 32'h00000000;
+parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR1 = 32'hF8F01304;
+parameter val_mpcore__ICDABR1 = 32'h00000000;
+parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDABR2 = 32'hF8F01308;
+parameter val_mpcore__ICDABR2 = 32'h00000000;
+parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR0 = 32'hF8F01400;
+parameter val_mpcore__ICDIPR0 = 32'h00000000;
+parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR1 = 32'hF8F01404;
+parameter val_mpcore__ICDIPR1 = 32'h00000000;
+parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR2 = 32'hF8F01408;
+parameter val_mpcore__ICDIPR2 = 32'h00000000;
+parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR3 = 32'hF8F0140C;
+parameter val_mpcore__ICDIPR3 = 32'h00000000;
+parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR4 = 32'hF8F01410;
+parameter val_mpcore__ICDIPR4 = 32'h00000000;
+parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR5 = 32'hF8F01414;
+parameter val_mpcore__ICDIPR5 = 32'h00000000;
+parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR6 = 32'hF8F01418;
+parameter val_mpcore__ICDIPR6 = 32'h00000000;
+parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR7 = 32'hF8F0141C;
+parameter val_mpcore__ICDIPR7 = 32'h00000000;
+parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR8 = 32'hF8F01420;
+parameter val_mpcore__ICDIPR8 = 32'h00000000;
+parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR9 = 32'hF8F01424;
+parameter val_mpcore__ICDIPR9 = 32'h00000000;
+parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR10 = 32'hF8F01428;
+parameter val_mpcore__ICDIPR10 = 32'h00000000;
+parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR11 = 32'hF8F0142C;
+parameter val_mpcore__ICDIPR11 = 32'h00000000;
+parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR12 = 32'hF8F01430;
+parameter val_mpcore__ICDIPR12 = 32'h00000000;
+parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR13 = 32'hF8F01434;
+parameter val_mpcore__ICDIPR13 = 32'h00000000;
+parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR14 = 32'hF8F01438;
+parameter val_mpcore__ICDIPR14 = 32'h00000000;
+parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR15 = 32'hF8F0143C;
+parameter val_mpcore__ICDIPR15 = 32'h00000000;
+parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR16 = 32'hF8F01440;
+parameter val_mpcore__ICDIPR16 = 32'h00000000;
+parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR17 = 32'hF8F01444;
+parameter val_mpcore__ICDIPR17 = 32'h00000000;
+parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR18 = 32'hF8F01448;
+parameter val_mpcore__ICDIPR18 = 32'h00000000;
+parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR19 = 32'hF8F0144C;
+parameter val_mpcore__ICDIPR19 = 32'h00000000;
+parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR20 = 32'hF8F01450;
+parameter val_mpcore__ICDIPR20 = 32'h00000000;
+parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR21 = 32'hF8F01454;
+parameter val_mpcore__ICDIPR21 = 32'h00000000;
+parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR22 = 32'hF8F01458;
+parameter val_mpcore__ICDIPR22 = 32'h00000000;
+parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPR23 = 32'hF8F0145C;
+parameter val_mpcore__ICDIPR23 = 32'h00000000;
+parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR0 = 32'hF8F01800;
+parameter val_mpcore__ICDIPTR0 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR1 = 32'hF8F01804;
+parameter val_mpcore__ICDIPTR1 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR2 = 32'hF8F01808;
+parameter val_mpcore__ICDIPTR2 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR3 = 32'hF8F0180C;
+parameter val_mpcore__ICDIPTR3 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR4 = 32'hF8F01810;
+parameter val_mpcore__ICDIPTR4 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR5 = 32'hF8F01814;
+parameter val_mpcore__ICDIPTR5 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR6 = 32'hF8F01818;
+parameter val_mpcore__ICDIPTR6 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR7 = 32'hF8F0181C;
+parameter val_mpcore__ICDIPTR7 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR8 = 32'hF8F01820;
+parameter val_mpcore__ICDIPTR8 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR9 = 32'hF8F01824;
+parameter val_mpcore__ICDIPTR9 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR10 = 32'hF8F01828;
+parameter val_mpcore__ICDIPTR10 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR11 = 32'hF8F0182C;
+parameter val_mpcore__ICDIPTR11 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR12 = 32'hF8F01830;
+parameter val_mpcore__ICDIPTR12 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR13 = 32'hF8F01834;
+parameter val_mpcore__ICDIPTR13 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR14 = 32'hF8F01838;
+parameter val_mpcore__ICDIPTR14 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR15 = 32'hF8F0183C;
+parameter val_mpcore__ICDIPTR15 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR16 = 32'hF8F01840;
+parameter val_mpcore__ICDIPTR16 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR17 = 32'hF8F01844;
+parameter val_mpcore__ICDIPTR17 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR18 = 32'hF8F01848;
+parameter val_mpcore__ICDIPTR18 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR19 = 32'hF8F0184C;
+parameter val_mpcore__ICDIPTR19 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR20 = 32'hF8F01850;
+parameter val_mpcore__ICDIPTR20 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR21 = 32'hF8F01854;
+parameter val_mpcore__ICDIPTR21 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR22 = 32'hF8F01858;
+parameter val_mpcore__ICDIPTR22 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDIPTR23 = 32'hF8F0185C;
+parameter val_mpcore__ICDIPTR23 = 32'h01010101;
+parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR0 = 32'hF8F01C00;
+parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA;
+parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR1 = 32'hF8F01C04;
+parameter val_mpcore__ICDICFR1 = 32'h7DC00000;
+parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR2 = 32'hF8F01C08;
+parameter val_mpcore__ICDICFR2 = 32'h55555555;
+parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR3 = 32'hF8F01C0C;
+parameter val_mpcore__ICDICFR3 = 32'h55555555;
+parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR4 = 32'hF8F01C10;
+parameter val_mpcore__ICDICFR4 = 32'h55555555;
+parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDICFR5 = 32'hF8F01C14;
+parameter val_mpcore__ICDICFR5 = 32'h55555555;
+parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ppi_status = 32'hF8F01D00;
+parameter val_mpcore__ppi_status = 32'h00000000;
+parameter mask_mpcore__ppi_status = 32'hFFFFFFFF;
+
+parameter mpcore__spi_status_0 = 32'hF8F01D04;
+parameter val_mpcore__spi_status_0 = 32'h00000000;
+parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF;
+
+parameter mpcore__spi_status_1 = 32'hF8F01D08;
+parameter val_mpcore__spi_status_1 = 32'h00000000;
+parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICDSGIR = 32'hF8F01F00;
+parameter val_mpcore__ICDSGIR = 32'h00000000;
+parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR4 = 32'hF8F01FD0;
+parameter val_mpcore__ICPIDR4 = 32'h00000004;
+parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR5 = 32'hF8F01FD4;
+parameter val_mpcore__ICPIDR5 = 32'h00000000;
+parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR6 = 32'hF8F01FD8;
+parameter val_mpcore__ICPIDR6 = 32'h00000000;
+parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR7 = 32'hF8F01FDC;
+parameter val_mpcore__ICPIDR7 = 32'h00000000;
+parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR0 = 32'hF8F01FE0;
+parameter val_mpcore__ICPIDR0 = 32'h00000090;
+parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR1 = 32'hF8F01FE4;
+parameter val_mpcore__ICPIDR1 = 32'h000000B3;
+parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR2 = 32'hF8F01FE8;
+parameter val_mpcore__ICPIDR2 = 32'h0000001B;
+parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICPIDR3 = 32'hF8F01FEC;
+parameter val_mpcore__ICPIDR3 = 32'h00000000;
+parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR0 = 32'hF8F01FF0;
+parameter val_mpcore__ICCIDR0 = 32'h0000000D;
+parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR1 = 32'hF8F01FF4;
+parameter val_mpcore__ICCIDR1 = 32'h000000F0;
+parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR2 = 32'hF8F01FF8;
+parameter val_mpcore__ICCIDR2 = 32'h00000005;
+parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF;
+
+parameter mpcore__ICCIDR3 = 32'hF8F01FFC;
+parameter val_mpcore__ICCIDR3 = 32'h000000B1;
+parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module ocm ocm
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ocm__OCM_PARITY_CTRL = 32'hF800C000;
+parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000;
+parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF;
+
+parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004;
+parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000;
+parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF;
+
+parameter ocm__OCM_IRQ_STS = 32'hF800C008;
+parameter val_ocm__OCM_IRQ_STS = 32'h00000000;
+parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF;
+
+parameter ocm__OCM_CONTROL = 32'hF800C00C;
+parameter val_ocm__OCM_CONTROL = 32'h00000000;
+parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module qspi qspi
+//   doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
+//   Design Specification document
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter qspi__Config_reg = 32'hE000D000;
+parameter val_qspi__Config_reg = 32'h80000000;
+parameter mask_qspi__Config_reg = 32'hFFFDFFFF;
+
+parameter qspi__Intr_status_REG = 32'hE000D004;
+parameter val_qspi__Intr_status_REG = 32'h00000004;
+parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_en_REG = 32'hE000D008;
+parameter val_qspi__Intrpt_en_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_dis_REG = 32'hE000D00C;
+parameter val_qspi__Intrpt_dis_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF;
+
+parameter qspi__Intrpt_mask_REG = 32'hE000D010;
+parameter val_qspi__Intrpt_mask_REG = 32'h00000000;
+parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF;
+
+parameter qspi__En_REG = 32'hE000D014;
+parameter val_qspi__En_REG = 32'h00000000;
+parameter mask_qspi__En_REG = 32'hFFFFFFFF;
+
+parameter qspi__Delay_REG = 32'hE000D018;
+parameter val_qspi__Delay_REG = 32'h00000000;
+parameter mask_qspi__Delay_REG = 32'hFFFFFFFF;
+
+parameter qspi__TXD0 = 32'hE000D01C;
+parameter val_qspi__TXD0 = 32'h00000000;
+parameter mask_qspi__TXD0 = 32'hFFFFFFFF;
+
+parameter qspi__Rx_data_REG = 32'hE000D020;
+parameter val_qspi__Rx_data_REG = 32'h00000000;
+parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF;
+
+parameter qspi__Slave_Idle_count_REG = 32'hE000D024;
+parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF;
+parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF;
+
+parameter qspi__TX_thres_REG = 32'hE000D028;
+parameter val_qspi__TX_thres_REG = 32'h00000001;
+parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF;
+
+parameter qspi__RX_thres_REG = 32'hE000D02C;
+parameter val_qspi__RX_thres_REG = 32'h00000001;
+parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF;
+
+parameter qspi__GPIO = 32'hE000D030;
+parameter val_qspi__GPIO = 32'h00000001;
+parameter mask_qspi__GPIO = 32'hFFFFFFFF;
+
+parameter qspi__LPBK_DLY_ADJ = 32'hE000D038;
+parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033;
+parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF;
+
+parameter qspi__TXD1 = 32'hE000D080;
+parameter val_qspi__TXD1 = 32'h00000000;
+parameter mask_qspi__TXD1 = 32'hFFFFFFFF;
+
+parameter qspi__TXD2 = 32'hE000D084;
+parameter val_qspi__TXD2 = 32'h00000000;
+parameter mask_qspi__TXD2 = 32'hFFFFFFFF;
+
+parameter qspi__TXD3 = 32'hE000D088;
+parameter val_qspi__TXD3 = 32'h00000000;
+parameter mask_qspi__TXD3 = 32'hFFFFFFFF;
+
+parameter qspi__LQSPI_CFG = 32'hE000D0A0;
+parameter val_qspi__LQSPI_CFG = 32'h03A002EB;
+parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF;
+
+parameter qspi__LQSPI_STS = 32'hE000D0A4;
+parameter val_qspi__LQSPI_STS = 32'h00000000;
+parameter mask_qspi__LQSPI_STS = 32'h000001FF;
+
+parameter qspi__MOD_ID = 32'hE000D0FC;
+parameter val_qspi__MOD_ID = 32'h01090101;
+parameter mask_qspi__MOD_ID = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module sd0 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter sd0__SDMA_system_address_register = 32'hE0100000;
+parameter val_sd0__SDMA_system_address_register = 32'h00000000;
+parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF;
+
+parameter sd0__Block_Size_Block_Count = 32'hE0100004;
+parameter val_sd0__Block_Size_Block_Count = 32'h00000000;
+parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF;
+
+parameter sd0__Argument = 32'hE0100008;
+parameter val_sd0__Argument = 32'h00000000;
+parameter mask_sd0__Argument = 32'hFFFFFFFF;
+
+parameter sd0__Transfer_Mode_Command = 32'hE010000C;
+parameter val_sd0__Transfer_Mode_Command = 32'h00000000;
+parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF;
+
+parameter sd0__Response0 = 32'hE0100010;
+parameter val_sd0__Response0 = 32'h00000000;
+parameter mask_sd0__Response0 = 32'hFFFFFFFF;
+
+parameter sd0__Response1 = 32'hE0100014;
+parameter val_sd0__Response1 = 32'h00000000;
+parameter mask_sd0__Response1 = 32'hFFFFFFFF;
+
+parameter sd0__Response2 = 32'hE0100018;
+parameter val_sd0__Response2 = 32'h00000000;
+parameter mask_sd0__Response2 = 32'hFFFFFFFF;
+
+parameter sd0__Response3 = 32'hE010001C;
+parameter val_sd0__Response3 = 32'h00000000;
+parameter mask_sd0__Response3 = 32'hFFFFFFFF;
+
+parameter sd0__Buffer_Data_Port = 32'hE0100020;
+parameter val_sd0__Buffer_Data_Port = 32'h00000000;
+parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF;
+
+parameter sd0__Present_State = 32'hE0100024;
+parameter val_sd0__Present_State = 32'h01F20000;
+parameter mask_sd0__Present_State = 32'h01FFFFFF;
+
+parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028;
+parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
+parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
+
+parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C;
+parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
+parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
+
+parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030;
+parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
+
+parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034;
+parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
+
+parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038;
+parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
+parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
+
+parameter sd0__Auto_CMD12_error_status = 32'hE010003C;
+parameter val_sd0__Auto_CMD12_error_status = 32'h00000000;
+parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF;
+
+parameter sd0__Capabilities = 32'hE0100040;
+parameter val_sd0__Capabilities = 32'h69EC0080;
+parameter mask_sd0__Capabilities = 32'h7FFFFFFF;
+
+parameter sd0__Maximum_current_capabilities = 32'hE0100048;
+parameter val_sd0__Maximum_current_capabilities = 32'h00000001;
+parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF;
+
+parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050;
+parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
+parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
+
+parameter sd0__ADMA_error_status = 32'hE0100054;
+parameter val_sd0__ADMA_error_status = 32'h00000000;
+parameter mask_sd0__ADMA_error_status = 32'h00000007;
+
+parameter sd0__ADMA_system_address = 32'hE0100058;
+parameter val_sd0__ADMA_system_address = 32'h00000000;
+parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF;
+
+parameter sd0__Boot_Timeout_control = 32'hE0100060;
+parameter val_sd0__Boot_Timeout_control = 32'h00000000;
+parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF;
+
+parameter sd0__Debug_Selection = 32'hE0100064;
+parameter val_sd0__Debug_Selection = 32'h00000000;
+parameter mask_sd0__Debug_Selection = 32'h00000001;
+
+parameter sd0__SPI_interrupt_support = 32'hE01000F0;
+parameter val_sd0__SPI_interrupt_support = 32'h00000000;
+parameter mask_sd0__SPI_interrupt_support = 32'h000000FF;
+
+parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC;
+parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000;
+parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module sd1 sdio
+//   doc version: 4.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter sd1__SDMA_system_address_register = 32'hE0101000;
+parameter val_sd1__SDMA_system_address_register = 32'h00000000;
+parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF;
+
+parameter sd1__Block_Size_Block_Count = 32'hE0101004;
+parameter val_sd1__Block_Size_Block_Count = 32'h00000000;
+parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF;
+
+parameter sd1__Argument = 32'hE0101008;
+parameter val_sd1__Argument = 32'h00000000;
+parameter mask_sd1__Argument = 32'hFFFFFFFF;
+
+parameter sd1__Transfer_Mode_Command = 32'hE010100C;
+parameter val_sd1__Transfer_Mode_Command = 32'h00000000;
+parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF;
+
+parameter sd1__Response0 = 32'hE0101010;
+parameter val_sd1__Response0 = 32'h00000000;
+parameter mask_sd1__Response0 = 32'hFFFFFFFF;
+
+parameter sd1__Response1 = 32'hE0101014;
+parameter val_sd1__Response1 = 32'h00000000;
+parameter mask_sd1__Response1 = 32'hFFFFFFFF;
+
+parameter sd1__Response2 = 32'hE0101018;
+parameter val_sd1__Response2 = 32'h00000000;
+parameter mask_sd1__Response2 = 32'hFFFFFFFF;
+
+parameter sd1__Response3 = 32'hE010101C;
+parameter val_sd1__Response3 = 32'h00000000;
+parameter mask_sd1__Response3 = 32'hFFFFFFFF;
+
+parameter sd1__Buffer_Data_Port = 32'hE0101020;
+parameter val_sd1__Buffer_Data_Port = 32'h00000000;
+parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF;
+
+parameter sd1__Present_State = 32'hE0101024;
+parameter val_sd1__Present_State = 32'h01F20000;
+parameter mask_sd1__Present_State = 32'h01FFFFFF;
+
+parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028;
+parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
+parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
+
+parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C;
+parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
+parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
+
+parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030;
+parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
+
+parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034;
+parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
+
+parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038;
+parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
+parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
+
+parameter sd1__Auto_CMD12_error_status = 32'hE010103C;
+parameter val_sd1__Auto_CMD12_error_status = 32'h00000000;
+parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF;
+
+parameter sd1__Capabilities = 32'hE0101040;
+parameter val_sd1__Capabilities = 32'h69EC0080;
+parameter mask_sd1__Capabilities = 32'h7FFFFFFF;
+
+parameter sd1__Maximum_current_capabilities = 32'hE0101048;
+parameter val_sd1__Maximum_current_capabilities = 32'h00000001;
+parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF;
+
+parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050;
+parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
+parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
+
+parameter sd1__ADMA_error_status = 32'hE0101054;
+parameter val_sd1__ADMA_error_status = 32'h00000000;
+parameter mask_sd1__ADMA_error_status = 32'h00000007;
+
+parameter sd1__ADMA_system_address = 32'hE0101058;
+parameter val_sd1__ADMA_system_address = 32'h00000000;
+parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF;
+
+parameter sd1__Boot_Timeout_control = 32'hE0101060;
+parameter val_sd1__Boot_Timeout_control = 32'h00000000;
+parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF;
+
+parameter sd1__Debug_Selection = 32'hE0101064;
+parameter val_sd1__Debug_Selection = 32'h00000000;
+parameter mask_sd1__Debug_Selection = 32'h00000001;
+
+parameter sd1__SPI_interrupt_support = 32'hE01010F0;
+parameter val_sd1__SPI_interrupt_support = 32'h00000000;
+parameter mask_sd1__SPI_interrupt_support = 32'h000000FF;
+
+parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC;
+parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000;
+parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module slcr slcr
+//   doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter slcr__SCL = 32'hF8000000;
+parameter val_slcr__SCL = 32'h00000000;
+parameter mask_slcr__SCL = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_LOCK = 32'hF8000004;
+parameter val_slcr__SLCR_LOCK = 32'h00000000;
+parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_UNLOCK = 32'hF8000008;
+parameter val_slcr__SLCR_UNLOCK = 32'h00000000;
+parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF;
+
+parameter slcr__SLCR_LOCKSTA = 32'hF800000C;
+parameter val_slcr__SLCR_LOCKSTA = 32'h00000001;
+parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF;
+
+parameter slcr__ARM_PLL_CTRL = 32'hF8000100;
+parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_PLL_CTRL = 32'hF8000104;
+parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__IO_PLL_CTRL = 32'hF8000108;
+parameter val_slcr__IO_PLL_CTRL = 32'h0001A008;
+parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PLL_STATUS = 32'hF800010C;
+parameter val_slcr__PLL_STATUS = 32'h0000003F;
+parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__ARM_PLL_CFG = 32'hF8000110;
+parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__DDR_PLL_CFG = 32'hF8000114;
+parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__IO_PLL_CFG = 32'hF8000118;
+parameter val_slcr__IO_PLL_CFG = 32'h00177EA0;
+parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF;
+
+parameter slcr__PLL_BG_CTRL = 32'hF800011C;
+parameter val_slcr__PLL_BG_CTRL = 32'h00000000;
+parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__ARM_CLK_CTRL = 32'hF8000120;
+parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400;
+parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CLK_CTRL = 32'hF8000124;
+parameter val_slcr__DDR_CLK_CTRL = 32'h18400003;
+parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DCI_CLK_CTRL = 32'hF8000128;
+parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201;
+parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__APER_CLK_CTRL = 32'hF800012C;
+parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD;
+parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB0_CLK_CTRL = 32'hF8000130;
+parameter val_slcr__USB0_CLK_CTRL = 32'h00101941;
+parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB1_CLK_CTRL = 32'hF8000134;
+parameter val_slcr__USB1_CLK_CTRL = 32'h00101941;
+parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138;
+parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001;
+parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C;
+parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001;
+parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM0_CLK_CTRL = 32'hF8000140;
+parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01;
+parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM1_CLK_CTRL = 32'hF8000144;
+parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01;
+parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SMC_CLK_CTRL = 32'hF8000148;
+parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21;
+parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C;
+parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821;
+parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SDIO_CLK_CTRL = 32'hF8000150;
+parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03;
+parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__UART_CLK_CTRL = 32'hF8000154;
+parameter val_slcr__UART_CLK_CTRL = 32'h00003F03;
+parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SPI_CLK_CTRL = 32'hF8000158;
+parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03;
+parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_CLK_CTRL = 32'hF800015C;
+parameter val_slcr__CAN_CLK_CTRL = 32'h00501903;
+parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160;
+parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000;
+parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DBG_CLK_CTRL = 32'hF8000164;
+parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03;
+parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PCAP_CLK_CTRL = 32'hF8000168;
+parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01;
+parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C;
+parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000;
+parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170;
+parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_CTRL = 32'hF8000174;
+parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_CNT = 32'hF8000178;
+parameter val_slcr__FPGA0_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA0_THR_STA = 32'hF800017C;
+parameter val_slcr__FPGA0_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180;
+parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_CTRL = 32'hF8000184;
+parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_CNT = 32'hF8000188;
+parameter val_slcr__FPGA1_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA1_THR_STA = 32'hF800018C;
+parameter val_slcr__FPGA1_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190;
+parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_CTRL = 32'hF8000194;
+parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_CNT = 32'hF8000198;
+parameter val_slcr__FPGA2_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA2_THR_STA = 32'hF800019C;
+parameter val_slcr__FPGA2_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0;
+parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800;
+parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4;
+parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000;
+parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_CNT = 32'hF80001A8;
+parameter val_slcr__FPGA3_THR_CNT = 32'h00000000;
+parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF;
+
+parameter slcr__FPGA3_THR_STA = 32'hF80001AC;
+parameter val_slcr__FPGA3_THR_STA = 32'h00010000;
+parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF;
+
+parameter slcr__SRST_UART_CTRL = 32'hF80001B0;
+parameter val_slcr__SRST_UART_CTRL = 32'h00000000;
+parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__BANDGAP_TRIM = 32'hF80001B8;
+parameter val_slcr__BANDGAP_TRIM = 32'h0000001F;
+parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF;
+
+parameter slcr__CC_TEST = 32'hF80001BC;
+parameter val_slcr__CC_TEST = 32'h00000000;
+parameter mask_slcr__CC_TEST = 32'hFFFFFFFF;
+
+parameter slcr__PLL_PREDIVISOR = 32'hF80001C0;
+parameter val_slcr__PLL_PREDIVISOR = 32'h00000001;
+parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF;
+
+parameter slcr__CLK_621_TRUE = 32'hF80001C4;
+parameter val_slcr__CLK_621_TRUE = 32'h00000001;
+parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1;
+
+parameter slcr__PICTURE_DBG = 32'hF80001D0;
+parameter val_slcr__PICTURE_DBG = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF;
+
+parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4;
+parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF;
+
+parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8;
+parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000;
+parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF;
+
+parameter slcr__PSS_RST_CTRL = 32'hF8000200;
+parameter val_slcr__PSS_RST_CTRL = 32'h00000000;
+parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_RST_CTRL = 32'hF8000204;
+parameter val_slcr__DDR_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__TOPSW_RST_CTRL = 32'hF8000208;
+parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000;
+parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DMAC_RST_CTRL = 32'hF800020C;
+parameter val_slcr__DMAC_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__USB_RST_CTRL = 32'hF8000210;
+parameter val_slcr__USB_RST_CTRL = 32'h00000000;
+parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GEM_RST_CTRL = 32'hF8000214;
+parameter val_slcr__GEM_RST_CTRL = 32'h00000000;
+parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SDIO_RST_CTRL = 32'hF8000218;
+parameter val_slcr__SDIO_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SPI_RST_CTRL = 32'hF800021C;
+parameter val_slcr__SPI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__CAN_RST_CTRL = 32'hF8000220;
+parameter val_slcr__CAN_RST_CTRL = 32'h00000000;
+parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__I2C_RST_CTRL = 32'hF8000224;
+parameter val_slcr__I2C_RST_CTRL = 32'h00000000;
+parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__UART_RST_CTRL = 32'hF8000228;
+parameter val_slcr__UART_RST_CTRL = 32'h00000000;
+parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GPIO_RST_CTRL = 32'hF800022C;
+parameter val_slcr__GPIO_RST_CTRL = 32'h00000000;
+parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__LQSPI_RST_CTRL = 32'hF8000230;
+parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__SMC_RST_CTRL = 32'hF8000234;
+parameter val_slcr__SMC_RST_CTRL = 32'h00000000;
+parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__OCM_RST_CTRL = 32'hF8000238;
+parameter val_slcr__OCM_RST_CTRL = 32'h00000000;
+parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DEVCI_RST_CTRL = 32'hF800023C;
+parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000;
+parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__FPGA_RST_CTRL = 32'hF8000240;
+parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F;
+parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244;
+parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000;
+parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__RS_AWDT_CTRL = 32'hF800024C;
+parameter val_slcr__RS_AWDT_CTRL = 32'h00000000;
+parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__RST_REASON = 32'hF8000250;
+parameter val_slcr__RST_REASON = 32'h00000040;
+parameter mask_slcr__RST_REASON = 32'hFFFFFFFF;
+
+parameter slcr__RST_REASON_CLR = 32'hF8000254;
+parameter val_slcr__RST_REASON_CLR = 32'h00000000;
+parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF;
+
+parameter slcr__REBOOT_STATUS = 32'hF8000258;
+parameter val_slcr__REBOOT_STATUS = 32'h00400000;
+parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__BOOT_MODE = 32'hF800025C;
+parameter val_slcr__BOOT_MODE = 32'h00000000;
+parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0;
+
+parameter slcr__APU_CTRL = 32'hF8000300;
+parameter val_slcr__APU_CTRL = 32'h00000000;
+parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__WDT_CLK_SEL = 32'hF8000304;
+parameter val_slcr__WDT_CLK_SEL = 32'h00000000;
+parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_RAM0 = 32'hF8000400;
+parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000;
+parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_RAM1 = 32'hF8000404;
+parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000;
+parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__TZ_OCM_ROM = 32'hF8000408;
+parameter val_slcr__TZ_OCM_ROM = 32'h00000000;
+parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DDR_RAM = 32'hF8000430;
+parameter val_slcr__TZ_DDR_RAM = 32'h00000000;
+parameter mask_slcr__TZ_DDR_RAM = 32'h00000001;
+
+parameter slcr__TZ_DMA_NS = 32'hF8000440;
+parameter val_slcr__TZ_DMA_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444;
+parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448;
+parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000;
+parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF;
+
+parameter slcr__TZ_GEM = 32'hF8000450;
+parameter val_slcr__TZ_GEM = 32'h00000000;
+parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF;
+
+parameter slcr__TZ_SDIO = 32'hF8000454;
+parameter val_slcr__TZ_SDIO = 32'h00000000;
+parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF;
+
+parameter slcr__TZ_USB = 32'hF8000458;
+parameter val_slcr__TZ_USB = 32'h00000000;
+parameter mask_slcr__TZ_USB = 32'hFFFFFFFF;
+
+parameter slcr__TZ_FPGA_M = 32'hF8000484;
+parameter val_slcr__TZ_FPGA_M = 32'h00000000;
+parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF;
+
+parameter slcr__TZ_FPGA_AFI = 32'hF8000488;
+parameter val_slcr__TZ_FPGA_AFI = 32'h00000000;
+parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF;
+
+parameter slcr__DBG_CTRL = 32'hF8000500;
+parameter val_slcr__DBG_CTRL = 32'h00000000;
+parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__PSS_IDCODE = 32'hF8000530;
+parameter val_slcr__PSS_IDCODE = 32'h03720093;
+parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF;
+
+parameter slcr__DDR_URGENT = 32'hF8000600;
+parameter val_slcr__DDR_URGENT = 32'h00000000;
+parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CAL_START = 32'hF800060C;
+parameter val_slcr__DDR_CAL_START = 32'h00000000;
+parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF;
+
+parameter slcr__DDR_REF_START = 32'hF8000614;
+parameter val_slcr__DDR_REF_START = 32'h00000000;
+parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF;
+
+parameter slcr__DDR_CMD_STA = 32'hF8000618;
+parameter val_slcr__DDR_CMD_STA = 32'h00000000;
+parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF;
+
+parameter slcr__DDR_URGENT_SEL = 32'hF800061C;
+parameter val_slcr__DDR_URGENT_SEL = 32'h00000000;
+parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF;
+
+parameter slcr__DDR_DFI_STATUS = 32'hF8000620;
+parameter val_slcr__DDR_DFI_STATUS = 32'h00000000;
+parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_00 = 32'hF8000700;
+parameter val_slcr__MIO_PIN_00 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_01 = 32'hF8000704;
+parameter val_slcr__MIO_PIN_01 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_02 = 32'hF8000708;
+parameter val_slcr__MIO_PIN_02 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_03 = 32'hF800070C;
+parameter val_slcr__MIO_PIN_03 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_04 = 32'hF8000710;
+parameter val_slcr__MIO_PIN_04 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_05 = 32'hF8000714;
+parameter val_slcr__MIO_PIN_05 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_06 = 32'hF8000718;
+parameter val_slcr__MIO_PIN_06 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_07 = 32'hF800071C;
+parameter val_slcr__MIO_PIN_07 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_08 = 32'hF8000720;
+parameter val_slcr__MIO_PIN_08 = 32'h00000601;
+parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_09 = 32'hF8000724;
+parameter val_slcr__MIO_PIN_09 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_10 = 32'hF8000728;
+parameter val_slcr__MIO_PIN_10 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_11 = 32'hF800072C;
+parameter val_slcr__MIO_PIN_11 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_12 = 32'hF8000730;
+parameter val_slcr__MIO_PIN_12 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_13 = 32'hF8000734;
+parameter val_slcr__MIO_PIN_13 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_14 = 32'hF8000738;
+parameter val_slcr__MIO_PIN_14 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_15 = 32'hF800073C;
+parameter val_slcr__MIO_PIN_15 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_16 = 32'hF8000740;
+parameter val_slcr__MIO_PIN_16 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_17 = 32'hF8000744;
+parameter val_slcr__MIO_PIN_17 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_18 = 32'hF8000748;
+parameter val_slcr__MIO_PIN_18 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_19 = 32'hF800074C;
+parameter val_slcr__MIO_PIN_19 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_20 = 32'hF8000750;
+parameter val_slcr__MIO_PIN_20 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_21 = 32'hF8000754;
+parameter val_slcr__MIO_PIN_21 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_22 = 32'hF8000758;
+parameter val_slcr__MIO_PIN_22 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_23 = 32'hF800075C;
+parameter val_slcr__MIO_PIN_23 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_24 = 32'hF8000760;
+parameter val_slcr__MIO_PIN_24 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_25 = 32'hF8000764;
+parameter val_slcr__MIO_PIN_25 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_26 = 32'hF8000768;
+parameter val_slcr__MIO_PIN_26 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_27 = 32'hF800076C;
+parameter val_slcr__MIO_PIN_27 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_28 = 32'hF8000770;
+parameter val_slcr__MIO_PIN_28 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_29 = 32'hF8000774;
+parameter val_slcr__MIO_PIN_29 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_30 = 32'hF8000778;
+parameter val_slcr__MIO_PIN_30 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_31 = 32'hF800077C;
+parameter val_slcr__MIO_PIN_31 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_32 = 32'hF8000780;
+parameter val_slcr__MIO_PIN_32 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_33 = 32'hF8000784;
+parameter val_slcr__MIO_PIN_33 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_34 = 32'hF8000788;
+parameter val_slcr__MIO_PIN_34 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_35 = 32'hF800078C;
+parameter val_slcr__MIO_PIN_35 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_36 = 32'hF8000790;
+parameter val_slcr__MIO_PIN_36 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_37 = 32'hF8000794;
+parameter val_slcr__MIO_PIN_37 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_38 = 32'hF8000798;
+parameter val_slcr__MIO_PIN_38 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_39 = 32'hF800079C;
+parameter val_slcr__MIO_PIN_39 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_40 = 32'hF80007A0;
+parameter val_slcr__MIO_PIN_40 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_41 = 32'hF80007A4;
+parameter val_slcr__MIO_PIN_41 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_42 = 32'hF80007A8;
+parameter val_slcr__MIO_PIN_42 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_43 = 32'hF80007AC;
+parameter val_slcr__MIO_PIN_43 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_44 = 32'hF80007B0;
+parameter val_slcr__MIO_PIN_44 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_45 = 32'hF80007B4;
+parameter val_slcr__MIO_PIN_45 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_46 = 32'hF80007B8;
+parameter val_slcr__MIO_PIN_46 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_47 = 32'hF80007BC;
+parameter val_slcr__MIO_PIN_47 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_48 = 32'hF80007C0;
+parameter val_slcr__MIO_PIN_48 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_49 = 32'hF80007C4;
+parameter val_slcr__MIO_PIN_49 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_50 = 32'hF80007C8;
+parameter val_slcr__MIO_PIN_50 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_51 = 32'hF80007CC;
+parameter val_slcr__MIO_PIN_51 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_52 = 32'hF80007D0;
+parameter val_slcr__MIO_PIN_52 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_PIN_53 = 32'hF80007D4;
+parameter val_slcr__MIO_PIN_53 = 32'h00001601;
+parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800;
+parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000;
+parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF;
+
+parameter slcr__MIO_LOOPBACK = 32'hF8000804;
+parameter val_slcr__MIO_LOOPBACK = 32'h00000000;
+parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF;
+
+parameter slcr__MIO_MST_TRI0 = 32'hF800080C;
+parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
+parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
+
+parameter slcr__MIO_MST_TRI1 = 32'hF8000810;
+parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF;
+parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF;
+
+parameter slcr__SD0_WP_CD_SEL = 32'hF8000830;
+parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000;
+parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF;
+
+parameter slcr__SD1_WP_CD_SEL = 32'hF8000834;
+parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000;
+parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF;
+
+parameter slcr__LVL_SHFTR_EN = 32'hF8000900;
+parameter val_slcr__LVL_SHFTR_EN = 32'h00000000;
+parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF;
+
+parameter slcr__OCM_CFG = 32'hF8000910;
+parameter val_slcr__OCM_CFG = 32'h00000000;
+parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF;
+
+parameter slcr__CPU0_RAM0 = 32'hF8000A00;
+parameter val_slcr__CPU0_RAM0 = 32'h00020202;
+parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF;
+
+parameter slcr__CPU0_RAM1 = 32'hF8000A04;
+parameter val_slcr__CPU0_RAM1 = 32'h00020202;
+parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF;
+
+parameter slcr__CPU0_RAM2 = 32'hF8000A08;
+parameter val_slcr__CPU0_RAM2 = 32'h02020202;
+parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF;
+
+parameter slcr__CPU1_RAM0 = 32'hF8000A0C;
+parameter val_slcr__CPU1_RAM0 = 32'h00020202;
+parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF;
+
+parameter slcr__CPU1_RAM1 = 32'hF8000A10;
+parameter val_slcr__CPU1_RAM1 = 32'h00020202;
+parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF;
+
+parameter slcr__CPU1_RAM2 = 32'hF8000A14;
+parameter val_slcr__CPU1_RAM2 = 32'h02020202;
+parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF;
+
+parameter slcr__SCU_RAM = 32'hF8000A18;
+parameter val_slcr__SCU_RAM = 32'h00000002;
+parameter mask_slcr__SCU_RAM = 32'h000000FF;
+
+parameter slcr__L2C_RAM = 32'hF8000A1C;
+parameter val_slcr__L2C_RAM = 32'h00020202;
+parameter mask_slcr__L2C_RAM = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30;
+parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_USB01 = 32'hF8000A34;
+parameter val_slcr__IOU_RAM_USB01 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38;
+parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C;
+parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909;
+parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF;
+
+parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40;
+parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909;
+parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44;
+parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909;
+parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF;
+
+parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48;
+parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909;
+parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF;
+
+parameter slcr__DMAC_RAM = 32'hF8000A50;
+parameter val_slcr__DMAC_RAM = 32'h00000009;
+parameter mask_slcr__DMAC_RAM = 32'h000000FF;
+
+parameter slcr__AFI0_RAM0 = 32'hF8000A60;
+parameter val_slcr__AFI0_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI0_RAM1 = 32'hF8000A64;
+parameter val_slcr__AFI0_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI0_RAM2 = 32'hF8000A68;
+parameter val_slcr__AFI0_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI1_RAM0 = 32'hF8000A6C;
+parameter val_slcr__AFI1_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI1_RAM1 = 32'hF8000A70;
+parameter val_slcr__AFI1_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI1_RAM2 = 32'hF8000A74;
+parameter val_slcr__AFI1_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI2_RAM0 = 32'hF8000A78;
+parameter val_slcr__AFI2_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI2_RAM1 = 32'hF8000A7C;
+parameter val_slcr__AFI2_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI2_RAM2 = 32'hF8000A80;
+parameter val_slcr__AFI2_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF;
+
+parameter slcr__AFI3_RAM0 = 32'hF8000A84;
+parameter val_slcr__AFI3_RAM0 = 32'h09090909;
+parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF;
+
+parameter slcr__AFI3_RAM1 = 32'hF8000A88;
+parameter val_slcr__AFI3_RAM1 = 32'h09090909;
+parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF;
+
+parameter slcr__AFI3_RAM2 = 32'hF8000A8C;
+parameter val_slcr__AFI3_RAM2 = 32'h00000909;
+parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF;
+
+parameter slcr__OCM_RAM = 32'hF8000A90;
+parameter val_slcr__OCM_RAM = 32'h01010101;
+parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF;
+
+parameter slcr__OCM_ROM0 = 32'hF8000A94;
+parameter val_slcr__OCM_ROM0 = 32'h09090909;
+parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF;
+
+parameter slcr__OCM_ROM1 = 32'hF8000A98;
+parameter val_slcr__OCM_ROM1 = 32'h09090909;
+parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF;
+
+parameter slcr__DEVCI_RAM = 32'hF8000AA0;
+parameter val_slcr__DEVCI_RAM = 32'h00000909;
+parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF;
+
+parameter slcr__CSG_RAM = 32'hF8000AB0;
+parameter val_slcr__CSG_RAM = 32'h00000001;
+parameter mask_slcr__CSG_RAM = 32'h000000FF;
+
+parameter slcr__GPIOB_CTRL = 32'hF8000B00;
+parameter val_slcr__GPIOB_CTRL = 32'h00000000;
+parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04;
+parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08;
+parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C;
+parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10;
+parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14;
+parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000;
+parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF;
+
+parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18;
+parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000;
+parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40;
+parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44;
+parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DATA0 = 32'hF8000B48;
+parameter val_slcr__DDRIOB_DATA0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C;
+parameter val_slcr__DDRIOB_DATA1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50;
+parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54;
+parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800;
+parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_CLOCK = 32'hF8000B58;
+parameter val_slcr__DDRIOB_CLOCK = 32'h00000800;
+parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68;
+parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000;
+parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C;
+parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000;
+parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70;
+parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020;
+parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF;
+
+parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74;
+parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000;
+parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module smcc pl353
+//   doc version: 1.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter smcc__memc_status = 32'hE000E000;
+parameter val_smcc__memc_status = 32'h00000000;
+parameter mask_smcc__memc_status = 32'h00001FFF;
+
+parameter smcc__memif_cfg = 32'hE000E004;
+parameter val_smcc__memif_cfg = 32'h00011205;
+parameter mask_smcc__memif_cfg = 32'h0003FFFF;
+
+parameter smcc__memc_cfg_set = 32'hE000E008;
+parameter val_smcc__memc_cfg_set = 32'h00000000;
+parameter mask_smcc__memc_cfg_set = 32'h00000000;
+
+parameter smcc__memc_cfg_clr = 32'hE000E00C;
+parameter val_smcc__memc_cfg_clr = 32'h00000000;
+parameter mask_smcc__memc_cfg_clr = 32'h00000000;
+
+parameter smcc__direct_cmd = 32'hE000E010;
+parameter val_smcc__direct_cmd = 32'h00000000;
+parameter mask_smcc__direct_cmd = 32'h00000000;
+
+parameter smcc__set_cycles = 32'hE000E014;
+parameter val_smcc__set_cycles = 32'h00000000;
+parameter mask_smcc__set_cycles = 32'h00000000;
+
+parameter smcc__set_opmode = 32'hE000E018;
+parameter val_smcc__set_opmode = 32'h00000000;
+parameter mask_smcc__set_opmode = 32'h00000000;
+
+parameter smcc__refresh_period_0 = 32'hE000E020;
+parameter val_smcc__refresh_period_0 = 32'h00000000;
+parameter mask_smcc__refresh_period_0 = 32'h0000000F;
+
+parameter smcc__refresh_period_1 = 32'hE000E024;
+parameter val_smcc__refresh_period_1 = 32'h00000000;
+parameter mask_smcc__refresh_period_1 = 32'h0000000F;
+
+parameter smcc__sram_cycles0_0 = 32'hE000E100;
+parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC;
+parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF;
+
+parameter smcc__opmode0_0 = 32'hE000E104;
+parameter val_smcc__opmode0_0 = 32'hE2FE0800;
+parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF;
+
+parameter smcc__sram_cycles0_1 = 32'hE000E120;
+parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC;
+parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF;
+
+parameter smcc__opmode0_1 = 32'hE000E124;
+parameter val_smcc__opmode0_1 = 32'hE4FE0800;
+parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF;
+
+parameter smcc__nand_cycles1_0 = 32'hE000E180;
+parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC;
+parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF;
+
+parameter smcc__opmode1_0 = 32'hE000E184;
+parameter val_smcc__opmode1_0 = 32'hE1FF0001;
+parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF;
+
+parameter smcc__user_status = 32'hE000E200;
+parameter val_smcc__user_status = 32'h00000000;
+parameter mask_smcc__user_status = 32'h000000FF;
+
+parameter smcc__user_config = 32'hE000E204;
+parameter val_smcc__user_config = 32'h00000000;
+parameter mask_smcc__user_config = 32'h00000000;
+
+parameter smcc__ecc_status_0 = 32'hE000E300;
+parameter val_smcc__ecc_status_0 = 32'h00000000;
+parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF;
+
+parameter smcc__ecc_memcfg_0 = 32'hE000E304;
+parameter val_smcc__ecc_memcfg_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF;
+
+parameter smcc__ecc_memcommand1_0 = 32'hE000E308;
+parameter val_smcc__ecc_memcommand1_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF;
+
+parameter smcc__ecc_memcommand2_0 = 32'hE000E30C;
+parameter val_smcc__ecc_memcommand2_0 = 32'h00000000;
+parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF;
+
+parameter smcc__ecc_addr0_0 = 32'hE000E310;
+parameter val_smcc__ecc_addr0_0 = 32'h00000000;
+parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_addr1_0 = 32'hE000E314;
+parameter val_smcc__ecc_addr1_0 = 32'h00000000;
+parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF;
+
+parameter smcc__ecc_value0_0 = 32'hE000E318;
+parameter val_smcc__ecc_value0_0 = 32'h00000000;
+parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value1_0 = 32'hE000E31C;
+parameter val_smcc__ecc_value1_0 = 32'h00000000;
+parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value2_0 = 32'hE000E320;
+parameter val_smcc__ecc_value2_0 = 32'h00000000;
+parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value3_0 = 32'hE000E324;
+parameter val_smcc__ecc_value3_0 = 32'h00000000;
+parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_status_1 = 32'hE000E400;
+parameter val_smcc__ecc_status_1 = 32'h00000000;
+parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF;
+
+parameter smcc__ecc_memcfg_1 = 32'hE000E404;
+parameter val_smcc__ecc_memcfg_1 = 32'h00000043;
+parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF;
+
+parameter smcc__ecc_memcommand1_1 = 32'hE000E408;
+parameter val_smcc__ecc_memcommand1_1 = 32'h01300080;
+parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF;
+
+parameter smcc__ecc_memcommand2_1 = 32'hE000E40C;
+parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585;
+parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF;
+
+parameter smcc__ecc_addr0_1 = 32'hE000E410;
+parameter val_smcc__ecc_addr0_1 = 32'h00000000;
+parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_addr1_1 = 32'hE000E414;
+parameter val_smcc__ecc_addr1_1 = 32'h00000000;
+parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF;
+
+parameter smcc__ecc_value0_1 = 32'hE000E418;
+parameter val_smcc__ecc_value0_1 = 32'h00000000;
+parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value1_1 = 32'hE000E41C;
+parameter val_smcc__ecc_value1_1 = 32'h00000000;
+parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value2_1 = 32'hE000E420;
+parameter val_smcc__ecc_value2_1 = 32'h00000000;
+parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF;
+
+parameter smcc__ecc_value3_1 = 32'hE000E424;
+parameter val_smcc__ecc_value3_1 = 32'h00000000;
+parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF;
+
+parameter smcc__integration_test = 32'hE000EE00;
+parameter val_smcc__integration_test = 32'h00000000;
+parameter mask_smcc__integration_test = 32'hFFFFFFFF;
+
+parameter smcc__periph_id_0 = 32'hE000EFE0;
+parameter val_smcc__periph_id_0 = 32'h00000053;
+parameter mask_smcc__periph_id_0 = 32'h000000FF;
+
+parameter smcc__periph_id_1 = 32'hE000EFE4;
+parameter val_smcc__periph_id_1 = 32'h00000013;
+parameter mask_smcc__periph_id_1 = 32'h000000FF;
+
+parameter smcc__periph_id_2 = 32'hE000EFE8;
+parameter val_smcc__periph_id_2 = 32'h00000054;
+parameter mask_smcc__periph_id_2 = 32'h000000FF;
+
+parameter smcc__periph_id_3 = 32'hE000EFEC;
+parameter val_smcc__periph_id_3 = 32'h00000000;
+parameter mask_smcc__periph_id_3 = 32'h00000001;
+
+parameter smcc__pcell_id_0 = 32'hE000EFF0;
+parameter val_smcc__pcell_id_0 = 32'h0000000D;
+parameter mask_smcc__pcell_id_0 = 32'h000000FF;
+
+parameter smcc__pcell_id_1 = 32'hE000EFF4;
+parameter val_smcc__pcell_id_1 = 32'h000000F0;
+parameter mask_smcc__pcell_id_1 = 32'h000000FF;
+
+parameter smcc__pcell_id_2 = 32'hE000EFF8;
+parameter val_smcc__pcell_id_2 = 32'h00000005;
+parameter mask_smcc__pcell_id_2 = 32'h000000FF;
+
+parameter smcc__pcell_id_3 = 32'hE000EFFC;
+parameter val_smcc__pcell_id_3 = 32'h000000B1;
+parameter mask_smcc__pcell_id_3 = 32'h000000FF;
+
+
+// ************************************************************
+//   Module spi0 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter spi0__Config_reg0 = 32'hE0006000;
+parameter val_spi0__Config_reg0 = 32'h00020000;
+parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intr_status_reg0 = 32'hE0006004;
+parameter val_spi0__Intr_status_reg0 = 32'h00000004;
+parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_en_reg0 = 32'hE0006008;
+parameter val_spi0__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_dis_reg0 = 32'hE000600C;
+parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Intrpt_mask_reg0 = 32'hE0006010;
+parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__En_reg0 = 32'hE0006014;
+parameter val_spi0__En_reg0 = 32'h00000000;
+parameter mask_spi0__En_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Delay_reg0 = 32'hE0006018;
+parameter val_spi0__Delay_reg0 = 32'h00000000;
+parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Tx_data_reg0 = 32'hE000601C;
+parameter val_spi0__Tx_data_reg0 = 32'h00000000;
+parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Rx_data_reg0 = 32'hE0006020;
+parameter val_spi0__Rx_data_reg0 = 32'h00000000;
+parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024;
+parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF;
+parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__TX_thres_reg0 = 32'hE0006028;
+parameter val_spi0__TX_thres_reg0 = 32'h00000001;
+parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__RX_thres_reg0 = 32'hE000602C;
+parameter val_spi0__RX_thres_reg0 = 32'h00000001;
+parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi0__Mod_id_reg0 = 32'hE00060FC;
+parameter val_spi0__Mod_id_reg0 = 32'h00090106;
+parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module spi1 SPI
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter spi1__Config_reg0 = 32'hE0007000;
+parameter val_spi1__Config_reg0 = 32'h00020000;
+parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intr_status_reg0 = 32'hE0007004;
+parameter val_spi1__Intr_status_reg0 = 32'h00000004;
+parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_en_reg0 = 32'hE0007008;
+parameter val_spi1__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_dis_reg0 = 32'hE000700C;
+parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Intrpt_mask_reg0 = 32'hE0007010;
+parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__En_reg0 = 32'hE0007014;
+parameter val_spi1__En_reg0 = 32'h00000000;
+parameter mask_spi1__En_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Delay_reg0 = 32'hE0007018;
+parameter val_spi1__Delay_reg0 = 32'h00000000;
+parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Tx_data_reg0 = 32'hE000701C;
+parameter val_spi1__Tx_data_reg0 = 32'h00000000;
+parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Rx_data_reg0 = 32'hE0007020;
+parameter val_spi1__Rx_data_reg0 = 32'h00000000;
+parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024;
+parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF;
+parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__TX_thres_reg0 = 32'hE0007028;
+parameter val_spi1__TX_thres_reg0 = 32'h00000001;
+parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__RX_thres_reg0 = 32'hE000702C;
+parameter val_spi1__RX_thres_reg0 = 32'h00000001;
+parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF;
+
+parameter spi1__Mod_id_reg0 = 32'hE00070FC;
+parameter val_spi1__Mod_id_reg0 = 32'h00090106;
+parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module swdt swdt
+//   doc version: 2.1
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter swdt__MODE = 32'hF8005000;
+parameter val_swdt__MODE = 32'h000001C2;
+parameter mask_swdt__MODE = 32'h00FFFFFF;
+
+parameter swdt__CONTROL = 32'hF8005004;
+parameter val_swdt__CONTROL = 32'h03FFC3FC;
+parameter mask_swdt__CONTROL = 32'h03FFFFFF;
+
+parameter swdt__RESTART = 32'hF8005008;
+parameter val_swdt__RESTART = 32'h00000000;
+parameter mask_swdt__RESTART = 32'h0000FFFF;
+
+parameter swdt__STATUS = 32'hF800500C;
+parameter val_swdt__STATUS = 32'h00000000;
+parameter mask_swdt__STATUS = 32'h00000001;
+
+
+// ************************************************************
+//   Module ttc0 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ttc0__Clock_Control_1 = 32'hF8001000;
+parameter val_ttc0__Clock_Control_1 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_1 = 32'h0000007F;
+
+parameter ttc0__Clock_Control_2 = 32'hF8001004;
+parameter val_ttc0__Clock_Control_2 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_2 = 32'h0000007F;
+
+parameter ttc0__Clock_Control_3 = 32'hF8001008;
+parameter val_ttc0__Clock_Control_3 = 32'h00000000;
+parameter mask_ttc0__Clock_Control_3 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_1 = 32'hF800100C;
+parameter val_ttc0__Counter_Control_1 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_1 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_2 = 32'hF8001010;
+parameter val_ttc0__Counter_Control_2 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_2 = 32'h0000007F;
+
+parameter ttc0__Counter_Control_3 = 32'hF8001014;
+parameter val_ttc0__Counter_Control_3 = 32'h00000021;
+parameter mask_ttc0__Counter_Control_3 = 32'h0000007F;
+
+parameter ttc0__Counter_Value_1 = 32'hF8001018;
+parameter val_ttc0__Counter_Value_1 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF;
+
+parameter ttc0__Counter_Value_2 = 32'hF800101C;
+parameter val_ttc0__Counter_Value_2 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF;
+
+parameter ttc0__Counter_Value_3 = 32'hF8001020;
+parameter val_ttc0__Counter_Value_3 = 32'h00000000;
+parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_1 = 32'hF8001024;
+parameter val_ttc0__Interval_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_2 = 32'hF8001028;
+parameter val_ttc0__Interval_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Interval_Counter_3 = 32'hF800102C;
+parameter val_ttc0__Interval_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_1 = 32'hF8001030;
+parameter val_ttc0__Match_1_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_2 = 32'hF8001034;
+parameter val_ttc0__Match_1_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_1_Counter_3 = 32'hF8001038;
+parameter val_ttc0__Match_1_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_1 = 32'hF800103C;
+parameter val_ttc0__Match_2_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_2 = 32'hF8001040;
+parameter val_ttc0__Match_2_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_2_Counter_3 = 32'hF8001044;
+parameter val_ttc0__Match_2_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_1 = 32'hF8001048;
+parameter val_ttc0__Match_3_Counter_1 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_2 = 32'hF800104C;
+parameter val_ttc0__Match_3_Counter_2 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF;
+
+parameter ttc0__Match_3_Counter_3 = 32'hF8001050;
+parameter val_ttc0__Match_3_Counter_3 = 32'h00000000;
+parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF;
+
+parameter ttc0__Interrupt_Register_1 = 32'hF8001054;
+parameter val_ttc0__Interrupt_Register_1 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Register_2 = 32'hF8001058;
+parameter val_ttc0__Interrupt_Register_2 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Register_3 = 32'hF800105C;
+parameter val_ttc0__Interrupt_Register_3 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_1 = 32'hF8001060;
+parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_2 = 32'hF8001064;
+parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F;
+
+parameter ttc0__Interrupt_Enable_3 = 32'hF8001068;
+parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000;
+parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F;
+
+parameter ttc0__Event_Control_Timer_1 = 32'hF800106C;
+parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007;
+
+parameter ttc0__Event_Control_Timer_2 = 32'hF8001070;
+parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007;
+
+parameter ttc0__Event_Control_Timer_3 = 32'hF8001074;
+parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000;
+parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007;
+
+parameter ttc0__Event_Register_1 = 32'hF8001078;
+parameter val_ttc0__Event_Register_1 = 32'h00000000;
+parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF;
+
+parameter ttc0__Event_Register_2 = 32'hF800107C;
+parameter val_ttc0__Event_Register_2 = 32'h00000000;
+parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF;
+
+parameter ttc0__Event_Register_3 = 32'hF8001080;
+parameter val_ttc0__Event_Register_3 = 32'h00000000;
+parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module ttc1 ttc
+//   doc version: 2.0
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter ttc1__Clock_Control_1 = 32'hF8002000;
+parameter val_ttc1__Clock_Control_1 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_1 = 32'h0000007F;
+
+parameter ttc1__Clock_Control_2 = 32'hF8002004;
+parameter val_ttc1__Clock_Control_2 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_2 = 32'h0000007F;
+
+parameter ttc1__Clock_Control_3 = 32'hF8002008;
+parameter val_ttc1__Clock_Control_3 = 32'h00000000;
+parameter mask_ttc1__Clock_Control_3 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_1 = 32'hF800200C;
+parameter val_ttc1__Counter_Control_1 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_1 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_2 = 32'hF8002010;
+parameter val_ttc1__Counter_Control_2 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_2 = 32'h0000007F;
+
+parameter ttc1__Counter_Control_3 = 32'hF8002014;
+parameter val_ttc1__Counter_Control_3 = 32'h00000021;
+parameter mask_ttc1__Counter_Control_3 = 32'h0000007F;
+
+parameter ttc1__Counter_Value_1 = 32'hF8002018;
+parameter val_ttc1__Counter_Value_1 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF;
+
+parameter ttc1__Counter_Value_2 = 32'hF800201C;
+parameter val_ttc1__Counter_Value_2 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF;
+
+parameter ttc1__Counter_Value_3 = 32'hF8002020;
+parameter val_ttc1__Counter_Value_3 = 32'h00000000;
+parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_1 = 32'hF8002024;
+parameter val_ttc1__Interval_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_2 = 32'hF8002028;
+parameter val_ttc1__Interval_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Interval_Counter_3 = 32'hF800202C;
+parameter val_ttc1__Interval_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_1 = 32'hF8002030;
+parameter val_ttc1__Match_1_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_2 = 32'hF8002034;
+parameter val_ttc1__Match_1_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_1_Counter_3 = 32'hF8002038;
+parameter val_ttc1__Match_1_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_1 = 32'hF800203C;
+parameter val_ttc1__Match_2_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_2 = 32'hF8002040;
+parameter val_ttc1__Match_2_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_2_Counter_3 = 32'hF8002044;
+parameter val_ttc1__Match_2_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_1 = 32'hF8002048;
+parameter val_ttc1__Match_3_Counter_1 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_2 = 32'hF800204C;
+parameter val_ttc1__Match_3_Counter_2 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF;
+
+parameter ttc1__Match_3_Counter_3 = 32'hF8002050;
+parameter val_ttc1__Match_3_Counter_3 = 32'h00000000;
+parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF;
+
+parameter ttc1__Interrupt_Register_1 = 32'hF8002054;
+parameter val_ttc1__Interrupt_Register_1 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Register_2 = 32'hF8002058;
+parameter val_ttc1__Interrupt_Register_2 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Register_3 = 32'hF800205C;
+parameter val_ttc1__Interrupt_Register_3 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_1 = 32'hF8002060;
+parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_2 = 32'hF8002064;
+parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F;
+
+parameter ttc1__Interrupt_Enable_3 = 32'hF8002068;
+parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000;
+parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F;
+
+parameter ttc1__Event_Control_Timer_1 = 32'hF800206C;
+parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007;
+
+parameter ttc1__Event_Control_Timer_2 = 32'hF8002070;
+parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007;
+
+parameter ttc1__Event_Control_Timer_3 = 32'hF8002074;
+parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000;
+parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007;
+
+parameter ttc1__Event_Register_1 = 32'hF8002078;
+parameter val_ttc1__Event_Register_1 = 32'h00000000;
+parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF;
+
+parameter ttc1__Event_Register_2 = 32'hF800207C;
+parameter val_ttc1__Event_Register_2 = 32'h00000000;
+parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF;
+
+parameter ttc1__Event_Register_3 = 32'hF8002080;
+parameter val_ttc1__Event_Register_3 = 32'h00000000;
+parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF;
+
+
+// ************************************************************
+//   Module uart0 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter uart0__Control_reg0 = 32'hE0000000;
+parameter val_uart0__Control_reg0 = 32'h00000128;
+parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__mode_reg0 = 32'hE0000004;
+parameter val_uart0__mode_reg0 = 32'h00000000;
+parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_en_reg0 = 32'hE0000008;
+parameter val_uart0__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_dis_reg0 = 32'hE000000C;
+parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Intrpt_mask_reg0 = 32'hE0000010;
+parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014;
+parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200;
+parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018;
+parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B;
+parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C;
+parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000;
+parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020;
+parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+parameter uart0__Modem_ctrl_reg0 = 32'hE0000024;
+parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000;
+parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Modem_sts_reg0 = 32'hE0000028;
+parameter val_uart0__Modem_sts_reg0 = 32'h00000000;
+parameter mask_uart0__Modem_sts_reg0 = 32'h00000000;
+
+parameter uart0__Channel_sts_reg0 = 32'hE000002C;
+parameter val_uart0__Channel_sts_reg0 = 32'h00000000;
+parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__TX_RX_FIFO0 = 32'hE0000030;
+parameter val_uart0__TX_RX_FIFO0 = 32'h00000000;
+parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF;
+
+parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034;
+parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F;
+parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__Flow_delay_reg0 = 32'hE0000038;
+parameter val_uart0__Flow_delay_reg0 = 32'h00000000;
+parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF;
+
+parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C;
+parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000;
+parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
+
+parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040;
+parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000;
+parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
+
+parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044;
+parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module uart1 UART
+//   doc version: 1.2
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter uart1__Control_reg0 = 32'hE0001000;
+parameter val_uart1__Control_reg0 = 32'h00000128;
+parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__mode_reg0 = 32'hE0001004;
+parameter val_uart1__mode_reg0 = 32'h00000000;
+parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_en_reg0 = 32'hE0001008;
+parameter val_uart1__Intrpt_en_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_dis_reg0 = 32'hE000100C;
+parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Intrpt_mask_reg0 = 32'hE0001010;
+parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000;
+parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014;
+parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200;
+parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018;
+parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B;
+parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C;
+parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000;
+parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020;
+parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+parameter uart1__Modem_ctrl_reg0 = 32'hE0001024;
+parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000;
+parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Modem_sts_reg0 = 32'hE0001028;
+parameter val_uart1__Modem_sts_reg0 = 32'h00000000;
+parameter mask_uart1__Modem_sts_reg0 = 32'h00000000;
+
+parameter uart1__Channel_sts_reg0 = 32'hE000102C;
+parameter val_uart1__Channel_sts_reg0 = 32'h00000000;
+parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__TX_RX_FIFO0 = 32'hE0001030;
+parameter val_uart1__TX_RX_FIFO0 = 32'h00000000;
+parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF;
+
+parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034;
+parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F;
+parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__Flow_delay_reg0 = 32'hE0001038;
+parameter val_uart1__Flow_delay_reg0 = 32'h00000000;
+parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF;
+
+parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C;
+parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000;
+parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
+
+parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040;
+parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000;
+parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
+
+parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044;
+parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020;
+parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
+
+
+// ************************************************************
+//   Module usb0 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter usb0__ID = 32'hE0002000;
+parameter val_usb0__ID = 32'hE441FA05;
+parameter mask_usb0__ID = 32'hFFFFFFFF;
+
+parameter usb0__HWGENERAL = 32'hE0002004;
+parameter val_usb0__HWGENERAL = 32'h00000083;
+parameter mask_usb0__HWGENERAL = 32'h00000FFF;
+
+parameter usb0__HWHOST = 32'hE0002008;
+parameter val_usb0__HWHOST = 32'h10020001;
+parameter mask_usb0__HWHOST = 32'hFFFFFFFF;
+
+parameter usb0__HWDEVICE = 32'hE000200C;
+parameter val_usb0__HWDEVICE = 32'h00000019;
+parameter mask_usb0__HWDEVICE = 32'h0000003F;
+
+parameter usb0__HWTXBUF = 32'hE0002010;
+parameter val_usb0__HWTXBUF = 32'h80060A10;
+parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF;
+
+parameter usb0__HWRXBUF = 32'hE0002014;
+parameter val_usb0__HWRXBUF = 32'h00000A10;
+parameter mask_usb0__HWRXBUF = 32'hFF00FFFF;
+
+parameter usb0__GPTIMER0LD = 32'hE0002080;
+parameter val_usb0__GPTIMER0LD = 32'h00000000;
+parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF;
+
+parameter usb0__GPTIMER0CTRL = 32'hE0002084;
+parameter val_usb0__GPTIMER0CTRL = 32'h00000000;
+parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF;
+
+parameter usb0__GPTIMER1LD = 32'hE0002088;
+parameter val_usb0__GPTIMER1LD = 32'h00000000;
+parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF;
+
+parameter usb0__GPTIMER1CTRL = 32'hE000208C;
+parameter val_usb0__GPTIMER1CTRL = 32'h00000000;
+parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF;
+
+parameter usb0__SBUSCFG = 32'hE0002090;
+parameter val_usb0__SBUSCFG = 32'h00000003;
+parameter mask_usb0__SBUSCFG = 32'h00000007;
+
+parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100;
+parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040;
+parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
+
+parameter usb0__HCSPARAMS = 32'hE0002104;
+parameter val_usb0__HCSPARAMS = 32'h00010011;
+parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF;
+
+parameter usb0__HCCPARAMS = 32'hE0002108;
+parameter val_usb0__HCCPARAMS = 32'h00000006;
+parameter mask_usb0__HCCPARAMS = 32'h0000FFFF;
+
+parameter usb0__DCIVERSION = 32'hE0002120;
+parameter val_usb0__DCIVERSION = 32'h00000001;
+parameter mask_usb0__DCIVERSION = 32'h0000FFFF;
+
+parameter usb0__DCCPARAMS = 32'hE0002124;
+parameter val_usb0__DCCPARAMS = 32'h0000018C;
+parameter mask_usb0__DCCPARAMS = 32'h000001FF;
+
+parameter usb0__USBCMD = 32'hE0002140;
+parameter val_usb0__USBCMD = 32'h00000B00;
+parameter mask_usb0__USBCMD = 32'h00FFFFFF;
+
+parameter usb0__USBSTS = 32'hE0002144;
+parameter val_usb0__USBSTS = 32'h00000000;
+parameter mask_usb0__USBSTS = 32'h03FFFFFF;
+
+parameter usb0__USBINTR = 32'hE0002148;
+parameter val_usb0__USBINTR = 32'h00000000;
+parameter mask_usb0__USBINTR = 32'h03FF0FFF;
+
+parameter usb0__FRINDEX = 32'hE000214C;
+parameter val_usb0__FRINDEX = 32'h00000000;
+parameter mask_usb0__FRINDEX = 32'h00003FFF;
+
+parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154;
+parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
+parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
+
+parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158;
+parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
+parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
+
+parameter usb0__TTCTRL = 32'hE000215C;
+parameter val_usb0__TTCTRL = 32'h00000000;
+parameter mask_usb0__TTCTRL = 32'hFFFFFFFF;
+
+parameter usb0__BURSTSIZE = 32'hE0002160;
+parameter val_usb0__BURSTSIZE = 32'h00001010;
+parameter mask_usb0__BURSTSIZE = 32'h0001FFFF;
+
+parameter usb0__TXFILLTUNING = 32'hE0002164;
+parameter val_usb0__TXFILLTUNING = 32'h00020000;
+parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF;
+
+parameter usb0__TXTTFILLTUNING = 32'hE0002168;
+parameter val_usb0__TXTTFILLTUNING = 32'h00000000;
+parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF;
+
+parameter usb0__IC_USB = 32'hE000216C;
+parameter val_usb0__IC_USB = 32'h00000000;
+parameter mask_usb0__IC_USB = 32'hFFFFFFFF;
+
+parameter usb0__ULPI_VIEWPORT = 32'hE0002170;
+parameter val_usb0__ULPI_VIEWPORT = 32'h00000000;
+parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTNAK = 32'hE0002178;
+parameter val_usb0__ENDPTNAK = 32'h00000000;
+parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTNAKEN = 32'hE000217C;
+parameter val_usb0__ENDPTNAKEN = 32'h00000000;
+parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF;
+
+parameter usb0__CONFIGFLAG = 32'hE0002180;
+parameter val_usb0__CONFIGFLAG = 32'h00000001;
+parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF;
+
+parameter usb0__PORTSC1 = 32'hE0002184;
+parameter val_usb0__PORTSC1 = 32'h00000000;
+parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF;
+
+parameter usb0__OTGSC = 32'hE00021A4;
+parameter val_usb0__OTGSC = 32'h00000020;
+parameter mask_usb0__OTGSC = 32'hFFFFFFFF;
+
+parameter usb0__USBMODE = 32'hE00021A8;
+parameter val_usb0__USBMODE = 32'h00000000;
+parameter mask_usb0__USBMODE = 32'h0000FFFF;
+
+parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC;
+parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000;
+parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF;
+
+parameter usb0__ENDPTPRIME = 32'hE00021B0;
+parameter val_usb0__ENDPTPRIME = 32'h00000000;
+parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTFLUSH = 32'hE00021B4;
+parameter val_usb0__ENDPTFLUSH = 32'h00000000;
+parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTSTAT = 32'hE00021B8;
+parameter val_usb0__ENDPTSTAT = 32'h00000000;
+parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTCOMPLETE = 32'hE00021BC;
+parameter val_usb0__ENDPTCOMPLETE = 32'h00000000;
+parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF;
+
+parameter usb0__ENDPTCTRL0 = 32'hE00021C0;
+parameter val_usb0__ENDPTCTRL0 = 32'h00800080;
+parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL1 = 32'hE00021C4;
+parameter val_usb0__ENDPTCTRL1 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL2 = 32'hE00021C8;
+parameter val_usb0__ENDPTCTRL2 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL3 = 32'hE00021CC;
+parameter val_usb0__ENDPTCTRL3 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL4 = 32'hE00021D0;
+parameter val_usb0__ENDPTCTRL4 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL5 = 32'hE00021D4;
+parameter val_usb0__ENDPTCTRL5 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL6 = 32'hE00021D8;
+parameter val_usb0__ENDPTCTRL6 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL7 = 32'hE00021DC;
+parameter val_usb0__ENDPTCTRL7 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL8 = 32'hE00021E0;
+parameter val_usb0__ENDPTCTRL8 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL9 = 32'hE00021E4;
+parameter val_usb0__ENDPTCTRL9 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL10 = 32'hE00021E8;
+parameter val_usb0__ENDPTCTRL10 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL11 = 32'hE00021EC;
+parameter val_usb0__ENDPTCTRL11 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF;
+
+parameter usb0__ENDPTCTRL12 = 32'hE00021F0;
+parameter val_usb0__ENDPTCTRL12 = 32'h00000000;
+parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF;
+
+
+// ************************************************************
+//   Module usb1 usb
+//   doc version: 1.3
+// ************************************************************
+
+// ADDRESS  DEVFALUE   MASK       NAME
+parameter usb1__ID = 32'hE0003000;
+parameter val_usb1__ID = 32'hE441FA05;
+parameter mask_usb1__ID = 32'hFFFFFFFF;
+
+parameter usb1__HWGENERAL = 32'hE0003004;
+parameter val_usb1__HWGENERAL = 32'h00000083;
+parameter mask_usb1__HWGENERAL = 32'h00000FFF;
+
+parameter usb1__HWHOST = 32'hE0003008;
+parameter val_usb1__HWHOST = 32'h10020001;
+parameter mask_usb1__HWHOST = 32'hFFFFFFFF;
+
+parameter usb1__HWDEVICE = 32'hE000300C;
+parameter val_usb1__HWDEVICE = 32'h00000019;
+parameter mask_usb1__HWDEVICE = 32'h0000003F;
+
+parameter usb1__HWTXBUF = 32'hE0003010;
+parameter val_usb1__HWTXBUF = 32'h80060A10;
+parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF;
+
+parameter usb1__HWRXBUF = 32'hE0003014;
+parameter val_usb1__HWRXBUF = 32'h00000A10;
+parameter mask_usb1__HWRXBUF = 32'hFF00FFFF;
+
+parameter usb1__GPTIMER0LD = 32'hE0003080;
+parameter val_usb1__GPTIMER0LD = 32'h00000000;
+parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF;
+
+parameter usb1__GPTIMER0CTRL = 32'hE0003084;
+parameter val_usb1__GPTIMER0CTRL = 32'h00000000;
+parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF;
+
+parameter usb1__GPTIMER1LD = 32'hE0003088;
+parameter val_usb1__GPTIMER1LD = 32'h00000000;
+parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF;
+
+parameter usb1__GPTIMER1CTRL = 32'hE000308C;
+parameter val_usb1__GPTIMER1CTRL = 32'h00000000;
+parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF;
+
+parameter usb1__SBUSCFG = 32'hE0003090;
+parameter val_usb1__SBUSCFG = 32'h00000003;
+parameter mask_usb1__SBUSCFG = 32'h00000007;
+
+parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100;
+parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040;
+parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
+
+parameter usb1__HCSPARAMS = 32'hE0003104;
+parameter val_usb1__HCSPARAMS = 32'h00010011;
+parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF;
+
+parameter usb1__HCCPARAMS = 32'hE0003108;
+parameter val_usb1__HCCPARAMS = 32'h00000006;
+parameter mask_usb1__HCCPARAMS = 32'h0000FFFF;
+
+parameter usb1__DCIVERSION = 32'hE0003120;
+parameter val_usb1__DCIVERSION = 32'h00000001;
+parameter mask_usb1__DCIVERSION = 32'h0000FFFF;
+
+parameter usb1__DCCPARAMS = 32'hE0003124;
+parameter val_usb1__DCCPARAMS = 32'h0000018C;
+parameter mask_usb1__DCCPARAMS = 32'h000001FF;
+
+parameter usb1__USBCMD = 32'hE0003140;
+parameter val_usb1__USBCMD = 32'h00000B00;
+parameter mask_usb1__USBCMD = 32'h00FFFFFF;
+
+parameter usb1__USBSTS = 32'hE0003144;
+parameter val_usb1__USBSTS = 32'h00000000;
+parameter mask_usb1__USBSTS = 32'h03FFFFFF;
+
+parameter usb1__USBINTR = 32'hE0003148;
+parameter val_usb1__USBINTR = 32'h00000000;
+parameter mask_usb1__USBINTR = 32'h03FF0FFF;
+
+parameter usb1__FRINDEX = 32'hE000314C;
+parameter val_usb1__FRINDEX = 32'h00000000;
+parameter mask_usb1__FRINDEX = 32'h00003FFF;
+
+parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154;
+parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
+parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
+
+parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158;
+parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
+parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
+
+parameter usb1__TTCTRL = 32'hE000315C;
+parameter val_usb1__TTCTRL = 32'h00000000;
+parameter mask_usb1__TTCTRL = 32'hFFFFFFFF;
+
+parameter usb1__BURSTSIZE = 32'hE0003160;
+parameter val_usb1__BURSTSIZE = 32'h00001010;
+parameter mask_usb1__BURSTSIZE = 32'h0001FFFF;
+
+parameter usb1__TXFILLTUNING = 32'hE0003164;
+parameter val_usb1__TXFILLTUNING = 32'h00020000;
+parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF;
+
+parameter usb1__TXTTFILLTUNING = 32'hE0003168;
+parameter val_usb1__TXTTFILLTUNING = 32'h00000000;
+parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF;
+
+parameter usb1__IC_USB = 32'hE000316C;
+parameter val_usb1__IC_USB = 32'h00000000;
+parameter mask_usb1__IC_USB = 32'hFFFFFFFF;
+
+parameter usb1__ULPI_VIEWPORT = 32'hE0003170;
+parameter val_usb1__ULPI_VIEWPORT = 32'h00000000;
+parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTNAK = 32'hE0003178;
+parameter val_usb1__ENDPTNAK = 32'h00000000;
+parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTNAKEN = 32'hE000317C;
+parameter val_usb1__ENDPTNAKEN = 32'h00000000;
+parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF;
+
+parameter usb1__CONFIGFLAG = 32'hE0003180;
+parameter val_usb1__CONFIGFLAG = 32'h00000001;
+parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF;
+
+parameter usb1__PORTSC1 = 32'hE0003184;
+parameter val_usb1__PORTSC1 = 32'h00000000;
+parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF;
+
+parameter usb1__OTGSC = 32'hE00031A4;
+parameter val_usb1__OTGSC = 32'h00000020;
+parameter mask_usb1__OTGSC = 32'hFFFFFFFF;
+
+parameter usb1__USBMODE = 32'hE00031A8;
+parameter val_usb1__USBMODE = 32'h00000000;
+parameter mask_usb1__USBMODE = 32'h0000FFFF;
+
+parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC;
+parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000;
+parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF;
+
+parameter usb1__ENDPTPRIME = 32'hE00031B0;
+parameter val_usb1__ENDPTPRIME = 32'h00000000;
+parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTFLUSH = 32'hE00031B4;
+parameter val_usb1__ENDPTFLUSH = 32'h00000000;
+parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTSTAT = 32'hE00031B8;
+parameter val_usb1__ENDPTSTAT = 32'h00000000;
+parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTCOMPLETE = 32'hE00031BC;
+parameter val_usb1__ENDPTCOMPLETE = 32'h00000000;
+parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF;
+
+parameter usb1__ENDPTCTRL0 = 32'hE00031C0;
+parameter val_usb1__ENDPTCTRL0 = 32'h00800080;
+parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL1 = 32'hE00031C4;
+parameter val_usb1__ENDPTCTRL1 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL2 = 32'hE00031C8;
+parameter val_usb1__ENDPTCTRL2 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL3 = 32'hE00031CC;
+parameter val_usb1__ENDPTCTRL3 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL4 = 32'hE00031D0;
+parameter val_usb1__ENDPTCTRL4 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL5 = 32'hE00031D4;
+parameter val_usb1__ENDPTCTRL5 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL6 = 32'hE00031D8;
+parameter val_usb1__ENDPTCTRL6 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL7 = 32'hE00031DC;
+parameter val_usb1__ENDPTCTRL7 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL8 = 32'hE00031E0;
+parameter val_usb1__ENDPTCTRL8 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL9 = 32'hE00031E4;
+parameter val_usb1__ENDPTCTRL9 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL10 = 32'hE00031E8;
+parameter val_usb1__ENDPTCTRL10 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL11 = 32'hE00031EC;
+parameter val_usb1__ENDPTCTRL11 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF;
+
+parameter usb1__ENDPTCTRL12 = 32'hE00031F0;
+parameter val_usb1__ENDPTCTRL12 = 32'h00000000;
+parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF;
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_unused_ports.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_unused_ports.v
new file mode 100644
index 0000000..67ce36b
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_3_unused_ports.v
@@ -0,0 +1,433 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_unused_ports.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Semantic checks for unused ports.
+ *
+ *****************************************************************************/
+
+/* CAN */
+assign CAN0_PHY_TX = 0;
+assign CAN1_PHY_TX = 0;
+always @(CAN0_PHY_RX or CAN1_PHY_RX)
+begin 
+ if(CAN0_PHY_RX | CAN1_PHY_RX)
+  $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* ETHERNET */
+/* ------------------------------------------- */
+
+assign ENET0_GMII_TX_EN = 0;
+assign ENET0_GMII_TX_ER = 0;
+assign ENET0_MDIO_MDC = 0;
+assign ENET0_MDIO_O = 0; /// confirm
+assign ENET0_MDIO_T = 0;
+assign ENET0_PTP_DELAY_REQ_RX = 0;
+assign ENET0_PTP_DELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_REQ_RX = 0;
+assign ENET0_PTP_PDELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_RESP_RX = 0;
+assign ENET0_PTP_PDELAY_RESP_TX = 0;
+assign ENET0_PTP_SYNC_FRAME_RX = 0;
+assign ENET0_PTP_SYNC_FRAME_TX = 0;
+assign ENET0_SOF_RX = 0;
+assign ENET0_SOF_TX = 0;
+assign ENET0_GMII_TXD = 0;
+always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or 
+        ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
+        ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
+begin 
+ if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | 
+        ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
+        ENET0_GMII_TX_CLK | ENET0_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+assign ENET1_GMII_TX_EN = 0;
+assign ENET1_GMII_TX_ER = 0;
+assign ENET1_MDIO_MDC = 0;
+assign ENET1_MDIO_O = 0;/// confirm
+assign ENET1_MDIO_T = 0;
+assign ENET1_PTP_DELAY_REQ_RX = 0;
+assign ENET1_PTP_DELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_REQ_RX = 0;
+assign ENET1_PTP_PDELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_RESP_RX = 0;
+assign ENET1_PTP_PDELAY_RESP_TX = 0;
+assign ENET1_PTP_SYNC_FRAME_RX = 0;
+assign ENET1_PTP_SYNC_FRAME_TX = 0;
+assign ENET1_SOF_RX = 0;
+assign ENET1_SOF_TX = 0;
+assign ENET1_GMII_TXD = 0;
+always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or 
+        ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
+        ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
+begin 
+ if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | 
+        ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
+        ENET1_GMII_TX_CLK | ENET1_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* GPIO */
+/* ------------------------------------------- */
+
+assign GPIO_O = 0;
+assign GPIO_T = 0;
+always@(GPIO_I)
+begin
+if(GPIO_I !== 0)
+ $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* I2C */
+/* ------------------------------------------- */
+
+assign I2C0_SDA_O = 0;
+assign I2C0_SDA_T = 0;
+assign I2C0_SCL_O = 0;
+assign I2C0_SCL_T = 0;
+assign I2C1_SDA_O = 0;
+assign I2C1_SDA_T = 0;
+assign I2C1_SCL_O = 0;
+assign I2C1_SCL_T = 0;
+always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
+begin
+ if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
+  $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* JTAG  */
+/* ------------------------------------------- */
+
+assign PJTAG_TD_T = 0;
+assign PJTAG_TD_O = 0;
+always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
+begin
+ if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
+  $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SDIO  */
+/* ------------------------------------------- */
+
+assign SDIO0_CLK = 0;
+assign SDIO0_CMD_O = 0;
+assign SDIO0_CMD_T = 0;
+assign SDIO0_DATA_O = 0;
+assign SDIO0_DATA_T = 0;
+assign SDIO0_LED = 0;
+assign SDIO0_BUSPOW = 0;
+assign SDIO0_BUSVOLT = 0;
+always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
+begin
+ if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SDIO1_CLK = 0;
+assign SDIO1_CMD_O = 0;
+assign SDIO1_CMD_T = 0;
+assign SDIO1_DATA_O = 0;
+assign SDIO1_DATA_T = 0;
+assign SDIO1_LED = 0;
+assign SDIO1_BUSPOW = 0;
+assign SDIO1_BUSVOLT = 0;
+always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
+begin
+ if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SPI  */
+/* ------------------------------------------- */
+
+assign SPI0_SCLK_O = 0;
+assign SPI0_SCLK_T = 0;
+assign SPI0_MOSI_O = 0;
+assign SPI0_MOSI_T = 0;
+assign SPI0_MISO_O = 0;
+assign SPI0_MISO_T = 0;
+assign SPI0_SS_O = 0; /// confirm
+assign SPI0_SS1_O = 0;/// confirm
+assign SPI0_SS2_O = 0;/// confirm
+assign SPI0_SS_T = 0;
+always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
+begin
+ if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SPI1_SCLK_O = 0;
+assign SPI1_SCLK_T = 0;
+assign SPI1_MOSI_O = 0;
+assign SPI1_MOSI_T = 0;
+assign SPI1_MISO_O = 0;
+assign SPI1_MISO_T = 0;
+assign SPI1_SS_O = 0;
+assign SPI1_SS1_O = 0;
+assign SPI1_SS2_O = 0;
+assign SPI1_SS_T = 0;
+always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
+begin
+ if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* UART  */
+/* ------------------------------------------- */
+/// confirm
+assign UART0_DTRN = 0;
+assign UART0_RTSN = 0;
+assign UART0_TX = 0;
+always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
+begin
+ if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+assign UART1_DTRN = 0;
+assign UART1_RTSN = 0;
+assign UART1_TX = 0;
+always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
+begin
+ if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TTC  */
+/* ------------------------------------------- */
+
+assign TTC0_WAVE0_OUT = 0;
+assign TTC0_WAVE1_OUT = 0;
+assign TTC0_WAVE2_OUT = 0;
+always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
+begin
+ if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+assign TTC1_WAVE0_OUT = 0;
+assign TTC1_WAVE1_OUT = 0;
+assign TTC1_WAVE2_OUT = 0;
+always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
+begin
+ if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* WDT  */
+/* ------------------------------------------- */
+
+assign WDT_RST_OUT = 0;
+always@(WDT_CLK_IN)
+begin
+ if(WDT_CLK_IN)
+  $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TRACE  */
+/* ------------------------------------------- */
+
+assign TRACE_CTL = 0;
+assign TRACE_DATA = 0;
+always@(TRACE_CLK)
+begin
+ if(TRACE_CLK)
+  $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* USB  */
+/* ------------------------------------------- */
+assign USB0_PORT_INDCTL = 0;
+assign USB0_VBUS_PWRSELECT = 0;
+always@(USB0_VBUS_PWRFAULT)
+begin
+ if(USB0_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+assign USB1_PORT_INDCTL = 0;
+assign USB1_VBUS_PWRSELECT = 0;
+always@(USB1_VBUS_PWRFAULT)
+begin
+ if(USB1_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+always@(SRAM_INTIN)
+begin
+ if(SRAM_INTIN)
+  $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
+end 
+
+/* ------------------------------------------- */
+/* DMA  */
+/* ------------------------------------------- */
+
+assign DMA0_DATYPE = 0;
+assign DMA0_DAVALID = 0;
+assign DMA0_DRREADY = 0;
+assign DMA0_RSTN = 0;
+always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
+begin
+ if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA1_DATYPE = 0;
+assign DMA1_DAVALID = 0;
+assign DMA1_DRREADY = 0;
+assign DMA1_RSTN = 0;
+always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
+begin
+ if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA2_DATYPE = 0;
+assign DMA2_DAVALID = 0;
+assign DMA2_DRREADY = 0;
+assign DMA2_RSTN = 0;
+always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
+begin
+ if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA3_DATYPE = 0;
+assign DMA3_DAVALID = 0;
+assign DMA3_DRREADY = 0;
+assign DMA3_RSTN = 0;
+always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
+begin
+ if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FTM  */
+/* ------------------------------------------- */
+
+assign FTMT_F2P_TRIGACK = 0;
+assign FTMT_P2F_TRIG = 0;
+assign FTMT_P2F_DEBUG = 0;
+always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or 
+        FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
+begin
+ if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
+  $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* EVENT  */
+/* ------------------------------------------- */
+
+assign EVENT_EVENTO = 0;
+assign EVENT_STANDBYWFE = 0;  
+assign EVENT_STANDBYWFI = 0;
+always@(EVENT_EVENTI)
+begin
+ if(EVENT_EVENTI)
+  $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MIO */
+/* ------------------------------------------- */
+
+always@(MIO)
+begin
+  if(MIO !== 0)
+  $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FCLK_TRIG */
+/* ------------------------------------------- */
+
+always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
+begin
+ if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
+  $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MISC */
+/* ------------------------------------------- */
+
+always@(FPGA_IDLE_N)
+begin
+ if(FPGA_IDLE_N)
+  $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
+end
+
+always@(DDR_ARB)
+begin
+ if(DDR_ARB !== 0)
+  $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
+end
+
+always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
+begin
+ if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) 
+  $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* DDR */
+/* ------------------------------------------- */
+
+assign DDR_WEB = 0;
+always@(DDR_Clk or DDR_CS_n)
+begin
+if(!DDR_CS_n)
+ $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* IRQ_P2F */
+/* ------------------------------------------- */
+
+assign IRQ_P2F_DMAC_ABORT = 0;
+assign IRQ_P2F_DMAC0 = 0;
+assign IRQ_P2F_DMAC1 = 0;
+assign IRQ_P2F_DMAC2 = 0;
+assign IRQ_P2F_DMAC3 = 0;
+assign IRQ_P2F_DMAC4 = 0;
+assign IRQ_P2F_DMAC5 = 0;
+assign IRQ_P2F_DMAC6 = 0;
+assign IRQ_P2F_DMAC7 = 0;
+assign IRQ_P2F_SMC = 0;
+assign IRQ_P2F_QSPI = 0;
+assign IRQ_P2F_CTI = 0;
+assign IRQ_P2F_GPIO = 0;
+assign IRQ_P2F_USB0 = 0;
+assign IRQ_P2F_ENET0 = 0;
+assign IRQ_P2F_ENET_WAKE0 = 0;
+assign IRQ_P2F_SDIO0 = 0;
+assign IRQ_P2F_I2C0 = 0;
+assign IRQ_P2F_SPI0 = 0;
+assign IRQ_P2F_UART0 = 0;
+assign IRQ_P2F_CAN0 = 0;
+assign IRQ_P2F_USB1 = 0;
+assign IRQ_P2F_ENET1 = 0;
+assign IRQ_P2F_ENET_WAKE1 = 0;
+assign IRQ_P2F_SDIO1 = 0;
+assign IRQ_P2F_I2C1 = 0;
+assign IRQ_P2F_SPI1 = 0;
+assign IRQ_P2F_UART1 = 0;
+assign IRQ_P2F_CAN1 = 0;
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv
new file mode 100644
index 0000000..f8f195c
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/1313/hdl/processing_system7_vip_v1_0_vl_rfs.sv
@@ -0,0 +1,9393 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_wr.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 2 write requests from 2 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_wr(
+ rstn,
+ sw_clk,
+ qos1,
+ qos2,
+ prt_dv1,
+ prt_dv2,
+ prt_data1,
+ prt_data2,
+ prt_addr1,
+ prt_addr2,
+ prt_bytes1,
+ prt_bytes2,
+ prt_ack1,
+ prt_ack2,
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_ack
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2;
+input [max_burst_bits-1:0] prt_data1,prt_data2;
+input [addr_width-1:0] prt_addr1,prt_addr2;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
+input prt_dv1, prt_dv2, prt_ack;
+output reg prt_ack1,prt_ack2,prt_req;
+output reg [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+
+parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
+reg [1:0] state,temp_state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1'b0;
+ prt_ack1 = 1'b0;
+ prt_ack2 = 1'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0; 
+         prt_req = 1'b0;
+         if(prt_dv1 && !prt_dv2) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+           prt_qos = qos1;
+         end else if(!prt_dv1 && prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv1 && prt_dv2) begin
+           if(qos1 > qos2) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else if(qos1 < qos2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_data = prt_data2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1; 
+         prt_ack2 = 1'b0;
+         if(prt_ack) begin 
+           prt_ack1 = 1'b1;
+           prt_req = 0;
+           if(prt_dv2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_data = prt_data2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+         //    state = wait_req;
+         state = wait_ack_low;
+           end
+         end
+       end 
+ serv_req2:begin
+         state = serv_req2; 
+         prt_ack1 = 1'b0;
+         if(prt_ack) begin 
+           prt_ack2 = 1'b1;
+           prt_req = 0;
+           if(prt_dv1) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_data = prt_data1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else begin
+         state = wait_ack_low;
+         //    state = wait_req;
+           end
+         end
+       end 
+ wait_ack_low:begin
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0;
+         state = wait_ack_low;
+         if(!prt_ack)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_rd.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 2 read requests from 2 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_rd(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+
+ prt_req1,
+ prt_req2,
+ prt_bytes1,
+ prt_bytes2,
+ prt_addr1,
+ prt_addr2,
+ prt_data1,
+ prt_data2,
+ prt_dv1,
+ prt_dv2,
+
+ prt_req,
+ prt_qos,
+ prt_addr,
+ prt_bytes,
+ prt_data,
+ prt_dv
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2;
+input prt_req1, prt_req2;
+input [addr_width-1:0] prt_addr1, prt_addr2;
+input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
+output reg prt_dv1, prt_dv2;
+output reg [max_burst_bits-1:0] prt_data1,prt_data2;
+
+output reg prt_req;
+output reg [axi_qos_width-1:0] prt_qos;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+input [max_burst_bits-1:0] prt_data;
+input prt_dv;
+
+parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
+reg [1:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1'b0;
+ prt_dv1 = 1'b0;
+ prt_dv2 = 1'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         prt_req = 0;
+         if(prt_req1 && !prt_req2) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(!prt_req1 && prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req1 && prt_req2) begin
+           if(qos1 > qos2) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else if(qos1 < qos2) begin
+             prt_req = 1;
+             prt_addr = prt_addr2;
+             prt_qos = qos2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1; 
+         prt_dv2 = 1'b0;
+         if(prt_dv) begin 
+           prt_dv1 = 1'b1;
+           prt_data1 = prt_data;
+           prt_req = 0;
+           if(prt_req2) begin
+             prt_req = 1;
+             prt_qos = qos2;
+             prt_addr = prt_addr2;
+             prt_bytes = prt_bytes2;
+             state = serv_req2;
+           end else begin
+             state = wait_dv_low;
+             //state = wait_req;
+           end
+         end
+       end 
+ serv_req2:begin
+         state = serv_req2; 
+         prt_dv1 = 1'b0;
+         if(prt_dv) begin 
+           prt_dv2 = 1'b1;
+           prt_data2 = prt_data;
+           prt_req = 0;
+           if(prt_req1) begin
+             prt_req = 1;
+             prt_qos = qos1;
+             prt_addr = prt_addr1;
+             prt_bytes = prt_bytes1;
+             state = serv_req1;
+           end else begin
+             state = wait_dv_low;
+             //state = wait_req;
+           end
+         end
+       end 
+
+ wait_dv_low:begin
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         state = wait_dv_low;
+         if(!prt_dv)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_wr_4.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 4 write requests from 4 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_wr_4(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+ qos3,
+ qos4,
+
+ prt_dv1,
+ prt_dv2,
+ prt_dv3,
+ prt_dv4,
+
+ prt_data1,
+ prt_data2,
+ prt_data3,
+ prt_data4,
+
+ prt_addr1,
+ prt_addr2,
+ prt_addr3,
+ prt_addr4,
+
+ prt_bytes1,
+ prt_bytes2,
+ prt_bytes3,
+ prt_bytes4,
+
+ prt_ack1,
+ prt_ack2,
+ prt_ack3,
+ prt_ack4,
+
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_ack
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
+input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
+input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
+input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
+output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
+output reg [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
+reg [2:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1'b0;
+ prt_ack1 = 1'b0;
+ prt_ack2 = 1'b0;
+ prt_ack3 = 1'b0;
+ prt_ack4 = 1'b0;
+ prt_qos = 0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0;
+         prt_ack3 = 1'b0;
+         prt_ack4 = 1'b0;
+         prt_req = 0;
+         if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1;
+         prt_ack2 = 1'b0;
+         prt_ack3 = 1'b0;
+         prt_ack4 = 1'b0;
+       if(prt_ack)begin 
+           prt_ack1 = 1'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv2) begin
+           state = serv_req2;
+           prt_qos = qos2;
+           prt_req = 1;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+       end
+ serv_req2:begin  
+         state = serv_req2;
+         prt_ack1 = 1'b0;
+         prt_ack3 = 1'b0;
+         prt_ack4 = 1'b0;
+       if(prt_ack)begin 
+           prt_ack2 = 1'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv3) begin
+           state = serv_req3;
+           prt_qos = qos3;
+           prt_req = 1;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_dv4) begin
+           state = serv_req4;
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_dv1) begin
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+           state = serv_req1;
+         end
+       end
+       end 
+ serv_req3:begin  
+         state = serv_req3;
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0;
+         prt_ack4 = 1'b0;
+       if(prt_ack)begin 
+           prt_ack3 = 1'b1;
+//           state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv4) begin
+           state = serv_req4;
+           prt_qos = qos4;
+           prt_req = 1;
+           prt_data = prt_data4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+           state = serv_req2;
+         end
+       end
+       end 
+ serv_req4:begin  
+         state = serv_req4;
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0;
+         prt_ack3 = 1'b0;
+       if(prt_ack)begin 
+           prt_ack4 = 1'b1;
+           //state = wait_req;
+           state = wait_ack_low;
+           prt_req = 0;
+         if(prt_dv1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_data = prt_data1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_dv2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_data = prt_data2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_dv3) begin
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_data = prt_data3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+           state = serv_req3;
+         end
+       end
+       end 
+ wait_ack_low:begin
+         state = wait_ack_low;
+         prt_ack1 = 1'b0;
+         prt_ack2 = 1'b0;
+         prt_ack3 = 1'b0;
+         prt_ack4 = 1'b0;
+         if(!prt_ack)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_rd_4.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between 4 read requests from 4 ports.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_rd_4(
+ rstn,
+ sw_clk,
+
+ qos1,
+ qos2,
+ qos3,
+ qos4,
+
+ prt_req1,
+ prt_req2,
+ prt_req3,
+ prt_req4,
+
+ prt_data1,
+ prt_data2,
+ prt_data3,
+ prt_data4,
+
+ prt_addr1,
+ prt_addr2,
+ prt_addr3,
+ prt_addr4,
+
+ prt_bytes1,
+ prt_bytes2,
+ prt_bytes3,
+ prt_bytes4,
+
+ prt_dv1,
+ prt_dv2,
+ prt_dv3,
+ prt_dv4,
+
+ prt_qos,
+ prt_req,
+ prt_data,
+ prt_addr,
+ prt_bytes,
+ prt_dv
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input rstn, sw_clk;
+input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
+input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
+output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
+input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
+input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
+output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
+input [max_burst_bits-1:0] prt_data;
+output reg [addr_width-1:0] prt_addr;
+output reg [max_burst_bytes_width:0] prt_bytes;
+output reg [axi_qos_width-1:0] prt_qos;
+
+parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
+reg [2:0] state;
+
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ state = wait_req;
+ prt_req = 1'b0;
+ prt_dv1 = 1'b0;
+ prt_dv2 = 1'b0;
+ prt_dv3 = 1'b0;
+ prt_dv4 = 1'b0;
+ prt_qos =    0;
+end else begin
+ case(state)
+ wait_req:begin  
+         state = wait_req;
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         prt_dv3 = 1'b0;
+         prt_dv4 = 1'b0;
+         prt_req = 1'b0;
+         if(prt_req1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           prt_req = 1;
+           prt_addr = prt_addr4;
+           prt_qos = qos4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+ serv_req1:begin  
+         state = serv_req1;
+         prt_dv2 = 1'b0;
+         prt_dv3 = 1'b0;
+         prt_dv4 = 1'b0;
+       if(prt_dv)begin 
+           prt_dv1 = 1'b1;
+           prt_data1 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1'b0;
+         if(prt_req2) begin
+           state = serv_req2;
+           prt_qos = qos2;
+           prt_req = 1;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           state = serv_req3;
+           prt_qos = qos3;
+           prt_req = 1;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+           state = serv_req4;
+         end
+       end 
+       end
+ serv_req2:begin  
+         state = serv_req2;
+         prt_dv1 = 1'b0;
+         prt_dv3 = 1'b0;
+         prt_dv4 = 1'b0;
+       if(prt_dv)begin 
+           prt_dv2 = 1'b1;
+           prt_data2 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1'b0;
+         if(prt_req3) begin
+           state = serv_req3;
+           prt_req = 1;
+           prt_qos = qos3;
+           prt_addr = prt_addr3;
+           prt_bytes = prt_bytes3;
+         end else if(prt_req4) begin
+           state = serv_req4;
+           prt_req = 1;
+           prt_qos = qos4;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_req1) begin
+           prt_req = 1;
+           prt_addr = prt_addr1;
+           prt_qos = qos1;
+           prt_bytes = prt_bytes1;
+           state = serv_req1;
+         end
+       end
+       end 
+ serv_req3:begin  
+         state = serv_req3;
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         prt_dv4 = 1'b0;
+       if(prt_dv)begin 
+           prt_dv3 = 1'b1;
+           prt_data3 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1'b0;
+         if(prt_req4) begin
+           state = serv_req4;
+           prt_qos = qos4;
+           prt_req = 1;
+           prt_addr = prt_addr4;
+           prt_bytes = prt_bytes4;
+         end else if(prt_req1) begin
+           state = serv_req1;
+           prt_req = 1;
+           prt_qos = qos1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+           state = serv_req2;
+         end
+       end
+       end 
+ serv_req4:begin  
+         state = serv_req4;
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         prt_dv3 = 1'b0;
+       if(prt_dv)begin 
+           prt_dv4 = 1'b1;
+           prt_data4 = prt_data;
+           //state = wait_req;
+           state = wait_dv_low;
+           prt_req = 1'b0;
+         if(prt_req1) begin
+           state = serv_req1;
+           prt_qos = qos1;
+           prt_req = 1;
+           prt_addr = prt_addr1;
+           prt_bytes = prt_bytes1;
+         end else if(prt_req2) begin
+           state = serv_req2;
+           prt_req = 1;
+           prt_qos = qos2;
+           prt_addr = prt_addr2;
+           prt_bytes = prt_bytes2;
+         end else if(prt_req3) begin
+           prt_req = 1;
+           prt_addr = prt_addr3;
+           prt_qos = qos3;
+           prt_bytes = prt_bytes3;
+           state = serv_req3;
+         end
+       end
+       end 
+ wait_dv_low:begin
+         state = wait_dv_low;
+         prt_dv1 = 1'b0;
+         prt_dv2 = 1'b0;
+         prt_dv3 = 1'b0;
+         prt_dv4 = 1'b0;
+         if(!prt_dv)
+           state = wait_req;
+       end  
+ endcase
+end /// if else
+end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_hp2_3.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between RD/WR requests from 2 ports.
+ *               Used for modelling the Top_Interconnect switch.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_hp2_3(
+ sw_clk,
+ rstn,
+ w_qos_hp2,
+ r_qos_hp2,
+ w_qos_hp3,
+ r_qos_hp3,
+
+ wr_ack_ddr_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ rd_req_ddr_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_dv_ddr_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ rd_req_ddr_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ddr_hp3,
+ rd_dv_ddr_hp3,
+
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+ ddr_rd_qos,
+ ddr_wr_qos,
+ 
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input sw_clk;
+input rstn;
+input [axi_qos_width-1:0] w_qos_hp2;
+input [axi_qos_width-1:0] r_qos_hp2;
+input [axi_qos_width-1:0] w_qos_hp3;
+input [axi_qos_width-1:0] r_qos_hp3;
+input [axi_qos_width-1:0] ddr_rd_qos;
+input [axi_qos_width-1:0] ddr_wr_qos;
+
+output wr_ack_ddr_hp2;
+input [max_burst_bits-1:0] wr_data_hp2;
+input [addr_width-1:0] wr_addr_hp2;
+input [max_burst_bytes_width:0] wr_bytes_hp2;
+output wr_dv_ddr_hp2;
+
+input rd_req_ddr_hp2;
+input [addr_width-1:0] rd_addr_hp2;
+input [max_burst_bytes_width:0] rd_bytes_hp2;
+output [max_burst_bits-1:0] rd_data_ddr_hp2;
+output rd_dv_ddr_hp2;
+ 
+output wr_ack_ddr_hp3;
+input [max_burst_bits-1:0] wr_data_hp3;
+input [addr_width-1:0] wr_addr_hp3;
+input [max_burst_bytes_width:0] wr_bytes_hp3;
+output wr_dv_ddr_hp3;
+
+input rd_req_ddr_hp3;
+input [addr_width-1:0] rd_addr_hp3;
+input [max_burst_bytes_width:0] rd_bytes_hp3;
+output [max_burst_bits-1:0] rd_data_ddr_hp3;
+output rd_dv_ddr_hp3;
+ 
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+
+
+
+processing_system7_vip_v1_0_3_arb_wr ddr_hp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_hp2),
+ .qos2(w_qos_hp3),
+ .prt_dv1(wr_dv_ddr_hp2),
+ .prt_dv2(wr_dv_ddr_hp3),
+ .prt_data1(wr_data_hp2),
+ .prt_data2(wr_data_hp3),
+ .prt_addr1(wr_addr_hp2),
+ .prt_addr2(wr_addr_hp3),
+ .prt_bytes1(wr_bytes_hp2),
+ .prt_bytes2(wr_bytes_hp3),
+ .prt_ack1(wr_ack_ddr_hp2),
+ .prt_ack2(wr_ack_ddr_hp3),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_vip_v1_0_3_arb_rd ddr_hp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_hp2),
+ .qos2(r_qos_hp3),
+ .prt_req1(rd_req_ddr_hp2),
+ .prt_req2(rd_req_ddr_hp3),
+ .prt_data1(rd_data_ddr_hp2),
+ .prt_data2(rd_data_ddr_hp3),
+ .prt_addr1(rd_addr_hp2),
+ .prt_addr2(rd_addr_hp3),
+ .prt_bytes1(rd_bytes_hp2),
+ .prt_bytes2(rd_bytes_hp3),
+ .prt_dv1(rd_dv_ddr_hp2),
+ .prt_dv2(rd_dv_ddr_hp3),
+ .prt_req(ddr_rd_req),
+ .prt_qos(ddr_rd_qos),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_arb_hp0_1.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that arbitrates between RD/WR requests from 2 ports.
+ *               Used for modelling the Top_Interconnect switch.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_arb_hp0_1(
+ sw_clk,
+ rstn,
+ w_qos_hp0,
+ r_qos_hp0,
+ w_qos_hp1,
+ r_qos_hp1,
+
+ wr_ack_ddr_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ rd_req_ddr_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_dv_ddr_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ rd_req_ddr_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_dv_ddr_hp1,
+
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+ ddr_rd_qos,
+ ddr_wr_qos,
+ 
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input sw_clk;
+input rstn;
+input [axi_qos_width-1:0] w_qos_hp0;
+input [axi_qos_width-1:0] r_qos_hp0;
+input [axi_qos_width-1:0] w_qos_hp1;
+input [axi_qos_width-1:0] r_qos_hp1;
+input [axi_qos_width-1:0] ddr_rd_qos;
+input [axi_qos_width-1:0] ddr_wr_qos;
+
+output wr_ack_ddr_hp0;
+input [max_burst_bits-1:0] wr_data_hp0;
+input [addr_width-1:0] wr_addr_hp0;
+input [max_burst_bytes_width:0] wr_bytes_hp0;
+output wr_dv_ddr_hp0;
+
+input rd_req_ddr_hp0;
+input [addr_width-1:0] rd_addr_hp0;
+input [max_burst_bytes_width:0] rd_bytes_hp0;
+output [max_burst_bits-1:0] rd_data_ddr_hp0;
+output rd_dv_ddr_hp0;
+ 
+output wr_ack_ddr_hp1;
+input [max_burst_bits-1:0] wr_data_hp1;
+input [addr_width-1:0] wr_addr_hp1;
+input [max_burst_bytes_width:0] wr_bytes_hp1;
+output wr_dv_ddr_hp1;
+
+input rd_req_ddr_hp1;
+input [addr_width-1:0] rd_addr_hp1;
+input [max_burst_bytes_width:0] rd_bytes_hp1;
+output [max_burst_bits-1:0] rd_data_ddr_hp1;
+output rd_dv_ddr_hp1;
+ 
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+
+
+
+processing_system7_vip_v1_0_3_arb_wr ddr_hp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_hp0),
+ .qos2(w_qos_hp1),
+ .prt_dv1(wr_dv_ddr_hp0),
+ .prt_dv2(wr_dv_ddr_hp1),
+ .prt_data1(wr_data_hp0),
+ .prt_data2(wr_data_hp1),
+ .prt_addr1(wr_addr_hp0),
+ .prt_addr2(wr_addr_hp1),
+ .prt_bytes1(wr_bytes_hp0),
+ .prt_bytes2(wr_bytes_hp1),
+ .prt_ack1(wr_ack_ddr_hp0),
+ .prt_ack2(wr_ack_ddr_hp1),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_vip_v1_0_3_arb_rd ddr_hp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_hp0),
+ .qos2(r_qos_hp1),
+ .prt_req1(rd_req_ddr_hp0),
+ .prt_req2(rd_req_ddr_hp1),
+ .prt_data1(rd_data_ddr_hp0),
+ .prt_data2(rd_data_ddr_hp1),
+ .prt_addr1(rd_addr_hp0),
+ .prt_addr2(rd_addr_hp1),
+ .prt_bytes1(rd_bytes_hp0),
+ .prt_bytes2(rd_bytes_hp1),
+ .prt_dv1(rd_dv_ddr_hp0),
+ .prt_dv2(rd_dv_ddr_hp1),
+ .prt_qos(ddr_rd_qos),
+ .prt_req(ddr_rd_req),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_ssw_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : SSW switch Model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_ssw_hp(
+ sw_clk,
+ rstn,
+ w_qos_hp0,
+ r_qos_hp0,
+ w_qos_hp1,
+ r_qos_hp1,
+ w_qos_hp2,
+ r_qos_hp2,
+ w_qos_hp3,
+ r_qos_hp3,
+
+ wr_ack_ddr_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ rd_req_ddr_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_dv_ddr_hp0,
+
+ rd_data_ocm_hp0,
+ wr_ack_ocm_hp0,
+ wr_dv_ocm_hp0,
+ rd_req_ocm_hp0,
+ rd_dv_ocm_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ rd_req_ddr_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_data_ocm_hp1,
+ rd_dv_ddr_hp1,
+
+ wr_ack_ocm_hp1,
+ wr_dv_ocm_hp1,
+ rd_req_ocm_hp1,
+ rd_dv_ocm_hp1,
+
+ wr_ack_ddr_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ rd_req_ddr_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_data_ocm_hp2,
+ rd_dv_ddr_hp2,
+
+ wr_ack_ocm_hp2,
+ wr_dv_ocm_hp2,
+ rd_req_ocm_hp2,
+ rd_dv_ocm_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ rd_req_ddr_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ocm_hp3,
+ rd_data_ddr_hp3,
+ rd_dv_ddr_hp3,
+
+ wr_ack_ocm_hp3,
+ wr_dv_ocm_hp3,
+ rd_req_ocm_hp3,
+ rd_dv_ocm_hp3,
+
+ ddr_wr_ack0,
+ ddr_wr_dv0,
+ ddr_rd_req0,
+ ddr_rd_dv0,
+ ddr_rd_qos0,
+ ddr_wr_qos0,
+
+ ddr_wr_addr0,
+ ddr_wr_data0,
+ ddr_wr_bytes0,
+ ddr_rd_addr0,
+ ddr_rd_data0,
+ ddr_rd_bytes0,
+
+ ddr_wr_ack1,
+ ddr_wr_dv1,
+ ddr_rd_req1,
+ ddr_rd_dv1,
+ ddr_rd_qos1,
+ ddr_wr_qos1,
+ ddr_wr_addr1,
+ ddr_wr_data1,
+ ddr_wr_bytes1,
+ ddr_rd_addr1,
+ ddr_rd_data1,
+ ddr_rd_bytes1,
+
+ ocm_wr_ack,
+ ocm_wr_dv,
+ ocm_rd_req,
+ ocm_rd_dv,
+
+ ocm_wr_qos,
+ ocm_rd_qos, 
+ ocm_wr_addr,
+ ocm_wr_data,
+ ocm_wr_bytes,
+ ocm_rd_addr,
+ ocm_rd_data,
+ ocm_rd_bytes
+ 
+
+
+);
+
+input sw_clk;
+input rstn;
+input [3:0] w_qos_hp0;
+input [3:0] r_qos_hp0;
+input [3:0] w_qos_hp1;
+input [3:0] r_qos_hp1;
+input [3:0] w_qos_hp2;
+input [3:0] r_qos_hp2;
+input [3:0] w_qos_hp3;
+input [3:0] r_qos_hp3;
+
+output [3:0] ddr_rd_qos0;
+output [3:0] ddr_wr_qos0;
+output [3:0] ddr_rd_qos1;
+output [3:0] ddr_wr_qos1;
+output [3:0] ocm_wr_qos;
+output [3:0] ocm_rd_qos; 
+
+output wr_ack_ddr_hp0;
+input [1023:0] wr_data_hp0;
+input [31:0] wr_addr_hp0;
+input [7:0] wr_bytes_hp0;
+output wr_dv_ddr_hp0;
+
+input rd_req_ddr_hp0;
+input [31:0] rd_addr_hp0;
+input [7:0] rd_bytes_hp0;
+output [1023:0] rd_data_ddr_hp0;
+output rd_dv_ddr_hp0;
+ 
+output wr_ack_ddr_hp1;
+input [1023:0] wr_data_hp1;
+input [31:0] wr_addr_hp1;
+input [7:0] wr_bytes_hp1;
+output wr_dv_ddr_hp1;
+
+input rd_req_ddr_hp1;
+input [31:0] rd_addr_hp1;
+input [7:0] rd_bytes_hp1;
+output [1023:0] rd_data_ddr_hp1;
+output rd_dv_ddr_hp1;
+
+output wr_ack_ddr_hp2;
+input [1023:0] wr_data_hp2;
+input [31:0] wr_addr_hp2;
+input [7:0] wr_bytes_hp2;
+output wr_dv_ddr_hp2;
+
+input rd_req_ddr_hp2;
+input [31:0] rd_addr_hp2;
+input [7:0] rd_bytes_hp2;
+output [1023:0] rd_data_ddr_hp2;
+output rd_dv_ddr_hp2;
+ 
+output wr_ack_ddr_hp3;
+input [1023:0] wr_data_hp3;
+input [31:0] wr_addr_hp3;
+input [7:0] wr_bytes_hp3;
+output wr_dv_ddr_hp3;
+
+input rd_req_ddr_hp3;
+input [31:0] rd_addr_hp3;
+input [7:0] rd_bytes_hp3;
+output [1023:0] rd_data_ddr_hp3;
+output rd_dv_ddr_hp3;
+
+input ddr_wr_ack0;
+output ddr_wr_dv0;
+output [31:0]ddr_wr_addr0;
+output [1023:0]ddr_wr_data0;
+output [7:0]ddr_wr_bytes0;
+
+input ddr_rd_dv0;
+input [1023:0] ddr_rd_data0;
+output ddr_rd_req0;
+output [31:0] ddr_rd_addr0;
+output [7:0] ddr_rd_bytes0;
+
+input ddr_wr_ack1;
+output ddr_wr_dv1;
+output [31:0]ddr_wr_addr1;
+output [1023:0]ddr_wr_data1;
+output [7:0]ddr_wr_bytes1;
+
+input ddr_rd_dv1;
+input [1023:0] ddr_rd_data1;
+output ddr_rd_req1;
+output [31:0] ddr_rd_addr1;
+output [7:0] ddr_rd_bytes1;
+
+output wr_ack_ocm_hp0;
+input wr_dv_ocm_hp0;
+input rd_req_ocm_hp0;
+output rd_dv_ocm_hp0;
+output [1023:0] rd_data_ocm_hp0;
+
+output wr_ack_ocm_hp1;
+input wr_dv_ocm_hp1;
+input rd_req_ocm_hp1;
+output rd_dv_ocm_hp1;
+output [1023:0] rd_data_ocm_hp1;
+
+output wr_ack_ocm_hp2;
+input wr_dv_ocm_hp2;
+input rd_req_ocm_hp2;
+output rd_dv_ocm_hp2;
+output [1023:0] rd_data_ocm_hp2;
+
+output wr_ack_ocm_hp3;
+input wr_dv_ocm_hp3;
+input rd_req_ocm_hp3;
+output rd_dv_ocm_hp3;
+output [1023:0] rd_data_ocm_hp3;
+
+input ocm_wr_ack;
+output ocm_wr_dv;
+output [31:0]ocm_wr_addr;
+output [1023:0]ocm_wr_data;
+output [7:0]ocm_wr_bytes;
+
+input ocm_rd_dv;
+input [1023:0] ocm_rd_data;
+output ocm_rd_req;
+output [31:0] ocm_rd_addr;
+output [7:0] ocm_rd_bytes;
+
+/* FOR DDR */
+processing_system7_vip_v1_0_3_arb_hp0_1 ddr_hp01 (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp0(w_qos_hp0),
+ .r_qos_hp0(r_qos_hp0),
+ .w_qos_hp1(w_qos_hp1),
+ .r_qos_hp1(r_qos_hp1),
+   
+ .wr_ack_ddr_hp0(wr_ack_ddr_hp0),
+ .wr_data_hp0(wr_data_hp0),
+ .wr_addr_hp0(wr_addr_hp0),
+ .wr_bytes_hp0(wr_bytes_hp0),
+ .wr_dv_ddr_hp0(wr_dv_ddr_hp0),
+ .rd_req_ddr_hp0(rd_req_ddr_hp0),
+ .rd_addr_hp0(rd_addr_hp0),
+ .rd_bytes_hp0(rd_bytes_hp0),
+ .rd_data_ddr_hp0(rd_data_ddr_hp0),
+ .rd_dv_ddr_hp0(rd_dv_ddr_hp0),
+   
+ .wr_ack_ddr_hp1(wr_ack_ddr_hp1),
+ .wr_data_hp1(wr_data_hp1),
+ .wr_addr_hp1(wr_addr_hp1),
+ .wr_bytes_hp1(wr_bytes_hp1),
+ .wr_dv_ddr_hp1(wr_dv_ddr_hp1),
+ .rd_req_ddr_hp1(rd_req_ddr_hp1),
+ .rd_addr_hp1(rd_addr_hp1),
+ .rd_bytes_hp1(rd_bytes_hp1),
+ .rd_data_ddr_hp1(rd_data_ddr_hp1),
+ .rd_dv_ddr_hp1(rd_dv_ddr_hp1),
+   
+ .ddr_wr_ack(ddr_wr_ack0),
+ .ddr_wr_dv(ddr_wr_dv0),
+ .ddr_rd_req(ddr_rd_req0),
+ .ddr_rd_dv(ddr_rd_dv0),
+ .ddr_rd_qos(ddr_rd_qos0),
+ .ddr_wr_qos(ddr_wr_qos0), 
+ .ddr_wr_addr(ddr_wr_addr0),
+ .ddr_wr_data(ddr_wr_data0),
+ .ddr_wr_bytes(ddr_wr_bytes0),
+ .ddr_rd_addr(ddr_rd_addr0),
+ .ddr_rd_data(ddr_rd_data0),
+ .ddr_rd_bytes(ddr_rd_bytes0)
+);
+
+/* FOR DDR */
+processing_system7_vip_v1_0_3_arb_hp2_3 ddr_hp23 (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp2(w_qos_hp2),
+ .r_qos_hp2(r_qos_hp2),
+ .w_qos_hp3(w_qos_hp3),
+ .r_qos_hp3(r_qos_hp3),
+   
+ .wr_ack_ddr_hp2(wr_ack_ddr_hp2),
+ .wr_data_hp2(wr_data_hp2),
+ .wr_addr_hp2(wr_addr_hp2),
+ .wr_bytes_hp2(wr_bytes_hp2),
+ .wr_dv_ddr_hp2(wr_dv_ddr_hp2),
+ .rd_req_ddr_hp2(rd_req_ddr_hp2),
+ .rd_addr_hp2(rd_addr_hp2),
+ .rd_bytes_hp2(rd_bytes_hp2),
+ .rd_data_ddr_hp2(rd_data_ddr_hp2),
+ .rd_dv_ddr_hp2(rd_dv_ddr_hp2),
+   
+ .wr_ack_ddr_hp3(wr_ack_ddr_hp3),
+ .wr_data_hp3(wr_data_hp3),
+ .wr_addr_hp3(wr_addr_hp3),
+ .wr_bytes_hp3(wr_bytes_hp3),
+ .wr_dv_ddr_hp3(wr_dv_ddr_hp3),
+ .rd_req_ddr_hp3(rd_req_ddr_hp3),
+ .rd_addr_hp3(rd_addr_hp3),
+ .rd_bytes_hp3(rd_bytes_hp3),
+ .rd_data_ddr_hp3(rd_data_ddr_hp3),
+ .rd_dv_ddr_hp3(rd_dv_ddr_hp3),
+   
+ .ddr_wr_ack(ddr_wr_ack1),
+ .ddr_wr_dv(ddr_wr_dv1),
+ .ddr_rd_req(ddr_rd_req1),
+ .ddr_rd_dv(ddr_rd_dv1),
+ .ddr_rd_qos(ddr_rd_qos1),
+ .ddr_wr_qos(ddr_wr_qos1), 
+
+ .ddr_wr_addr(ddr_wr_addr1),
+ .ddr_wr_data(ddr_wr_data1),
+ .ddr_wr_bytes(ddr_wr_bytes1),
+ .ddr_rd_addr(ddr_rd_addr1),
+ .ddr_rd_data(ddr_rd_data1),
+ .ddr_rd_bytes(ddr_rd_bytes1)
+);
+
+
+/* FOR OCM_WR */
+processing_system7_vip_v1_0_3_arb_wr_4 ocm_wr_hp(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(w_qos_hp0),
+ .qos2(w_qos_hp1),
+ .qos3(w_qos_hp2),
+ .qos4(w_qos_hp3),
+   
+ .prt_dv1(wr_dv_ocm_hp0),
+ .prt_dv2(wr_dv_ocm_hp1),
+ .prt_dv3(wr_dv_ocm_hp2),
+ .prt_dv4(wr_dv_ocm_hp3),
+   
+ .prt_data1(wr_data_hp0),
+ .prt_data2(wr_data_hp1),
+ .prt_data3(wr_data_hp2),
+ .prt_data4(wr_data_hp3),
+   
+ .prt_addr1(wr_addr_hp0),
+ .prt_addr2(wr_addr_hp1),
+ .prt_addr3(wr_addr_hp2),
+ .prt_addr4(wr_addr_hp3),
+   
+ .prt_bytes1(wr_bytes_hp0),
+ .prt_bytes2(wr_bytes_hp1),
+ .prt_bytes3(wr_bytes_hp2),
+ .prt_bytes4(wr_bytes_hp3),
+   
+ .prt_ack1(wr_ack_ocm_hp0),
+ .prt_ack2(wr_ack_ocm_hp1),
+ .prt_ack3(wr_ack_ocm_hp2),
+ .prt_ack4(wr_ack_ocm_hp3),
+   
+ .prt_qos(ocm_wr_qos),
+ .prt_req(ocm_wr_dv),
+ .prt_data(ocm_wr_data),
+ .prt_addr(ocm_wr_addr),
+ .prt_bytes(ocm_wr_bytes),
+ .prt_ack(ocm_wr_ack)
+
+);
+
+/* FOR OCM_RD */
+processing_system7_vip_v1_0_3_arb_rd_4 ocm_rd_hp(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(r_qos_hp0),
+ .qos2(r_qos_hp1),
+ .qos3(r_qos_hp2),
+ .qos4(r_qos_hp3),
+   
+ .prt_req1(rd_req_ocm_hp0),
+ .prt_req2(rd_req_ocm_hp1),
+ .prt_req3(rd_req_ocm_hp2),
+ .prt_req4(rd_req_ocm_hp3),
+   
+ .prt_data1(rd_data_ocm_hp0),
+ .prt_data2(rd_data_ocm_hp1),
+ .prt_data3(rd_data_ocm_hp2),
+ .prt_data4(rd_data_ocm_hp3),
+   
+ .prt_addr1(rd_addr_hp0),
+ .prt_addr2(rd_addr_hp1),
+ .prt_addr3(rd_addr_hp2),
+ .prt_addr4(rd_addr_hp3),
+   
+ .prt_bytes1(rd_bytes_hp0),
+ .prt_bytes2(rd_bytes_hp1),
+ .prt_bytes3(rd_bytes_hp2),
+ .prt_bytes4(rd_bytes_hp3),
+   
+ .prt_dv1(rd_dv_ocm_hp0),
+ .prt_dv2(rd_dv_ocm_hp1),
+ .prt_dv3(rd_dv_ocm_hp2),
+ .prt_dv4(rd_dv_ocm_hp3),
+   
+ .prt_qos(ocm_rd_qos),
+ .prt_req(ocm_rd_req),
+ .prt_data(ocm_rd_data),
+ .prt_addr(ocm_rd_addr),
+ .prt_bytes(ocm_rd_bytes),
+ .prt_dv(ocm_rd_dv)
+
+);
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_sparse_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Sparse Memory Model
+ *
+ *****************************************************************************/
+
+/*** WA for CR # 695818 ***/
+`ifdef XILINX_SIMULATOR
+   `define XSIM_ISIM
+`endif
+`ifdef XILINX_ISIM
+   `define XSIM_ISIM
+`endif
+
+ `timescale 1ns/1ps
+module processing_system7_vip_v1_0_3_sparse_mem();
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+parameter mem_size = 32'h4000_0000; /// 1GB mem size
+parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
+
+
+`ifdef XSIM_ISIM
+ reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+`else
+ reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
+`endif
+
+event mem_updated;
+reg check_we;
+reg [addr_width-1:0] check_up_add;
+reg [data_width-1:0] updated_data;
+
+/* preload memory from file */
+task automatic pre_load_mem_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+`ifdef XSIM_ISIM
+  case(start_addr[31:28])
+    4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
+    4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
+    4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
+    4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
+  endcase
+`else
+  $readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
+`endif
+endtask
+
+/* preload memory with some random data */
+task automatic pre_load_mem;
+input [1:0]  data_type;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+begin
+addr = start_addr >> shft_addr_bits;
+for (i = 0; i < no_of_bytes; i = i + mem_width) begin
+   case(data_type)
+     ALL_RANDOM : set_data(addr , $random);
+     ALL_ZEROS  : set_data(addr , 32'h0000_0000);
+     ALL_ONES   : set_data(addr , 32'hFFFF_FFFF);
+     default    : set_data(addr , $random);
+   endcase
+   addr = addr+1;
+end 
+end
+endtask
+
+/* wait for memory update at certain location */
+task automatic wait_mem_update;
+input[addr_width-1:0] address;
+output[data_width-1:0] dataout;
+begin
+  check_up_add = address >> shft_addr_bits;
+  check_we = 1;
+  @(mem_updated); 
+  dataout = updated_data;
+  check_we = 0;
+end
+endtask
+
+/* internal task to write data in memory */
+task automatic set_data;
+input [addr_width-1:0] addr;
+input [data_width-1:0] data;
+begin
+if(check_we && (addr === check_up_add)) begin
+ updated_data = data;
+ -> mem_updated;
+end
+`ifdef XSIM_ISIM
+  case(addr[31:26])
+    6'd0 : ddr_mem0[addr[25:0]] = data;
+    6'd1 : ddr_mem1[addr[25:0]] = data;
+    6'd2 : ddr_mem2[addr[25:0]] = data;
+    6'd3 : ddr_mem3[addr[25:0]] = data;
+  endcase
+`else
+  ddr_mem[addr] = data;
+`endif
+end
+endtask
+
+/* internal task to read data from memory */
+task automatic get_data;
+input [addr_width-1:0] addr;
+output [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[31:26])
+    6'd0 : data = ddr_mem0[addr[25:0]];
+    6'd1 : data = ddr_mem1[addr[25:0]];
+    6'd2 : data = ddr_mem2[addr[25:0]];
+    6'd3 : data = ddr_mem3[addr[25:0]];
+  endcase
+`else
+  data = ddr_mem[addr];
+`endif
+end
+endtask
+
+/* Write memory */
+task write_mem;
+input [max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+reg [addr_width-1:0] addr;
+reg [max_burst_bits-1 :0] wr_temp_data;
+reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
+integer bytes_left;
+integer pre_pad_bytes;
+integer post_pad_bytes;
+begin
+addr = start_addr >> shft_addr_bits;
+wr_temp_data = data;
+
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); 
+`endif
+
+temp_data = wr_temp_data[data_width-1:0];
+bytes_left = no_of_bytes;
+/* when the no. of bytes to be updated is less than mem_width */
+if(bytes_left < mem_width) begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+   //temp_data     = ddr_mem[addr];
+   get_data(addr,temp_data);
+   pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+   repeat(pre_pad_bytes) temp_data = temp_data << 8;
+   repeat(pre_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+     wr_temp_data = wr_temp_data >> 8;
+   end
+   bytes_left = bytes_left + pre_pad_bytes;
+ end
+ /* This is needed for post padding the data ...*/
+ post_pad_bytes = mem_width - bytes_left;
+ //post_pad_data  = ddr_mem[addr];
+ get_data(addr,post_pad_data);
+ repeat(post_pad_bytes) temp_data = temp_data << 8;
+ repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+ repeat(post_pad_bytes) begin
+   temp_data = temp_data >> 8;
+   temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+   post_pad_data = post_pad_data >> 8; 
+ end
+ //ddr_mem[addr] = temp_data;
+ set_data(addr,temp_data);
+end else begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+  //temp_data     = ddr_mem[addr];
+  get_data(addr,temp_data);
+  pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+  repeat(pre_pad_bytes) temp_data = temp_data << 8;
+  repeat(pre_pad_bytes) begin
+    temp_data = temp_data >> 8;
+    temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+    wr_temp_data = wr_temp_data >> 8;
+    bytes_left = bytes_left -1;  
+  end
+ end else begin
+  wr_temp_data = wr_temp_data >> data_width;  
+  bytes_left = bytes_left - mem_width;
+ end
+ /* first data word end */
+ //ddr_mem[addr] = temp_data;
+ set_data(addr,temp_data);
+ addr = addr + 1;
+ while(bytes_left > (mem_width-1) ) begin  /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
+  //ddr_mem[addr] = wr_temp_data[data_width-1:0];
+  set_data(addr,wr_temp_data[data_width-1:0]);
+  addr = addr+1;
+  wr_temp_data = wr_temp_data >> data_width;
+  bytes_left = bytes_left - mem_width;
+ end
+ 
+ //post_pad_data   = ddr_mem[addr];
+ get_data(addr,post_pad_data);
+ post_pad_bytes  = mem_width - bytes_left;
+ /* This is needed for last transfer in unaliged burst */
+ if(bytes_left > 0) begin
+   temp_data = wr_temp_data[data_width-1:0];
+   repeat(post_pad_bytes) temp_data = temp_data << 8;
+   repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+   repeat(post_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+     post_pad_data = post_pad_data >> 8; 
+   end
+   //ddr_mem[addr] = temp_data;
+   set_data(addr,temp_data);
+ end
+end
+`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); 
+`endif
+end
+endtask
+
+/* read_memory */
+task read_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width :0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer pre_bytes;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+pre_bytes  = start_addr[shft_addr_bits-1:0];
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
+get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+
+if(no_of_bytes < mem_width ) begin
+  temp_data = temp_data >> (pre_bytes * 8);
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - (mem_width - pre_bytes);
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   //temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
+   get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  //temp_rd_data = ddr_mem[addr];
+  get_data(addr,temp_rd_data);
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+/* backdoor read to memory */
+task peek_mem_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+
+integer rd_fd;
+integer bytes;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] rd_data;
+begin
+rd_fd = $fopen(file_name,"w");
+bytes = no_of_bytes;
+
+addr = start_addr >> shft_addr_bits;
+while (bytes > 0) begin
+  get_data(addr,rd_data);
+  $fdisplayh(rd_fd,rd_data);
+  bytes = bytes - 4;
+  addr = addr + 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_reg_map.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for Register Map Memory
+ *
+ *****************************************************************************/
+/*** WA for CR # 695818 ***/
+`ifdef XILINX_SIMULATOR
+   `define XSIM_ISIM
+`endif
+`ifdef XILINX_ISIM
+   `define XSIM_ISIM
+`endif
+
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_reg_map();
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+/* Register definitions */
+`include "processing_system7_vip_v1_0_3_reg_params.v"
+
+parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
+parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB 
+
+`ifdef XSIM_ISIM
+ reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
+ parameter addr_offset_bits = 26;
+`else
+ reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; //  512 MB needed for reg space
+ parameter addr_offset_bits = 27;
+`endif
+
+/* preload reset_values from file */
+task automatic pre_load_rst_values;
+input dummy;
+begin
+ `include "processing_system7_vip_v1_0_3_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
+end
+endtask
+
+/* writes the reset data into the reg memory */
+task automatic set_reset_data;
+input [addr_width-1:0] address;
+input [data_width-1:0] data;
+reg   [addr_width-1:0] addr;
+begin
+addr = address >> 2; 
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
+    15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
+  endcase
+`else
+  reg_mem[addr[addr_offset_bits-1:0]] = data;
+`endif
+end
+endtask
+
+/* writes the data into the reg memory */
+task automatic set_data;
+input [addr_width-1:0] addr;
+input [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
+    6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
+  endcase
+`else
+  reg_mem[addr[addr_offset_bits-1:0]] = data;
+`endif
+end
+endtask
+
+/* get the read data from reg mem */
+task automatic get_data;
+input [addr_width-1:0] addr;
+output [data_width-1:0] data;
+begin
+`ifdef XSIM_ISIM
+  case(addr[addr_width-1:addr_offset_bits])
+    6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
+    6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
+  endcase
+`else
+  data = reg_mem[addr[addr_offset_bits-1:0]];
+`endif
+end
+endtask
+
+/* read chunk of registers */
+task read_reg_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+integer i;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
+
+if(no_of_bytes < mem_width ) begin
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - mem_width;
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  get_data(addr,temp_rd_data);
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+initial 
+begin
+ pre_load_rst_values(1);
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_ocm_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics OCM model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_ocm_mem();
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+parameter mem_size = 32'h4_0000; /// 256 KB 
+parameter mem_addr_width = clogb2(mem_size/mem_width);
+
+reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory 
+
+/* preload memory from file */
+task automatic pre_load_mem_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+ $readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
+endtask
+
+/* preload memory with some random data */
+task automatic pre_load_mem;
+input [1:0]  data_type;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+integer i;
+reg [mem_addr_width-1:0] addr;
+begin
+addr = start_addr >> shft_addr_bits;
+
+for (i = 0; i < no_of_bytes; i = i + mem_width) begin
+   case(data_type)
+     ALL_RANDOM : ocm_memory[addr] = $random;
+     ALL_ZEROS  : ocm_memory[addr] = 32'h0000_0000;
+     ALL_ONES   : ocm_memory[addr] = 32'hFFFF_FFFF;
+     default    : ocm_memory[addr] = $random;
+   endcase
+   addr = addr+1;
+end 
+end
+endtask
+
+/* Write memory */
+task write_mem;
+input [max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+reg [mem_addr_width-1:0] addr;
+reg [max_burst_bits-1 :0] wr_temp_data;
+reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
+integer bytes_left;
+integer pre_pad_bytes;
+integer post_pad_bytes;
+begin
+addr = start_addr >> shft_addr_bits;
+wr_temp_data = data;
+
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data); 
+`endif
+
+temp_data = wr_temp_data[data_width-1:0];
+bytes_left = no_of_bytes;
+/* when the no. of bytes to be updated is less than mem_width */
+if(bytes_left < mem_width) begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+   temp_data     = ocm_memory[addr];
+   pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+   repeat(pre_pad_bytes) temp_data = temp_data << 8;
+   repeat(pre_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+     wr_temp_data = wr_temp_data >> 8;
+   end
+   bytes_left = bytes_left + pre_pad_bytes;
+ end
+ /* This is needed for post padding the data ...*/
+ post_pad_bytes = mem_width - bytes_left;
+ post_pad_data  = ocm_memory[addr];
+ repeat(post_pad_bytes) temp_data = temp_data << 8;
+ repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+ repeat(post_pad_bytes) begin
+   temp_data = temp_data >> 8;
+   temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+   post_pad_data = post_pad_data >> 8; 
+ end
+ ocm_memory[addr] = temp_data;
+end else begin
+ /* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
+ if(start_addr[shft_addr_bits-1:0] > 0) begin
+  temp_data     = ocm_memory[addr];
+  pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
+  repeat(pre_pad_bytes) temp_data = temp_data << 8;
+  repeat(pre_pad_bytes) begin
+    temp_data = temp_data >> 8;
+    temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
+    wr_temp_data = wr_temp_data >> 8;
+    bytes_left = bytes_left -1;  
+  end
+ end else begin
+  wr_temp_data = wr_temp_data >> data_width;  
+  bytes_left = bytes_left - mem_width;
+ end
+ /* first data word end */
+ ocm_memory[addr] = temp_data;
+ addr = addr + 1;
+ while(bytes_left > (mem_width-1) ) begin  /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
+  ocm_memory[addr] = wr_temp_data[data_width-1:0];
+  addr = addr+1;
+  wr_temp_data = wr_temp_data >> data_width;
+  bytes_left = bytes_left - mem_width;
+ end
+ 
+ post_pad_data   = ocm_memory[addr];
+ post_pad_bytes  = mem_width - bytes_left;
+ /* This is needed for last transfer in unaliged burst */
+ if(bytes_left > 0) begin
+   temp_data = wr_temp_data[data_width-1:0];
+   repeat(post_pad_bytes) temp_data = temp_data << 8;
+   repeat(bytes_left) post_pad_data = post_pad_data >> 8;
+   repeat(post_pad_bytes) begin
+     temp_data = temp_data >> 8;
+     temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
+     post_pad_data = post_pad_data >> 8; 
+   end
+   ocm_memory[addr] = temp_data;
+ end
+end
+`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr ); 
+`endif
+end
+endtask
+
+/* read_memory */
+task read_mem;
+output[max_burst_bits-1 :0] data;
+input [addr_width-1:0] start_addr;
+input [max_burst_bytes_width:0] no_of_bytes;
+integer i;
+reg [mem_addr_width-1:0] addr;
+reg [data_width-1:0] temp_rd_data;
+reg [max_burst_bits-1:0] temp_data;
+integer pre_bytes;
+integer bytes_left;
+begin
+addr = start_addr >> shft_addr_bits;
+pre_bytes  = start_addr[shft_addr_bits-1:0];
+bytes_left = no_of_bytes;
+
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes ); 
+`endif 
+
+/* Get first data ... if unaligned address */
+temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
+
+if(no_of_bytes < mem_width ) begin
+  temp_data = temp_data >> (pre_bytes * 8);
+  repeat(max_burst_bytes - mem_width)
+   temp_data = temp_data >> 8;
+
+end else begin
+  bytes_left = bytes_left - (mem_width - pre_bytes);
+  addr  = addr+1;
+  /* Got first data */
+  while (bytes_left > (mem_width-1) ) begin
+   temp_data = temp_data >> data_width;
+   temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
+   addr = addr+1;
+   bytes_left = bytes_left - mem_width;
+  end 
+
+  /* Get last valid data in the burst*/
+  temp_rd_data = ocm_memory[addr];
+  while(bytes_left > 0) begin
+    temp_data = temp_data >> 8;
+    temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
+    temp_rd_data = temp_rd_data >> 8;
+    bytes_left = bytes_left - 1;
+  end
+  /* align to the brst_byte length */
+  repeat(max_burst_bytes - no_of_bytes)
+    temp_data = temp_data >> 8;
+end 
+data = temp_data;
+`ifdef XLNX_INT_DBG
+   $display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data ); 
+`endif 
+end
+endtask
+
+/* backdoor read to memory */
+task peek_mem_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] no_of_bytes;
+
+integer rd_fd;
+integer bytes;
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] rd_data;
+begin
+rd_fd = $fopen(file_name,"w");
+bytes = no_of_bytes;
+
+addr = start_addr >> shft_addr_bits;
+while (bytes > 0) begin
+  rd_data = ocm_memory[addr];
+  $fdisplayh(rd_fd,rd_data);
+  bytes = bytes - 4;
+  addr = addr + 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_intr_wr_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics interconnect for Writes between AFI and DDRC/OCM
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_intr_wr_mem(
+sw_clk,
+rstn,
+ 
+full,
+
+WR_DATA_ACK_OCM,
+WR_DATA_ACK_DDR,
+WR_ADDR,
+WR_DATA,
+WR_BYTES,
+WR_QOS,
+WR_DATA_VALID_OCM,
+WR_DATA_VALID_DDR
+);
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+/* local parameters for interconnect wr fifo model */
+
+input sw_clk, rstn;
+output full; 
+
+input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+output reg [max_burst_bits-1:0] WR_DATA;
+output reg [addr_width-1:0] WR_ADDR;
+output reg [max_burst_bytes_width:0] WR_BYTES;
+output reg [axi_qos_width-1:0] WR_QOS;
+reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
+reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
+wire empty;
+
+assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
+assign full  = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
+
+parameter SEND_DATA = 0,  WAIT_ACK = 1;
+reg state;
+
+task automatic write_mem;
+input [wr_fifo_data_bits-1:0] data;
+begin
+ wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
+ if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+   wr_ptr[intr_cnt_width-2:0] = 0;
+ else 
+   wr_ptr = wr_ptr + 1;
+end
+endtask
+
+always@(negedge rstn or posedge sw_clk)
+begin
+if(!rstn) begin
+ wr_ptr = 0;
+ rd_ptr = 0;
+ WR_DATA_VALID_DDR = 1'b0;
+ WR_DATA_VALID_OCM = 1'b0;
+ WR_QOS = 0;
+ state = SEND_DATA;
+end else begin
+ case(state)
+ SEND_DATA :begin
+    state = SEND_DATA;
+    WR_DATA_VALID_OCM = 1'b0;
+    WR_DATA_VALID_DDR = 1'b0;
+    if(!empty) begin
+      WR_DATA  = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
+      WR_ADDR  = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
+      WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
+      WR_QOS   = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
+      state  = WAIT_ACK;
+      case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
+       OCM_MEM : WR_DATA_VALID_OCM = 1;
+       DDR_MEM : WR_DATA_VALID_DDR = 1;
+       default : state = SEND_DATA;
+      endcase 
+      if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin
+	    rd_ptr[intr_cnt_width-2:0] = 0;
+	   end else begin
+        rd_ptr = rd_ptr+1;
+	   end
+    end
+    end
+ WAIT_ACK :begin
+    state = WAIT_ACK;
+    if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin 
+      WR_DATA_VALID_OCM = 1'b0;
+      WR_DATA_VALID_DDR = 1'b0;
+      state = SEND_DATA;
+    end
+    end
+ endcase
+end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_intr_rd_mem.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics interconnect for Reads between AFI and DDRC/OCM
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_intr_rd_mem(
+sw_clk,
+rstn,
+ 
+full,
+empty,
+
+req,
+invalid_rd_req,
+rd_info,
+
+RD_DATA_OCM,
+RD_DATA_DDR,
+RD_DATA_VALID_OCM,
+RD_DATA_VALID_DDR
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+input sw_clk, rstn;
+output full, empty;
+
+input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
+input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
+input req, invalid_rd_req;
+input [rd_info_bits-1:0] rd_info;
+
+reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
+reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
+wire full, empty;
+
+
+assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
+assign full  = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
+
+/* read from the fifo */
+task read_mem;
+output [rd_afi_fifo_bits-1:0] data;
+begin
+ data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
+ if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+   rd_ptr[intr_cnt_width-2:0] = 0;
+ else 
+   rd_ptr = rd_ptr + 1;
+end
+endtask
+
+reg state;
+reg invalid_rd;
+/* write in the fifo */
+always@(negedge rstn or posedge sw_clk)
+begin
+if(!rstn) begin
+ wr_ptr  = 0;
+ rd_ptr  = 0;
+ state   = 0;
+ invalid_rd  = 0;
+end else begin
+ case (state)
+ 0 : begin
+  state  = 0;  
+  invalid_rd  = 0;
+  if(req)begin
+   state     = 1;
+   invalid_rd  = invalid_rd_req;
+  end
+ end
+ 1 : begin
+  state     = 1;
+  if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin 
+   if(RD_DATA_VALID_DDR)
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = {RD_DATA_DDR,rd_info};
+   else if(RD_DATA_VALID_OCM)
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = {RD_DATA_OCM,rd_info};
+   else 
+     rd_fifo[wr_ptr[intr_cnt_width-2:0]]  = rd_info;
+   if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 
+     wr_ptr[intr_cnt_width-2:0]  = 0;
+   else 
+     wr_ptr  = wr_ptr + 1;
+   state   = 0;
+   invalid_rd  = 0;
+  end
+ end
+ endcase
+end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_fmsw_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics FMSW switch.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_fmsw_gp(
+ sw_clk,
+ rstn,
+
+ w_qos_gp0,
+ r_qos_gp0,
+ wr_ack_ocm_gp0,
+ wr_ack_ddr_gp0,
+ wr_data_gp0,
+ wr_addr_gp0,
+ wr_bytes_gp0,
+ wr_dv_ocm_gp0,
+ wr_dv_ddr_gp0,
+ rd_req_ocm_gp0,
+ rd_req_ddr_gp0,
+ rd_req_reg_gp0,
+ rd_addr_gp0,
+ rd_bytes_gp0,
+ rd_data_ocm_gp0,
+ rd_data_ddr_gp0,
+ rd_data_reg_gp0,
+ rd_dv_ocm_gp0,
+ rd_dv_ddr_gp0,
+ rd_dv_reg_gp0,
+ 
+ w_qos_gp1,
+ r_qos_gp1,
+ wr_ack_ocm_gp1,
+ wr_ack_ddr_gp1,
+ wr_data_gp1,
+ wr_addr_gp1,
+ wr_bytes_gp1,
+ wr_dv_ocm_gp1,
+ wr_dv_ddr_gp1,
+ rd_req_ocm_gp1,
+ rd_req_ddr_gp1,
+ rd_req_reg_gp1,
+ rd_addr_gp1,
+ rd_bytes_gp1,
+ rd_data_ocm_gp1,
+ rd_data_ddr_gp1,
+ rd_data_reg_gp1,
+ rd_dv_ocm_gp1,
+ rd_dv_ddr_gp1,
+ rd_dv_reg_gp1,
+
+ ocm_wr_ack,
+ ocm_wr_dv,
+ ocm_rd_req,
+ ocm_rd_dv,
+ ddr_wr_ack,
+ ddr_wr_dv,
+ ddr_rd_req,
+ ddr_rd_dv,
+
+ reg_rd_req,
+ reg_rd_dv,
+
+ ocm_wr_qos,
+ ddr_wr_qos,
+ ocm_rd_qos,
+ ddr_rd_qos,
+ reg_rd_qos,
+
+ ocm_wr_addr,
+ ocm_wr_data,
+ ocm_wr_bytes,
+ ocm_rd_addr,
+ ocm_rd_data,
+ ocm_rd_bytes,
+
+ ddr_wr_addr,
+ ddr_wr_data,
+ ddr_wr_bytes,
+ ddr_rd_addr,
+ ddr_rd_data,
+ ddr_rd_bytes,
+
+ reg_rd_addr,
+ reg_rd_data,
+ reg_rd_bytes
+
+);
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+input sw_clk;
+input rstn;
+
+input [axi_qos_width-1:0]w_qos_gp0;
+input [axi_qos_width-1:0]r_qos_gp0;
+input [axi_qos_width-1:0]w_qos_gp1;
+input [axi_qos_width-1:0]r_qos_gp1;
+
+output [axi_qos_width-1:0]ocm_wr_qos;
+output [axi_qos_width-1:0]ocm_rd_qos;
+output [axi_qos_width-1:0]ddr_wr_qos;
+output [axi_qos_width-1:0]ddr_rd_qos;
+output [axi_qos_width-1:0]reg_rd_qos;
+
+output wr_ack_ocm_gp0;
+output wr_ack_ddr_gp0;
+input [max_burst_bits-1:0] wr_data_gp0;
+input [addr_width-1:0] wr_addr_gp0;
+input [max_burst_bytes_width:0] wr_bytes_gp0;
+output wr_dv_ocm_gp0;
+output wr_dv_ddr_gp0;
+
+input rd_req_ocm_gp0;
+input rd_req_ddr_gp0;
+input rd_req_reg_gp0;
+input [addr_width-1:0] rd_addr_gp0;
+input [max_burst_bytes_width:0] rd_bytes_gp0;
+output [max_burst_bits-1:0] rd_data_ocm_gp0;
+output [max_burst_bits-1:0] rd_data_ddr_gp0;
+output [max_burst_bits-1:0] rd_data_reg_gp0;
+output rd_dv_ocm_gp0;
+output rd_dv_ddr_gp0;
+output rd_dv_reg_gp0;
+ 
+output wr_ack_ocm_gp1;
+output wr_ack_ddr_gp1;
+input [max_burst_bits-1:0] wr_data_gp1;
+input [addr_width-1:0] wr_addr_gp1;
+input [max_burst_bytes_width:0] wr_bytes_gp1;
+output wr_dv_ocm_gp1;
+output wr_dv_ddr_gp1;
+
+input rd_req_ocm_gp1;
+input rd_req_ddr_gp1;
+input rd_req_reg_gp1;
+input [addr_width-1:0] rd_addr_gp1;
+input [max_burst_bytes_width:0] rd_bytes_gp1;
+output [max_burst_bits-1:0] rd_data_ocm_gp1;
+output [max_burst_bits-1:0] rd_data_ddr_gp1;
+output [max_burst_bits-1:0] rd_data_reg_gp1;
+output rd_dv_ocm_gp1;
+output rd_dv_ddr_gp1;
+output rd_dv_reg_gp1;
+ 
+ 
+input ocm_wr_ack;
+output ocm_wr_dv;
+output [addr_width-1:0]ocm_wr_addr;
+output [max_burst_bits-1:0]ocm_wr_data;
+output [max_burst_bytes_width:0]ocm_wr_bytes;
+
+input ocm_rd_dv;
+input [max_burst_bits-1:0] ocm_rd_data;
+output ocm_rd_req;
+output [addr_width-1:0] ocm_rd_addr;
+output [max_burst_bytes_width:0] ocm_rd_bytes;
+
+input ddr_wr_ack;
+output ddr_wr_dv;
+output [addr_width-1:0]ddr_wr_addr;
+output [max_burst_bits-1:0]ddr_wr_data;
+output [max_burst_bytes_width:0]ddr_wr_bytes;
+
+input ddr_rd_dv;
+input [max_burst_bits-1:0] ddr_rd_data;
+output ddr_rd_req;
+output [addr_width-1:0] ddr_rd_addr;
+output [max_burst_bytes_width:0] ddr_rd_bytes;
+
+input reg_rd_dv;
+input [max_burst_bits-1:0] reg_rd_data;
+output reg_rd_req;
+output [addr_width-1:0] reg_rd_addr;
+output [max_burst_bytes_width:0] reg_rd_bytes;
+
+
+
+processing_system7_vip_v1_0_3_arb_wr ocm_gp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_gp0),
+ .qos2(w_qos_gp1),
+ .prt_dv1(wr_dv_ocm_gp0),
+ .prt_dv2(wr_dv_ocm_gp1),
+ .prt_data1(wr_data_gp0),
+ .prt_data2(wr_data_gp1),
+ .prt_addr1(wr_addr_gp0),
+ .prt_addr2(wr_addr_gp1),
+ .prt_bytes1(wr_bytes_gp0),
+ .prt_bytes2(wr_bytes_gp1),
+ .prt_ack1(wr_ack_ocm_gp0),
+ .prt_ack2(wr_ack_ocm_gp1),
+ .prt_req(ocm_wr_dv),
+ .prt_qos(ocm_wr_qos),
+ .prt_data(ocm_wr_data),
+ .prt_addr(ocm_wr_addr),
+ .prt_bytes(ocm_wr_bytes),
+ .prt_ack(ocm_wr_ack)
+);
+
+processing_system7_vip_v1_0_3_arb_wr ddr_gp_wr(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(w_qos_gp0),
+ .qos2(w_qos_gp1),
+ .prt_dv1(wr_dv_ddr_gp0),
+ .prt_dv2(wr_dv_ddr_gp1),
+ .prt_data1(wr_data_gp0),
+ .prt_data2(wr_data_gp1),
+ .prt_addr1(wr_addr_gp0),
+ .prt_addr2(wr_addr_gp1),
+ .prt_bytes1(wr_bytes_gp0),
+ .prt_bytes2(wr_bytes_gp1),
+ .prt_ack1(wr_ack_ddr_gp0),
+ .prt_ack2(wr_ack_ddr_gp1),
+ .prt_req(ddr_wr_dv),
+ .prt_qos(ddr_wr_qos),
+ .prt_data(ddr_wr_data),
+ .prt_addr(ddr_wr_addr),
+ .prt_bytes(ddr_wr_bytes),
+ .prt_ack(ddr_wr_ack)
+);
+
+processing_system7_vip_v1_0_3_arb_rd ocm_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_ocm_gp0),
+ .prt_req2(rd_req_ocm_gp1),
+ .prt_data1(rd_data_ocm_gp0),
+ .prt_data2(rd_data_ocm_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_ocm_gp0),
+ .prt_dv2(rd_dv_ocm_gp1),
+ .prt_req(ocm_rd_req),
+ .prt_qos(ocm_rd_qos),
+ .prt_data(ocm_rd_data),
+ .prt_addr(ocm_rd_addr),
+ .prt_bytes(ocm_rd_bytes),
+ .prt_dv(ocm_rd_dv)
+);
+
+processing_system7_vip_v1_0_3_arb_rd ddr_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_ddr_gp0),
+ .prt_req2(rd_req_ddr_gp1),
+ .prt_data1(rd_data_ddr_gp0),
+ .prt_data2(rd_data_ddr_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_ddr_gp0),
+ .prt_dv2(rd_dv_ddr_gp1),
+ .prt_req(ddr_rd_req),
+ .prt_qos(ddr_rd_qos),
+ .prt_data(ddr_rd_data),
+ .prt_addr(ddr_rd_addr),
+ .prt_bytes(ddr_rd_bytes),
+ .prt_dv(ddr_rd_dv)
+);
+
+processing_system7_vip_v1_0_3_arb_rd reg_gp_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(r_qos_gp0),
+ .qos2(r_qos_gp1),
+ .prt_req1(rd_req_reg_gp0),
+ .prt_req2(rd_req_reg_gp1),
+ .prt_data1(rd_data_reg_gp0),
+ .prt_data2(rd_data_reg_gp1),
+ .prt_addr1(rd_addr_gp0),
+ .prt_addr2(rd_addr_gp1),
+ .prt_bytes1(rd_bytes_gp0),
+ .prt_bytes2(rd_bytes_gp1),
+ .prt_dv1(rd_dv_reg_gp0),
+ .prt_dv2(rd_dv_reg_gp1),
+ .prt_req(reg_rd_req),
+ .prt_qos(reg_rd_qos),
+ .prt_data(reg_rd_data),
+ .prt_addr(reg_rd_addr),
+ .prt_bytes(reg_rd_bytes),
+ .prt_dv(reg_rd_dv)
+);
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_regc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for Register Map Memory
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_regc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of REG */
+ reg_rd_req_port0,
+ reg_rd_dv_port0,
+ reg_rd_addr_port0,
+ reg_rd_data_port0,
+ reg_rd_bytes_port0,
+ reg_rd_qos_port0,
+
+
+/* Goes to port 1 of REG */
+ reg_rd_req_port1,
+ reg_rd_dv_port1,
+ reg_rd_addr_port1,
+ reg_rd_data_port1,
+ reg_rd_bytes_port1,
+ reg_rd_qos_port1 
+
+);
+
+input rstn;
+input sw_clk;
+
+input reg_rd_req_port0;
+output reg_rd_dv_port0;
+input[31:0] reg_rd_addr_port0;
+output[1023:0] reg_rd_data_port0;
+input[7:0] reg_rd_bytes_port0;
+input [3:0] reg_rd_qos_port0;
+
+input reg_rd_req_port1;
+output reg_rd_dv_port1;
+input[31:0] reg_rd_addr_port1;
+output[1023:0] reg_rd_data_port1;
+input[7:0] reg_rd_bytes_port1;
+input[3:0] reg_rd_qos_port1;
+
+wire [3:0] rd_qos;
+reg [1023:0] rd_data;
+wire [31:0] rd_addr;
+wire [7:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_vip_v1_0_3_arb_rd reg_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(reg_rd_qos_port0),
+ .qos2(reg_rd_qos_port1),
+   
+ .prt_req1(reg_rd_req_port0),
+ .prt_req2(reg_rd_req_port1),
+   
+ .prt_data1(reg_rd_data_port0),
+ .prt_data2(reg_rd_data_port1),
+   
+ .prt_addr1(reg_rd_addr_port0),
+ .prt_addr2(reg_rd_addr_port1),
+   
+ .prt_bytes1(reg_rd_bytes_port0),
+ .prt_bytes2(reg_rd_bytes_port1),
+   
+ .prt_dv1(reg_rd_dv_port0),
+ .prt_dv2(reg_rd_dv_port1),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_vip_v1_0_3_reg_map regm();
+
+reg state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ rd_dv <= 0;
+ state <= 0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     rd_dv <= 0;
+     if(rd_req) begin
+       regm.read_reg_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_ocmc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Controller for OCM model
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_ocmc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of OCM */
+ ocm_wr_ack_port0,
+ ocm_wr_dv_port0,
+ ocm_rd_req_port0,
+ ocm_rd_dv_port0,
+ ocm_wr_addr_port0,
+ ocm_wr_data_port0,
+ ocm_wr_bytes_port0,
+ ocm_rd_addr_port0,
+ ocm_rd_data_port0,
+ ocm_rd_bytes_port0,
+ ocm_wr_qos_port0,
+ ocm_rd_qos_port0,
+
+
+/* Goes to port 1 of OCM */
+ ocm_wr_ack_port1,
+ ocm_wr_dv_port1,
+ ocm_rd_req_port1,
+ ocm_rd_dv_port1,
+ ocm_wr_addr_port1,
+ ocm_wr_data_port1,
+ ocm_wr_bytes_port1,
+ ocm_rd_addr_port1,
+ ocm_rd_data_port1,
+ ocm_rd_bytes_port1,
+ ocm_wr_qos_port1,
+ ocm_rd_qos_port1 
+
+);
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+input rstn;
+input sw_clk;
+
+output ocm_wr_ack_port0;
+input ocm_wr_dv_port0;
+input ocm_rd_req_port0;
+output ocm_rd_dv_port0;
+input[addr_width-1:0] ocm_wr_addr_port0;
+input[max_burst_bits-1:0] ocm_wr_data_port0;
+input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
+input[addr_width-1:0] ocm_rd_addr_port0;
+output[max_burst_bits-1:0] ocm_rd_data_port0;
+input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
+input [axi_qos_width-1:0] ocm_wr_qos_port0;
+input [axi_qos_width-1:0] ocm_rd_qos_port0;
+
+output ocm_wr_ack_port1;
+input ocm_wr_dv_port1;
+input ocm_rd_req_port1;
+output ocm_rd_dv_port1;
+input[addr_width-1:0] ocm_wr_addr_port1;
+input[max_burst_bits-1:0] ocm_wr_data_port1;
+input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
+input[addr_width-1:0] ocm_rd_addr_port1;
+output[max_burst_bits-1:0] ocm_rd_data_port1;
+input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
+input[axi_qos_width-1:0] ocm_wr_qos_port1;
+input[axi_qos_width-1:0] ocm_rd_qos_port1;
+
+wire [axi_qos_width-1:0] wr_qos;
+wire wr_req;
+wire [max_burst_bits-1:0] wr_data;
+wire [addr_width-1:0] wr_addr;
+wire [max_burst_bytes_width:0] wr_bytes;
+reg wr_ack;
+
+wire [axi_qos_width-1:0] rd_qos;
+reg [max_burst_bits-1:0] rd_data;
+wire [addr_width-1:0] rd_addr;
+wire [max_burst_bytes_width:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_vip_v1_0_3_arb_wr ocm_write_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ocm_wr_qos_port0),
+ .qos2(ocm_wr_qos_port1),
+   
+ .prt_dv1(ocm_wr_dv_port0),
+ .prt_dv2(ocm_wr_dv_port1),
+   
+ .prt_data1(ocm_wr_data_port0),
+ .prt_data2(ocm_wr_data_port1),
+   
+ .prt_addr1(ocm_wr_addr_port0),
+ .prt_addr2(ocm_wr_addr_port1),
+   
+ .prt_bytes1(ocm_wr_bytes_port0),
+ .prt_bytes2(ocm_wr_bytes_port1),
+   
+ .prt_ack1(ocm_wr_ack_port0),
+ .prt_ack2(ocm_wr_ack_port1),
+   
+ .prt_qos(wr_qos),
+ .prt_req(wr_req),
+ .prt_data(wr_data),
+ .prt_addr(wr_addr),
+ .prt_bytes(wr_bytes),
+ .prt_ack(wr_ack)
+
+);
+
+processing_system7_vip_v1_0_3_arb_rd ocm_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ocm_rd_qos_port0),
+ .qos2(ocm_rd_qos_port1),
+   
+ .prt_req1(ocm_rd_req_port0),
+ .prt_req2(ocm_rd_req_port1),
+   
+ .prt_data1(ocm_rd_data_port0),
+ .prt_data2(ocm_rd_data_port1),
+   
+ .prt_addr1(ocm_rd_addr_port0),
+ .prt_addr2(ocm_rd_addr_port1),
+   
+ .prt_bytes1(ocm_rd_bytes_port0),
+ .prt_bytes2(ocm_rd_bytes_port1),
+   
+ .prt_dv1(ocm_rd_dv_port0),
+ .prt_dv2(ocm_rd_dv_port1),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_vip_v1_0_3_ocm_mem ocm();
+
+reg [1:0] state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ wr_ack <= 0; 
+ rd_dv <= 0;
+ state <= 2'd0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     wr_ack <= 0;
+     rd_dv <= 0;
+     if(wr_req) begin
+       ocm.write_mem(wr_data , wr_addr, wr_bytes); 
+       wr_ack <= 1;
+       state <= 1;
+     end
+     if(rd_req) begin
+       ocm.read_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       wr_ack <= 0;
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_interconnect_model.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Mimics Top_interconnect Switch.
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_interconnect_model (
+ rstn,
+ sw_clk, 
+ 
+ w_qos_gp0,
+ w_qos_gp1,
+ w_qos_hp0,
+ w_qos_hp1,
+ w_qos_hp2,
+ w_qos_hp3,
+
+ r_qos_gp0,
+ r_qos_gp1,
+ r_qos_hp0,
+ r_qos_hp1,
+ r_qos_hp2,
+ r_qos_hp3,
+
+ wr_ack_ddr_gp0,
+ wr_ack_ocm_gp0,
+ wr_data_gp0,
+ wr_addr_gp0,
+ wr_bytes_gp0,
+ wr_dv_ddr_gp0,
+ wr_dv_ocm_gp0,
+
+ rd_req_ddr_gp0,
+ rd_req_ocm_gp0,
+ rd_req_reg_gp0,
+ rd_addr_gp0,
+ rd_bytes_gp0,
+ rd_data_ddr_gp0,
+ rd_data_ocm_gp0,
+ rd_data_reg_gp0,
+ rd_dv_ddr_gp0,
+ rd_dv_ocm_gp0,
+ rd_dv_reg_gp0,
+
+ wr_ack_ddr_gp1,
+ wr_ack_ocm_gp1,
+ wr_data_gp1,
+ wr_addr_gp1,
+ wr_bytes_gp1,
+ wr_dv_ddr_gp1,
+ wr_dv_ocm_gp1,
+ rd_req_ddr_gp1,
+ rd_req_ocm_gp1,
+ rd_req_reg_gp1,
+ rd_addr_gp1,
+ rd_bytes_gp1,
+ rd_data_ddr_gp1,
+ rd_data_ocm_gp1,
+ rd_data_reg_gp1,
+ rd_dv_ddr_gp1,
+ rd_dv_ocm_gp1,
+ rd_dv_reg_gp1,
+
+ wr_ack_ddr_hp0,
+ wr_ack_ocm_hp0,
+ wr_data_hp0,
+ wr_addr_hp0,
+ wr_bytes_hp0,
+ wr_dv_ddr_hp0,
+ wr_dv_ocm_hp0,
+ rd_req_ddr_hp0,
+ rd_req_ocm_hp0,
+ rd_addr_hp0,
+ rd_bytes_hp0,
+ rd_data_ddr_hp0,
+ rd_data_ocm_hp0,
+ rd_dv_ddr_hp0,
+ rd_dv_ocm_hp0,
+
+ wr_ack_ddr_hp1,
+ wr_ack_ocm_hp1,
+ wr_data_hp1,
+ wr_addr_hp1,
+ wr_bytes_hp1,
+ wr_dv_ddr_hp1,
+ wr_dv_ocm_hp1,
+ rd_req_ddr_hp1,
+ rd_req_ocm_hp1,
+ rd_addr_hp1,
+ rd_bytes_hp1,
+ rd_data_ddr_hp1,
+ rd_data_ocm_hp1,
+ rd_dv_ddr_hp1,
+ rd_dv_ocm_hp1,
+
+ wr_ack_ddr_hp2,
+ wr_ack_ocm_hp2,
+ wr_data_hp2,
+ wr_addr_hp2,
+ wr_bytes_hp2,
+ wr_dv_ddr_hp2,
+ wr_dv_ocm_hp2,
+ rd_req_ddr_hp2,
+ rd_req_ocm_hp2,
+ rd_addr_hp2,
+ rd_bytes_hp2,
+ rd_data_ddr_hp2,
+ rd_data_ocm_hp2,
+ rd_dv_ddr_hp2,
+ rd_dv_ocm_hp2,
+
+ wr_ack_ddr_hp3,
+ wr_ack_ocm_hp3,
+ wr_data_hp3,
+ wr_addr_hp3,
+ wr_bytes_hp3,
+ wr_dv_ddr_hp3,
+ wr_dv_ocm_hp3,
+ rd_req_ddr_hp3,
+ rd_req_ocm_hp3,
+ rd_addr_hp3,
+ rd_bytes_hp3,
+ rd_data_ddr_hp3,
+ rd_data_ocm_hp3,
+ rd_dv_ddr_hp3,
+ rd_dv_ocm_hp3,
+
+/* Goes to port 1 of DDR */
+ ddr_wr_ack_port1,
+ ddr_wr_dv_port1,
+ ddr_rd_req_port1,
+ ddr_rd_dv_port1,
+ ddr_wr_addr_port1,
+ ddr_wr_data_port1,
+ ddr_wr_bytes_port1,
+ ddr_rd_addr_port1,
+ ddr_rd_data_port1,
+ ddr_rd_bytes_port1,
+ ddr_wr_qos_port1,
+ ddr_rd_qos_port1,
+
+/* Goes to port2 of DDR */
+ ddr_wr_ack_port2,
+ ddr_wr_dv_port2,
+ ddr_rd_req_port2,
+ ddr_rd_dv_port2,
+ ddr_wr_addr_port2,
+ ddr_wr_data_port2,
+ ddr_wr_bytes_port2,
+ ddr_rd_addr_port2,
+ ddr_rd_data_port2,
+ ddr_rd_bytes_port2,
+ ddr_wr_qos_port2,
+ ddr_rd_qos_port2,
+
+/* Goes to port3 of DDR */
+ ddr_wr_ack_port3,
+ ddr_wr_dv_port3,
+ ddr_rd_req_port3,
+ ddr_rd_dv_port3,
+ ddr_wr_addr_port3,
+ ddr_wr_data_port3,
+ ddr_wr_bytes_port3,
+ ddr_rd_addr_port3,
+ ddr_rd_data_port3,
+ ddr_rd_bytes_port3,
+ ddr_wr_qos_port3,
+ ddr_rd_qos_port3,
+
+/* Goes to port1 of OCM */
+ ocm_wr_qos_port1,
+ ocm_rd_qos_port1,
+ ocm_wr_dv_port1,
+ ocm_wr_data_port1,
+ ocm_wr_addr_port1,
+ ocm_wr_bytes_port1,
+ ocm_wr_ack_port1,
+ ocm_rd_req_port1,
+ ocm_rd_data_port1,
+ ocm_rd_addr_port1,
+ ocm_rd_bytes_port1,
+ ocm_rd_dv_port1,
+
+/* Goes to port1 for RegMap  */
+ reg_rd_qos_port1,
+ reg_rd_req_port1,
+ reg_rd_data_port1,
+ reg_rd_addr_port1,
+ reg_rd_bytes_port1,
+ reg_rd_dv_port1
+
+);
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+input rstn;
+input sw_clk;
+
+input [axi_qos_width-1:0] w_qos_gp0;
+input [axi_qos_width-1:0] w_qos_gp1;
+input [axi_qos_width-1:0] w_qos_hp0;
+input [axi_qos_width-1:0] w_qos_hp1;
+input [axi_qos_width-1:0] w_qos_hp2;
+input [axi_qos_width-1:0] w_qos_hp3;
+
+input [axi_qos_width-1:0] r_qos_gp0;
+input [axi_qos_width-1:0] r_qos_gp1;
+input [axi_qos_width-1:0] r_qos_hp0;
+input [axi_qos_width-1:0] r_qos_hp1;
+input [axi_qos_width-1:0] r_qos_hp2;
+input [axi_qos_width-1:0] r_qos_hp3;
+ 
+output [axi_qos_width-1:0] ocm_wr_qos_port1;
+output [axi_qos_width-1:0] ocm_rd_qos_port1;
+
+output wr_ack_ddr_gp0;
+output wr_ack_ocm_gp0;
+input[max_burst_bits-1:0] wr_data_gp0;
+input[addr_width-1:0] wr_addr_gp0;
+input[max_burst_bytes_width:0] wr_bytes_gp0;
+input wr_dv_ddr_gp0;
+input wr_dv_ocm_gp0;
+input rd_req_ddr_gp0;
+input rd_req_ocm_gp0;
+input rd_req_reg_gp0;
+input[addr_width-1:0] rd_addr_gp0;
+input[max_burst_bytes_width:0] rd_bytes_gp0;
+output[max_burst_bits-1:0] rd_data_ddr_gp0;
+output[max_burst_bits-1:0] rd_data_ocm_gp0;
+output[max_burst_bits-1:0] rd_data_reg_gp0;
+output rd_dv_ddr_gp0;
+output rd_dv_ocm_gp0;
+output rd_dv_reg_gp0;
+
+output wr_ack_ddr_gp1;
+output wr_ack_ocm_gp1;
+input[max_burst_bits-1:0] wr_data_gp1;
+input[addr_width-1:0] wr_addr_gp1;
+input[max_burst_bytes_width:0] wr_bytes_gp1;
+input wr_dv_ddr_gp1;
+input wr_dv_ocm_gp1;
+input rd_req_ddr_gp1;
+input rd_req_ocm_gp1;
+input rd_req_reg_gp1;
+input[addr_width-1:0] rd_addr_gp1;
+input[max_burst_bytes_width:0] rd_bytes_gp1;
+output[max_burst_bits-1:0] rd_data_ddr_gp1;
+output[max_burst_bits-1:0] rd_data_ocm_gp1;
+output[max_burst_bits-1:0] rd_data_reg_gp1;
+output rd_dv_ddr_gp1;
+output rd_dv_ocm_gp1;
+output rd_dv_reg_gp1;
+
+output wr_ack_ddr_hp0;
+output wr_ack_ocm_hp0;
+input[max_burst_bits-1:0] wr_data_hp0;
+input[addr_width-1:0] wr_addr_hp0;
+input[max_burst_bytes_width:0] wr_bytes_hp0;
+input wr_dv_ddr_hp0;
+input wr_dv_ocm_hp0;
+input rd_req_ddr_hp0;
+input rd_req_ocm_hp0;
+input[addr_width-1:0] rd_addr_hp0;
+input[max_burst_bytes_width:0] rd_bytes_hp0;
+output[max_burst_bits-1:0] rd_data_ddr_hp0;
+output[max_burst_bits-1:0] rd_data_ocm_hp0;
+output rd_dv_ddr_hp0;
+output rd_dv_ocm_hp0;
+
+output wr_ack_ddr_hp1;
+output wr_ack_ocm_hp1;
+input[max_burst_bits-1:0] wr_data_hp1;
+input[addr_width-1:0] wr_addr_hp1;
+input[max_burst_bytes_width:0] wr_bytes_hp1;
+input wr_dv_ddr_hp1;
+input wr_dv_ocm_hp1;
+input rd_req_ddr_hp1;
+input rd_req_ocm_hp1;
+input[addr_width-1:0] rd_addr_hp1;
+input[max_burst_bytes_width:0] rd_bytes_hp1;
+output[max_burst_bits-1:0] rd_data_ddr_hp1;
+output[max_burst_bits-1:0] rd_data_ocm_hp1;
+output rd_dv_ddr_hp1;
+output rd_dv_ocm_hp1;
+
+output wr_ack_ddr_hp2;
+output wr_ack_ocm_hp2;
+input[max_burst_bits-1:0] wr_data_hp2;
+input[addr_width-1:0] wr_addr_hp2;
+input[max_burst_bytes_width:0] wr_bytes_hp2;
+input wr_dv_ddr_hp2;
+input wr_dv_ocm_hp2;
+input rd_req_ddr_hp2;
+input rd_req_ocm_hp2;
+input[addr_width-1:0] rd_addr_hp2;
+input[max_burst_bytes_width:0] rd_bytes_hp2;
+output[max_burst_bits-1:0] rd_data_ddr_hp2;
+output[max_burst_bits-1:0] rd_data_ocm_hp2;
+output rd_dv_ddr_hp2;
+output rd_dv_ocm_hp2;
+
+output wr_ack_ddr_hp3;
+output wr_ack_ocm_hp3;
+input[max_burst_bits-1:0] wr_data_hp3;
+input[addr_width-1:0] wr_addr_hp3;
+input[max_burst_bytes_width:0] wr_bytes_hp3;
+input wr_dv_ddr_hp3;
+input wr_dv_ocm_hp3;
+input rd_req_ddr_hp3;
+input rd_req_ocm_hp3;
+input[addr_width-1:0] rd_addr_hp3;
+input[max_burst_bytes_width:0] rd_bytes_hp3;
+output[max_burst_bits-1:0] rd_data_ddr_hp3;
+output[max_burst_bits-1:0] rd_data_ocm_hp3;
+output rd_dv_ddr_hp3;
+output rd_dv_ocm_hp3;
+
+/* Goes to port 1 of DDR */
+input ddr_wr_ack_port1;
+output ddr_wr_dv_port1;
+output ddr_rd_req_port1;
+input ddr_rd_dv_port1;
+output[addr_width-1:0] ddr_wr_addr_port1;
+output[max_burst_bits-1:0] ddr_wr_data_port1;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+output[addr_width-1:0] ddr_rd_addr_port1;
+input[max_burst_bits-1:0] ddr_rd_data_port1;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+output [axi_qos_width-1:0] ddr_wr_qos_port1;
+output [axi_qos_width-1:0] ddr_rd_qos_port1;
+
+/* Goes to port2 of DDR */
+input ddr_wr_ack_port2;
+output ddr_wr_dv_port2;
+output ddr_rd_req_port2;
+input ddr_rd_dv_port2;
+output[addr_width-1:0] ddr_wr_addr_port2;
+output[max_burst_bits-1:0] ddr_wr_data_port2;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+output[addr_width-1:0] ddr_rd_addr_port2;
+input[max_burst_bits-1:0] ddr_rd_data_port2;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+output [axi_qos_width-1:0] ddr_wr_qos_port2;
+output [axi_qos_width-1:0] ddr_rd_qos_port2;
+
+/* Goes to port3 of DDR */
+input ddr_wr_ack_port3;
+output ddr_wr_dv_port3;
+output ddr_rd_req_port3;
+input ddr_rd_dv_port3;
+output[addr_width-1:0] ddr_wr_addr_port3;
+output[max_burst_bits-1:0] ddr_wr_data_port3;
+output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+output[addr_width-1:0] ddr_rd_addr_port3;
+input[max_burst_bits-1:0] ddr_rd_data_port3;
+output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+output [axi_qos_width-1:0] ddr_wr_qos_port3;
+output [axi_qos_width-1:0] ddr_rd_qos_port3;
+
+/* Goes to port1 of OCM */
+input ocm_wr_ack_port1;
+output ocm_wr_dv_port1;
+output ocm_rd_req_port1;
+input ocm_rd_dv_port1;
+output[max_burst_bits-1:0] ocm_wr_data_port1;
+output[addr_width-1:0] ocm_wr_addr_port1;
+output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
+input[max_burst_bits-1:0] ocm_rd_data_port1;
+output[addr_width-1:0] ocm_rd_addr_port1;
+output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
+
+/* Goes to port1 of REG */
+output [axi_qos_width-1:0] reg_rd_qos_port1;  
+output reg_rd_req_port1;
+input reg_rd_dv_port1;
+input[max_burst_bits-1:0] reg_rd_data_port1;
+output[addr_width-1:0] reg_rd_addr_port1;
+output[max_burst_bytes_width:0] reg_rd_bytes_port1;
+
+wire ocm_wr_dv_osw0;
+wire ocm_wr_dv_osw1;
+wire[max_burst_bits-1:0] ocm_wr_data_osw0;
+wire[max_burst_bits-1:0] ocm_wr_data_osw1;
+wire[addr_width-1:0] ocm_wr_addr_osw0;
+wire[addr_width-1:0] ocm_wr_addr_osw1;
+wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
+wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
+wire ocm_wr_ack_osw0;
+wire ocm_wr_ack_osw1;
+wire ocm_rd_req_osw0;
+wire ocm_rd_req_osw1;
+wire[max_burst_bits-1:0] ocm_rd_data_osw0;
+wire[max_burst_bits-1:0] ocm_rd_data_osw1;
+wire[addr_width-1:0] ocm_rd_addr_osw0;
+wire[addr_width-1:0] ocm_rd_addr_osw1;
+wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
+wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
+wire ocm_rd_dv_osw0;
+wire ocm_rd_dv_osw1;
+
+wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
+wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
+wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
+wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
+
+
+processing_system7_vip_v1_0_3_fmsw_gp fmsw (
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+   
+ .w_qos_gp0(w_qos_gp0),
+ .r_qos_gp0(r_qos_gp0),
+ .wr_ack_ocm_gp0(wr_ack_ocm_gp0),
+ .wr_ack_ddr_gp0(wr_ack_ddr_gp0),
+ .wr_data_gp0(wr_data_gp0),
+ .wr_addr_gp0(wr_addr_gp0),
+ .wr_bytes_gp0(wr_bytes_gp0),
+ .wr_dv_ocm_gp0(wr_dv_ocm_gp0),
+ .wr_dv_ddr_gp0(wr_dv_ddr_gp0),
+ .rd_req_ocm_gp0(rd_req_ocm_gp0),
+ .rd_req_ddr_gp0(rd_req_ddr_gp0),
+ .rd_req_reg_gp0(rd_req_reg_gp0),
+ .rd_addr_gp0(rd_addr_gp0),
+ .rd_bytes_gp0(rd_bytes_gp0),
+ .rd_data_ddr_gp0(rd_data_ddr_gp0),
+ .rd_data_ocm_gp0(rd_data_ocm_gp0),
+ .rd_data_reg_gp0(rd_data_reg_gp0),
+ .rd_dv_ocm_gp0(rd_dv_ocm_gp0),
+ .rd_dv_ddr_gp0(rd_dv_ddr_gp0),
+ .rd_dv_reg_gp0(rd_dv_reg_gp0),
+ 
+ .w_qos_gp1(w_qos_gp1),
+ .r_qos_gp1(r_qos_gp1),
+ .wr_ack_ocm_gp1(wr_ack_ocm_gp1),
+ .wr_ack_ddr_gp1(wr_ack_ddr_gp1),
+ .wr_data_gp1(wr_data_gp1),
+ .wr_addr_gp1(wr_addr_gp1),
+ .wr_bytes_gp1(wr_bytes_gp1),
+ .wr_dv_ocm_gp1(wr_dv_ocm_gp1),
+ .wr_dv_ddr_gp1(wr_dv_ddr_gp1),
+ .rd_req_ocm_gp1(rd_req_ocm_gp1),
+ .rd_req_ddr_gp1(rd_req_ddr_gp1),
+ .rd_req_reg_gp1(rd_req_reg_gp1),
+ .rd_addr_gp1(rd_addr_gp1),
+ .rd_bytes_gp1(rd_bytes_gp1),
+ .rd_data_ddr_gp1(rd_data_ddr_gp1),
+ .rd_data_ocm_gp1(rd_data_ocm_gp1),
+ .rd_data_reg_gp1(rd_data_reg_gp1),
+ .rd_dv_ocm_gp1(rd_dv_ocm_gp1),
+ .rd_dv_ddr_gp1(rd_dv_ddr_gp1),
+ .rd_dv_reg_gp1(rd_dv_reg_gp1),
+    
+ .ocm_wr_ack (ocm_wr_ack_osw0),
+ .ocm_wr_dv  (ocm_wr_dv_osw0),
+ .ocm_rd_req (ocm_rd_req_osw0),
+ .ocm_rd_dv  (ocm_rd_dv_osw0),
+ .ocm_wr_addr(ocm_wr_addr_osw0),
+ .ocm_wr_data(ocm_wr_data_osw0),
+ .ocm_wr_bytes(ocm_wr_bytes_osw0),
+ .ocm_rd_addr(ocm_rd_addr_osw0),
+ .ocm_rd_data(ocm_rd_data_osw0),
+ .ocm_rd_bytes(ocm_rd_bytes_osw0),
+
+ .ocm_wr_qos(ocm_wr_qos_osw0),
+ .ocm_rd_qos(ocm_rd_qos_osw0),
+ 
+ .ddr_wr_qos(ddr_wr_qos_port1),
+ .ddr_rd_qos(ddr_rd_qos_port1),
+
+ .reg_rd_qos(reg_rd_qos_port1),
+
+ .ddr_wr_ack(ddr_wr_ack_port1),
+ .ddr_wr_dv(ddr_wr_dv_port1),
+ .ddr_rd_req(ddr_rd_req_port1),
+ .ddr_rd_dv(ddr_rd_dv_port1),
+ .ddr_wr_addr(ddr_wr_addr_port1),
+ .ddr_wr_data(ddr_wr_data_port1),
+ .ddr_wr_bytes(ddr_wr_bytes_port1),
+ .ddr_rd_addr(ddr_rd_addr_port1),
+ .ddr_rd_data(ddr_rd_data_port1),
+ .ddr_rd_bytes(ddr_rd_bytes_port1),
+
+ .reg_rd_req(reg_rd_req_port1),
+ .reg_rd_dv(reg_rd_dv_port1),
+ .reg_rd_addr(reg_rd_addr_port1),
+ .reg_rd_data(reg_rd_data_port1),
+ .reg_rd_bytes(reg_rd_bytes_port1)
+);
+
+
+processing_system7_vip_v1_0_3_ssw_hp ssw(
+ .sw_clk(sw_clk),
+ .rstn(rstn),
+ .w_qos_hp0(w_qos_hp0),
+ .r_qos_hp0(r_qos_hp0),
+ .w_qos_hp1(w_qos_hp1),
+ .r_qos_hp1(r_qos_hp1),
+ .w_qos_hp2(w_qos_hp2),
+ .r_qos_hp2(r_qos_hp2),
+ .w_qos_hp3(w_qos_hp3),
+ .r_qos_hp3(r_qos_hp3),
+   
+ .wr_ack_ddr_hp0(wr_ack_ddr_hp0),
+ .wr_data_hp0(wr_data_hp0),
+ .wr_addr_hp0(wr_addr_hp0),
+ .wr_bytes_hp0(wr_bytes_hp0),
+ .wr_dv_ddr_hp0(wr_dv_ddr_hp0),
+ .rd_req_ddr_hp0(rd_req_ddr_hp0),
+ .rd_addr_hp0(rd_addr_hp0),
+ .rd_bytes_hp0(rd_bytes_hp0),
+ .rd_data_ddr_hp0(rd_data_ddr_hp0),
+ .rd_data_ocm_hp0(rd_data_ocm_hp0),
+ .rd_dv_ddr_hp0(rd_dv_ddr_hp0),
+   
+ .wr_ack_ocm_hp0(wr_ack_ocm_hp0),
+ .wr_dv_ocm_hp0(wr_dv_ocm_hp0),
+ .rd_req_ocm_hp0(rd_req_ocm_hp0),
+ .rd_dv_ocm_hp0(rd_dv_ocm_hp0),
+   
+ .wr_ack_ddr_hp1(wr_ack_ddr_hp1),
+ .wr_data_hp1(wr_data_hp1),
+ .wr_addr_hp1(wr_addr_hp1),
+ .wr_bytes_hp1(wr_bytes_hp1),
+ .wr_dv_ddr_hp1(wr_dv_ddr_hp1),
+ .rd_req_ddr_hp1(rd_req_ddr_hp1),
+ .rd_addr_hp1(rd_addr_hp1),
+ .rd_bytes_hp1(rd_bytes_hp1),
+ .rd_data_ddr_hp1(rd_data_ddr_hp1),
+ .rd_data_ocm_hp1(rd_data_ocm_hp1),
+ .rd_dv_ddr_hp1(rd_dv_ddr_hp1),
+   
+ .wr_ack_ocm_hp1(wr_ack_ocm_hp1),
+ .wr_dv_ocm_hp1(wr_dv_ocm_hp1),
+ .rd_req_ocm_hp1(rd_req_ocm_hp1),
+ .rd_dv_ocm_hp1(rd_dv_ocm_hp1),
+   
+ .wr_ack_ddr_hp2(wr_ack_ddr_hp2),
+ .wr_data_hp2(wr_data_hp2),
+ .wr_addr_hp2(wr_addr_hp2),
+ .wr_bytes_hp2(wr_bytes_hp2),
+ .wr_dv_ddr_hp2(wr_dv_ddr_hp2),
+ .rd_req_ddr_hp2(rd_req_ddr_hp2),
+ .rd_addr_hp2(rd_addr_hp2),
+ .rd_bytes_hp2(rd_bytes_hp2),
+ .rd_data_ddr_hp2(rd_data_ddr_hp2),
+ .rd_data_ocm_hp2(rd_data_ocm_hp2),
+ .rd_dv_ddr_hp2(rd_dv_ddr_hp2),
+   
+ .wr_ack_ocm_hp2(wr_ack_ocm_hp2),
+ .wr_dv_ocm_hp2(wr_dv_ocm_hp2),
+ .rd_req_ocm_hp2(rd_req_ocm_hp2),
+ .rd_dv_ocm_hp2(rd_dv_ocm_hp2),
+   
+ .wr_ack_ddr_hp3(wr_ack_ddr_hp3),
+ .wr_data_hp3(wr_data_hp3),
+ .wr_addr_hp3(wr_addr_hp3),
+ .wr_bytes_hp3(wr_bytes_hp3),
+ .wr_dv_ddr_hp3(wr_dv_ddr_hp3),
+ .rd_req_ddr_hp3(rd_req_ddr_hp3),
+ .rd_addr_hp3(rd_addr_hp3),
+ .rd_bytes_hp3(rd_bytes_hp3),
+ .rd_data_ddr_hp3(rd_data_ddr_hp3),
+ .rd_data_ocm_hp3(rd_data_ocm_hp3),
+ .rd_dv_ddr_hp3(rd_dv_ddr_hp3),
+   
+ .wr_ack_ocm_hp3(wr_ack_ocm_hp3),
+ .wr_dv_ocm_hp3(wr_dv_ocm_hp3),
+ .rd_req_ocm_hp3(rd_req_ocm_hp3),
+ .rd_dv_ocm_hp3(rd_dv_ocm_hp3),
+   
+ .ddr_wr_ack0(ddr_wr_ack_port2),
+ .ddr_wr_dv0(ddr_wr_dv_port2),
+ .ddr_rd_req0(ddr_rd_req_port2),
+ .ddr_rd_dv0(ddr_rd_dv_port2),
+ .ddr_wr_addr0(ddr_wr_addr_port2),
+ .ddr_wr_data0(ddr_wr_data_port2),
+ .ddr_wr_bytes0(ddr_wr_bytes_port2),
+ .ddr_rd_addr0(ddr_rd_addr_port2),
+ .ddr_rd_data0(ddr_rd_data_port2),
+ .ddr_rd_bytes0(ddr_rd_bytes_port2),
+ .ddr_wr_qos0(ddr_wr_qos_port2),
+ .ddr_rd_qos0(ddr_rd_qos_port2),
+    
+ .ddr_wr_ack1(ddr_wr_ack_port3),
+ .ddr_wr_dv1(ddr_wr_dv_port3),
+ .ddr_rd_req1(ddr_rd_req_port3),
+ .ddr_rd_dv1(ddr_rd_dv_port3),
+ .ddr_wr_addr1(ddr_wr_addr_port3),
+ .ddr_wr_data1(ddr_wr_data_port3),
+ .ddr_wr_bytes1(ddr_wr_bytes_port3),
+ .ddr_rd_addr1(ddr_rd_addr_port3),
+ .ddr_rd_data1(ddr_rd_data_port3),
+ .ddr_rd_bytes1(ddr_rd_bytes_port3),
+ .ddr_wr_qos1(ddr_wr_qos_port3),
+ .ddr_rd_qos1(ddr_rd_qos_port3),
+
+ .ocm_wr_qos(ocm_wr_qos_osw1),
+ .ocm_rd_qos(ocm_rd_qos_osw1),
+ 
+ .ocm_wr_ack (ocm_wr_ack_osw1),
+ .ocm_wr_dv  (ocm_wr_dv_osw1),
+ .ocm_rd_req (ocm_rd_req_osw1),
+ .ocm_rd_dv  (ocm_rd_dv_osw1),
+ .ocm_wr_addr(ocm_wr_addr_osw1),
+ .ocm_wr_data(ocm_wr_data_osw1),
+ .ocm_wr_bytes(ocm_wr_bytes_osw1),
+ .ocm_rd_addr(ocm_rd_addr_osw1),
+ .ocm_rd_data(ocm_rd_data_osw1),
+ .ocm_rd_bytes(ocm_rd_bytes_osw1)
+
+);
+
+processing_system7_vip_v1_0_3_arb_wr osw_wr (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(ocm_wr_qos_osw0), /// chk
+ .qos2(ocm_wr_qos_osw1), /// chk
+ .prt_dv1(ocm_wr_dv_osw0),
+ .prt_dv2(ocm_wr_dv_osw1),
+ .prt_data1(ocm_wr_data_osw0),
+ .prt_data2(ocm_wr_data_osw1),
+ .prt_addr1(ocm_wr_addr_osw0),
+ .prt_addr2(ocm_wr_addr_osw1),
+ .prt_bytes1(ocm_wr_bytes_osw0),
+ .prt_bytes2(ocm_wr_bytes_osw1),
+ .prt_ack1(ocm_wr_ack_osw0),
+ .prt_ack2(ocm_wr_ack_osw1),
+ .prt_req(ocm_wr_dv_port1),
+ .prt_qos(ocm_wr_qos_port1),
+ .prt_data(ocm_wr_data_port1),
+ .prt_addr(ocm_wr_addr_port1),
+ .prt_bytes(ocm_wr_bytes_port1),
+ .prt_ack(ocm_wr_ack_port1)
+);
+
+processing_system7_vip_v1_0_3_arb_rd osw_rd(
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+ .qos1(ocm_rd_qos_osw0), // chk
+ .qos2(ocm_rd_qos_osw1), // chk
+ .prt_req1(ocm_rd_req_osw0),
+ .prt_req2(ocm_rd_req_osw1),
+ .prt_data1(ocm_rd_data_osw0),
+ .prt_data2(ocm_rd_data_osw1),
+ .prt_addr1(ocm_rd_addr_osw0),
+ .prt_addr2(ocm_rd_addr_osw1),
+ .prt_bytes1(ocm_rd_bytes_osw0),
+ .prt_bytes2(ocm_rd_bytes_osw1),
+ .prt_dv1(ocm_rd_dv_osw0),
+ .prt_dv2(ocm_rd_dv_osw1),
+ .prt_req(ocm_rd_req_port1),
+ .prt_qos(ocm_rd_qos_port1),
+ .prt_data(ocm_rd_data_port1),
+ .prt_addr(ocm_rd_addr_port1),
+ .prt_bytes(ocm_rd_bytes_port1),
+ .prt_dv(ocm_rd_dv_port1)
+);
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_gen_reset.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
+ *               respective clocks.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+module processing_system7_vip_v1_0_3_gen_reset(
+ por_rst_n,
+ sys_rst_n,
+ rst_out_n,
+
+ m_axi_gp0_clk,
+ m_axi_gp1_clk,
+ s_axi_gp0_clk,
+ s_axi_gp1_clk,
+ s_axi_hp0_clk,
+ s_axi_hp1_clk,
+ s_axi_hp2_clk,
+ s_axi_hp3_clk,
+ s_axi_acp_clk,
+
+ m_axi_gp0_rstn,
+ m_axi_gp1_rstn,
+ s_axi_gp0_rstn,
+ s_axi_gp1_rstn,
+ s_axi_hp0_rstn,
+ s_axi_hp1_rstn,
+ s_axi_hp2_rstn,
+ s_axi_hp3_rstn,
+ s_axi_acp_rstn,
+
+ fclk_reset3_n,
+ fclk_reset2_n,
+ fclk_reset1_n,
+ fclk_reset0_n,
+
+ fpga_acp_reset_n,
+ fpga_gp_m0_reset_n,
+ fpga_gp_m1_reset_n,
+ fpga_gp_s0_reset_n,
+ fpga_gp_s1_reset_n,
+ fpga_hp_s0_reset_n,
+ fpga_hp_s1_reset_n,
+ fpga_hp_s2_reset_n,
+ fpga_hp_s3_reset_n
+
+);
+
+input por_rst_n;
+input sys_rst_n;
+input m_axi_gp0_clk;
+input m_axi_gp1_clk;
+input s_axi_gp0_clk;
+input s_axi_gp1_clk;
+input s_axi_hp0_clk;
+input s_axi_hp1_clk;
+input s_axi_hp2_clk;
+input s_axi_hp3_clk;
+input s_axi_acp_clk;
+
+output reg m_axi_gp0_rstn;
+output reg m_axi_gp1_rstn;
+output reg s_axi_gp0_rstn;
+output reg s_axi_gp1_rstn;
+output reg s_axi_hp0_rstn;
+output reg s_axi_hp1_rstn;
+output reg s_axi_hp2_rstn;
+output reg s_axi_hp3_rstn;
+output reg s_axi_acp_rstn;
+
+output rst_out_n;
+output fclk_reset3_n;
+output fclk_reset2_n;
+output fclk_reset1_n;
+output fclk_reset0_n;
+
+output fpga_acp_reset_n;
+output fpga_gp_m0_reset_n;
+output fpga_gp_m1_reset_n;
+output fpga_gp_s0_reset_n;
+output fpga_gp_s1_reset_n;
+output fpga_hp_s0_reset_n;
+output fpga_hp_s1_reset_n;
+output fpga_hp_s2_reset_n;
+output fpga_hp_s3_reset_n;
+
+reg [31:0] fabric_rst_n;
+
+reg r_m_axi_gp0_rstn;
+reg r_m_axi_gp1_rstn;
+reg r_s_axi_gp0_rstn;
+reg r_s_axi_gp1_rstn;
+reg r_s_axi_hp0_rstn;
+reg r_s_axi_hp1_rstn;
+reg r_s_axi_hp2_rstn;
+reg r_s_axi_hp3_rstn;
+reg r_s_axi_acp_rstn;
+
+assign rst_out_n = por_rst_n & sys_rst_n;
+
+assign fclk_reset0_n = !fabric_rst_n[0];
+assign fclk_reset1_n = !fabric_rst_n[1];
+assign fclk_reset2_n = !fabric_rst_n[2];
+assign fclk_reset3_n = !fabric_rst_n[3];
+
+assign fpga_acp_reset_n = !fabric_rst_n[24];
+
+assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
+assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
+assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
+assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
+
+assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
+assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
+assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
+assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
+
+task fpga_soft_reset;
+input[31:0] reset_ctrl;
+ begin 
+  fabric_rst_n[0] = reset_ctrl[0];
+  fabric_rst_n[1] = reset_ctrl[1];
+  fabric_rst_n[2] = reset_ctrl[2];
+  fabric_rst_n[3] = reset_ctrl[3];
+  
+  fabric_rst_n[12] = reset_ctrl[12];
+  fabric_rst_n[13] = reset_ctrl[13];
+  fabric_rst_n[16] = reset_ctrl[16];
+  fabric_rst_n[17] = reset_ctrl[17];
+  
+  fabric_rst_n[20] = reset_ctrl[20];
+  fabric_rst_n[21] = reset_ctrl[21];
+  fabric_rst_n[22] = reset_ctrl[22];
+  fabric_rst_n[23] = reset_ctrl[23];
+  
+  fabric_rst_n[24] = reset_ctrl[24];
+ end
+endtask
+
+always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
+
+always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      m_axi_gp0_rstn = 1'b0;
+	else
+      m_axi_gp0_rstn = 1'b1;
+  end
+
+always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      m_axi_gp1_rstn = 1'b0;
+	else
+      m_axi_gp1_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_gp0_rstn = 1'b0;
+	else
+      s_axi_gp0_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_gp1_rstn = 1'b0;
+	else
+      s_axi_gp1_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp0_rstn = 1'b0;
+	else
+      s_axi_hp0_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp1_rstn = 1'b0;
+	else
+      s_axi_hp1_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp2_rstn = 1'b0;
+	else
+      s_axi_hp2_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_hp3_rstn = 1'b0;
+	else
+      s_axi_hp3_rstn = 1'b1;
+  end
+
+always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
+  begin 
+    if (!(por_rst_n & sys_rst_n))
+      s_axi_acp_rstn = 1'b0;
+	else
+      s_axi_acp_rstn = 1'b1;
+  end
+
+
+always@(*) begin
+  if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n !=  1'b0) && (sys_rst_n != 1'b1)) begin
+     $display(" Error:processing_system7_vip_v1_0_3_gen_reset.  PS_PORB and PS_SRSTB must be driven to known state");
+     $finish();
+  end
+end
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_gen_clock.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that generates FCLK clocks and internal clock for Zynq VIP. 
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_gen_clock(
+ ps_clk, 
+ sw_clk,
+ 
+ fclk_clk3,
+ fclk_clk2,
+ fclk_clk1,
+ fclk_clk0
+);
+
+input ps_clk;
+output sw_clk;
+
+output fclk_clk3;
+output fclk_clk2;
+output fclk_clk1;
+output fclk_clk0;
+
+parameter freq_clk3 = 50;
+parameter freq_clk2 = 50;
+parameter freq_clk1 = 50;
+parameter freq_clk0 = 50;
+
+reg clk0 = 1'b0;
+reg clk1 = 1'b0;
+reg clk2 = 1'b0;
+reg clk3 = 1'b0;
+reg sw_clk = 1'b0;
+
+assign fclk_clk0 = clk0;
+assign fclk_clk1 = clk1;
+assign fclk_clk2 = clk2;
+assign fclk_clk3 = clk3;
+ 
+real clk3_p = (1000.00/freq_clk3)/2;
+real clk2_p = (1000.00/freq_clk2)/2;
+real clk1_p = (1000.00/freq_clk1)/2;
+real clk0_p = (1000.00/freq_clk0)/2;
+
+always #(clk3_p) clk3 = !clk3;
+always #(clk2_p) clk2 = !clk2;
+always #(clk1_p) clk1 = !clk1;
+always #(clk0_p) clk0 = !clk0;
+
+always #(0.5) sw_clk = !sw_clk;
+
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_ddrc.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Module that acts as controller for sparse memory (DDR).
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3_ddrc(
+ rstn,
+ sw_clk,
+
+/* Goes to port 0 of DDR */
+ ddr_wr_ack_port0,
+ ddr_wr_dv_port0,
+ ddr_rd_req_port0,
+ ddr_rd_dv_port0,
+ ddr_wr_addr_port0,
+ ddr_wr_data_port0,
+ ddr_wr_bytes_port0,
+ ddr_rd_addr_port0,
+ ddr_rd_data_port0,
+ ddr_rd_bytes_port0,
+ ddr_wr_qos_port0,
+ ddr_rd_qos_port0,
+
+
+/* Goes to port 1 of DDR */
+ ddr_wr_ack_port1,
+ ddr_wr_dv_port1,
+ ddr_rd_req_port1,
+ ddr_rd_dv_port1,
+ ddr_wr_addr_port1,
+ ddr_wr_data_port1,
+ ddr_wr_bytes_port1,
+ ddr_rd_addr_port1,
+ ddr_rd_data_port1,
+ ddr_rd_bytes_port1,
+ ddr_wr_qos_port1,
+ ddr_rd_qos_port1,
+
+/* Goes to port2 of DDR */
+ ddr_wr_ack_port2,
+ ddr_wr_dv_port2,
+ ddr_rd_req_port2,
+ ddr_rd_dv_port2,
+ ddr_wr_addr_port2,
+ ddr_wr_data_port2,
+ ddr_wr_bytes_port2,
+ ddr_rd_addr_port2,
+ ddr_rd_data_port2,
+ ddr_rd_bytes_port2,
+ ddr_wr_qos_port2,
+ ddr_rd_qos_port2,
+
+/* Goes to port3 of DDR */
+ ddr_wr_ack_port3,
+ ddr_wr_dv_port3,
+ ddr_rd_req_port3,
+ ddr_rd_dv_port3,
+ ddr_wr_addr_port3,
+ ddr_wr_data_port3,
+ ddr_wr_bytes_port3,
+ ddr_rd_addr_port3,
+ ddr_rd_data_port3,
+ ddr_rd_bytes_port3,
+ ddr_wr_qos_port3,
+ ddr_rd_qos_port3 
+
+);
+
+`include "processing_system7_vip_v1_0_3_local_params.v"
+
+input rstn;
+input sw_clk;
+
+output ddr_wr_ack_port0;
+input ddr_wr_dv_port0;
+input ddr_rd_req_port0;
+output ddr_rd_dv_port0;
+input[addr_width-1:0] ddr_wr_addr_port0;
+input[max_burst_bits-1:0] ddr_wr_data_port0;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
+input[addr_width-1:0] ddr_rd_addr_port0;
+output[max_burst_bits-1:0] ddr_rd_data_port0;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
+input [axi_qos_width-1:0] ddr_wr_qos_port0;
+input [axi_qos_width-1:0] ddr_rd_qos_port0;
+
+output ddr_wr_ack_port1;
+input ddr_wr_dv_port1;
+input ddr_rd_req_port1;
+output ddr_rd_dv_port1;
+input[addr_width-1:0] ddr_wr_addr_port1;
+input[max_burst_bits-1:0] ddr_wr_data_port1;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+input[addr_width-1:0] ddr_rd_addr_port1;
+output[max_burst_bits-1:0] ddr_rd_data_port1;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+input[axi_qos_width-1:0] ddr_wr_qos_port1;
+input[axi_qos_width-1:0] ddr_rd_qos_port1;
+
+output ddr_wr_ack_port2;
+input ddr_wr_dv_port2;
+input ddr_rd_req_port2;
+output ddr_rd_dv_port2;
+input[addr_width-1:0] ddr_wr_addr_port2;
+input[max_burst_bits-1:0] ddr_wr_data_port2;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+input[addr_width-1:0] ddr_rd_addr_port2;
+output[max_burst_bits-1:0] ddr_rd_data_port2;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+input[axi_qos_width-1:0] ddr_wr_qos_port2;
+input[axi_qos_width-1:0] ddr_rd_qos_port2;
+
+output ddr_wr_ack_port3;
+input ddr_wr_dv_port3;
+input ddr_rd_req_port3;
+output ddr_rd_dv_port3;
+input[addr_width-1:0] ddr_wr_addr_port3;
+input[max_burst_bits-1:0] ddr_wr_data_port3;
+input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+input[addr_width-1:0] ddr_rd_addr_port3;
+output[max_burst_bits-1:0] ddr_rd_data_port3;
+input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+input[axi_qos_width-1:0] ddr_wr_qos_port3;
+input[axi_qos_width-1:0] ddr_rd_qos_port3;
+
+wire [axi_qos_width-1:0] wr_qos;
+wire wr_req;
+wire [max_burst_bits-1:0] wr_data;
+wire [addr_width-1:0] wr_addr;
+wire [max_burst_bytes_width:0] wr_bytes;
+reg wr_ack;
+
+wire [axi_qos_width-1:0] rd_qos;
+reg [max_burst_bits-1:0] rd_data;
+wire [addr_width-1:0] rd_addr;
+wire [max_burst_bytes_width:0] rd_bytes;
+reg rd_dv;
+wire rd_req;
+
+processing_system7_vip_v1_0_3_arb_wr_4 ddr_write_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ddr_wr_qos_port0),
+ .qos2(ddr_wr_qos_port1),
+ .qos3(ddr_wr_qos_port2),
+ .qos4(ddr_wr_qos_port3),
+   
+ .prt_dv1(ddr_wr_dv_port0),
+ .prt_dv2(ddr_wr_dv_port1),
+ .prt_dv3(ddr_wr_dv_port2),
+ .prt_dv4(ddr_wr_dv_port3),
+   
+ .prt_data1(ddr_wr_data_port0),
+ .prt_data2(ddr_wr_data_port1),
+ .prt_data3(ddr_wr_data_port2),
+ .prt_data4(ddr_wr_data_port3),
+   
+ .prt_addr1(ddr_wr_addr_port0),
+ .prt_addr2(ddr_wr_addr_port1),
+ .prt_addr3(ddr_wr_addr_port2),
+ .prt_addr4(ddr_wr_addr_port3),
+   
+ .prt_bytes1(ddr_wr_bytes_port0),
+ .prt_bytes2(ddr_wr_bytes_port1),
+ .prt_bytes3(ddr_wr_bytes_port2),
+ .prt_bytes4(ddr_wr_bytes_port3),
+   
+ .prt_ack1(ddr_wr_ack_port0),
+ .prt_ack2(ddr_wr_ack_port1),
+ .prt_ack3(ddr_wr_ack_port2),
+ .prt_ack4(ddr_wr_ack_port3),
+   
+ .prt_qos(wr_qos),
+ .prt_req(wr_req),
+ .prt_data(wr_data),
+ .prt_addr(wr_addr),
+ .prt_bytes(wr_bytes),
+ .prt_ack(wr_ack)
+
+);
+
+processing_system7_vip_v1_0_3_arb_rd_4 ddr_read_ports (
+ .rstn(rstn),
+ .sw_clk(sw_clk),
+   
+ .qos1(ddr_rd_qos_port0),
+ .qos2(ddr_rd_qos_port1),
+ .qos3(ddr_rd_qos_port2),
+ .qos4(ddr_rd_qos_port3),
+   
+ .prt_req1(ddr_rd_req_port0),
+ .prt_req2(ddr_rd_req_port1),
+ .prt_req3(ddr_rd_req_port2),
+ .prt_req4(ddr_rd_req_port3),
+   
+ .prt_data1(ddr_rd_data_port0),
+ .prt_data2(ddr_rd_data_port1),
+ .prt_data3(ddr_rd_data_port2),
+ .prt_data4(ddr_rd_data_port3),
+   
+ .prt_addr1(ddr_rd_addr_port0),
+ .prt_addr2(ddr_rd_addr_port1),
+ .prt_addr3(ddr_rd_addr_port2),
+ .prt_addr4(ddr_rd_addr_port3),
+   
+ .prt_bytes1(ddr_rd_bytes_port0),
+ .prt_bytes2(ddr_rd_bytes_port1),
+ .prt_bytes3(ddr_rd_bytes_port2),
+ .prt_bytes4(ddr_rd_bytes_port3),
+   
+ .prt_dv1(ddr_rd_dv_port0),
+ .prt_dv2(ddr_rd_dv_port1),
+ .prt_dv3(ddr_rd_dv_port2),
+ .prt_dv4(ddr_rd_dv_port3),
+   
+ .prt_qos(rd_qos),
+ .prt_req(rd_req),
+ .prt_data(rd_data),
+ .prt_addr(rd_addr),
+ .prt_bytes(rd_bytes),
+ .prt_dv(rd_dv)
+
+);
+
+processing_system7_vip_v1_0_3_sparse_mem ddr();
+
+reg [1:0] state;
+always@(posedge sw_clk or negedge rstn)
+begin
+if(!rstn) begin
+ wr_ack <= 0; 
+ rd_dv <= 0;
+ state <= 2'd0;
+end else begin
+ case(state) 
+ 0:begin
+     state <= 0;
+     wr_ack <= 0;
+     rd_dv <= 0;
+     if(wr_req) begin
+       ddr.write_mem(wr_data , wr_addr, wr_bytes); 
+       wr_ack <= 1;
+       state <= 1;
+     end
+     if(rd_req) begin
+       ddr.read_mem(rd_data,rd_addr, rd_bytes); 
+       rd_dv <= 1;
+       state <= 1;
+     end
+
+   end
+ 1:begin
+       wr_ack <= 0;
+       rd_dv  <= 0;
+       state <= 0;
+   end 
+
+ endcase
+end /// if
+end// always
+
+endmodule 
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_axi_slave.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as PS AXI Slave  port interface. 
+ *               It uses AXI3 Slave  VIP
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+import axi_vip_pkg::*;
+
+module processing_system7_vip_v1_0_3_axi_slave (
+  S_RESETN,
+
+  S_ARREADY,
+  S_AWREADY,
+  S_BVALID,
+  S_RLAST,
+  S_RVALID,
+  S_WREADY,
+  S_BRESP,
+  S_RRESP,
+  S_RDATA,
+  S_BID,
+  S_RID,
+  S_ACLK,
+  S_ARVALID,
+  S_AWVALID,
+  S_BREADY,
+  S_RREADY,
+  S_WLAST,
+  S_WVALID,
+  S_ARBURST,
+  S_ARLOCK,
+  S_ARSIZE,
+  S_AWBURST,
+  S_AWLOCK,
+  S_AWSIZE,
+  S_ARPROT,
+  S_AWPROT,
+  S_ARADDR,
+  S_AWADDR,
+  S_WDATA,
+  S_ARCACHE,
+  S_ARLEN,
+  S_AWCACHE,
+  S_AWLEN,
+  S_WSTRB,
+  S_ARID,
+  S_AWID,
+  S_WID,
+  
+  S_AWQOS,
+  S_ARQOS,
+
+  SW_CLK,
+  WR_DATA_ACK_OCM,
+  WR_DATA_ACK_DDR,
+  WR_ADDR,
+  WR_DATA,
+  WR_BYTES,
+  WR_DATA_VALID_OCM,
+  WR_DATA_VALID_DDR,
+  WR_QOS,
+
+  RD_QOS, 
+  RD_REQ_DDR,
+  RD_REQ_OCM,
+  RD_REQ_REG,
+  RD_ADDR,
+  RD_DATA_OCM,
+  RD_DATA_DDR,
+  RD_DATA_REG,
+  RD_BYTES,
+  RD_DATA_VALID_OCM,
+  RD_DATA_VALID_DDR,
+  RD_DATA_VALID_REG
+
+);
+  parameter enable_this_port = 0;  
+  parameter slave_name = "Slave";
+  parameter data_bus_width = 32;
+  parameter address_bus_width = 32;
+  parameter id_bus_width = 6;
+  parameter slave_base_address = 0;
+  parameter slave_high_address = 4;
+  parameter max_outstanding_transactions = 8;
+  parameter exclusive_access_supported = 0;
+  parameter max_wr_outstanding_transactions = 8;
+  parameter max_rd_outstanding_transactions = 8;
+  
+  `include "processing_system7_vip_v1_0_3_local_params.v"
+
+  /* Local parameters only for this module */
+  /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
+     This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
+     1-bit extra width than the no.of.bits needed to represent the outstanding transactions
+     Extra bit helps in generating the empty and full flags
+  */
+  parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
+  parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
+
+  /* RESP data */
+  parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; 
+  parameter rsp_lsb = 0;
+  parameter rsp_msb = axi_rsp_width-1;
+  parameter rsp_id_lsb = rsp_msb + 1;  
+  parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;  
+
+  input  S_RESETN;
+
+  output  S_ARREADY;
+  output  S_AWREADY;
+  output  S_BVALID;
+  output  S_RLAST;
+  output  S_RVALID;
+  output  S_WREADY;
+  output  [axi_rsp_width-1:0] S_BRESP;
+  output  [axi_rsp_width-1:0] S_RRESP;
+  output  [data_bus_width-1:0] S_RDATA;
+  output  [id_bus_width-1:0] S_BID;
+  output  [id_bus_width-1:0] S_RID;
+  input S_ACLK;
+  input S_ARVALID;
+  input S_AWVALID;
+  input S_BREADY;
+  input S_RREADY;
+  input S_WLAST;
+  input S_WVALID;
+  input [axi_brst_type_width-1:0] S_ARBURST;
+  input [axi_lock_width-1:0] S_ARLOCK;
+  input [axi_size_width-1:0] S_ARSIZE;
+  input [axi_brst_type_width-1:0] S_AWBURST;
+  input [axi_lock_width-1:0] S_AWLOCK;
+  input [axi_size_width-1:0] S_AWSIZE;
+  input [axi_prot_width-1:0] S_ARPROT;
+  input [axi_prot_width-1:0] S_AWPROT;
+  input [address_bus_width-1:0] S_ARADDR;
+  input [address_bus_width-1:0] S_AWADDR;
+  input [data_bus_width-1:0] S_WDATA;
+  input [axi_cache_width-1:0] S_ARCACHE;
+  input [axi_cache_width-1:0] S_ARLEN;
+  
+  input [axi_qos_width-1:0] S_ARQOS;
+ 
+  input [axi_cache_width-1:0] S_AWCACHE;
+  input [axi_len_width-1:0] S_AWLEN;
+
+  input [axi_qos_width-1:0] S_AWQOS;
+  input [(data_bus_width/8)-1:0] S_WSTRB;
+  input [id_bus_width-1:0] S_ARID;
+  input [id_bus_width-1:0] S_AWID;
+  input [id_bus_width-1:0] S_WID;
+
+  input SW_CLK;
+  input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+  output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+  output reg [max_burst_bits-1:0] WR_DATA;
+  output reg [addr_width-1:0] WR_ADDR;
+  output reg [max_burst_bytes_width:0] WR_BYTES;
+  output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
+  output reg [addr_width-1:0] RD_ADDR;
+  input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
+  output reg[max_burst_bytes_width:0] RD_BYTES;
+  input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
+  output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
+  wire net_ARVALID;
+  wire net_AWVALID;
+  wire net_WVALID;
+  bit [31:0] static_count;
+
+  real s_aclk_period;
+
+   axi_slv_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) slv;
+
+   axi_vip_v1_1_1_top #(
+     .C_AXI_PROTOCOL(1),
+     .C_AXI_INTERFACE_MODE(2),
+     .C_AXI_ADDR_WIDTH(address_bus_width),
+     .C_AXI_WDATA_WIDTH(data_bus_width),
+     .C_AXI_RDATA_WIDTH(data_bus_width),
+     .C_AXI_WID_WIDTH(id_bus_width),
+     .C_AXI_RID_WIDTH(id_bus_width),
+     .C_AXI_AWUSER_WIDTH(0),
+     .C_AXI_ARUSER_WIDTH(0),
+     .C_AXI_WUSER_WIDTH(0),
+     .C_AXI_RUSER_WIDTH(0),
+     .C_AXI_BUSER_WIDTH(0),
+     .C_AXI_SUPPORTS_NARROW(1),
+     .C_AXI_HAS_BURST(1),
+     .C_AXI_HAS_LOCK(1),
+     .C_AXI_HAS_CACHE(1),
+     .C_AXI_HAS_REGION(0),
+     .C_AXI_HAS_PROT(1),
+     .C_AXI_HAS_QOS(1),
+     .C_AXI_HAS_WSTRB(1),
+     .C_AXI_HAS_BRESP(1),
+     .C_AXI_HAS_RRESP(1),
+ 	 .C_AXI_HAS_ARESETN(1)
+   ) slave (
+     .aclk(S_ACLK),
+     .aclken(1'B1),
+     .aresetn(S_RESETN),
+     .s_axi_awid(S_AWID),
+     .s_axi_awaddr(S_AWADDR),
+     .s_axi_awlen(S_AWLEN),
+     .s_axi_awsize(S_AWSIZE),
+     .s_axi_awburst(S_AWBURST),
+     .s_axi_awlock(S_AWLOCK),
+     .s_axi_awcache(S_AWCACHE),
+     .s_axi_awprot(S_AWPROT),
+     .s_axi_awregion(4'B0),
+     .s_axi_awqos(4'h0),
+     .s_axi_awuser(1'B0),
+     .s_axi_awvalid(S_AWVALID),
+     .s_axi_awready(S_AWREADY),
+     .s_axi_wid(S_WID),
+     .s_axi_wdata(S_WDATA),
+     .s_axi_wstrb(S_WSTRB),
+     .s_axi_wlast(S_WLAST),
+     .s_axi_wuser(1'B0),
+     .s_axi_wvalid(S_WVALID),
+     .s_axi_wready(S_WREADY),
+     .s_axi_bid(S_BID),
+     .s_axi_bresp(S_BRESP),
+     .s_axi_buser(),
+     .s_axi_bvalid(S_BVALID),
+     .s_axi_bready(S_BREADY),
+     .s_axi_arid(S_ARID),
+     .s_axi_araddr(S_ARADDR),
+     .s_axi_arlen(S_ARLEN),
+     .s_axi_arsize(S_ARSIZE),
+     .s_axi_arburst(S_ARBURST),
+     .s_axi_arlock(S_ARLOCK),
+     .s_axi_arcache(S_ARCACHE),
+     .s_axi_arprot(S_ARPROT),
+     .s_axi_arregion(4'B0),
+     .s_axi_arqos(S_ARQOS),
+     .s_axi_aruser(1'B0),
+     .s_axi_arvalid(S_ARVALID),
+     .s_axi_arready(S_ARREADY),
+     .s_axi_rid(S_RID),
+     .s_axi_rdata(S_RDATA),
+     .s_axi_rresp(S_RRESP),
+     .s_axi_rlast(S_RLAST),
+     .s_axi_ruser(),
+     .s_axi_rvalid(S_RVALID),
+     .s_axi_rready(S_RREADY),
+     .m_axi_awid(),
+     .m_axi_awaddr(),
+     .m_axi_awlen(),
+     .m_axi_awsize(),
+     .m_axi_awburst(),
+     .m_axi_awlock(),
+     .m_axi_awcache(),
+     .m_axi_awprot(),
+     .m_axi_awregion(),
+     .m_axi_awqos(),
+     .m_axi_awuser(),
+     .m_axi_awvalid(),
+     .m_axi_awready(1'b0),
+     .m_axi_wid(),
+     .m_axi_wdata(),
+     .m_axi_wstrb(),
+     .m_axi_wlast(),
+     .m_axi_wuser(),
+     .m_axi_wvalid(),
+     .m_axi_wready(1'b0),
+     .m_axi_bid(12'h000),
+     .m_axi_bresp(2'b00),
+     .m_axi_buser(1'B0),
+     .m_axi_bvalid(1'b0),
+     .m_axi_bready(),
+     .m_axi_arid(),
+     .m_axi_araddr(),
+     .m_axi_arlen(),
+     .m_axi_arsize(),
+     .m_axi_arburst(),
+     .m_axi_arlock(),
+     .m_axi_arcache(),
+     .m_axi_arprot(),
+     .m_axi_arregion(),
+     .m_axi_arqos(),
+     .m_axi_aruser(),
+     .m_axi_arvalid(),
+     .m_axi_arready(1'b0),
+     .m_axi_rid(12'h000),
+     .m_axi_rdata(32'h00000000),
+     .m_axi_rresp(2'b00),
+     .m_axi_rlast(1'b0),
+     .m_axi_ruser(1'B0),
+     .m_axi_rvalid(1'b0),
+     .m_axi_rready()
+   );
+
+   xil_axi_cmd_beat twc, trc;
+   xil_axi_write_beat twd;
+   xil_axi_read_beat trd;
+   axi_transaction twr, trr;
+   axi_ready_gen           awready_gen;
+   axi_ready_gen           wready_gen;
+   axi_ready_gen           arready_gen;
+   integer i,j,k;
+
+  initial begin
+   slv = new("slv",slave.IF);
+   twr = new("twr");
+   trr = new("trr");
+   wready_gen = slv.wr_driver.create_ready("wready");
+   slv.monitor.axi_wr_cmd_port.set_enabled();
+   slv.monitor.axi_wr_beat_port.set_enabled();
+   slv.monitor.axi_rd_cmd_port.set_enabled();
+   slv.wr_driver.set_transaction_depth(max_wr_outstanding_transactions);
+   slv.rd_driver.set_transaction_depth(max_rd_outstanding_transactions);
+   slv.start_slave();
+  end
+
+  /* Latency type and Debug/Error Control */
+  reg[1:0] latency_type = RANDOM_CASE;
+  reg DEBUG_INFO = 1; 
+  reg STOP_ON_ERROR = 1'b1; 
+
+  /* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
+  reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
+  reg [int_wr_cntr_width-1:0]    wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
+  wire wr_fifo_empty;
+
+  /* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
+  reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
+  real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
+  reg  awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received 
+
+  /* Address Write Channel handshake*/
+  reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  awsize [0:max_wr_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  awprot [0:max_wr_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  awlock [0:max_wr_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  awcache [0:max_wr_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  awbrst [0:max_wr_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  awlen [0:max_wr_outstanding_transactions-1];
+  reg aw_flag [0:max_wr_outstanding_transactions-1];
+  reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
+  reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
+  reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
+  wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
+
+  /* internal fifos to store burst write data, ID & strobes*/
+  reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
+  reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
+  reg [max_burst_bytes_width:0] valid_bytes = 0; /// total valid bytes received in a complete burst transfer
+  reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag  to indicate WLAST received
+  wire wd_fifo_full;
+
+  /* Write Data Channel and Write Response handshake signals*/
+  reg [int_wr_cntr_width-1:0] wd_cnt = 0;
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
+  reg [addr_width-1:0] aligned_wr_addr;
+  reg [max_burst_bytes_width:0] valid_data_bytes;
+  reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
+  reg [axi_rsp_width-1:0] bresp;
+  reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_bresp;
+  reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
+  integer wr_latency_count;
+  reg  wr_delayed;
+  wire bresp_fifo_empty;
+
+  /* states for managing read/write to WR_FIFO */ 
+  parameter SEND_DATA = 0,  WAIT_ACK = 1;
+  reg state;
+
+  /* Qos*/
+  reg [axi_qos_width-1:0] ar_qos, aw_qos;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
+    else
+     $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
+   end
+  end
+
+//initial slave.set_disable_reset_value_checks(1); 
+  initial begin
+     repeat(2) @(posedge S_ACLK);
+     if(!enable_this_port) begin
+//      slave.set_channel_level_info(0);
+//      slave.set_function_level_info(0);
+     end 
+//   slave.RESPONSE_TIMEOUT = 0;
+  end
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set Latency type to be used */
+  task set_latency_type;
+    input[1:0] lat;
+  begin
+   if(enable_this_port) 
+    latency_type = lat;
+   else begin
+    if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set ARQoS to be used */
+  task set_arqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    ar_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
+   end
+
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set AWQoS to be used */
+  task set_awqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    aw_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+  /* get the wr latency number */
+  function [31:0] get_wr_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;            
+    AVG_CASE    : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;            
+    WORST_CASE  : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2'b00   : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min); 
+                    2'b01   : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg); 
+                    default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* get the rd latency number */
+  function [31:0] get_rd_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;            
+    AVG_CASE    : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;            
+    WORST_CASE  : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2'b00   : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min); 
+                    2'b01   : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg); 
+                    default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* Store the Clock cycle time period */
+  always@(S_RESETN)
+  begin
+   if(S_RESETN) begin
+    @(posedge S_ACLK);
+    s_aclk_period = $time;
+    @(posedge S_ACLK);
+    s_aclk_period = $time - s_aclk_period;
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+ /* Check for any WRITE/READs when this port is disabled */
+ always@(S_AWVALID or S_WVALID or S_ARVALID)
+ begin
+  if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
+    $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
+    $stop;
+  end
+ end
+
+ /*--------------------------------------------------------------------------------*/
+
+ 
+  assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
+  assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
+  assign net_WVALID  = enable_this_port ? S_WVALID : 1'b0;
+
+  assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
+  assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
+  assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
+  assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
+ 
+
+  /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)
+   aw_time_cnt = 0;
+  else begin
+  if(net_AWVALID && S_AWREADY) begin
+     awvalid_receive_time[aw_time_cnt] = $time;
+     awvalid_flag[aw_time_cnt] = 1'b1;
+     aw_time_cnt = aw_time_cnt + 1;
+     if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0; 
+   end
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_AWVALID && S_AWREADY) begin
+    if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos; 
+    else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS; 
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  always@(aw_fifo_full)
+  begin
+  if(aw_fifo_full && DEBUG_INFO) 
+    $display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  /* Address Write Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    aw_cnt = 0;
+  end else begin
+    if(!aw_fifo_full) begin 
+        slv.monitor.axi_wr_cmd_port.get(twc);
+        awaddr[aw_cnt[int_wr_cntr_width-2:0]] = twc.addr;
+        awlen[aw_cnt[int_wr_cntr_width-2:0]]  = twc.len;
+        awsize[aw_cnt[int_wr_cntr_width-2:0]] = twc.size;
+        awbrst[aw_cnt[int_wr_cntr_width-2:0]] = twc.burst;
+        awlock[aw_cnt[int_wr_cntr_width-2:0]] = twc.lock;
+        awcache[aw_cnt[int_wr_cntr_width-2:0]]= twc.cache;
+        awprot[aw_cnt[int_wr_cntr_width-2:0]] = twc.prot;
+        awid[aw_cnt[int_wr_cntr_width-2:0]]   = twc.id;
+        aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
+        aw_cnt   = aw_cnt + 1;
+        if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+          aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
+          aw_cnt[int_wr_cntr_width-2:0] = 0;
+        end
+    end // if (!aw_fifo_full)
+  end /// if else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+
+  /* Write Data Channel Handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   wd_cnt = 0;
+  end else begin
+    if(!wd_fifo_full && S_WVALID) begin
+      slv.monitor.axi_wr_beat_port.get(twd);
+      for(i = 0; i < (2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]); i = i+1) begin
+	    burst_data[wd_cnt[int_wr_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i];
+      end
+      valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
+      if (twd.last) begin
+        wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1;
+        burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]] = valid_bytes;
+		valid_bytes = 0;
+        wd_cnt   = wd_cnt + 1;
+        if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+          wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
+          wd_cnt[int_wr_cntr_width-2:0] = 0;
+        end
+  	  end
+    end /// if
+  end /// else
+  end /// always
+  
+  /* Align the wrap data for write transaction */
+  task automatic get_wrap_aligned_wr_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  output [addr_width-1:0] start_addr; /// aligned start address
+  input  [addr_width-1:0] addr;
+  input  [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input  [max_burst_bytes_width:0] v_bytes;
+  reg    [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data;
+    temp_data = 0;
+    wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+      temp_data = temp_data << 8;
+      temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
+      wrp_data = wrp_data << 8;
+      wrp_bytes = wrp_bytes - 1;
+    end
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data << (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+   
+  /* Calculate the Response for each read/write transaction */
+  function [axi_rsp_width-1:0] calculate_resp;
+  input rd_wr; // indicates Read(1) or Write(0) transaction 
+  input [addr_width-1:0] awaddr; 
+  input [axi_prot_width-1:0] awprot;
+  reg [axi_rsp_width-1:0] rsp;
+  begin
+    rsp = AXI_OK;
+    /* Address Decode */
+    if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
+     rsp = AXI_SLV_ERR; //slave error
+     $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
+    end
+    if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
+     rsp = AXI_SLV_ERR; //slave error
+     $display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
+    end
+    if(secure_access_enabled && awprot[1])
+     rsp = AXI_DEC_ERR; // decode error
+    calculate_resp = rsp;
+  end
+  endfunction
+  /*--------------------------------------------------------------------------------*/
+
+  /* Store the Write response for each write transaction */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   wr_bresp_cnt = 0;
+   wr_fifo_wr_ptr = 0;
+  end else begin
+   enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
+   /* calculate bresp only when AWVALID && WLAST is received */
+   if(enable_write_bresp) begin
+     aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]]    = 0;
+     wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
+  
+     bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
+     fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
+     /* Fill WR data FIFO */
+     if(bresp === AXI_OK) begin
+       if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
+         get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]);      /// gives wrapped start address
+       end else begin
+         aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]]; 
+         aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
+       end
+       valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
+     end else 
+       valid_data_bytes = 0;  
+
+     wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
+     wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1; 
+     wr_bresp_cnt = wr_bresp_cnt+1;
+     if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+       wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
+       wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
+     end
+   end
+  end // else
+  end // always
+  /*--------------------------------------------------------------------------------*/
+
+  /* Send Write Response Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+   rd_bresp_cnt = 0;
+   wr_latency_count = get_wr_lat_number(1);
+   wr_delayed = 0;
+   bresp_time_cnt = 0; 
+  end else begin
+  if(static_count < 32 ) begin
+    wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); 
+    wready_gen.set_low_time(0); 
+    wready_gen.set_high_time(1); 
+    slv.wr_driver.send_wready(wready_gen);
+  end
+   if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
+     wr_delayed = 1;
+   if(!bresp_fifo_empty && wr_delayed) begin
+     slv.wr_driver.get_wr_reactive(twr);
+	 twr.set_id(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]);
+     case(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb])
+	  2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY);
+	  2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY);
+	  2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR);
+	  2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR);
+	 endcase
+   if(static_count > 32) begin
+   wready_gen.set_ready_policy(XIL_AXI_READY_GEN_SINGLE); 
+   wready_gen.set_low_time(3); 
+   wready_gen.set_high_time(3); 
+   wready_gen.set_low_time_range(3,6); 
+   wready_gen.set_high_time_range(3,6); 
+   slv.wr_driver.send_wready(wready_gen);
+  end
+   // wr_delayed = 1'b0;
+       slv.wr_driver.send(twr);
+     wr_delayed = 0;
+     awvalid_flag[bresp_time_cnt] = 1'b0;
+     bresp_time_cnt = bresp_time_cnt+1;
+     rd_bresp_cnt = rd_bresp_cnt + 1;
+     if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
+       rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
+       rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
+     end
+     if(bresp_time_cnt === max_wr_outstanding_transactions) begin
+       bresp_time_cnt = 0; 
+     end
+     wr_latency_count = get_wr_lat_number(1);
+     	 static_count++;
+   end 
+   	 static_count++;
+  end // else
+end
+  /*--------------------------------------------------------------------------------*/
+
+  /* Reading from the wr_fifo */
+  always@(negedge S_RESETN or posedge SW_CLK) begin
+  if(!S_RESETN) begin 
+   WR_DATA_VALID_DDR = 1'b0;
+   WR_DATA_VALID_OCM = 1'b0;
+   wr_fifo_rd_ptr = 0;
+   state = SEND_DATA;
+   WR_QOS = 0;
+  end else begin
+   case(state)
+   SEND_DATA :begin
+      state = SEND_DATA;
+      WR_DATA_VALID_OCM = 0;
+      WR_DATA_VALID_DDR = 0;
+      if(!wr_fifo_empty) begin
+        WR_DATA  = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
+        WR_ADDR  = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
+        WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
+        WR_QOS   = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
+        state = WAIT_ACK;
+        case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
+         OCM_MEM : WR_DATA_VALID_OCM = 1;
+         DDR_MEM : WR_DATA_VALID_DDR = 1;
+         default : state = SEND_DATA;
+        endcase
+        wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
+      end
+      end
+   WAIT_ACK :begin
+      state = WAIT_ACK;
+      if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin 
+        WR_DATA_VALID_OCM = 1'b0;
+        WR_DATA_VALID_DDR = 1'b0;
+        state = SEND_DATA;
+      end
+      end
+   endcase
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
+
+/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
+
+  /* READ CHANNELS */
+  /* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
+  reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
+  real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
+  reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
+  reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  arsize [0:max_rd_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  arprot [0:max_rd_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  arbrst [0:max_rd_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  arlen [0:max_rd_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  arcache [0:max_rd_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  arlock [0:max_rd_outstanding_transactions-1];
+  reg ar_flag [0:max_rd_outstanding_transactions-1];
+  reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
+  reg [id_bus_width-1:0]  arid [0:max_rd_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  arqos [0:max_rd_outstanding_transactions-1];
+  wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
+
+  reg [int_rd_cntr_width-1:0] rd_cnt = 0;
+  reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
+  reg [axi_rsp_width-1:0] rresp;
+  reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
+
+  /* Send Read Response  & Data Channel handshake */
+  integer rd_latency_count;
+  reg  rd_delayed;
+
+  reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
+  reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
+  wire read_fifo_full; 
+ 
+  assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
+  assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
+  assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0; 
+
+  /* Store the arvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)
+   ar_time_cnt = 0;
+  else begin
+  if(net_ARVALID && S_ARREADY) begin
+     arvalid_receive_time[ar_time_cnt] = $time;
+     arvalid_flag[ar_time_cnt] = 1'b1;
+     ar_time_cnt = ar_time_cnt + 1;
+     if(ar_time_cnt === max_rd_outstanding_transactions)
+       ar_time_cnt = 0; 
+   end 
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_ARVALID && S_ARREADY) begin
+    if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos; 
+    else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS; 
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  always@(ar_fifo_full)
+  begin
+  if(ar_fifo_full && DEBUG_INFO) 
+    $display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  /* Address Read  Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    ar_cnt = 0;
+  end else begin
+    if(!ar_fifo_full) begin
+      slv.monitor.axi_rd_cmd_port.get(trc);
+      araddr[ar_cnt[int_rd_cntr_width-2:0]] = trc.addr;
+      arlen[ar_cnt[int_rd_cntr_width-2:0]]  = trc.len;
+      arsize[ar_cnt[int_rd_cntr_width-2:0]] = trc.size;
+      arbrst[ar_cnt[int_rd_cntr_width-2:0]] = trc.burst;
+      arlock[ar_cnt[int_rd_cntr_width-2:0]] = trc.lock;
+      arcache[ar_cnt[int_rd_cntr_width-2:0]]= trc.cache;
+      arprot[ar_cnt[int_rd_cntr_width-2:0]] = trc.prot;
+      arid[ar_cnt[int_rd_cntr_width-2:0]]   = trc.id;
+      ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1;
+        ar_cnt = ar_cnt+1;
+        if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
+          ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
+          ar_cnt[int_rd_cntr_width-2:0] = 0;
+        end 
+    end /// if(!ar_fifo_full)
+  end /// if else
+  end /// always*/
+  /*--------------------------------------------------------------------------------*/
+
+  /* Align Wrap data for read transaction*/
+  task automatic get_wrap_aligned_rd_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  input [addr_width-1:0] addr;
+  input [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input [max_burst_bytes_width:0] v_bytes;
+  reg [addr_width-1:0] start_addr;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data  = b_data;
+    temp_data = 0;
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data >> 8;
+     temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
+     wrp_data = wrp_data >> 8;
+     wrp_bytes = wrp_bytes - 1;
+    end
+    temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data >> (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+   
+  parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
+  reg [addr_width-1:0] temp_read_address;
+  reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
+  reg rd_fifo_state; 
+  reg invalid_rd_req;
+  /* get the data from memory && also calculate the rresp*/
+  always@(negedge S_RESETN or posedge SW_CLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_wr_ptr = 0; 
+   wr_rresp_cnt =0;
+   rd_fifo_state = RD_DATA_REQ;
+   temp_rd_valid_bytes = 0;
+   temp_read_address = 0;
+   RD_REQ_DDR = 0;
+   RD_REQ_OCM = 0;
+   RD_REQ_REG = 0;
+   RD_QOS  = 0;
+   invalid_rd_req = 0;
+  end else begin
+   case(rd_fifo_state)
+    RD_DATA_REQ : begin
+     rd_fifo_state = RD_DATA_REQ;
+     RD_REQ_DDR = 0;
+     RD_REQ_OCM = 0;
+     RD_REQ_REG = 0;
+     RD_QOS  = 0;
+     if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
+       ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
+       rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
+       fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
+       temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
+
+       if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
+        temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
+       else 
+        temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       if(rresp === AXI_OK) begin 
+        case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
+          OCM_MEM : RD_REQ_OCM = 1;
+          DDR_MEM : RD_REQ_DDR = 1;
+          REG_MEM : RD_REQ_REG = 1;
+          default : invalid_rd_req = 1;
+        endcase
+       end else
+        invalid_rd_req = 1;
+        
+       RD_QOS     = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       RD_ADDR    = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
+       RD_BYTES   = temp_rd_valid_bytes;
+       rd_fifo_state = WAIT_RD_VALID;
+       wr_rresp_cnt = wr_rresp_cnt + 1;
+       if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
+         wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
+         wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
+       end
+     end
+    end
+    WAIT_RD_VALID : begin    
+     rd_fifo_state = WAIT_RD_VALID; 
+     if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
+       if(RD_DATA_VALID_DDR)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
+       else if(RD_DATA_VALID_OCM)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
+       else if(RD_DATA_VALID_REG)
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
+       else
+         read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
+       rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
+       RD_REQ_DDR = 0;
+       RD_REQ_OCM = 0;
+       RD_REQ_REG = 0;
+       RD_QOS  = 0;
+       invalid_rd_req = 0;
+       rd_fifo_state = RD_DATA_REQ;
+     end
+    end
+   endcase
+  end /// else
+  end /// always
+
+  /*--------------------------------------------------------------------------------*/
+  reg[max_burst_bytes_width:0] rd_v_b;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
+  reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
+
+  xil_axi_data_beat new_data;
+
+
+  /* Read Data Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_rd_ptr = 0;
+   rd_cnt = 0;
+   rd_latency_count = get_rd_lat_number(1);
+   rd_delayed = 0;
+   rresp_time_cnt = 0;
+   rd_v_b = 0;
+  end else begin
+     if(net_ARVALID && S_ARREADY)
+       slv.rd_driver.get_rd_reactive(trr);
+     if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) 
+       rd_delayed = 1;
+     if(!read_fifo_empty && rd_delayed)begin
+       rd_delayed = 0;  
+       arvalid_flag[rresp_time_cnt] = 1'b0;
+       rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
+       temp_read_data =  read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
+       rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
+
+       if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
+         get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
+         temp_read_data = temp_wrap_data;
+       end 
+       temp_read_rsp = 0;
+       repeat(axi_burst_len) begin
+         temp_read_rsp = temp_read_rsp >> axi_rsp_width;
+         temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
+       end 
+	   case (arsize[rd_cnt[int_rd_cntr_width-2:0]])
+         3'b000: trr.size = XIL_AXI_SIZE_1BYTE;
+         3'b001: trr.size = XIL_AXI_SIZE_2BYTE;
+         3'b010: trr.size = XIL_AXI_SIZE_4BYTE;
+         3'b011: trr.size = XIL_AXI_SIZE_8BYTE;
+         3'b100: trr.size = XIL_AXI_SIZE_16BYTE;
+         3'b101: trr.size = XIL_AXI_SIZE_32BYTE;
+         3'b110: trr.size = XIL_AXI_SIZE_64BYTE;
+         3'b111: trr.size = XIL_AXI_SIZE_128BYTE;
+       endcase
+	   trr.len = arlen[rd_cnt[int_rd_cntr_width-2:0]];
+	   trr.id = (arid[rd_cnt[int_rd_cntr_width-2:0]]);
+//	   trr.data  = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))];
+	   trr.rresp = new[((2**arsize[rd_cnt[int_rd_cntr_width-2:0]])*(arlen[rd_cnt[int_rd_cntr_width-2:0]]+1))];
+       for(j = 0; j < (arlen[rd_cnt[int_rd_cntr_width-2:0]]+1); j = j+1) begin
+         for(k = 0; k < (2**arsize[rd_cnt[int_rd_cntr_width-2:0]]); k = k+1) begin
+		   new_data[(k*8)+:8] = temp_read_data[7:0];
+		   temp_read_data = temp_read_data >> 8;
+		 end
+         trr.set_data_beat(j, new_data);
+	     case(temp_read_rsp[(j*2)+:2])
+	       2'b00: trr.rresp[j] = XIL_AXI_RESP_OKAY;
+	       2'b01: trr.rresp[j] = XIL_AXI_RESP_EXOKAY;
+	       2'b10: trr.rresp[j] = XIL_AXI_RESP_SLVERR;
+	       2'b11: trr.rresp[j] = XIL_AXI_RESP_DECERR;
+	     endcase
+       end
+       slv.rd_driver.send(trr);
+       rd_cnt = rd_cnt + 1; 
+       rresp_time_cnt = rresp_time_cnt+1;
+       if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
+       if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
+         rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
+         rd_cnt[int_rd_cntr_width-2:0] = 0;
+       end
+       rd_latency_count = get_rd_lat_number(1);
+     end
+  end /// else
+  end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_axi_master.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as PS AXI Master port interface. 
+ *               It uses AXI3 Master VIP
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+import axi_vip_pkg::*;
+
+module processing_system7_vip_v1_0_3_axi_master (
+    M_RESETN,
+    M_ARVALID,
+    M_AWVALID,
+    M_BREADY,
+    M_RREADY,
+    M_WLAST,
+    M_WVALID,
+    M_ARID,
+    M_AWID,
+    M_WID,
+    M_ARBURST,
+    M_ARLOCK,
+    M_ARSIZE,
+    M_AWBURST,
+    M_AWLOCK,
+    M_AWSIZE,
+    M_ARPROT,
+    M_AWPROT,
+    M_ARADDR,
+    M_AWADDR,
+    M_WDATA,
+    M_ARCACHE,
+    M_ARLEN,
+    M_AWCACHE,
+    M_AWLEN,
+    M_ARQOS,  // not connected to AXI VIP
+    M_AWQOS,  // not connected to AXI VIP
+    M_WSTRB,
+    M_ACLK,
+    M_ARREADY,
+    M_AWREADY,
+    M_BVALID,
+    M_RLAST,
+    M_RVALID,
+    M_WREADY,
+    M_BID,
+    M_RID,
+    M_BRESP,
+    M_RRESP,
+    M_RDATA
+
+);
+   parameter enable_this_port = 0;  
+   parameter master_name = "Master";
+   parameter data_bus_width = 32;
+   parameter address_bus_width = 32;
+   parameter id_bus_width = 6;
+   parameter max_outstanding_transactions = 8;
+   parameter exclusive_access_supported = 0;
+   parameter ID = 12'hC00;
+   `include "processing_system7_vip_v1_0_3_local_params.v"
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12'b11_000_000_00_00    
+       12'b11_010_000_00_00     
+       12'b11_011_000_00_00   
+       12'b11_100_000_00_00   
+       12'b11_101_000_00_00   
+       12'b11_110_000_00_00     
+       12'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12'b11_000_001_00_00    
+       12'b11_010_001_00_00     
+       12'b11_011_001_00_00    
+       12'b11_100_001_00_00    
+       12'b11_101_001_00_00    
+       12'b11_110_001_00_00     
+       12'b11_111_001_00_00    
+   */
+
+   input  M_RESETN;
+
+   output M_ARVALID;
+   output M_AWVALID;
+   output M_BREADY;
+   output M_RREADY;
+   output M_WLAST;
+   output M_WVALID;
+   output [id_bus_width-1:0] M_ARID;
+   output [id_bus_width-1:0] M_AWID;
+   output [id_bus_width-1:0] M_WID;
+   output [axi_brst_type_width-1:0] M_ARBURST;
+   output [axi_lock_width-1:0] M_ARLOCK;
+   output [axi_size_width-1:0] M_ARSIZE;
+   output [axi_brst_type_width-1:0] M_AWBURST;
+   output [axi_lock_width-1:0] M_AWLOCK;
+   output [axi_size_width-1:0] M_AWSIZE;
+   output [axi_prot_width-1:0] M_ARPROT;
+   output [axi_prot_width-1:0] M_AWPROT;
+   output [address_bus_width-1:0] M_ARADDR;
+   output [address_bus_width-1:0] M_AWADDR;
+   output [data_bus_width-1:0] M_WDATA;
+   output [axi_cache_width-1:0] M_ARCACHE;
+   output [axi_len_width-1:0] M_ARLEN;
+   output [axi_qos_width-1:0] M_ARQOS;  // not connected to AXI VIP
+   output [axi_cache_width-1:0] M_AWCACHE;
+   output [axi_len_width-1:0] M_AWLEN;
+   output [axi_qos_width-1:0] M_AWQOS;  // not connected to AXI VIP
+   output [(data_bus_width/8)-1:0] M_WSTRB;
+   input M_ACLK;
+   input M_ARREADY;
+   input M_AWREADY;
+   input M_BVALID;
+   input M_RLAST;
+   input M_RVALID;
+   input M_WREADY;
+   input [id_bus_width-1:0] M_BID;
+   input [id_bus_width-1:0] M_RID;
+   input [axi_rsp_width-1:0] M_BRESP;
+   input [axi_rsp_width-1:0] M_RRESP;
+   input [data_bus_width-1:0] M_RDATA;
+
+   wire net_RESETN;
+   wire net_RVALID;
+   wire net_BVALID;
+   reg DEBUG_INFO = 1'b1; 
+   reg STOP_ON_ERROR = 1'b1; 
+
+   integer use_id_no = 0;
+
+   assign M_ARQOS = 'b0;
+   assign M_AWQOS = 'b0;
+   assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0;
+   assign net_RVALID = enable_this_port ? M_RVALID : 1'b0;
+   assign net_BVALID = enable_this_port ? M_BVALID : 1'b0;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name);
+    else
+     $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name);
+   end
+  end
+
+   initial master.IF.xilinx_slave_ready_check_enable = 0; 
+   initial begin
+     repeat(2) @(posedge M_ACLK);
+     if(!enable_this_port) begin
+//      master.set_channel_level_info(0);
+//      master.set_function_level_info(0);
+     end
+//     master.RESPONSE_TIMEOUT = 0;
+   end
+
+   axi_mst_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) mst;
+
+   axi_vip_v1_1_1_top #(
+     .C_AXI_PROTOCOL(1),
+     .C_AXI_INTERFACE_MODE(0),
+     .C_AXI_ADDR_WIDTH(address_bus_width),
+     .C_AXI_WDATA_WIDTH(data_bus_width),
+     .C_AXI_RDATA_WIDTH(data_bus_width),
+     .C_AXI_WID_WIDTH(id_bus_width),
+     .C_AXI_RID_WIDTH(id_bus_width),
+     .C_AXI_AWUSER_WIDTH(0),
+     .C_AXI_ARUSER_WIDTH(0),
+     .C_AXI_WUSER_WIDTH(0),
+     .C_AXI_RUSER_WIDTH(0),
+     .C_AXI_BUSER_WIDTH(0),
+     .C_AXI_SUPPORTS_NARROW(1),
+     .C_AXI_HAS_BURST(1),
+     .C_AXI_HAS_LOCK(1),
+     .C_AXI_HAS_CACHE(1),
+     .C_AXI_HAS_REGION(0),
+     .C_AXI_HAS_PROT(1),
+     .C_AXI_HAS_QOS(1),
+     .C_AXI_HAS_WSTRB(1),
+     .C_AXI_HAS_BRESP(1),
+     .C_AXI_HAS_RRESP(1),
+	 .C_AXI_HAS_ARESETN(1)
+   ) master (
+     .aclk(M_ACLK),
+     .aclken(1'B1),
+     .aresetn(net_RESETN),
+     .s_axi_awid(12'h000),
+     .s_axi_awaddr(32'B0),
+     .s_axi_awlen(4'h0),
+     .s_axi_awsize(3'B0),
+     .s_axi_awburst(2'B0),
+     .s_axi_awlock(2'b00),
+     .s_axi_awcache(4'B0),
+     .s_axi_awprot(3'B0),
+     .s_axi_awregion(4'B0),
+     .s_axi_awqos(4'B0),
+     .s_axi_awuser(1'B0),
+     .s_axi_awvalid(1'B0),
+     .s_axi_awready(),
+     .s_axi_wid(12'h000),
+     .s_axi_wdata(32'B0),
+     .s_axi_wstrb(4'B0),
+     .s_axi_wlast(1'B0),
+     .s_axi_wuser(1'B0),
+     .s_axi_wvalid(1'B0),
+     .s_axi_wready(),
+     .s_axi_bid(),
+     .s_axi_bresp(),
+     .s_axi_buser(),
+     .s_axi_bvalid(),
+     .s_axi_bready(1'B0),
+     .s_axi_arid(12'h000),
+     .s_axi_araddr(32'B0),
+     .s_axi_arlen(4'h0),
+     .s_axi_arsize(3'B0),
+     .s_axi_arburst(2'B0),
+     .s_axi_arlock(2'b00),
+     .s_axi_arcache(4'B0),
+     .s_axi_arprot(3'B0),
+     .s_axi_arregion(4'B0),
+     .s_axi_arqos(4'B0),
+     .s_axi_aruser(1'B0),
+     .s_axi_arvalid(1'B0),
+     .s_axi_arready(),
+     .s_axi_rid(),
+     .s_axi_rdata(),
+     .s_axi_rresp(),
+     .s_axi_rlast(),
+     .s_axi_ruser(),
+     .s_axi_rvalid(),
+     .s_axi_rready(1'B0),
+     .m_axi_awid(M_AWID),
+     .m_axi_awaddr(M_AWADDR),
+     .m_axi_awlen(M_AWLEN),
+     .m_axi_awsize(M_AWSIZE),
+     .m_axi_awburst(M_AWBURST),
+     .m_axi_awlock(M_AWLOCK),
+     .m_axi_awcache(M_AWCACHE),
+     .m_axi_awprot(M_AWPROT),
+     .m_axi_awregion(),
+     .m_axi_awqos(),
+     .m_axi_awuser(),
+     .m_axi_awvalid(M_AWVALID),
+     .m_axi_awready(M_AWREADY),
+     .m_axi_wid(M_WID),
+     .m_axi_wdata(M_WDATA),
+     .m_axi_wstrb(M_WSTRB),
+     .m_axi_wlast(M_WLAST),
+     .m_axi_wuser(),
+     .m_axi_wvalid(M_WVALID),
+     .m_axi_wready(M_WREADY),
+     .m_axi_bid(M_BID),
+     .m_axi_bresp(M_BRESP),
+     .m_axi_buser(1'B0),
+     .m_axi_bvalid(M_BVALID),
+     .m_axi_bready(M_BREADY),
+     .m_axi_arid(M_ARID),
+     .m_axi_araddr(M_ARADDR),
+     .m_axi_arlen(M_ARLEN),
+     .m_axi_arsize(M_ARSIZE),
+     .m_axi_arburst(M_ARBURST),
+     .m_axi_arlock(M_ARLOCK),
+     .m_axi_arcache(M_ARCACHE),
+     .m_axi_arprot(M_ARPROT),
+     .m_axi_arregion(),
+     .m_axi_arqos(M_ARQOS),
+     .m_axi_aruser(),
+     .m_axi_arvalid(M_ARVALID),
+     .m_axi_arready(M_ARREADY),
+     .m_axi_rid(M_RID),
+     .m_axi_rdata(M_RDATA),
+     .m_axi_rresp(M_RRESP),
+     .m_axi_rlast(M_RLAST),
+     .m_axi_ruser(1'B0),
+     .m_axi_rvalid(M_RVALID),
+     .m_axi_rready(M_RREADY)
+   );
+
+   axi_transaction tw, tr;
+   axi_monitor_transaction tr_m, tw_m;
+   axi_ready_gen           bready_gen;
+   axi_ready_gen           rready_gen;
+
+  initial begin
+   mst = new("mst",master.IF);
+   tr_m = new("master monitor trans");
+   mst.start_master();
+  end
+
+/* Call to VIP APIs */
+task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
+ integer i;
+ xil_axi_burst_t burst_i;
+ xil_axi_size_t  size_i;
+ xil_axi_data_beat new_data;
+ xil_axi_lock_t  lock_i;
+ integer datasize;
+ case (burst)
+   2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED;
+   2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR;
+   2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP;
+   2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD;
+ endcase
+ case (siz)
+   3'b000: size_i = XIL_AXI_SIZE_1BYTE;
+   3'b001: size_i = XIL_AXI_SIZE_2BYTE;
+   3'b010: size_i = XIL_AXI_SIZE_4BYTE;
+   3'b011: size_i = XIL_AXI_SIZE_8BYTE;
+   3'b100: size_i = XIL_AXI_SIZE_16BYTE;
+   3'b101: size_i = XIL_AXI_SIZE_32BYTE;
+   3'b110: size_i = XIL_AXI_SIZE_64BYTE;
+   3'b111: size_i = XIL_AXI_SIZE_128BYTE;
+ endcase
+ case (lck)
+   2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK;
+   2'b01: lock_i = XIL_AXI_ALOCK_EXCL;
+   2'b10: lock_i = XIL_AXI_ALOCK_LOCKED;
+   2'b11: lock_i = XIL_AXI_ALOCK_RSVD;
+ endcase
+ if(enable_this_port)begin
+  fork 
+    begin
+      rready_gen = mst.rd_driver.create_ready("rready");
+      rready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC);
+      rready_gen.set_high_time(len+1);
+      mst.rd_driver.send_rready(rready_gen);
+	end
+	begin
+      tr = mst.rd_driver.create_transaction("write_tran");
+      mst.rd_driver.set_transaction_depth(max_outstanding_transactions);
+      assert(tr.randomize());
+      tr.set_read_cmd(addr,burst_i,ID,len,size_i);
+      tr.set_cache(cache);
+      tr.set_lock(lock_i);
+      tr.set_prot(prot);
+      mst.rd_driver.send(tr);
+	end
+  join
+   mst.monitor.item_collected_port.get(tr_m);
+   datasize = 0;
+   for(i = 0; i < (len+1); i = i+1) begin
+     new_data = tr_m.get_data_beat(i);
+     for(int k = 0; k < (2**siz); k = k+1) begin
+	   data[(datasize*8)+:8] = new_data[(k*8)+:8];
+	   datasize = datasize+1;
+	 end
+	 response = response << 2;
+     response[1:0] = tr_m.rresp[i];
+   end
+ end else begin
+   $display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+ integer i,j;
+ xil_axi_burst_t burst_i;
+ xil_axi_size_t  size_i;
+ xil_axi_lock_t  lock_i;
+ xil_axi_data_beat new_data;
+ xil_axi_strb_beat new_strb;
+
+ case (burst)
+   2'b00: burst_i = XIL_AXI_BURST_TYPE_FIXED;
+   2'b01: burst_i = XIL_AXI_BURST_TYPE_INCR;
+   2'b10: burst_i = XIL_AXI_BURST_TYPE_WRAP;
+   2'b11: burst_i = XIL_AXI_BURST_TYPE_RSVD;
+ endcase
+ case (siz)
+   3'b000: size_i = XIL_AXI_SIZE_1BYTE;
+   3'b001: size_i = XIL_AXI_SIZE_2BYTE;
+   3'b010: size_i = XIL_AXI_SIZE_4BYTE;
+   3'b011: size_i = XIL_AXI_SIZE_8BYTE;
+   3'b100: size_i = XIL_AXI_SIZE_16BYTE;
+   3'b101: size_i = XIL_AXI_SIZE_32BYTE;
+   3'b110: size_i = XIL_AXI_SIZE_64BYTE;
+   3'b111: size_i = XIL_AXI_SIZE_128BYTE;
+ endcase
+ case (lck)
+   2'b00: lock_i = XIL_AXI_ALOCK_NOLOCK;
+   2'b01: lock_i = XIL_AXI_ALOCK_EXCL;
+   2'b10: lock_i = XIL_AXI_ALOCK_LOCKED;
+   2'b11: lock_i = XIL_AXI_ALOCK_RSVD;
+ endcase
+ if(enable_this_port)begin
+   fork 
+     begin
+       bready_gen = mst.wr_driver.create_ready("bready");
+       bready_gen.set_ready_policy(XIL_AXI_READY_GEN_OSC);
+       bready_gen.set_high_time(1);
+       mst.wr_driver.send_bready(bready_gen);
+     end
+     begin
+       tw = mst.wr_driver.create_transaction("write_tran");
+       mst.wr_driver.set_transaction_depth(max_outstanding_transactions);
+       assert(tw.randomize());
+       tw.set_write_cmd(addr,burst_i,ID,len,size_i);
+       tw.set_cache(cache);
+       tw.set_lock(lock_i);
+       tw.set_prot(prot);
+       for(i = 0; i < (len+1); i = i+1) begin
+         for(j = 0; j < (2**siz); j = j+1) begin
+           new_data[j*8+:8] = data[7:0];
+		   new_strb[j*1+:1] = 1'b1;
+           data = data >> 8;
+		 end
+         tw.set_data_beat(i, new_data);
+		 tw.set_strb_beat(i, new_strb);
+       end
+       mst.wr_driver.send(tw);
+     end
+   join
+   mst.monitor.item_collected_port.get(tw_m);
+   response = tw_m.bresp;
+ end else begin
+   $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+ integer i;
+ if(enable_this_port)begin
+   write_burst(addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+ end else begin
+   $display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end
+endtask 
+
+/* local */
+function automatic[id_bus_width-1:0] get_id;
+input dummy; 
+begin
+ case(use_id_no)
+  // l2m1 (CPU000)
+  0 : get_id = 12'b11_000_000_00_00;   
+  1 : get_id = 12'b11_010_000_00_00;    
+  2 : get_id = 12'b11_011_000_00_00;  
+  3 : get_id = 12'b11_100_000_00_00;  
+  4 : get_id = 12'b11_101_000_00_00;  
+  5 : get_id = 12'b11_110_000_00_00;    
+  6 : get_id = 12'b11_111_000_00_00;    
+  // l2m1 (CPU001)
+  7 : get_id = 12'b11_000_001_00_00;   
+  8 : get_id = 12'b11_010_001_00_00;    
+  9 : get_id = 12'b11_011_001_00_00;   
+ 10 : get_id = 12'b11_100_001_00_00;   
+ 11 : get_id = 12'b11_101_001_00_00;   
+ 12 : get_id = 12'b11_110_001_00_00;    
+ 13 : get_id = 12'b11_111_001_00_00;   
+ endcase
+ if(use_id_no == 13)
+  use_id_no = 0;
+ else
+  use_id_no = use_id_no+1;
+end
+endfunction
+
+/* Write data from file */
+task automatic write_from_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] wr_size;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] wresp,rwrsp;
+reg [addr_width-1:0] addr;
+reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
+integer bytes;
+integer trnsfr_bytes;
+integer wr_fd;
+integer succ;
+integer trnsfr_lngth;
+reg concurrent; 
+integer i;
+
+reg [id_bus_width-1:0] wr_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+begin
+if(!enable_this_port) begin
+ $display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+
+ addr = start_addr;
+ bytes = wr_size;
+ wresp = 0;
+ concurrent = $random; 
+ if(bytes > (axi_burst_len * data_bus_width/8))
+  trnsfr_bytes = (axi_burst_len * data_bus_width/8);
+ else
+  trnsfr_bytes = bytes;
+ 
+ if(bytes > (axi_burst_len * data_bus_width/8))
+  trnsfr_lngth = axi_burst_len-1;
+ else if(bytes%(data_bus_width/8) == 0)
+  trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+ else 
+  trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+ wr_id = ID;
+ wr_fd = $fopen(file_name,"r");
+ 
+ while (bytes > 0) begin
+   repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
+    wr_data = wr_data >> data_bus_width;
+    succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
+   end
+   write_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes >= (axi_burst_len * data_bus_width/8) )
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
+   else
+    trnsfr_bytes = bytes;
+ 
+   if(bytes > (axi_burst_len * data_bus_width/8))
+    trnsfr_lngth = axi_burst_len-1;
+   else if(bytes%(data_bus_width/8) == 0)
+    trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+   else 
+    trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+   wresp = wresp | rwrsp;
+ end /// while 
+ response = wresp;
+end
+end
+endtask
+
+/* Read data to file */
+task automatic read_to_file;
+input [(max_chars*8)-1:0] file_name;
+input [addr_width-1:0] start_addr;
+input [int_width-1:0] rd_size;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] rresp, rrrsp;
+reg [addr_width-1:0] addr;
+integer bytes;
+integer trnsfr_lngth;
+reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
+integer rd_fd;
+reg [id_bus_width-1:0] rd_id;
+
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+begin
+if(!enable_this_port) begin
+ $display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+  siz =  2; 
+  burst = 1;
+  lck = 0;
+  cache = 0;
+  prot = 0;
+
+  addr = start_addr;
+  rresp = 0;
+  bytes = rd_size;
+  
+  rd_id = ID;
+  
+  if(bytes > (axi_burst_len * data_bus_width/8))
+   trnsfr_lngth = axi_burst_len-1;
+  else if(bytes%(data_bus_width/8) == 0)
+   trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+  else 
+   trnsfr_lngth = bytes/(data_bus_width/8);
+ 
+  rd_fd = $fopen(file_name,"w");
+  
+  while (bytes > 0) begin
+    read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
+    repeat(trnsfr_lngth+1) begin
+     $fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
+     rd_data = rd_data >> data_bus_width;
+    end
+    
+    addr = addr + (trnsfr_lngth+1)*4;
+
+    if(bytes >= (axi_burst_len * data_bus_width/8) )
+     bytes = bytes - (axi_burst_len * data_bus_width/8); //
+    else
+     bytes = 0;
+ 
+    if(bytes > (axi_burst_len * data_bus_width/8))
+     trnsfr_lngth = axi_burst_len-1;
+    else if(bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = bytes/(data_bus_width/8) - 1;
+    else 
+     trnsfr_lngth = bytes/(data_bus_width/8);
+
+    rresp = rresp | rrrsp;
+  end /// while 
+  response = rresp;
+end
+end
+endtask
+
+/* Write data (used for transfer size <= 128 Bytes */
+task automatic write_data;
+input [addr_width-1:0] start_addr;
+input [max_transfer_bytes_width:0] wr_size;
+input [(max_transfer_bytes*8)-1:0] w_data;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] wresp,rwrsp;
+reg [addr_width-1:0] addr;
+reg [7:0] bytes,tmp_bytes;
+integer trnsfr_bytes;
+reg [(max_transfer_bytes*8)-1:0] wr_data;
+integer trnsfr_lngth;
+reg concurrent; 
+
+reg [id_bus_width-1:0] wr_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+
+integer pad_bytes;
+begin
+if(!enable_this_port) begin
+ $display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ addr = start_addr;
+ bytes = wr_size;
+ wresp = 0;
+ wr_data = w_data;
+ concurrent = $random; 
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
+ wr_id = ID;
+ if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
+   trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0]; 
+   trnsfr_lngth = axi_burst_len-1;
+ end else begin 
+   trnsfr_bytes = bytes;
+   tmp_bytes   = bytes + pad_bytes;//start_addr[1:0];
+   if(tmp_bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+   else 
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+ end
+
+ while (bytes > 0) begin
+   write_burst(addr, trnsfr_lngth,  siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
+   wr_data = wr_data >> (trnsfr_bytes*8);
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes  > (axi_burst_len * data_bus_width/8)) begin
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+    trnsfr_lngth = axi_burst_len-1;
+   end else begin 
+     trnsfr_bytes = bytes;
+     tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+     if(tmp_bytes%(data_bus_width/8) == 0)
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+     else 
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+   end
+   wresp = wresp | rwrsp;
+ end /// while 
+ response = wresp;
+end
+end
+endtask
+
+/* Read data (used for transfer size <= 128 Bytes */
+task automatic read_data;
+input [addr_width-1:0] start_addr;
+input [max_transfer_bytes_width:0] rd_size;
+output [(max_transfer_bytes*8)-1:0] r_data;
+output [axi_rsp_width-1:0] response;
+reg [axi_rsp_width-1:0] rresp,rdrsp;
+reg [addr_width-1:0] addr;
+reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
+integer trnsfr_bytes;
+reg [(max_transfer_bytes*8)-1 : 0] rd_data;
+reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
+integer total_rcvd_bytes;
+integer trnsfr_lngth;
+integer i;
+reg [id_bus_width-1:0] rd_id;
+
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+
+integer pad_bytes;
+
+begin
+if(!enable_this_port) begin
+ $display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name);
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ addr = start_addr;
+ bytes = rd_size;
+ rresp = 0;
+ total_rcvd_bytes = 0;
+ rd_data = 0; 
+ rd_id = ID;
+
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
+
+ if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
+   trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+   trnsfr_lngth = axi_burst_len-1;
+ end else begin 
+   trnsfr_bytes = bytes;
+   tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+   if(tmp_bytes%(data_bus_width/8) == 0)
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+   else 
+     trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+ end
+ while (bytes > 0) begin
+   read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
+   for(i = 0; i < trnsfr_bytes; i = i+1) begin
+     rd_data = rd_data >> 8;
+     rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
+     rcv_rd_data =  rcv_rd_data >> 8;
+     total_rcvd_bytes = total_rcvd_bytes+1;
+   end
+   bytes = bytes - trnsfr_bytes;
+   addr = addr + trnsfr_bytes;
+   if(bytes  > (axi_burst_len * data_bus_width/8)) begin
+    trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0]; 
+    trnsfr_lngth = 15;
+   end else begin 
+     trnsfr_bytes = bytes;
+     tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
+     if(tmp_bytes%(data_bus_width/8) == 0)
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
+     else 
+       trnsfr_lngth = tmp_bytes/(data_bus_width/8);
+   end
+   rresp = rresp | rdrsp;
+ end /// while 
+ rd_data =  rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
+ r_data = rd_data;
+ response = rresp;
+end
+end
+endtask
+
+
+/* Wait Register Update in PL */
+/* Issue a series of 1 burst length reads until the expected data pattern is received */
+
+task automatic wait_reg_update;
+input [addr_width-1:0] addri;
+input [data_width-1:0] datai;
+input [data_width-1:0] maski;
+input [int_width-1:0] time_interval;
+input [int_width-1:0] time_out;
+output [data_width-1:0] data_o;
+output upd_done;
+
+reg [addr_width-1:0] addr;
+reg [data_width-1:0] data_i;
+reg [data_width-1:0] mask_i;
+integer time_int;
+integer timeout;
+
+reg [axi_rsp_width-1:0] rdrsp;
+reg [id_bus_width-1:0] rd_id;
+reg [axi_size_width-1:0] siz;
+reg [axi_brst_type_width-1:0] burst;
+reg [axi_lock_width-1:0] lck;
+reg [axi_cache_width-1:0] cache;
+reg [axi_prot_width-1:0] prot; 
+reg [data_width-1:0] rcv_data;
+integer trnsfr_lngth; 
+reg rd_loop;
+reg timed_out; 
+integer i;
+integer cycle_cnt;
+
+begin
+addr = addri;
+data_i = datai;
+mask_i = maski;
+time_int = time_interval;
+timeout = time_out;
+timed_out = 0;
+cycle_cnt = 0;
+
+if(!enable_this_port) begin
+ $display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name);
+ upd_done = 0;
+ if(STOP_ON_ERROR) $stop;
+end else begin
+ rd_id = ID;
+ siz =  2; 
+ burst = 1;
+ lck = 0;
+ cache = 0;
+ prot = 0;
+ trnsfr_lngth = 0;
+ rd_loop = 1;
+ fork 
+  begin
+    while(!timed_out & rd_loop) begin
+      cycle_cnt = cycle_cnt + 1;
+      if(cycle_cnt >= timeout) timed_out = 1;
+      @(posedge M_ACLK);
+    end
+  end
+  begin
+    while (rd_loop) begin 
+     if(DEBUG_INFO)
+       $display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr); 
+     read_burst(addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
+     if(DEBUG_INFO)
+       $display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data); 
+     if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
+       rd_loop = 0;
+     else
+       repeat(time_int) @(posedge M_ACLK);
+    end /// while 
+  end 
+ join
+ data_o = rcv_data & ~mask_i; 
+ if(timed_out) begin
+   $display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name);
+   if(STOP_ON_ERROR) $stop;
+ end else
+   upd_done = 1;
+end
+end
+endtask
+
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3_afi_slave.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Model that acts as AFI port interface. It uses AXI3 Slave VIP
+ *               from Cadence.
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+import axi_vip_pkg::*;
+
+module processing_system7_vip_v1_0_3_afi_slave (
+  S_RESETN,
+
+  S_ARREADY,
+  S_AWREADY,
+  S_BVALID,
+  S_RLAST,
+  S_RVALID,
+  S_WREADY,
+  S_BRESP,
+  S_RRESP,
+  S_RDATA,
+  S_BID,
+  S_RID,
+  S_ACLK,
+  S_ARVALID,
+  S_AWVALID,
+  S_BREADY,
+  S_RREADY,
+  S_WLAST,
+  S_WVALID,
+  S_ARBURST,
+  S_ARLOCK,
+  S_ARSIZE,
+  S_AWBURST,
+  S_AWLOCK,
+  S_AWSIZE,
+  S_ARPROT,
+  S_AWPROT,
+  S_ARADDR,
+  S_AWADDR,
+  S_WDATA,
+  S_ARCACHE,
+  S_ARLEN,
+  S_AWCACHE,
+  S_AWLEN,
+  S_WSTRB,
+  S_ARID,
+  S_AWID,
+  S_WID,
+  
+  S_AWQOS,
+  S_ARQOS,
+
+  SW_CLK,
+  WR_DATA_ACK_OCM,
+  WR_DATA_ACK_DDR,
+  WR_ADDR,
+  WR_DATA,
+  WR_BYTES,
+  WR_DATA_VALID_OCM,
+  WR_DATA_VALID_DDR,
+  WR_QOS,
+  
+  RD_REQ_DDR,
+  RD_REQ_OCM,
+  RD_ADDR,
+  RD_DATA_OCM,
+  RD_DATA_DDR,
+  RD_BYTES,
+  RD_QOS,
+  RD_DATA_VALID_OCM,
+  RD_DATA_VALID_DDR,
+  S_RDISSUECAP1_EN,
+  S_WRISSUECAP1_EN,
+  S_RCOUNT,
+  S_WCOUNT,
+  S_RACOUNT,
+  S_WACOUNT
+
+);
+  parameter enable_this_port = 0;  
+  parameter slave_name = "Slave";
+  parameter data_bus_width = 32;
+  parameter address_bus_width = 32;
+  parameter id_bus_width = 6;
+  parameter slave_base_address = 0;
+  parameter slave_high_address = 4;
+  parameter max_outstanding_transactions = 8;
+  parameter exclusive_access_supported = 0;
+
+  `include "processing_system7_vip_v1_0_3_local_params.v"
+
+  /* Local parameters only for this module */
+  /* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
+     This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
+     1-bit extra width than the no.of.bits needed to represent the outstanding transactions
+     Extra bit helps in generating the empty and full flags
+  */
+  parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
+
+  /* RESP data */
+  parameter rsp_fifo_bits = axi_rsp_width+id_bus_width; 
+  parameter rsp_lsb = 0;
+  parameter rsp_msb = axi_rsp_width-1;
+  parameter rsp_id_lsb = rsp_msb + 1;  
+  parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;  
+
+  input  S_RESETN;
+
+  output  S_ARREADY;
+  output  S_AWREADY;
+  output  S_BVALID;
+  output  S_RLAST;
+  output  S_RVALID;
+  output  S_WREADY;
+  output  [axi_rsp_width-1:0] S_BRESP;
+  output  [axi_rsp_width-1:0] S_RRESP;
+  output  [data_bus_width-1:0] S_RDATA;
+  output  [id_bus_width-1:0] S_BID;
+  output  [id_bus_width-1:0] S_RID;
+  input S_ACLK;
+  input S_ARVALID;
+  input S_AWVALID;
+  input S_BREADY;
+  input S_RREADY;
+  input S_WLAST;
+  input S_WVALID;
+  input [axi_brst_type_width-1:0] S_ARBURST;
+  input [axi_lock_width-1:0] S_ARLOCK;
+  input [axi_size_width-1:0] S_ARSIZE;
+  input [axi_brst_type_width-1:0] S_AWBURST;
+  input [axi_lock_width-1:0] S_AWLOCK;
+  input [axi_size_width-1:0] S_AWSIZE;
+  input [axi_prot_width-1:0] S_ARPROT;
+  input [axi_prot_width-1:0] S_AWPROT;
+  input [address_bus_width-1:0] S_ARADDR;
+  input [address_bus_width-1:0] S_AWADDR;
+  input [data_bus_width-1:0] S_WDATA;
+  input [axi_cache_width-1:0] S_ARCACHE;
+  input [axi_cache_width-1:0] S_ARLEN;
+  
+  input [axi_qos_width-1:0] S_ARQOS;
+ 
+  input [axi_cache_width-1:0] S_AWCACHE;
+  input [axi_len_width-1:0] S_AWLEN;
+
+  input [axi_qos_width-1:0] S_AWQOS;
+  input [(data_bus_width/8)-1:0] S_WSTRB;
+  input [id_bus_width-1:0] S_ARID;
+  input [id_bus_width-1:0] S_AWID;
+  input [id_bus_width-1:0] S_WID;
+
+  input SW_CLK;
+  input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
+  output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
+  output [max_burst_bits-1:0] WR_DATA;
+  output [addr_width-1:0] WR_ADDR;
+  output [max_transfer_bytes_width:0] WR_BYTES;
+  output reg RD_REQ_OCM, RD_REQ_DDR;
+  output reg [addr_width-1:0] RD_ADDR;
+  input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
+  output reg[max_transfer_bytes_width:0] RD_BYTES;
+  input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
+  output [axi_qos_width-1:0] WR_QOS;
+  output reg [axi_qos_width-1:0] RD_QOS;
+ 
+  input S_RDISSUECAP1_EN;
+  input S_WRISSUECAP1_EN;
+
+  output [7:0] S_RCOUNT;
+  output [7:0] S_WCOUNT;
+  output [2:0] S_RACOUNT;
+  output [5:0] S_WACOUNT;
+
+  wire net_ARVALID;
+  wire net_AWVALID;
+  wire net_WVALID;
+
+  real s_aclk_period;
+
+     axi_slv_agent #(1,address_bus_width, data_bus_width, data_bus_width, id_bus_width,id_bus_width,0,0,0,0,0,1,1,1,1,0,1,1,1,1,1,1) slv;
+
+   axi_vip_v1_1_1_top #(
+     .C_AXI_PROTOCOL(1),
+     .C_AXI_INTERFACE_MODE(2),
+     .C_AXI_ADDR_WIDTH(address_bus_width),
+     .C_AXI_WDATA_WIDTH(data_bus_width),
+     .C_AXI_RDATA_WIDTH(data_bus_width),
+     .C_AXI_WID_WIDTH(id_bus_width),
+     .C_AXI_RID_WIDTH(id_bus_width),
+     .C_AXI_AWUSER_WIDTH(0),
+     .C_AXI_ARUSER_WIDTH(0),
+     .C_AXI_WUSER_WIDTH(0),
+     .C_AXI_RUSER_WIDTH(0),
+     .C_AXI_BUSER_WIDTH(0),
+     .C_AXI_SUPPORTS_NARROW(1),
+     .C_AXI_HAS_BURST(1),
+     .C_AXI_HAS_LOCK(1),
+     .C_AXI_HAS_CACHE(1),
+     .C_AXI_HAS_REGION(0),
+     .C_AXI_HAS_PROT(1),
+     .C_AXI_HAS_QOS(1),
+     .C_AXI_HAS_WSTRB(1),
+     .C_AXI_HAS_BRESP(1),
+     .C_AXI_HAS_RRESP(1),
+	 .C_AXI_HAS_ARESETN(1)
+   ) slave (
+     .aclk(S_ACLK),
+     .aclken(1'B1),
+     .aresetn(S_RESETN),
+     .s_axi_awid(S_AWID),
+     .s_axi_awaddr(S_AWADDR),
+     .s_axi_awlen(S_AWLEN),
+     .s_axi_awsize(S_AWSIZE),
+     .s_axi_awburst(S_AWBURST),
+     .s_axi_awlock(S_AWLOCK),
+     .s_axi_awcache(S_AWCACHE),
+     .s_axi_awprot(S_AWPROT),
+     .s_axi_awregion(4'B0),
+     .s_axi_awqos(S_AWQOS),
+     .s_axi_awuser(1'B0),
+     .s_axi_awvalid(S_AWVALID),
+     .s_axi_awready(S_AWREADY),
+     .s_axi_wid(S_WID),
+     .s_axi_wdata(S_WDATA),
+     .s_axi_wstrb(S_WSTRB),
+     .s_axi_wlast(S_WLAST),
+     .s_axi_wuser(1'B0),
+     .s_axi_wvalid(S_WVALID),
+     .s_axi_wready(S_WREADY),
+     .s_axi_bid(S_BID),
+     .s_axi_bresp(S_BRESP),
+     .s_axi_buser(),
+     .s_axi_bvalid(S_BVALID),
+     .s_axi_bready(S_BREADY),
+     .s_axi_arid(S_ARID),
+     .s_axi_araddr(S_ARADDR),
+     .s_axi_arlen(S_ARLEN),
+     .s_axi_arsize(S_ARSIZE),
+     .s_axi_arburst(S_ARBURST),
+     .s_axi_arlock(S_ARLOCK),
+     .s_axi_arcache(S_ARCACHE),
+     .s_axi_arprot(S_ARPROT),
+     .s_axi_arregion(4'B0),
+     .s_axi_arqos(S_ARQOS),
+     .s_axi_aruser(1'B0),
+     .s_axi_arvalid(S_ARVALID),
+     .s_axi_arready(S_ARREADY),
+     .s_axi_rid(S_RID),
+     .s_axi_rdata(S_RDATA),
+     .s_axi_rresp(S_RRESP),
+     .s_axi_rlast(S_RLAST),
+     .s_axi_ruser(),
+     .s_axi_rvalid(S_RVALID),
+     .s_axi_rready(S_RREADY),
+     .m_axi_awid(),
+     .m_axi_awaddr(),
+     .m_axi_awlen(),
+     .m_axi_awsize(),
+     .m_axi_awburst(),
+     .m_axi_awlock(),
+     .m_axi_awcache(),
+     .m_axi_awprot(),
+     .m_axi_awregion(),
+     .m_axi_awqos(),
+     .m_axi_awuser(),
+     .m_axi_awvalid(),
+     .m_axi_awready(1'b0),
+     .m_axi_wid(),
+     .m_axi_wdata(),
+     .m_axi_wstrb(),
+     .m_axi_wlast(),
+     .m_axi_wuser(),
+     .m_axi_wvalid(),
+     .m_axi_wready(1'b0),
+     .m_axi_bid(12'h000),
+     .m_axi_bresp(2'b00),
+     .m_axi_buser(1'B0),
+     .m_axi_bvalid(1'b0),
+     .m_axi_bready(),
+     .m_axi_arid(),
+     .m_axi_araddr(),
+     .m_axi_arlen(),
+     .m_axi_arsize(),
+     .m_axi_arburst(),
+     .m_axi_arlock(),
+     .m_axi_arcache(),
+     .m_axi_arprot(),
+     .m_axi_arregion(),
+     .m_axi_arqos(),
+     .m_axi_aruser(),
+     .m_axi_arvalid(),
+     .m_axi_arready(1'b0),
+     .m_axi_rid(12'h000),
+     .m_axi_rdata(32'h00000000),
+     .m_axi_rresp(2'b00),
+     .m_axi_rlast(1'b0),
+     .m_axi_ruser(1'B0),
+     .m_axi_rvalid(1'b0),
+     .m_axi_rready()
+   );
+
+   xil_axi_cmd_beat twc, trc;
+   xil_axi_write_beat twd;
+   xil_axi_read_beat trd;
+   axi_transaction twr, trr;
+   axi_ready_gen           awready_gen;
+   axi_ready_gen           wready_gen;
+   axi_ready_gen           arready_gen;
+   integer i,j,k;
+
+  initial begin
+   slv = new("slv",slave.IF);
+   twr = new("twr");
+   trr = new("trr");
+   slv.monitor.axi_wr_cmd_port.set_enabled();
+   slv.monitor.axi_wr_beat_port.set_enabled();
+   slv.monitor.axi_rd_cmd_port.set_enabled();
+   slv.wr_driver.set_transaction_depth(max_outstanding_transactions);
+   slv.rd_driver.set_transaction_depth(max_outstanding_transactions);
+   slv.start_slave();
+  end
+
+  wire wr_intr_fifo_full;
+  reg temp_wr_intr_fifo_full; 
+
+  /* Interconnect WR_FIFO model instance */
+  processing_system7_vip_v1_0_3_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
+
+  /* Register the async 'full' signal to S_ACLK clock */
+  always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
+
+  /* Latency type and Debug/Error Control */
+  reg[1:0] latency_type = RANDOM_CASE;
+  reg DEBUG_INFO = 1; 
+  reg STOP_ON_ERROR = 1'b1; 
+
+  /* Internal nets/regs for calling slave VIP API's*/
+  reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
+  reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
+  wire wr_fifo_empty;
+
+  /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+  reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
+  real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
+  reg  awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
+
+  /* Address Write Channel handshake*/
+  reg[int_cntr_width-1:0] aw_cnt = 0;//
+
+  /* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  awsize [0:max_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  awprot [0:max_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  awlock [0:max_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  awcache [0:max_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  awbrst [0:max_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  awlen [0:max_outstanding_transactions-1];
+  reg aw_flag [0:max_outstanding_transactions-1];
+  reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
+  reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  awqos [0:max_outstanding_transactions-1];
+  wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
+
+  /* internal fifos to store burst write data, ID & strobes*/
+  reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
+  reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
+  reg [max_burst_bytes_width:0] valid_bytes = 0; /// total valid bytes received in a complete burst transfer
+  reg wlast_flag [0:max_outstanding_transactions-1]; // flag  to indicate WLAST received
+  wire wd_fifo_full;
+
+  /* Write Data Channel and Write Response handshake signals*/
+  reg [int_cntr_width-1:0] wd_cnt = 0;
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
+  reg [addr_width-1:0] aligned_wr_addr;
+  reg [max_burst_bytes_width:0] valid_data_bytes;
+  reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
+  reg [axi_rsp_width-1:0] bresp;
+  reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_bresp;
+  reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
+  integer wr_latency_count;
+  reg  wr_delayed;
+  wire bresp_fifo_empty;
+
+  /* keep track of count values */
+  reg[7:0] wcount;
+  reg[5:0] wacount;
+
+  /* Qos*/
+  reg [axi_qos_width-1:0] ar_qos=0, aw_qos=0;
+
+  initial begin
+   if(DEBUG_INFO) begin
+    if(enable_this_port)
+     $display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
+    else
+     $display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+  /* Store the Clock cycle time period */
+          
+  always@(S_RESETN)
+  begin
+   if(S_RESETN) begin
+    @(posedge S_ACLK);
+    s_aclk_period = $time;
+    @(posedge S_ACLK);
+    s_aclk_period = $time - s_aclk_period;
+   end
+  end
+ /*--------------------------------------------------------------------------------*/
+
+//initial slave.set_disable_reset_value_checks(1); 
+  initial begin
+     repeat(2) @(posedge S_ACLK);
+     if(!enable_this_port) begin
+//      slave.set_channel_level_info(0);
+//      slave.set_function_level_info(0);
+     end 
+//   slave.RESPONSE_TIMEOUT = 0;
+  end
+ /*--------------------------------------------------------------------------------*/
+
+  /* Set Latency type to be used */
+  task set_latency_type;
+    input[1:0] lat;
+  begin
+   if(enable_this_port) 
+    latency_type = lat;
+   else begin
+    //if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+ /*--------------------------------------------------------------------------------*/
+  /* Set ARQoS to be used */
+  task set_arqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    ar_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* Set AWQoS to be used */
+  task set_awqos;
+    input[axi_qos_width-1:0] qos;
+  begin
+   if(enable_this_port) 
+    aw_qos = qos;
+   else begin
+    if(DEBUG_INFO)
+     $display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
+   end
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  /* get the wr latency number */
+  function [31:0] get_wr_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : get_wr_lat_number = afi_wr_min;            
+    AVG_CASE    : get_wr_lat_number = afi_wr_avg;            
+    WORST_CASE  : get_wr_lat_number = afi_wr_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2'b00   : get_wr_lat_number = ($random()%10+ afi_wr_min); 
+                    2'b01   : get_wr_lat_number = ($random()%40+ afi_wr_avg); 
+                    default : get_wr_lat_number = ($random()%60+ afi_wr_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+
+  /* get the rd latency number */
+  function [31:0] get_rd_lat_number;
+  input dummy;
+  reg[1:0] temp;
+  begin 
+   case(latency_type)
+    BEST_CASE   : get_rd_lat_number = afi_rd_min;            
+    AVG_CASE    : get_rd_lat_number = afi_rd_avg;            
+    WORST_CASE  : get_rd_lat_number = afi_rd_max;            
+    default     : begin  // RANDOM_CASE
+                   temp = $random;
+                   case(temp) 
+                    2'b00   : get_rd_lat_number = ($random()%10+ afi_rd_min); 
+                    2'b01   : get_rd_lat_number = ($random()%40+ afi_rd_avg); 
+                    default : get_rd_lat_number = ($random()%60+ afi_rd_max); 
+                   endcase        
+                  end
+   endcase
+  end
+  endfunction
+ /*--------------------------------------------------------------------------------*/
+ /* Check for any WRITE/READs when this port is disabled */
+ always@(S_AWVALID or S_WVALID or S_ARVALID)
+ begin
+  if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
+    $display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
+    $stop;
+  end
+ end
+
+ /*--------------------------------------------------------------------------------*/
+
+  assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
+  assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
+  assign net_WVALID  = enable_this_port ? S_WVALID : 1'b0;
+
+  assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
+  assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
+  assign bresp_fifo_full  = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
+
+  assign S_WCOUNT = wcount;
+  assign S_WACOUNT = wacount;
+
+ // FIFO_STATUS (only if AFI port) 1- full 
+ function automatic wrfifo_full ;
+ input [axi_len_width:0] fifo_space_exp;
+ integer fifo_space_left; 
+ begin
+   fifo_space_left = afi_fifo_locations - wcount;
+   if(fifo_space_left < fifo_space_exp) 
+     wrfifo_full = 1;
+   else
+     wrfifo_full = 0;
+ end
+ endfunction
+ /*--------------------------------------------------------------------------------*/
+
+ /* Store the awvalid receive time --- necessary for calculating the bresp latency */
+ always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
+ begin
+ if(!S_RESETN)
+  aw_time_cnt = 0;
+ else begin
+  if(S_AWVALID) begin
+    awvalid_receive_time[aw_time_cnt] = $time;
+    awvalid_flag[aw_time_cnt] = 1'b1;
+    aw_time_cnt = aw_time_cnt + 1;
+  end
+ end // else
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_AWVALID && S_AWREADY) begin
+    if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos; 
+    else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS; 
+  end
+  end
+
+ /* Address Write Channel handshake*/
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+   aw_cnt = 0;
+   wacount = 0;
+ end else begin
+   if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin 
+      slv.monitor.axi_wr_cmd_port.get(twc);
+      awaddr[aw_cnt[int_cntr_width-2:0]] = twc.addr;
+      awlen[aw_cnt[int_cntr_width-2:0]]  = twc.len;
+      awsize[aw_cnt[int_cntr_width-2:0]] = twc.size;
+      awbrst[aw_cnt[int_cntr_width-2:0]] = twc.burst;
+      awlock[aw_cnt[int_cntr_width-2:0]] = twc.lock;
+      awcache[aw_cnt[int_cntr_width-2:0]]= twc.cache;
+      awprot[aw_cnt[int_cntr_width-2:0]] = twc.prot;
+      awid[aw_cnt[int_cntr_width-2:0]]   = twc.id;
+      aw_flag[aw_cnt[int_cntr_width-2:0]] = 1;
+      aw_cnt   = aw_cnt + 1;
+      wacount                             = wacount + 1;
+   end // if (!aw_fifo_full)
+ end /// if else
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Write Data Channel Handshake */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  wd_cnt = 0;
+ end else begin
+    if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
+	  slv.monitor.axi_wr_beat_port.get(twd);
+      for(i = 0; i < (2**awsize[wr_bresp_cnt[int_cntr_width-2:0]]); i = i+1) begin
+        burst_data[wd_cnt[int_cntr_width-2:0]][((valid_bytes*8)+(i*8))+:8] = twd.data[i];
+      end
+      valid_bytes = valid_bytes+(2**awsize[wr_bresp_cnt[int_cntr_width-2:0]]);
+      if (twd.last) begin
+        wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
+        burst_valid_bytes[wd_cnt[int_cntr_width-2:0]] = valid_bytes;
+		valid_bytes = 0;
+        wd_cnt   = wd_cnt + 1;
+        if(wd_cnt[int_cntr_width-2:0] === (max_outstanding_transactions)) begin
+          wd_cnt[int_cntr_width-1] = ~wd_cnt[int_cntr_width-1];
+          wd_cnt[int_cntr_width-2:0] = 0;
+        end
+  	  end
+    end
+  end /// if
+ end /// always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Align the wrap data for write transaction */
+ task automatic get_wrap_aligned_wr_data;
+ output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+ output [addr_width-1:0] start_addr; /// aligned start address
+ input  [addr_width-1:0] addr;
+ input  [(data_bus_width*axi_burst_len)-1:0] b_data;
+ input  [max_burst_bytes_width:0] v_bytes;
+ reg    [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+ integer wrp_bytes;
+ integer i;
+ begin
+   start_addr = (addr/v_bytes) * v_bytes;
+   wrp_bytes = addr - start_addr;
+   wrp_data = b_data;
+   temp_data = 0;
+   wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
+   while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data << 8;
+     temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
+     wrp_data = wrp_data << 8;
+     wrp_bytes = wrp_bytes - 1;
+   end
+   wrp_bytes = addr - start_addr;
+   wrp_data = b_data << (wrp_bytes*8);
+   
+   aligned_data = (temp_data | wrp_data);
+ end
+ endtask
+ /*--------------------------------------------------------------------------------*/
+  
+ /* Calculate the Response for each read/write transaction */
+ function [axi_rsp_width-1:0] calculate_resp;
+ input [addr_width-1:0] awaddr; 
+ input [axi_prot_width-1:0] awprot;
+ reg [axi_rsp_width-1:0] rsp;
+ begin
+   rsp = AXI_OK;
+   /* Address Decode */
+   if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
+    rsp = AXI_SLV_ERR; //slave error
+    $display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
+   end
+   else if(decode_address(awaddr) === REG_MEM) begin
+    rsp = AXI_SLV_ERR; //slave error
+    $display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
+   end
+   if(secure_access_enabled && awprot[1])
+    rsp = AXI_DEC_ERR; // decode error
+   calculate_resp = rsp;
+ end
+ endfunction
+ /*--------------------------------------------------------------------------------*/
+ reg[max_burst_bits-1:0] temp_wr_data;
+ /* Store the Write response for each write transaction */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  wr_fifo_wr_ptr = 0;
+  wcount = 0;
+ end else begin
+  enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
+  /* calculate bresp only when AWVALID && WLAST is received */
+  if(enable_write_bresp) begin
+    aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]]    = 0;
+    wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
+ 
+    bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
+    /* Fill AFI_WR_data FIFO */
+    if(bresp === AXI_OK ) begin
+      if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
+        get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]);      /// gives wrapped start address
+      end else begin
+        aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]]; 
+        aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
+      end
+      valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
+    end else
+      valid_data_bytes = 0;
+    temp_wr_data = aligned_wr_data;
+    wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
+    wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
+    wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
+  end
+ end // else
+ end // always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Send Write Response Channel handshake */
+ always@(negedge S_RESETN or posedge S_ACLK)
+ begin
+ if(!S_RESETN) begin
+  rd_bresp_cnt = 0;
+  wr_latency_count = get_wr_lat_number(1);
+  wr_delayed = 0;
+  bresp_time_cnt = 0; 
+ end else begin
+  wr_delayed = 1'b0;
+  if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
+    wr_delayed = 1;
+  if(!bresp_fifo_empty && wr_delayed) begin
+    slv.wr_driver.get_wr_reactive(twr);
+	twr.set_id(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb]);
+	case(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb])
+	  2'b00: twr.set_bresp(XIL_AXI_RESP_OKAY);
+	  2'b01: twr.set_bresp(XIL_AXI_RESP_EXOKAY);
+	  2'b10: twr.set_bresp(XIL_AXI_RESP_SLVERR);
+	  2'b11: twr.set_bresp(XIL_AXI_RESP_DECERR);
+	endcase
+    slv.wr_driver.send(twr);
+    wr_delayed = 0;
+    awvalid_flag[bresp_time_cnt] = 1'b0;
+    bresp_time_cnt = bresp_time_cnt+1;
+    rd_bresp_cnt   = rd_bresp_cnt + 1;
+    wr_latency_count = get_wr_lat_number(1);
+  end 
+ end // else
+ end//always
+ /*--------------------------------------------------------------------------------*/
+ 
+ /* Write Response Channel handshake */
+ reg wr_int_state;
+ /* Reading from the wr_fifo and sending to Interconnect fifo*/
+ always@(negedge S_RESETN or posedge S_ACLK) 
+ begin
+ if(!S_RESETN) begin
+  wr_int_state = 1'b0;
+  wr_bresp_cnt = 0;
+  wr_fifo_rd_ptr = 0;
+ end else begin
+  case(wr_int_state)
+  1'b0 : begin
+    wr_int_state = 1'b0;
+    if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
+      wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
+      wr_int_state = 1'b1;
+      /* start filling the write response fifo at the same time */
+      fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
+      wcount  = wcount  - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
+      wacount = wacount - 1;
+      wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
+      wr_bresp_cnt   = wr_bresp_cnt+1;
+    end
+  end
+  1'b1 : begin
+    wr_int_state = 0;
+  end
+  endcase
+ end
+ end
+  /*--------------------------------------------------------------------------------*/
+/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
+ 
+/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
+
+/* READ CHANNELS */
+/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
+  reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
+  real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
+  reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
+  reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
+
+/* various FIFOs for storing the ADDR channel info */
+  reg [axi_size_width-1:0]  arsize [0:max_outstanding_transactions-1];
+  reg [axi_prot_width-1:0]  arprot [0:max_outstanding_transactions-1];
+  reg [axi_brst_type_width-1:0]  arbrst [0:max_outstanding_transactions-1];
+  reg [axi_len_width-1:0]  arlen [0:max_outstanding_transactions-1];
+  reg [axi_cache_width-1:0]  arcache [0:max_outstanding_transactions-1];
+  reg [axi_lock_width-1:0]  arlock [0:max_outstanding_transactions-1];
+  reg ar_flag [0:max_outstanding_transactions-1];
+  reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
+  reg [id_bus_width-1:0]  arid [0:max_outstanding_transactions-1];
+  reg [axi_qos_width-1:0]  arqos [0:max_outstanding_transactions-1];
+  wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
+
+  reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
+  reg [axi_rsp_width-1:0] rresp;
+  reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
+  reg enable_write_rresp;
+
+  /* Send Read Response & Data Channel handshake */
+  integer rd_latency_count;
+  reg  rd_delayed;
+
+  reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
+  reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
+  wire read_fifo_full; 
+
+  reg [7:0] rcount;
+  reg [2:0] racount;
+  
+  wire rd_intr_fifo_full, rd_intr_fifo_empty;
+  wire read_fifo_empty;
+
+  /* signals to communicate with interconnect RD_FIFO model */
+  reg rd_req, invalid_rd_req;
+  
+  /* REad control Info 
+    56:25 : Address (32)
+    24:22 : Size (3)
+    21:20 : BRST (2)
+    19:16 : LEN (4)
+    15:10 : RID (6)
+    9:8 : RRSP (2)
+    7:0 : byte cnt (8)
+  */
+  reg [rd_info_bits-1:0] read_control_info;   
+  reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
+  reg temp_rd_intr_fifo_empty;
+
+  processing_system7_vip_v1_0_3_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
+
+  assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
+  assign S_RCOUNT = rcount;
+  assign S_RACOUNT = racount;
+
+  /* Register the asynch signal empty coming from Interconnect READ FIFO */
+  always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
+   
+  // FIFO_STATUS (only if AFI port) 1- full 
+   function automatic rdfifo_full ;
+   input [axi_len_width:0] fifo_space_exp;
+   integer fifo_space_left; 
+   begin
+     fifo_space_left = afi_fifo_locations - rcount;
+     if(fifo_space_left < fifo_space_exp) 
+       rdfifo_full = 1;
+     else
+       rdfifo_full = 0;
+   end
+   endfunction
+
+  /* Store the arvalid receive time --- necessary for calculating the bresp latency */
+  always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
+  begin
+  if(!S_RESETN)
+   ar_time_cnt = 0;
+  else begin
+   if(S_ARVALID) begin
+     arvalid_receive_time[ar_time_cnt] = $time;
+     arvalid_flag[ar_time_cnt] = 1'b1;
+     ar_time_cnt = ar_time_cnt + 1;
+   end 
+  end // else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  always@(posedge S_ACLK)
+  begin
+  if(net_ARVALID && S_ARREADY) begin
+    if(S_ARQOS === 0) arqos[ar_cnt[int_cntr_width-2:0]] = ar_qos; 
+    else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS; 
+  end
+  end
+
+  /* Address Read  Channel handshake*/
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN) begin
+    ar_cnt = 0;
+    racount = 0;
+  end else begin
+    if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
+      slv.monitor.axi_rd_cmd_port.get(trc);
+      araddr[ar_cnt[int_cntr_width-2:0]] = trc.addr;
+      arlen[ar_cnt[int_cntr_width-2:0]]  = trc.len;
+      arsize[ar_cnt[int_cntr_width-2:0]] = trc.size;
+      arbrst[ar_cnt[int_cntr_width-2:0]] = trc.burst;
+      arlock[ar_cnt[int_cntr_width-2:0]] = trc.lock;
+      arcache[ar_cnt[int_cntr_width-2:0]]= trc.cache;
+      arprot[ar_cnt[int_cntr_width-2:0]] = trc.prot;
+      arid[ar_cnt[int_cntr_width-2:0]]   = trc.id;
+      ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
+      ar_cnt    = ar_cnt+1;
+      racount   = racount + 1;
+    end /// if(!ar_fifo_full)
+  end /// if else
+  end /// always*/
+  
+  /*--------------------------------------------------------------------------------*/
+
+  /* Align Wrap data for read transaction*/
+  task automatic get_wrap_aligned_rd_data;
+  output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
+  input [addr_width-1:0] addr;
+  input [(data_bus_width*axi_burst_len)-1:0] b_data;
+  input [max_burst_bytes_width:0] v_bytes;
+  reg [addr_width-1:0] start_addr;
+  reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
+  integer wrp_bytes;
+  integer i;
+  begin
+    start_addr = (addr/v_bytes) * v_bytes;
+    wrp_bytes = addr - start_addr;
+    wrp_data  = b_data;
+    temp_data = 0;
+    while(wrp_bytes > 0) begin /// get the data that is wrapped
+     temp_data = temp_data >> 8;
+     temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
+     wrp_data = wrp_data >> 8;
+     wrp_bytes = wrp_bytes - 1;
+    end
+    temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
+    wrp_bytes = addr - start_addr;
+    wrp_data = b_data >> (wrp_bytes*8);
+    
+    aligned_data = (temp_data | wrp_data);
+  end
+  endtask
+  /*--------------------------------------------------------------------------------*/
+
+  parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
+  reg rd_fifo_state; 
+  reg [addr_width-1:0] temp_read_address;
+  reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
+  /* get the data from memory && also calculate the rresp*/
+  always@(negedge S_RESETN or posedge SW_CLK)
+  begin
+  if(!S_RESETN)begin
+   wr_rresp_cnt =0;
+   rd_fifo_state = RD_DATA_REQ;
+   temp_rd_valid_bytes = 0;
+   temp_read_address = 0;
+   RD_REQ_DDR = 1'b0;
+   RD_REQ_OCM = 1'b0;
+   rd_req        = 0;
+   invalid_rd_req= 0;
+   RD_QOS  = 0;
+  end else begin
+   case(rd_fifo_state)
+   RD_DATA_REQ : begin
+     rd_fifo_state = RD_DATA_REQ;
+     RD_REQ_DDR = 1'b0;
+     RD_REQ_OCM = 1'b0;
+     invalid_rd_req = 0;
+     if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
+       ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
+       rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
+       temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
+
+       if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
+        temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
+       else 
+        temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
+       
+       if(rresp === AXI_OK) begin 
+         case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
+          OCM_MEM : RD_REQ_OCM = 1;
+          DDR_MEM : RD_REQ_DDR = 1;
+          default : invalid_rd_req = 1;
+         endcase
+       end else
+         invalid_rd_req = 1;
+       RD_ADDR    = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
+       RD_BYTES   = temp_rd_valid_bytes;
+       RD_QOS     = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
+       rd_fifo_state = WAIT_RD_VALID; 
+       rd_req     = 1;
+       racount    = racount - 1;
+       read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes  };
+       wr_rresp_cnt = wr_rresp_cnt + 1;
+     end
+   end
+   WAIT_RD_VALID : begin    
+     rd_fifo_state = WAIT_RD_VALID;  
+     rd_req        = 0;
+     if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
+       RD_REQ_DDR = 1'b0;
+       RD_REQ_OCM = 1'b0;
+       invalid_rd_req = 0;
+       rd_fifo_state = RD_DATA_REQ;
+     end
+   end
+   endcase
+  end /// else
+  end /// always
+  /*--------------------------------------------------------------------------------*/
+  
+  /* thread to fill in the AFI RD_FIFO */
+  reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  reg tmp_state; 
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_wr_ptr = 0; 
+   rcount = 0;
+   tmp_state = 0;
+  end else begin
+   case(tmp_state)
+   0 : begin 
+       tmp_state = 0;
+       if(!temp_rd_intr_fifo_empty) begin
+         rd_intr_fifo.read_mem(temp_rd_data);
+         tmp_state = 1;
+       end
+      end
+   1 : begin  
+       tmp_state = 1;
+       if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
+        read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
+        rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
+        rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
+        tmp_state = 0;
+       end
+      end
+    endcase
+  end
+  end
+  /*--------------------------------------------------------------------------------*/
+  
+  reg[max_burst_bytes_width:0] rd_v_b;
+  reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd;  /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
+  reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
+  reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
+
+  xil_axi_data_beat new_data;
+
+  /* Read Data Channel handshake */
+  always@(negedge S_RESETN or posedge S_ACLK)
+  begin
+  if(!S_RESETN)begin
+   rd_fifo_rd_ptr = 0;
+   rd_latency_count = get_rd_lat_number(1);
+   rd_delayed = 0;
+   rresp_time_cnt = 0;
+   rd_v_b = 0;
+  end else begin
+     if(net_ARVALID && S_ARREADY)
+       slv.rd_driver.get_rd_reactive(trr);
+     if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
+       rd_delayed = 1;
+     end
+     if(!read_fifo_empty && rd_delayed)begin
+       rd_delayed = 0;  
+       arvalid_flag[rresp_time_cnt] = 1'b0;
+       tmp_fifo_rd =  read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
+       rd_v_b      = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
+       temp_read_data =  tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
+       if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
+          get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
+          temp_read_data = aligned_rd_data;
+       end
+       temp_read_rsp = 0;
+       repeat(axi_burst_len) begin
+         temp_read_rsp = temp_read_rsp >> axi_rsp_width;
+         temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
+       end 
+	   case (tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb])
+         3'b000: trr.size = XIL_AXI_SIZE_1BYTE;
+         3'b001: trr.size = XIL_AXI_SIZE_2BYTE;
+         3'b010: trr.size = XIL_AXI_SIZE_4BYTE;
+         3'b011: trr.size = XIL_AXI_SIZE_8BYTE;
+         3'b100: trr.size = XIL_AXI_SIZE_16BYTE;
+         3'b101: trr.size = XIL_AXI_SIZE_32BYTE;
+         3'b110: trr.size = XIL_AXI_SIZE_64BYTE;
+         3'b111: trr.size = XIL_AXI_SIZE_128BYTE;
+       endcase
+	   trr.len = tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb];
+	   trr.id = (tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb]);
+//     trr.data  = new[((2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb])*(tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1))];
+	   trr.rresp = new[((2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb])*(tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1))];
+       for(j = 0; j < (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1); j = j+1) begin
+         for(k = 0; k < (2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]); k = k+1) begin
+		   new_data[(k*8)+:8] = temp_read_data[7:0];
+		   temp_read_data = temp_read_data >> 8;
+		 end
+         trr.set_data_beat(j, new_data);
+	     case(temp_read_rsp[(j*2)+:2])
+	       2'b00: trr.rresp[j] = XIL_AXI_RESP_OKAY;
+	       2'b01: trr.rresp[j] = XIL_AXI_RESP_EXOKAY;
+	       2'b10: trr.rresp[j] = XIL_AXI_RESP_SLVERR;
+	       2'b11: trr.rresp[j] = XIL_AXI_RESP_DECERR;
+	     endcase
+       end
+//	   trr.last = 1;
+       slv.rd_driver.send(trr);
+       rcount = rcount -  (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
+       rresp_time_cnt = rresp_time_cnt+1;
+       rd_latency_count = get_rd_lat_number(1);
+       rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
+     end
+  end /// else
+  end /// always
+endmodule
+
+
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_3.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Processing_system7_vip Top (zynq_vip top)
+ *
+ *****************************************************************************/
+ `timescale 1ns/1ps
+
+module processing_system7_vip_v1_0_3
+  (
+    CAN0_PHY_TX,
+    CAN0_PHY_RX,
+    CAN1_PHY_TX,
+    CAN1_PHY_RX,
+    ENET0_GMII_TX_EN,
+    ENET0_GMII_TX_ER,
+    ENET0_MDIO_MDC,
+    ENET0_MDIO_O,
+    ENET0_MDIO_T,
+    ENET0_PTP_DELAY_REQ_RX,
+    ENET0_PTP_DELAY_REQ_TX,
+    ENET0_PTP_PDELAY_REQ_RX,
+    ENET0_PTP_PDELAY_REQ_TX,
+    ENET0_PTP_PDELAY_RESP_RX,
+    ENET0_PTP_PDELAY_RESP_TX,
+    ENET0_PTP_SYNC_FRAME_RX,
+    ENET0_PTP_SYNC_FRAME_TX,
+    ENET0_SOF_RX,
+    ENET0_SOF_TX,
+    ENET0_GMII_TXD,
+    ENET0_GMII_COL,
+    ENET0_GMII_CRS,
+    ENET0_EXT_INTIN,
+    ENET0_GMII_RX_CLK,
+    ENET0_GMII_RX_DV,
+    ENET0_GMII_RX_ER,
+    ENET0_GMII_TX_CLK,
+    ENET0_MDIO_I,
+    ENET0_GMII_RXD,
+    ENET1_GMII_TX_EN,
+    ENET1_GMII_TX_ER,
+    ENET1_MDIO_MDC,
+    ENET1_MDIO_O,
+    ENET1_MDIO_T,
+    ENET1_PTP_DELAY_REQ_RX,
+    ENET1_PTP_DELAY_REQ_TX,
+    ENET1_PTP_PDELAY_REQ_RX,
+    ENET1_PTP_PDELAY_REQ_TX,
+    ENET1_PTP_PDELAY_RESP_RX,
+    ENET1_PTP_PDELAY_RESP_TX,
+    ENET1_PTP_SYNC_FRAME_RX,
+    ENET1_PTP_SYNC_FRAME_TX,
+    ENET1_SOF_RX,
+    ENET1_SOF_TX,
+    ENET1_GMII_TXD,
+    ENET1_GMII_COL,
+    ENET1_GMII_CRS,
+    ENET1_EXT_INTIN,
+    ENET1_GMII_RX_CLK,
+    ENET1_GMII_RX_DV,
+    ENET1_GMII_RX_ER,
+    ENET1_GMII_TX_CLK,
+    ENET1_MDIO_I,
+    ENET1_GMII_RXD,
+    GPIO_I,
+    GPIO_O,
+    GPIO_T,
+    I2C0_SDA_I,
+    I2C0_SDA_O,
+    I2C0_SDA_T,
+    I2C0_SCL_I,
+    I2C0_SCL_O,
+    I2C0_SCL_T,
+    I2C1_SDA_I,
+    I2C1_SDA_O,
+    I2C1_SDA_T,
+    I2C1_SCL_I,
+    I2C1_SCL_O,
+    I2C1_SCL_T,
+    PJTAG_TCK,
+    PJTAG_TMS,
+    PJTAG_TD_I,
+    PJTAG_TD_T,
+    PJTAG_TD_O,
+    SDIO0_CLK,
+    SDIO0_CLK_FB,
+    SDIO0_CMD_O,
+    SDIO0_CMD_I,
+    SDIO0_CMD_T,
+    SDIO0_DATA_I,
+    SDIO0_DATA_O,
+    SDIO0_DATA_T,
+    SDIO0_LED,
+    SDIO0_CDN,
+    SDIO0_WP,
+    SDIO0_BUSPOW,
+    SDIO0_BUSVOLT,
+    SDIO1_CLK,
+    SDIO1_CLK_FB,
+    SDIO1_CMD_O,
+    SDIO1_CMD_I,
+    SDIO1_CMD_T,
+    SDIO1_DATA_I,
+    SDIO1_DATA_O,
+    SDIO1_DATA_T,
+    SDIO1_LED,
+    SDIO1_CDN,
+    SDIO1_WP,
+    SDIO1_BUSPOW,
+    SDIO1_BUSVOLT,
+    SPI0_SCLK_I,
+    SPI0_SCLK_O,
+    SPI0_SCLK_T,
+    SPI0_MOSI_I,
+    SPI0_MOSI_O,
+    SPI0_MOSI_T,
+    SPI0_MISO_I,
+    SPI0_MISO_O,
+    SPI0_MISO_T,
+    SPI0_SS_I,
+    SPI0_SS_O,
+    SPI0_SS1_O,
+    SPI0_SS2_O,
+    SPI0_SS_T,
+    SPI1_SCLK_I,
+    SPI1_SCLK_O,
+    SPI1_SCLK_T,
+    SPI1_MOSI_I,
+    SPI1_MOSI_O,
+    SPI1_MOSI_T,
+    SPI1_MISO_I,
+    SPI1_MISO_O,
+    SPI1_MISO_T,
+    SPI1_SS_I,
+    SPI1_SS_O,
+    SPI1_SS1_O,
+    SPI1_SS2_O,
+    SPI1_SS_T,
+    UART0_DTRN,
+    UART0_RTSN,
+    UART0_TX,
+    UART0_CTSN,
+    UART0_DCDN,
+    UART0_DSRN,
+    UART0_RIN,
+    UART0_RX,
+    UART1_DTRN,
+    UART1_RTSN,
+    UART1_TX,
+    UART1_CTSN,
+    UART1_DCDN,
+    UART1_DSRN,
+    UART1_RIN,
+    UART1_RX,
+    TTC0_WAVE0_OUT,
+    TTC0_WAVE1_OUT,
+    TTC0_WAVE2_OUT,
+    TTC0_CLK0_IN,
+    TTC0_CLK1_IN,
+    TTC0_CLK2_IN,
+    TTC1_WAVE0_OUT,
+    TTC1_WAVE1_OUT,
+    TTC1_WAVE2_OUT,
+    TTC1_CLK0_IN,
+    TTC1_CLK1_IN,
+    TTC1_CLK2_IN,
+    WDT_CLK_IN,
+    WDT_RST_OUT,
+    TRACE_CLK,
+    TRACE_CTL,
+    TRACE_DATA,
+    USB0_PORT_INDCTL,
+    USB1_PORT_INDCTL,
+    USB0_VBUS_PWRSELECT,
+    USB1_VBUS_PWRSELECT,
+    USB0_VBUS_PWRFAULT,
+    USB1_VBUS_PWRFAULT,
+    SRAM_INTIN,
+    M_AXI_GP0_ARVALID,
+    M_AXI_GP0_AWVALID,
+    M_AXI_GP0_BREADY,
+    M_AXI_GP0_RREADY,
+    M_AXI_GP0_WLAST,
+    M_AXI_GP0_WVALID,
+    M_AXI_GP0_ARID,
+    M_AXI_GP0_AWID,
+    M_AXI_GP0_WID,
+    M_AXI_GP0_ARBURST,
+    M_AXI_GP0_ARLOCK,
+    M_AXI_GP0_ARSIZE,
+    M_AXI_GP0_AWBURST,
+    M_AXI_GP0_AWLOCK,
+    M_AXI_GP0_AWSIZE,
+    M_AXI_GP0_ARPROT,
+    M_AXI_GP0_AWPROT,
+    M_AXI_GP0_ARADDR,
+    M_AXI_GP0_AWADDR,
+    M_AXI_GP0_WDATA,
+    M_AXI_GP0_ARCACHE,
+    M_AXI_GP0_ARLEN,
+    M_AXI_GP0_ARQOS,
+    M_AXI_GP0_AWCACHE,
+    M_AXI_GP0_AWLEN,
+    M_AXI_GP0_AWQOS,
+    M_AXI_GP0_WSTRB,
+    M_AXI_GP0_ACLK,
+    M_AXI_GP0_ARREADY,
+    M_AXI_GP0_AWREADY,
+    M_AXI_GP0_BVALID,
+    M_AXI_GP0_RLAST,
+    M_AXI_GP0_RVALID,
+    M_AXI_GP0_WREADY,
+    M_AXI_GP0_BID,
+    M_AXI_GP0_RID,
+    M_AXI_GP0_BRESP,
+    M_AXI_GP0_RRESP,
+    M_AXI_GP0_RDATA,
+    M_AXI_GP1_ARVALID,
+    M_AXI_GP1_AWVALID,
+    M_AXI_GP1_BREADY,
+    M_AXI_GP1_RREADY,
+    M_AXI_GP1_WLAST,
+    M_AXI_GP1_WVALID,
+    M_AXI_GP1_ARID,
+    M_AXI_GP1_AWID,
+    M_AXI_GP1_WID,
+    M_AXI_GP1_ARBURST,
+    M_AXI_GP1_ARLOCK,
+    M_AXI_GP1_ARSIZE,
+    M_AXI_GP1_AWBURST,
+    M_AXI_GP1_AWLOCK,
+    M_AXI_GP1_AWSIZE,
+    M_AXI_GP1_ARPROT,
+    M_AXI_GP1_AWPROT,
+    M_AXI_GP1_ARADDR,
+    M_AXI_GP1_AWADDR,
+    M_AXI_GP1_WDATA,
+    M_AXI_GP1_ARCACHE,
+    M_AXI_GP1_ARLEN,
+    M_AXI_GP1_ARQOS,
+    M_AXI_GP1_AWCACHE,
+    M_AXI_GP1_AWLEN,
+    M_AXI_GP1_AWQOS,
+    M_AXI_GP1_WSTRB,
+    M_AXI_GP1_ACLK,
+    M_AXI_GP1_ARREADY,
+    M_AXI_GP1_AWREADY,
+    M_AXI_GP1_BVALID,
+    M_AXI_GP1_RLAST,
+    M_AXI_GP1_RVALID,
+    M_AXI_GP1_WREADY,
+    M_AXI_GP1_BID,
+    M_AXI_GP1_RID,
+    M_AXI_GP1_BRESP,
+    M_AXI_GP1_RRESP,
+    M_AXI_GP1_RDATA,
+    S_AXI_GP0_ARREADY,
+    S_AXI_GP0_AWREADY,
+    S_AXI_GP0_BVALID,
+    S_AXI_GP0_RLAST,
+    S_AXI_GP0_RVALID,
+    S_AXI_GP0_WREADY,
+    S_AXI_GP0_BRESP,
+    S_AXI_GP0_RRESP,
+    S_AXI_GP0_RDATA,
+    S_AXI_GP0_BID,
+    S_AXI_GP0_RID,
+    S_AXI_GP0_ACLK,
+    S_AXI_GP0_ARVALID,
+    S_AXI_GP0_AWVALID,
+    S_AXI_GP0_BREADY,
+    S_AXI_GP0_RREADY,
+    S_AXI_GP0_WLAST,
+    S_AXI_GP0_WVALID,
+    S_AXI_GP0_ARBURST,
+    S_AXI_GP0_ARLOCK,
+    S_AXI_GP0_ARSIZE,
+    S_AXI_GP0_AWBURST,
+    S_AXI_GP0_AWLOCK,
+    S_AXI_GP0_AWSIZE,
+    S_AXI_GP0_ARPROT,
+    S_AXI_GP0_AWPROT,
+    S_AXI_GP0_ARADDR,
+    S_AXI_GP0_AWADDR,
+    S_AXI_GP0_WDATA,
+    S_AXI_GP0_ARCACHE,
+    S_AXI_GP0_ARLEN,
+    S_AXI_GP0_ARQOS,
+    S_AXI_GP0_AWCACHE,
+    S_AXI_GP0_AWLEN,
+    S_AXI_GP0_AWQOS,
+    S_AXI_GP0_WSTRB,
+    S_AXI_GP0_ARID,
+    S_AXI_GP0_AWID,
+    S_AXI_GP0_WID,
+    S_AXI_GP1_ARREADY,
+    S_AXI_GP1_AWREADY,
+    S_AXI_GP1_BVALID,
+    S_AXI_GP1_RLAST,
+    S_AXI_GP1_RVALID,
+    S_AXI_GP1_WREADY,
+    S_AXI_GP1_BRESP,
+    S_AXI_GP1_RRESP,
+    S_AXI_GP1_RDATA,
+    S_AXI_GP1_BID,
+    S_AXI_GP1_RID,
+    S_AXI_GP1_ACLK,
+    S_AXI_GP1_ARVALID,
+    S_AXI_GP1_AWVALID,
+    S_AXI_GP1_BREADY,
+    S_AXI_GP1_RREADY,
+    S_AXI_GP1_WLAST,
+    S_AXI_GP1_WVALID,
+    S_AXI_GP1_ARBURST,
+    S_AXI_GP1_ARLOCK,
+    S_AXI_GP1_ARSIZE,
+    S_AXI_GP1_AWBURST,
+    S_AXI_GP1_AWLOCK,
+    S_AXI_GP1_AWSIZE,
+    S_AXI_GP1_ARPROT,
+    S_AXI_GP1_AWPROT,
+    S_AXI_GP1_ARADDR,
+    S_AXI_GP1_AWADDR,
+    S_AXI_GP1_WDATA,
+    S_AXI_GP1_ARCACHE,
+    S_AXI_GP1_ARLEN,
+    S_AXI_GP1_ARQOS,
+    S_AXI_GP1_AWCACHE,
+    S_AXI_GP1_AWLEN,
+    S_AXI_GP1_AWQOS,
+    S_AXI_GP1_WSTRB,
+    S_AXI_GP1_ARID,
+    S_AXI_GP1_AWID,
+    S_AXI_GP1_WID,
+    S_AXI_ACP_AWREADY,
+    S_AXI_ACP_ARREADY,
+    S_AXI_ACP_BVALID,
+    S_AXI_ACP_RLAST,
+    S_AXI_ACP_RVALID,
+    S_AXI_ACP_WREADY,
+    S_AXI_ACP_BRESP,
+    S_AXI_ACP_RRESP,
+    S_AXI_ACP_BID,
+    S_AXI_ACP_RID,
+    S_AXI_ACP_RDATA,
+    S_AXI_ACP_ACLK,
+    S_AXI_ACP_ARVALID,
+    S_AXI_ACP_AWVALID,
+    S_AXI_ACP_BREADY,
+    S_AXI_ACP_RREADY,
+    S_AXI_ACP_WLAST,
+    S_AXI_ACP_WVALID,
+    S_AXI_ACP_ARID,
+    S_AXI_ACP_ARPROT,
+    S_AXI_ACP_AWID,
+    S_AXI_ACP_AWPROT,
+    S_AXI_ACP_WID,
+    S_AXI_ACP_ARADDR,
+    S_AXI_ACP_AWADDR,
+    S_AXI_ACP_ARCACHE,
+    S_AXI_ACP_ARLEN,
+    S_AXI_ACP_ARQOS,
+    S_AXI_ACP_AWCACHE,
+    S_AXI_ACP_AWLEN,
+    S_AXI_ACP_AWQOS,
+    S_AXI_ACP_ARBURST,
+    S_AXI_ACP_ARLOCK,
+    S_AXI_ACP_ARSIZE,
+    S_AXI_ACP_AWBURST,
+    S_AXI_ACP_AWLOCK,
+    S_AXI_ACP_AWSIZE,
+    S_AXI_ACP_ARUSER,
+    S_AXI_ACP_AWUSER,
+    S_AXI_ACP_WDATA,
+    S_AXI_ACP_WSTRB,
+    S_AXI_HP0_ARREADY,
+    S_AXI_HP0_AWREADY,
+    S_AXI_HP0_BVALID,
+    S_AXI_HP0_RLAST,
+    S_AXI_HP0_RVALID,
+    S_AXI_HP0_WREADY,
+    S_AXI_HP0_BRESP,
+    S_AXI_HP0_RRESP,
+    S_AXI_HP0_BID,
+    S_AXI_HP0_RID,
+    S_AXI_HP0_RDATA,
+    S_AXI_HP0_RCOUNT,
+    S_AXI_HP0_WCOUNT,
+    S_AXI_HP0_RACOUNT,
+    S_AXI_HP0_WACOUNT,
+    S_AXI_HP0_ACLK,
+    S_AXI_HP0_ARVALID,
+    S_AXI_HP0_AWVALID,
+    S_AXI_HP0_BREADY,
+    S_AXI_HP0_RDISSUECAP1_EN,
+    S_AXI_HP0_RREADY,
+    S_AXI_HP0_WLAST,
+    S_AXI_HP0_WRISSUECAP1_EN,
+    S_AXI_HP0_WVALID,
+    S_AXI_HP0_ARBURST,
+    S_AXI_HP0_ARLOCK,
+    S_AXI_HP0_ARSIZE,
+    S_AXI_HP0_AWBURST,
+    S_AXI_HP0_AWLOCK,
+    S_AXI_HP0_AWSIZE,
+    S_AXI_HP0_ARPROT,
+    S_AXI_HP0_AWPROT,
+    S_AXI_HP0_ARADDR,
+    S_AXI_HP0_AWADDR,
+    S_AXI_HP0_ARCACHE,
+    S_AXI_HP0_ARLEN,
+    S_AXI_HP0_ARQOS,
+    S_AXI_HP0_AWCACHE,
+    S_AXI_HP0_AWLEN,
+    S_AXI_HP0_AWQOS,
+    S_AXI_HP0_ARID,
+    S_AXI_HP0_AWID,
+    S_AXI_HP0_WID,
+    S_AXI_HP0_WDATA,
+    S_AXI_HP0_WSTRB,
+    S_AXI_HP1_ARREADY,
+    S_AXI_HP1_AWREADY,
+    S_AXI_HP1_BVALID,
+    S_AXI_HP1_RLAST,
+    S_AXI_HP1_RVALID,
+    S_AXI_HP1_WREADY,
+    S_AXI_HP1_BRESP,
+    S_AXI_HP1_RRESP,
+    S_AXI_HP1_BID,
+    S_AXI_HP1_RID,
+    S_AXI_HP1_RDATA,
+    S_AXI_HP1_RCOUNT,
+    S_AXI_HP1_WCOUNT,
+    S_AXI_HP1_RACOUNT,
+    S_AXI_HP1_WACOUNT,
+    S_AXI_HP1_ACLK,
+    S_AXI_HP1_ARVALID,
+    S_AXI_HP1_AWVALID,
+    S_AXI_HP1_BREADY,
+    S_AXI_HP1_RDISSUECAP1_EN,
+    S_AXI_HP1_RREADY,
+    S_AXI_HP1_WLAST,
+    S_AXI_HP1_WRISSUECAP1_EN,
+    S_AXI_HP1_WVALID,
+    S_AXI_HP1_ARBURST,
+    S_AXI_HP1_ARLOCK,
+    S_AXI_HP1_ARSIZE,
+    S_AXI_HP1_AWBURST,
+    S_AXI_HP1_AWLOCK,
+    S_AXI_HP1_AWSIZE,
+    S_AXI_HP1_ARPROT,
+    S_AXI_HP1_AWPROT,
+    S_AXI_HP1_ARADDR,
+    S_AXI_HP1_AWADDR,
+    S_AXI_HP1_ARCACHE,
+    S_AXI_HP1_ARLEN,
+    S_AXI_HP1_ARQOS,
+    S_AXI_HP1_AWCACHE,
+    S_AXI_HP1_AWLEN,
+    S_AXI_HP1_AWQOS,
+    S_AXI_HP1_ARID,
+    S_AXI_HP1_AWID,
+    S_AXI_HP1_WID,
+    S_AXI_HP1_WDATA,
+    S_AXI_HP1_WSTRB,
+    S_AXI_HP2_ARREADY,
+    S_AXI_HP2_AWREADY,
+    S_AXI_HP2_BVALID,
+    S_AXI_HP2_RLAST,
+    S_AXI_HP2_RVALID,
+    S_AXI_HP2_WREADY,
+    S_AXI_HP2_BRESP,
+    S_AXI_HP2_RRESP,
+    S_AXI_HP2_BID,
+    S_AXI_HP2_RID,
+    S_AXI_HP2_RDATA,
+    S_AXI_HP2_RCOUNT,
+    S_AXI_HP2_WCOUNT,
+    S_AXI_HP2_RACOUNT,
+    S_AXI_HP2_WACOUNT,
+    S_AXI_HP2_ACLK,
+    S_AXI_HP2_ARVALID,
+    S_AXI_HP2_AWVALID,
+    S_AXI_HP2_BREADY,
+    S_AXI_HP2_RDISSUECAP1_EN,
+    S_AXI_HP2_RREADY,
+    S_AXI_HP2_WLAST,
+    S_AXI_HP2_WRISSUECAP1_EN,
+    S_AXI_HP2_WVALID,
+    S_AXI_HP2_ARBURST,
+    S_AXI_HP2_ARLOCK,
+    S_AXI_HP2_ARSIZE,
+    S_AXI_HP2_AWBURST,
+    S_AXI_HP2_AWLOCK,
+    S_AXI_HP2_AWSIZE,
+    S_AXI_HP2_ARPROT,
+    S_AXI_HP2_AWPROT,
+    S_AXI_HP2_ARADDR,
+    S_AXI_HP2_AWADDR,
+    S_AXI_HP2_ARCACHE,
+    S_AXI_HP2_ARLEN,
+    S_AXI_HP2_ARQOS,
+    S_AXI_HP2_AWCACHE,
+    S_AXI_HP2_AWLEN,
+    S_AXI_HP2_AWQOS,
+    S_AXI_HP2_ARID,
+    S_AXI_HP2_AWID,
+    S_AXI_HP2_WID,
+    S_AXI_HP2_WDATA,
+    S_AXI_HP2_WSTRB,
+    S_AXI_HP3_ARREADY,
+    S_AXI_HP3_AWREADY,
+    S_AXI_HP3_BVALID,
+    S_AXI_HP3_RLAST,
+    S_AXI_HP3_RVALID,
+    S_AXI_HP3_WREADY,
+    S_AXI_HP3_BRESP,
+    S_AXI_HP3_RRESP,
+    S_AXI_HP3_BID,
+    S_AXI_HP3_RID,
+    S_AXI_HP3_RDATA,
+    S_AXI_HP3_RCOUNT,
+    S_AXI_HP3_WCOUNT,
+    S_AXI_HP3_RACOUNT,
+    S_AXI_HP3_WACOUNT,
+    S_AXI_HP3_ACLK,
+    S_AXI_HP3_ARVALID,
+    S_AXI_HP3_AWVALID,
+    S_AXI_HP3_BREADY,
+    S_AXI_HP3_RDISSUECAP1_EN,
+    S_AXI_HP3_RREADY,
+    S_AXI_HP3_WLAST,
+    S_AXI_HP3_WRISSUECAP1_EN,
+    S_AXI_HP3_WVALID,
+    S_AXI_HP3_ARBURST,
+    S_AXI_HP3_ARLOCK,
+    S_AXI_HP3_ARSIZE,
+    S_AXI_HP3_AWBURST,
+    S_AXI_HP3_AWLOCK,
+    S_AXI_HP3_AWSIZE,
+    S_AXI_HP3_ARPROT,
+    S_AXI_HP3_AWPROT,
+    S_AXI_HP3_ARADDR,
+    S_AXI_HP3_AWADDR,
+    S_AXI_HP3_ARCACHE,
+    S_AXI_HP3_ARLEN,
+    S_AXI_HP3_ARQOS,
+    S_AXI_HP3_AWCACHE,
+    S_AXI_HP3_AWLEN,
+    S_AXI_HP3_AWQOS,
+    S_AXI_HP3_ARID,
+    S_AXI_HP3_AWID,
+    S_AXI_HP3_WID,
+    S_AXI_HP3_WDATA,
+    S_AXI_HP3_WSTRB,
+    DMA0_DATYPE,
+    DMA0_DAVALID,
+    DMA0_DRREADY,
+    DMA0_ACLK,
+    DMA0_DAREADY,
+    DMA0_DRLAST,
+    DMA0_DRVALID,
+    DMA0_DRTYPE,
+    DMA1_DATYPE,
+    DMA1_DAVALID,
+    DMA1_DRREADY,
+    DMA1_ACLK,
+    DMA1_DAREADY,
+    DMA1_DRLAST,
+    DMA1_DRVALID,
+    DMA1_DRTYPE,
+    DMA2_DATYPE,
+    DMA2_DAVALID,
+    DMA2_DRREADY,
+    DMA2_ACLK,
+    DMA2_DAREADY,
+    DMA2_DRLAST,
+    DMA2_DRVALID,
+    DMA3_DRVALID,
+    DMA3_DATYPE,
+    DMA3_DAVALID,
+    DMA3_DRREADY,
+    DMA3_ACLK,
+    DMA3_DAREADY,
+    DMA3_DRLAST,
+    DMA2_DRTYPE,
+    DMA3_DRTYPE,
+    FTMD_TRACEIN_DATA,
+    FTMD_TRACEIN_VALID,
+    FTMD_TRACEIN_CLK,
+    FTMD_TRACEIN_ATID,
+    FTMT_F2P_TRIG,
+    FTMT_F2P_TRIGACK,
+    FTMT_F2P_DEBUG,
+    FTMT_P2F_TRIGACK,
+    FTMT_P2F_TRIG,
+    FTMT_P2F_DEBUG,
+    FCLK_CLK3,
+    FCLK_CLK2,
+    FCLK_CLK1,
+    FCLK_CLK0,
+    FCLK_CLKTRIG3_N,
+    FCLK_CLKTRIG2_N,
+    FCLK_CLKTRIG1_N,
+    FCLK_CLKTRIG0_N,
+    FCLK_RESET3_N,
+    FCLK_RESET2_N,
+    FCLK_RESET1_N,
+    FCLK_RESET0_N,
+    FPGA_IDLE_N,
+    DDR_ARB,
+    IRQ_F2P,
+    Core0_nFIQ,
+    Core0_nIRQ,
+    Core1_nFIQ,
+    Core1_nIRQ,
+    EVENT_EVENTO,
+    EVENT_STANDBYWFE,
+    EVENT_STANDBYWFI,
+    EVENT_EVENTI,
+    MIO,
+    DDR_Clk,
+    DDR_Clk_n,
+    DDR_CKE,
+    DDR_CS_n,
+    DDR_RAS_n,
+    DDR_CAS_n,
+    DDR_WEB,
+    DDR_BankAddr,
+    DDR_Addr,
+    DDR_ODT,
+    DDR_DRSTB,
+    DDR_DQ,
+    DDR_DM,
+    DDR_DQS,
+    DDR_DQS_n,
+    DDR_VRN,
+    DDR_VRP,
+    PS_SRSTB,
+    PS_CLK,
+    PS_PORB,
+    IRQ_P2F_DMAC_ABORT,
+    IRQ_P2F_DMAC0,
+    IRQ_P2F_DMAC1,
+    IRQ_P2F_DMAC2,
+    IRQ_P2F_DMAC3,
+    IRQ_P2F_DMAC4,
+    IRQ_P2F_DMAC5,
+    IRQ_P2F_DMAC6,
+    IRQ_P2F_DMAC7,
+    IRQ_P2F_SMC,
+    IRQ_P2F_QSPI,
+    IRQ_P2F_CTI,
+    IRQ_P2F_GPIO,
+    IRQ_P2F_USB0,
+    IRQ_P2F_ENET0,
+    IRQ_P2F_ENET_WAKE0,
+    IRQ_P2F_SDIO0,
+    IRQ_P2F_I2C0,
+    IRQ_P2F_SPI0,
+    IRQ_P2F_UART0,
+    IRQ_P2F_CAN0,
+    IRQ_P2F_USB1,
+    IRQ_P2F_ENET1,
+    IRQ_P2F_ENET_WAKE1,
+    IRQ_P2F_SDIO1,
+    IRQ_P2F_I2C1,
+    IRQ_P2F_SPI1,
+    IRQ_P2F_UART1,
+    IRQ_P2F_CAN1
+  );
+
+
+  /* parameters for gen_clk */
+  parameter C_FCLK_CLK0_FREQ = 50;
+  parameter C_FCLK_CLK1_FREQ = 50;
+  parameter C_FCLK_CLK3_FREQ = 50;
+  parameter C_FCLK_CLK2_FREQ = 50;
+
+  parameter C_HIGH_OCM_EN    = 0;
+
+
+  /* parameters for HP ports */
+  parameter C_USE_S_AXI_HP0 = 0;
+  parameter C_USE_S_AXI_HP1 = 0;
+  parameter C_USE_S_AXI_HP2 = 0;
+  parameter C_USE_S_AXI_HP3 = 0;
+
+  parameter C_S_AXI_HP0_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP1_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP2_DATA_WIDTH = 32;
+  parameter C_S_AXI_HP3_DATA_WIDTH = 32;
+  
+  parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
+  parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12; 
+  parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
+  parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0; 
+  
+/* Do we need these 
+  parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
+
+  parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000;
+  parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000;
+  parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000;
+  parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000;
+  
+  parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF;
+  parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF;
+  parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF;
+  parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF;
+ 
+  /* parameters for GP and ACP ports */
+  parameter C_USE_M_AXI_GP0 = 0;
+  parameter C_USE_M_AXI_GP1 = 0;
+  parameter C_USE_S_AXI_GP0 = 1;
+  parameter C_USE_S_AXI_GP1 = 1;
+  
+  /* Do we need this?
+  parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
+  parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
+  parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
+  
+  parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
+
+  parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000;
+  parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000;
+  
+  parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF;
+  parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF;
+  
+  parameter C_USE_S_AXI_ACP = 1;
+  parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000;
+  parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF;
+ 
+  `include "processing_system7_vip_v1_0_3_local_params.v"
+
+  output CAN0_PHY_TX;
+  input CAN0_PHY_RX;
+  output CAN1_PHY_TX;
+  input CAN1_PHY_RX;
+  output ENET0_GMII_TX_EN;
+  output ENET0_GMII_TX_ER;
+  output ENET0_MDIO_MDC;
+  output ENET0_MDIO_O;
+  output ENET0_MDIO_T;
+  output ENET0_PTP_DELAY_REQ_RX;
+  output ENET0_PTP_DELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_REQ_RX;
+  output ENET0_PTP_PDELAY_REQ_TX;
+  output ENET0_PTP_PDELAY_RESP_RX;
+  output ENET0_PTP_PDELAY_RESP_TX;
+  output ENET0_PTP_SYNC_FRAME_RX;
+  output ENET0_PTP_SYNC_FRAME_TX;
+  output ENET0_SOF_RX;
+  output ENET0_SOF_TX;
+  output [7:0] ENET0_GMII_TXD;
+  input ENET0_GMII_COL;
+  input ENET0_GMII_CRS;
+  input ENET0_EXT_INTIN;
+  input ENET0_GMII_RX_CLK;
+  input ENET0_GMII_RX_DV;
+  input ENET0_GMII_RX_ER;
+  input ENET0_GMII_TX_CLK;
+  input ENET0_MDIO_I;
+  input [7:0] ENET0_GMII_RXD;
+  output ENET1_GMII_TX_EN;
+  output ENET1_GMII_TX_ER;
+  output ENET1_MDIO_MDC;
+  output ENET1_MDIO_O;
+  output ENET1_MDIO_T;
+  output ENET1_PTP_DELAY_REQ_RX;
+  output ENET1_PTP_DELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_REQ_RX;
+  output ENET1_PTP_PDELAY_REQ_TX;
+  output ENET1_PTP_PDELAY_RESP_RX;
+  output ENET1_PTP_PDELAY_RESP_TX;
+  output ENET1_PTP_SYNC_FRAME_RX;
+  output ENET1_PTP_SYNC_FRAME_TX;
+  output ENET1_SOF_RX;
+  output ENET1_SOF_TX;
+  output [7:0] ENET1_GMII_TXD;
+  input ENET1_GMII_COL;
+  input ENET1_GMII_CRS;
+  input ENET1_EXT_INTIN;
+  input ENET1_GMII_RX_CLK;
+  input ENET1_GMII_RX_DV;
+  input ENET1_GMII_RX_ER;
+  input ENET1_GMII_TX_CLK;
+  input ENET1_MDIO_I;
+  input [7:0] ENET1_GMII_RXD;
+  input [63:0] GPIO_I;
+  output [63:0] GPIO_O;
+  output [63:0] GPIO_T;
+  input I2C0_SDA_I;
+  output I2C0_SDA_O;
+  output I2C0_SDA_T;
+  input I2C0_SCL_I;
+  output I2C0_SCL_O;
+  output I2C0_SCL_T;
+  input I2C1_SDA_I;
+  output I2C1_SDA_O;
+  output I2C1_SDA_T;
+  input I2C1_SCL_I;
+  output I2C1_SCL_O;
+  output I2C1_SCL_T;
+  input PJTAG_TCK;
+  input PJTAG_TMS;
+  input PJTAG_TD_I;
+  output PJTAG_TD_T;
+  output PJTAG_TD_O;
+  output SDIO0_CLK;
+  input SDIO0_CLK_FB;
+  output SDIO0_CMD_O;
+  input SDIO0_CMD_I;
+  output SDIO0_CMD_T;
+  input [3:0] SDIO0_DATA_I;
+  output [3:0] SDIO0_DATA_O;
+  output [3:0] SDIO0_DATA_T;
+  output SDIO0_LED;
+  input SDIO0_CDN;
+  input SDIO0_WP;
+  output SDIO0_BUSPOW;
+  output [2:0] SDIO0_BUSVOLT;
+  output SDIO1_CLK;
+  input SDIO1_CLK_FB;
+  output SDIO1_CMD_O;
+  input SDIO1_CMD_I;
+  output SDIO1_CMD_T;
+  input [3:0] SDIO1_DATA_I;
+  output [3:0] SDIO1_DATA_O;
+  output [3:0] SDIO1_DATA_T;
+  output SDIO1_LED;
+  input SDIO1_CDN;
+  input SDIO1_WP;
+  output SDIO1_BUSPOW;
+  output [2:0] SDIO1_BUSVOLT;
+  input SPI0_SCLK_I;
+  output SPI0_SCLK_O;
+  output SPI0_SCLK_T;
+  input SPI0_MOSI_I;
+  output SPI0_MOSI_O;
+  output SPI0_MOSI_T;
+  input SPI0_MISO_I;
+  output SPI0_MISO_O;
+  output SPI0_MISO_T;
+  input SPI0_SS_I;
+  output SPI0_SS_O;
+  output SPI0_SS1_O;
+  output SPI0_SS2_O;
+  output SPI0_SS_T;
+  input SPI1_SCLK_I;
+  output SPI1_SCLK_O;
+  output SPI1_SCLK_T;
+  input SPI1_MOSI_I;
+  output SPI1_MOSI_O;
+  output SPI1_MOSI_T;
+  input SPI1_MISO_I;
+  output SPI1_MISO_O;
+  output SPI1_MISO_T;
+  input SPI1_SS_I;
+  output SPI1_SS_O;
+  output SPI1_SS1_O;
+  output SPI1_SS2_O;
+  output SPI1_SS_T;
+  output UART0_DTRN;
+  output UART0_RTSN;
+  output UART0_TX;
+  input UART0_CTSN;
+  input UART0_DCDN;
+  input UART0_DSRN;
+  input UART0_RIN;
+  input UART0_RX;
+  output UART1_DTRN;
+  output UART1_RTSN;
+  output UART1_TX;
+  input UART1_CTSN;
+  input UART1_DCDN;
+  input UART1_DSRN;
+  input UART1_RIN;
+  input UART1_RX;
+  output TTC0_WAVE0_OUT;
+  output TTC0_WAVE1_OUT;
+  output TTC0_WAVE2_OUT;
+  input TTC0_CLK0_IN;
+  input TTC0_CLK1_IN;
+  input TTC0_CLK2_IN;
+  output TTC1_WAVE0_OUT;
+  output TTC1_WAVE1_OUT;
+  output TTC1_WAVE2_OUT;
+  input TTC1_CLK0_IN;
+  input TTC1_CLK1_IN;
+  input TTC1_CLK2_IN;
+  input WDT_CLK_IN;
+  output WDT_RST_OUT;
+  input TRACE_CLK;
+  output TRACE_CTL;
+  output [31:0] TRACE_DATA;
+  output [1:0] USB0_PORT_INDCTL;
+  output [1:0] USB1_PORT_INDCTL;
+  output USB0_VBUS_PWRSELECT;
+  output USB1_VBUS_PWRSELECT;
+  input USB0_VBUS_PWRFAULT;
+  input USB1_VBUS_PWRFAULT;
+  input SRAM_INTIN;
+  output M_AXI_GP0_ARVALID;
+  output M_AXI_GP0_AWVALID;
+  output M_AXI_GP0_BREADY;
+  output M_AXI_GP0_RREADY;
+  output M_AXI_GP0_WLAST;
+  output M_AXI_GP0_WVALID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
+  output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
+  output [1:0] M_AXI_GP0_ARBURST;
+  output [1:0] M_AXI_GP0_ARLOCK;
+  output [2:0] M_AXI_GP0_ARSIZE;
+  output [1:0] M_AXI_GP0_AWBURST;
+  output [1:0] M_AXI_GP0_AWLOCK;
+  output [2:0] M_AXI_GP0_AWSIZE;
+  output [2:0] M_AXI_GP0_ARPROT;
+  output [2:0] M_AXI_GP0_AWPROT;
+  output [31:0] M_AXI_GP0_ARADDR;
+  output [31:0] M_AXI_GP0_AWADDR;
+  output [31:0] M_AXI_GP0_WDATA;
+  output [3:0] M_AXI_GP0_ARCACHE;
+  output [3:0] M_AXI_GP0_ARLEN;
+  output [3:0] M_AXI_GP0_ARQOS;
+  output [3:0] M_AXI_GP0_AWCACHE;
+  output [3:0] M_AXI_GP0_AWLEN;
+  output [3:0] M_AXI_GP0_AWQOS;
+  output [3:0] M_AXI_GP0_WSTRB;
+  input M_AXI_GP0_ACLK;
+  input M_AXI_GP0_ARREADY;
+  input M_AXI_GP0_AWREADY;
+  input M_AXI_GP0_BVALID;
+  input M_AXI_GP0_RLAST;
+  input M_AXI_GP0_RVALID;
+  input M_AXI_GP0_WREADY;
+  input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
+  input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
+  input [1:0] M_AXI_GP0_BRESP;
+  input [1:0] M_AXI_GP0_RRESP;
+  input [31:0] M_AXI_GP0_RDATA;
+  output M_AXI_GP1_ARVALID;
+  output M_AXI_GP1_AWVALID;
+  output M_AXI_GP1_BREADY;
+  output M_AXI_GP1_RREADY;
+  output M_AXI_GP1_WLAST;
+  output M_AXI_GP1_WVALID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
+  output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
+  output [1:0] M_AXI_GP1_ARBURST;
+  output [1:0] M_AXI_GP1_ARLOCK;
+  output [2:0] M_AXI_GP1_ARSIZE;
+  output [1:0] M_AXI_GP1_AWBURST;
+  output [1:0] M_AXI_GP1_AWLOCK;
+  output [2:0] M_AXI_GP1_AWSIZE;
+  output [2:0] M_AXI_GP1_ARPROT;
+  output [2:0] M_AXI_GP1_AWPROT;
+  output [31:0] M_AXI_GP1_ARADDR;
+  output [31:0] M_AXI_GP1_AWADDR;
+  output [31:0] M_AXI_GP1_WDATA;
+  output [3:0] M_AXI_GP1_ARCACHE;
+  output [3:0] M_AXI_GP1_ARLEN;
+  output [3:0] M_AXI_GP1_ARQOS;
+  output [3:0] M_AXI_GP1_AWCACHE;
+  output [3:0] M_AXI_GP1_AWLEN;
+  output [3:0] M_AXI_GP1_AWQOS;
+  output [3:0] M_AXI_GP1_WSTRB;
+  input M_AXI_GP1_ACLK;
+  input M_AXI_GP1_ARREADY;
+  input M_AXI_GP1_AWREADY;
+  input M_AXI_GP1_BVALID;
+  input M_AXI_GP1_RLAST;
+  input M_AXI_GP1_RVALID;
+  input M_AXI_GP1_WREADY;
+  input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
+  input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
+  input [1:0] M_AXI_GP1_BRESP;
+  input [1:0] M_AXI_GP1_RRESP;
+  input [31:0] M_AXI_GP1_RDATA;
+  output S_AXI_GP0_ARREADY;
+  output S_AXI_GP0_AWREADY;
+  output S_AXI_GP0_BVALID;
+  output S_AXI_GP0_RLAST;
+  output S_AXI_GP0_RVALID;
+  output S_AXI_GP0_WREADY;
+  output [1:0] S_AXI_GP0_BRESP;
+  output [1:0] S_AXI_GP0_RRESP;
+  output [31:0] S_AXI_GP0_RDATA;
+  output [5:0] S_AXI_GP0_BID;
+  output [5:0] S_AXI_GP0_RID;
+  input S_AXI_GP0_ACLK;
+  input S_AXI_GP0_ARVALID;
+  input S_AXI_GP0_AWVALID;
+  input S_AXI_GP0_BREADY;
+  input S_AXI_GP0_RREADY;
+  input S_AXI_GP0_WLAST;
+  input S_AXI_GP0_WVALID;
+  input [1:0] S_AXI_GP0_ARBURST;
+  input [1:0] S_AXI_GP0_ARLOCK;
+  input [2:0] S_AXI_GP0_ARSIZE;
+  input [1:0] S_AXI_GP0_AWBURST;
+  input [1:0] S_AXI_GP0_AWLOCK;
+  input [2:0] S_AXI_GP0_AWSIZE;
+  input [2:0] S_AXI_GP0_ARPROT;
+  input [2:0] S_AXI_GP0_AWPROT;
+  input [31:0] S_AXI_GP0_ARADDR;
+  input [31:0] S_AXI_GP0_AWADDR;
+  input [31:0] S_AXI_GP0_WDATA;
+  input [3:0] S_AXI_GP0_ARCACHE;
+  input [3:0] S_AXI_GP0_ARLEN;
+  input [3:0] S_AXI_GP0_ARQOS;
+  input [3:0] S_AXI_GP0_AWCACHE;
+  input [3:0] S_AXI_GP0_AWLEN;
+  input [3:0] S_AXI_GP0_AWQOS;
+  input [3:0] S_AXI_GP0_WSTRB;
+  input [5:0] S_AXI_GP0_ARID;
+  input [5:0] S_AXI_GP0_AWID;
+  input [5:0] S_AXI_GP0_WID;
+  output S_AXI_GP1_ARREADY;
+  output S_AXI_GP1_AWREADY;
+  output S_AXI_GP1_BVALID;
+  output S_AXI_GP1_RLAST;
+  output S_AXI_GP1_RVALID;
+  output S_AXI_GP1_WREADY;
+  output [1:0] S_AXI_GP1_BRESP;
+  output [1:0] S_AXI_GP1_RRESP;
+  output [31:0] S_AXI_GP1_RDATA;
+  output [5:0] S_AXI_GP1_BID;
+  output [5:0] S_AXI_GP1_RID;
+  input S_AXI_GP1_ACLK;
+  input S_AXI_GP1_ARVALID;
+  input S_AXI_GP1_AWVALID;
+  input S_AXI_GP1_BREADY;
+  input S_AXI_GP1_RREADY;
+  input S_AXI_GP1_WLAST;
+  input S_AXI_GP1_WVALID;
+  input [1:0] S_AXI_GP1_ARBURST;
+  input [1:0] S_AXI_GP1_ARLOCK;
+  input [2:0] S_AXI_GP1_ARSIZE;
+  input [1:0] S_AXI_GP1_AWBURST;
+  input [1:0] S_AXI_GP1_AWLOCK;
+  input [2:0] S_AXI_GP1_AWSIZE;
+  input [2:0] S_AXI_GP1_ARPROT;
+  input [2:0] S_AXI_GP1_AWPROT;
+  input [31:0] S_AXI_GP1_ARADDR;
+  input [31:0] S_AXI_GP1_AWADDR;
+  input [31:0] S_AXI_GP1_WDATA;
+  input [3:0] S_AXI_GP1_ARCACHE;
+  input [3:0] S_AXI_GP1_ARLEN;
+  input [3:0] S_AXI_GP1_ARQOS;
+  input [3:0] S_AXI_GP1_AWCACHE;
+  input [3:0] S_AXI_GP1_AWLEN;
+  input [3:0] S_AXI_GP1_AWQOS;
+  input [3:0] S_AXI_GP1_WSTRB;
+  input [5:0] S_AXI_GP1_ARID;
+  input [5:0] S_AXI_GP1_AWID;
+  input [5:0] S_AXI_GP1_WID;
+  output S_AXI_ACP_AWREADY;
+  output S_AXI_ACP_ARREADY;
+  output S_AXI_ACP_BVALID;
+  output S_AXI_ACP_RLAST;
+  output S_AXI_ACP_RVALID;
+  output S_AXI_ACP_WREADY;
+  output [1:0] S_AXI_ACP_BRESP;
+  output [1:0] S_AXI_ACP_RRESP;
+  output [2:0] S_AXI_ACP_BID;
+  output [2:0] S_AXI_ACP_RID;
+  output [63:0] S_AXI_ACP_RDATA;
+  input S_AXI_ACP_ACLK;
+  input S_AXI_ACP_ARVALID;
+  input S_AXI_ACP_AWVALID;
+  input S_AXI_ACP_BREADY;
+  input S_AXI_ACP_RREADY;
+  input S_AXI_ACP_WLAST;
+  input S_AXI_ACP_WVALID;
+  input [2:0] S_AXI_ACP_ARID;
+  input [2:0] S_AXI_ACP_ARPROT;
+  input [2:0] S_AXI_ACP_AWID;
+  input [2:0] S_AXI_ACP_AWPROT;
+  input [2:0] S_AXI_ACP_WID;
+  input [31:0] S_AXI_ACP_ARADDR;
+  input [31:0] S_AXI_ACP_AWADDR;
+  input [3:0] S_AXI_ACP_ARCACHE;
+  input [3:0] S_AXI_ACP_ARLEN;
+  input [3:0] S_AXI_ACP_ARQOS;
+  input [3:0] S_AXI_ACP_AWCACHE;
+  input [3:0] S_AXI_ACP_AWLEN;
+  input [3:0] S_AXI_ACP_AWQOS;
+  input [1:0] S_AXI_ACP_ARBURST;
+  input [1:0] S_AXI_ACP_ARLOCK;
+  input [2:0] S_AXI_ACP_ARSIZE;
+  input [1:0] S_AXI_ACP_AWBURST;
+  input [1:0] S_AXI_ACP_AWLOCK;
+  input [2:0] S_AXI_ACP_AWSIZE;
+  input [4:0] S_AXI_ACP_ARUSER;
+  input [4:0] S_AXI_ACP_AWUSER;
+  input [63:0] S_AXI_ACP_WDATA;
+  input [7:0] S_AXI_ACP_WSTRB;
+  output S_AXI_HP0_ARREADY;
+  output S_AXI_HP0_AWREADY;
+  output S_AXI_HP0_BVALID;
+  output S_AXI_HP0_RLAST;
+  output S_AXI_HP0_RVALID;
+  output S_AXI_HP0_WREADY;
+  output [1:0] S_AXI_HP0_BRESP;
+  output [1:0] S_AXI_HP0_RRESP;
+  output [5:0] S_AXI_HP0_BID;
+  output [5:0] S_AXI_HP0_RID;
+  output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
+  output [7:0] S_AXI_HP0_RCOUNT;
+  output [7:0] S_AXI_HP0_WCOUNT;
+  output [2:0] S_AXI_HP0_RACOUNT;
+  output [5:0] S_AXI_HP0_WACOUNT;
+  input S_AXI_HP0_ACLK;
+  input S_AXI_HP0_ARVALID;
+  input S_AXI_HP0_AWVALID;
+  input S_AXI_HP0_BREADY;
+  input S_AXI_HP0_RDISSUECAP1_EN;
+  input S_AXI_HP0_RREADY;
+  input S_AXI_HP0_WLAST;
+  input S_AXI_HP0_WRISSUECAP1_EN;
+  input S_AXI_HP0_WVALID;
+  input [1:0] S_AXI_HP0_ARBURST;
+  input [1:0] S_AXI_HP0_ARLOCK;
+  input [2:0] S_AXI_HP0_ARSIZE;
+  input [1:0] S_AXI_HP0_AWBURST;
+  input [1:0] S_AXI_HP0_AWLOCK;
+  input [2:0] S_AXI_HP0_AWSIZE;
+  input [2:0] S_AXI_HP0_ARPROT;
+  input [2:0] S_AXI_HP0_AWPROT;
+  input [31:0] S_AXI_HP0_ARADDR;
+  input [31:0] S_AXI_HP0_AWADDR;
+  input [3:0] S_AXI_HP0_ARCACHE;
+  input [3:0] S_AXI_HP0_ARLEN;
+  input [3:0] S_AXI_HP0_ARQOS;
+  input [3:0] S_AXI_HP0_AWCACHE;
+  input [3:0] S_AXI_HP0_AWLEN;
+  input [3:0] S_AXI_HP0_AWQOS;
+  input [5:0] S_AXI_HP0_ARID;
+  input [5:0] S_AXI_HP0_AWID;
+  input [5:0] S_AXI_HP0_WID;
+  input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
+  input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
+  output S_AXI_HP1_ARREADY;
+  output S_AXI_HP1_AWREADY;
+  output S_AXI_HP1_BVALID;
+  output S_AXI_HP1_RLAST;
+  output S_AXI_HP1_RVALID;
+  output S_AXI_HP1_WREADY;
+  output [1:0] S_AXI_HP1_BRESP;
+  output [1:0] S_AXI_HP1_RRESP;
+  output [5:0] S_AXI_HP1_BID;
+  output [5:0] S_AXI_HP1_RID;
+  output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
+  output [7:0] S_AXI_HP1_RCOUNT;
+  output [7:0] S_AXI_HP1_WCOUNT;
+  output [2:0] S_AXI_HP1_RACOUNT;
+  output [5:0] S_AXI_HP1_WACOUNT;
+  input S_AXI_HP1_ACLK;
+  input S_AXI_HP1_ARVALID;
+  input S_AXI_HP1_AWVALID;
+  input S_AXI_HP1_BREADY;
+  input S_AXI_HP1_RDISSUECAP1_EN;
+  input S_AXI_HP1_RREADY;
+  input S_AXI_HP1_WLAST;
+  input S_AXI_HP1_WRISSUECAP1_EN;
+  input S_AXI_HP1_WVALID;
+  input [1:0] S_AXI_HP1_ARBURST;
+  input [1:0] S_AXI_HP1_ARLOCK;
+  input [2:0] S_AXI_HP1_ARSIZE;
+  input [1:0] S_AXI_HP1_AWBURST;
+  input [1:0] S_AXI_HP1_AWLOCK;
+  input [2:0] S_AXI_HP1_AWSIZE;
+  input [2:0] S_AXI_HP1_ARPROT;
+  input [2:0] S_AXI_HP1_AWPROT;
+  input [31:0] S_AXI_HP1_ARADDR;
+  input [31:0] S_AXI_HP1_AWADDR;
+  input [3:0] S_AXI_HP1_ARCACHE;
+  input [3:0] S_AXI_HP1_ARLEN;
+  input [3:0] S_AXI_HP1_ARQOS;
+  input [3:0] S_AXI_HP1_AWCACHE;
+  input [3:0] S_AXI_HP1_AWLEN;
+  input [3:0] S_AXI_HP1_AWQOS;
+  input [5:0] S_AXI_HP1_ARID;
+  input [5:0] S_AXI_HP1_AWID;
+  input [5:0] S_AXI_HP1_WID;
+  input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
+  input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
+  output S_AXI_HP2_ARREADY;
+  output S_AXI_HP2_AWREADY;
+  output S_AXI_HP2_BVALID;
+  output S_AXI_HP2_RLAST;
+  output S_AXI_HP2_RVALID;
+  output S_AXI_HP2_WREADY;
+  output [1:0] S_AXI_HP2_BRESP;
+  output [1:0] S_AXI_HP2_RRESP;
+  output [5:0] S_AXI_HP2_BID;
+  output [5:0] S_AXI_HP2_RID;
+  output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
+  output [7:0] S_AXI_HP2_RCOUNT;
+  output [7:0] S_AXI_HP2_WCOUNT;
+  output [2:0] S_AXI_HP2_RACOUNT;
+  output [5:0] S_AXI_HP2_WACOUNT;
+  input S_AXI_HP2_ACLK;
+  input S_AXI_HP2_ARVALID;
+  input S_AXI_HP2_AWVALID;
+  input S_AXI_HP2_BREADY;
+  input S_AXI_HP2_RDISSUECAP1_EN;
+  input S_AXI_HP2_RREADY;
+  input S_AXI_HP2_WLAST;
+  input S_AXI_HP2_WRISSUECAP1_EN;
+  input S_AXI_HP2_WVALID;
+  input [1:0] S_AXI_HP2_ARBURST;
+  input [1:0] S_AXI_HP2_ARLOCK;
+  input [2:0] S_AXI_HP2_ARSIZE;
+  input [1:0] S_AXI_HP2_AWBURST;
+  input [1:0] S_AXI_HP2_AWLOCK;
+  input [2:0] S_AXI_HP2_AWSIZE;
+  input [2:0] S_AXI_HP2_ARPROT;
+  input [2:0] S_AXI_HP2_AWPROT;
+  input [31:0] S_AXI_HP2_ARADDR;
+  input [31:0] S_AXI_HP2_AWADDR;
+  input [3:0] S_AXI_HP2_ARCACHE;
+  input [3:0] S_AXI_HP2_ARLEN;
+  input [3:0] S_AXI_HP2_ARQOS;
+  input [3:0] S_AXI_HP2_AWCACHE;
+  input [3:0] S_AXI_HP2_AWLEN;
+  input [3:0] S_AXI_HP2_AWQOS;
+  input [5:0] S_AXI_HP2_ARID;
+  input [5:0] S_AXI_HP2_AWID;
+  input [5:0] S_AXI_HP2_WID;
+  input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
+  input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
+  output S_AXI_HP3_ARREADY;
+  output S_AXI_HP3_AWREADY;
+  output S_AXI_HP3_BVALID;
+  output S_AXI_HP3_RLAST;
+  output S_AXI_HP3_RVALID;
+  output S_AXI_HP3_WREADY;
+  output [1:0] S_AXI_HP3_BRESP;
+  output [1:0] S_AXI_HP3_RRESP;
+  output [5:0] S_AXI_HP3_BID;
+  output [5:0] S_AXI_HP3_RID;
+  output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
+  output [7:0] S_AXI_HP3_RCOUNT;
+  output [7:0] S_AXI_HP3_WCOUNT;
+  output [2:0] S_AXI_HP3_RACOUNT;
+  output [5:0] S_AXI_HP3_WACOUNT;
+  input S_AXI_HP3_ACLK;
+  input S_AXI_HP3_ARVALID;
+  input S_AXI_HP3_AWVALID;
+  input S_AXI_HP3_BREADY;
+  input S_AXI_HP3_RDISSUECAP1_EN;
+  input S_AXI_HP3_RREADY;
+  input S_AXI_HP3_WLAST;
+  input S_AXI_HP3_WRISSUECAP1_EN;
+  input S_AXI_HP3_WVALID;
+  input [1:0] S_AXI_HP3_ARBURST;
+  input [1:0] S_AXI_HP3_ARLOCK;
+  input [2:0] S_AXI_HP3_ARSIZE;
+  input [1:0] S_AXI_HP3_AWBURST;
+  input [1:0] S_AXI_HP3_AWLOCK;
+  input [2:0] S_AXI_HP3_AWSIZE;
+  input [2:0] S_AXI_HP3_ARPROT;
+  input [2:0] S_AXI_HP3_AWPROT;
+  input [31:0] S_AXI_HP3_ARADDR;
+  input [31:0] S_AXI_HP3_AWADDR;
+  input [3:0] S_AXI_HP3_ARCACHE;
+  input [3:0] S_AXI_HP3_ARLEN;
+  input [3:0] S_AXI_HP3_ARQOS;
+  input [3:0] S_AXI_HP3_AWCACHE;
+  input [3:0] S_AXI_HP3_AWLEN;
+  input [3:0] S_AXI_HP3_AWQOS;
+  input [5:0] S_AXI_HP3_ARID;
+  input [5:0] S_AXI_HP3_AWID;
+  input [5:0] S_AXI_HP3_WID;
+  input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
+  input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
+  output [1:0] DMA0_DATYPE;
+  output DMA0_DAVALID;
+  output DMA0_DRREADY;
+  input DMA0_ACLK;
+  input DMA0_DAREADY;
+  input DMA0_DRLAST;
+  input DMA0_DRVALID;
+  input [1:0] DMA0_DRTYPE;
+  output [1:0] DMA1_DATYPE;
+  output DMA1_DAVALID;
+  output DMA1_DRREADY;
+  input DMA1_ACLK;
+  input DMA1_DAREADY;
+  input DMA1_DRLAST;
+  input DMA1_DRVALID;
+  input [1:0] DMA1_DRTYPE;
+  output [1:0] DMA2_DATYPE;
+  output DMA2_DAVALID;
+  output DMA2_DRREADY;
+  input DMA2_ACLK;
+  input DMA2_DAREADY;
+  input DMA2_DRLAST;
+  input DMA2_DRVALID;
+  input DMA3_DRVALID;
+  output [1:0] DMA3_DATYPE;
+  output DMA3_DAVALID;
+  output DMA3_DRREADY;
+  input DMA3_ACLK;
+  input DMA3_DAREADY;
+  input DMA3_DRLAST;
+  input [1:0] DMA2_DRTYPE;
+  input [1:0] DMA3_DRTYPE;
+  input [31:0] FTMD_TRACEIN_DATA;
+  input FTMD_TRACEIN_VALID;
+  input FTMD_TRACEIN_CLK;
+  input [3:0] FTMD_TRACEIN_ATID;
+  input [3:0] FTMT_F2P_TRIG;
+  output [3:0] FTMT_F2P_TRIGACK;
+  input [31:0] FTMT_F2P_DEBUG;
+  input [3:0] FTMT_P2F_TRIGACK;
+  output [3:0] FTMT_P2F_TRIG;
+  output [31:0] FTMT_P2F_DEBUG;
+  output FCLK_CLK3;
+  output FCLK_CLK2;
+  output FCLK_CLK1;
+  output FCLK_CLK0;
+  input FCLK_CLKTRIG3_N;
+  input FCLK_CLKTRIG2_N;
+  input FCLK_CLKTRIG1_N;
+  input FCLK_CLKTRIG0_N;
+  output FCLK_RESET3_N;
+  output FCLK_RESET2_N;
+  output FCLK_RESET1_N;
+  output FCLK_RESET0_N;
+  input FPGA_IDLE_N;
+  input [3:0] DDR_ARB;
+  input [irq_width-1:0] IRQ_F2P;
+  input Core0_nFIQ;
+  input Core0_nIRQ;
+  input Core1_nFIQ;
+  input Core1_nIRQ;
+  output EVENT_EVENTO;
+  output [1:0] EVENT_STANDBYWFE;
+  output [1:0] EVENT_STANDBYWFI;
+  input EVENT_EVENTI;
+  inout [53:0] MIO;
+  inout DDR_Clk;
+  inout DDR_Clk_n;
+  inout DDR_CKE;
+  inout DDR_CS_n;
+  inout DDR_RAS_n;
+  inout DDR_CAS_n;
+  output DDR_WEB;
+  inout [2:0] DDR_BankAddr;
+  inout [14:0] DDR_Addr;
+  inout DDR_ODT;
+  inout DDR_DRSTB;
+  inout [31:0] DDR_DQ;
+  inout [3:0] DDR_DM;
+  inout [3:0] DDR_DQS;
+  inout [3:0] DDR_DQS_n;
+  inout DDR_VRN;
+  inout DDR_VRP;
+/* Reset Input & Clock Input */
+  input PS_SRSTB;
+  input PS_CLK;
+  input PS_PORB;
+  output IRQ_P2F_DMAC_ABORT;
+  output IRQ_P2F_DMAC0;
+  output IRQ_P2F_DMAC1;
+  output IRQ_P2F_DMAC2;
+  output IRQ_P2F_DMAC3;
+  output IRQ_P2F_DMAC4;
+  output IRQ_P2F_DMAC5;
+  output IRQ_P2F_DMAC6;
+  output IRQ_P2F_DMAC7;
+  output IRQ_P2F_SMC;
+  output IRQ_P2F_QSPI;
+  output IRQ_P2F_CTI;
+  output IRQ_P2F_GPIO;
+  output IRQ_P2F_USB0;
+  output IRQ_P2F_ENET0;
+  output IRQ_P2F_ENET_WAKE0;
+  output IRQ_P2F_SDIO0;
+  output IRQ_P2F_I2C0;
+  output IRQ_P2F_SPI0;
+  output IRQ_P2F_UART0;
+  output IRQ_P2F_CAN0;
+  output IRQ_P2F_USB1;
+  output IRQ_P2F_ENET1;
+  output IRQ_P2F_ENET_WAKE1;
+  output IRQ_P2F_SDIO1;
+  output IRQ_P2F_I2C1;
+  output IRQ_P2F_SPI1;
+  output IRQ_P2F_UART1;
+  output IRQ_P2F_CAN1;
+
+
+  /* Internal wires/nets used for connectivity */
+  wire net_rstn;
+  wire net_sw_clk;
+  wire net_ocm_clk;
+  wire net_arbiter_clk;
+
+  wire net_axi_mgp0_rstn;
+  wire net_axi_mgp1_rstn;
+  wire net_axi_gp0_rstn;
+  wire net_axi_gp1_rstn;
+  wire net_axi_hp0_rstn;
+  wire net_axi_hp1_rstn;
+  wire net_axi_hp2_rstn;
+  wire net_axi_hp3_rstn;
+  wire net_axi_acp_rstn;
+  wire [4:0] net_axi_acp_awuser;
+  wire [4:0] net_axi_acp_aruser;
+
+
+  /* Dummy */
+  assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
+  assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
+
+  /* Global variables */
+  reg DEBUG_INFO = 1;
+  reg STOP_ON_ERROR = 1;
+  
+  /* local variable acting as semaphore for wait_mem_update and wait_reg_update task */ 
+  reg mem_update_key = 1; 
+  reg reg_update_key_0 = 1; 
+  reg reg_update_key_1 = 1; 
+  
+  /* assignments and semantic checks for unused ports */
+  `include "processing_system7_vip_v1_0_3_unused_ports.v"
+ 
+  /* include api definition */
+  `include "processing_system7_vip_v1_0_3_apis.v"
+ 
+  /* Reset Generator */
+  processing_system7_vip_v1_0_3_gen_reset gen_rst(.por_rst_n(PS_PORB),
+                    .sys_rst_n(PS_SRSTB),
+                    .rst_out_n(net_rstn),
+
+                    .m_axi_gp0_clk(M_AXI_GP0_ACLK),
+                    .m_axi_gp1_clk(M_AXI_GP1_ACLK),
+                    .s_axi_gp0_clk(S_AXI_GP0_ACLK),
+                    .s_axi_gp1_clk(S_AXI_GP1_ACLK),
+                    .s_axi_hp0_clk(S_AXI_HP0_ACLK),
+                    .s_axi_hp1_clk(S_AXI_HP1_ACLK),
+                    .s_axi_hp2_clk(S_AXI_HP2_ACLK),
+                    .s_axi_hp3_clk(S_AXI_HP3_ACLK),
+                    .s_axi_acp_clk(S_AXI_ACP_ACLK),
+
+                    .m_axi_gp0_rstn(net_axi_mgp0_rstn),
+                    .m_axi_gp1_rstn(net_axi_mgp1_rstn),
+                    .s_axi_gp0_rstn(net_axi_gp0_rstn),
+                    .s_axi_gp1_rstn(net_axi_gp1_rstn),
+                    .s_axi_hp0_rstn(net_axi_hp0_rstn),
+                    .s_axi_hp1_rstn(net_axi_hp1_rstn),
+                    .s_axi_hp2_rstn(net_axi_hp2_rstn),
+                    .s_axi_hp3_rstn(net_axi_hp3_rstn),
+                    .s_axi_acp_rstn(net_axi_acp_rstn),
+
+                    .fclk_reset3_n(FCLK_RESET3_N),
+                    .fclk_reset2_n(FCLK_RESET2_N),
+                    .fclk_reset1_n(FCLK_RESET1_N),
+                    .fclk_reset0_n(FCLK_RESET0_N),
+
+                    .fpga_acp_reset_n(),   ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
+                    .fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
+                    .fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
+                    .fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
+                    .fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
+                    .fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
+                    .fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
+                    .fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
+                    .fpga_hp_s3_reset_n()  ////S_AXI_HP3_ARESETN)
+                   );
+
+  /* Clock Generator */
+  processing_system7_vip_v1_0_3_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
+            gen_clk(.ps_clk(PS_CLK),
+                    .sw_clk(net_sw_clk),
+
+                    .fclk_clk3(FCLK_CLK3),
+                    .fclk_clk2(FCLK_CLK2),
+                    .fclk_clk1(FCLK_CLK1),
+                    .fclk_clk0(FCLK_CLK0)
+                    );
+
+  wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
+  wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
+  wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
+  wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
+  wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
+  wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
+
+  wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
+  wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
+  wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
+  wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
+  wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
+  wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
+  wire  net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
+  wire  net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
+  wire  net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
+  wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
+  
+  wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
+  wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
+  wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
+  wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
+  wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
+  wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
+  wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
+  wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
+  
+  wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
+  wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
+  wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
+  wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
+  wire  net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
+  wire  net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
+  wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
+
+  wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
+  wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
+  wire [max_burst_bits-1:0] net_wr_data_acp;
+  wire [addr_width-1:0] net_wr_addr_acp;
+  wire [max_burst_bytes_width:0] net_wr_bytes_acp;
+  wire [axi_qos_width-1:0] net_wr_qos_acp;
+  
+  wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
+  wire [addr_width-1:0] net_rd_addr_acp;
+  wire [max_burst_bytes_width:0] net_rd_bytes_acp;
+  wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
+  wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
+  wire  net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
+  wire [axi_qos_width-1:0] net_rd_qos_acp;
+  
+  wire ocm_wr_ack_port0;
+  wire ocm_wr_dv_port0;
+  wire ocm_rd_req_port0;
+  wire ocm_rd_dv_port0;
+  wire [addr_width-1:0] ocm_wr_addr_port0;
+  wire [max_burst_bits-1:0] ocm_wr_data_port0;
+  wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
+  wire [addr_width-1:0] ocm_rd_addr_port0;
+  wire [max_burst_bits-1:0] ocm_rd_data_port0;
+  wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
+  wire [axi_qos_width-1:0] ocm_wr_qos_port0;
+  wire [axi_qos_width-1:0] ocm_rd_qos_port0;
+
+  wire ocm_wr_ack_port1;
+  wire ocm_wr_dv_port1;
+  wire ocm_rd_req_port1;
+  wire ocm_rd_dv_port1;
+  wire [addr_width-1:0] ocm_wr_addr_port1;
+  wire [max_burst_bits-1:0] ocm_wr_data_port1;
+  wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
+  wire [addr_width-1:0] ocm_rd_addr_port1;
+  wire [max_burst_bits-1:0] ocm_rd_data_port1;
+  wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
+  wire [axi_qos_width-1:0] ocm_wr_qos_port1;
+  wire [axi_qos_width-1:0] ocm_rd_qos_port1;
+
+  wire ddr_wr_ack_port0;
+  wire ddr_wr_dv_port0;
+  wire ddr_rd_req_port0;
+  wire ddr_rd_dv_port0;
+  wire[addr_width-1:0] ddr_wr_addr_port0;
+  wire[max_burst_bits-1:0] ddr_wr_data_port0;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
+  wire[addr_width-1:0] ddr_rd_addr_port0;
+  wire[max_burst_bits-1:0] ddr_rd_data_port0;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
+  wire [axi_qos_width-1:0] ddr_wr_qos_port0;
+  wire [axi_qos_width-1:0] ddr_rd_qos_port0;
+
+  wire ddr_wr_ack_port1;
+  wire ddr_wr_dv_port1;
+  wire ddr_rd_req_port1;
+  wire ddr_rd_dv_port1;
+  wire[addr_width-1:0] ddr_wr_addr_port1;
+  wire[max_burst_bits-1:0] ddr_wr_data_port1;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
+  wire[addr_width-1:0] ddr_rd_addr_port1;
+  wire[max_burst_bits-1:0] ddr_rd_data_port1;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port1;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port1;
+  
+  wire ddr_wr_ack_port2;
+  wire ddr_wr_dv_port2;
+  wire ddr_rd_req_port2;
+  wire ddr_rd_dv_port2;
+  wire[addr_width-1:0] ddr_wr_addr_port2;
+  wire[max_burst_bits-1:0] ddr_wr_data_port2;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
+  wire[addr_width-1:0] ddr_rd_addr_port2;
+  wire[max_burst_bits-1:0] ddr_rd_data_port2;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port2;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port2;
+  
+  wire ddr_wr_ack_port3;
+  wire ddr_wr_dv_port3;
+  wire ddr_rd_req_port3;
+  wire ddr_rd_dv_port3;
+  wire[addr_width-1:0] ddr_wr_addr_port3;
+  wire[max_burst_bits-1:0] ddr_wr_data_port3;
+  wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
+  wire[addr_width-1:0] ddr_rd_addr_port3;
+  wire[max_burst_bits-1:0] ddr_rd_data_port3;
+  wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
+  wire[axi_qos_width-1:0] ddr_wr_qos_port3;
+  wire[axi_qos_width-1:0] ddr_rd_qos_port3;
+
+  wire reg_rd_req_port0;
+  wire reg_rd_dv_port0;
+  wire[addr_width-1:0] reg_rd_addr_port0;
+  wire[max_burst_bits-1:0] reg_rd_data_port0;
+  wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
+  wire [axi_qos_width-1:0] reg_rd_qos_port0;
+
+  wire reg_rd_req_port1;
+  wire reg_rd_dv_port1;
+  wire[addr_width-1:0] reg_rd_addr_port1;
+  wire[max_burst_bits-1:0] reg_rd_data_port1;
+  wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
+  wire [axi_qos_width-1:0] reg_rd_qos_port1;
+
+  wire [11:0]  M_AXI_GP0_AWID_FULL;
+  wire [11:0]  M_AXI_GP0_WID_FULL;
+  wire [11:0]  M_AXI_GP0_ARID_FULL;
+  
+  wire [11:0]  M_AXI_GP0_BID_FULL;
+  wire [11:0]  M_AXI_GP0_RID_FULL;
+  
+  wire [11:0]  M_AXI_GP1_AWID_FULL;
+  wire [11:0]  M_AXI_GP1_WID_FULL;
+  wire [11:0]  M_AXI_GP1_ARID_FULL;
+  
+  wire [11:0]  M_AXI_GP1_BID_FULL;
+  wire [11:0]  M_AXI_GP1_RID_FULL;
+
+  
+  function [5:0] compress_id; 
+  	input [11:0] id; 
+  		begin 
+  			compress_id = id[5:0]; 
+  		end 
+  endfunction 
+  
+  function [11:0] uncompress_id; 
+  	input [5:0] id; 
+  		begin 
+  		    uncompress_id = {6'b110000, id[5:0]};
+  		end 
+  endfunction
+
+  assign M_AXI_GP0_AWID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
+  assign M_AXI_GP0_WID         = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL)  : M_AXI_GP0_WID_FULL;   
+  assign M_AXI_GP0_ARID        = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;      
+  assign M_AXI_GP0_BID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID)     : M_AXI_GP0_BID;
+  assign M_AXI_GP0_RID_FULL    = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID)     : M_AXI_GP0_RID;      
+
+
+  assign M_AXI_GP1_AWID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
+  assign M_AXI_GP1_WID         = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL)  : M_AXI_GP1_WID_FULL;   
+  assign M_AXI_GP1_ARID        = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;      
+  assign M_AXI_GP1_BID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID)     : M_AXI_GP1_BID;
+  assign M_AXI_GP1_RID_FULL    = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID)     : M_AXI_GP1_RID;      
+
+
+
+
+  processing_system7_vip_v1_0_3_interconnect_model icm (
+                 .rstn(net_rstn),
+                 .sw_clk(net_sw_clk),
+
+                 .w_qos_gp0(net_wr_qos_gp0),
+                 .w_qos_gp1(net_wr_qos_gp1),
+                 .w_qos_hp0(net_wr_qos_hp0),
+                 .w_qos_hp1(net_wr_qos_hp1),
+                 .w_qos_hp2(net_wr_qos_hp2),
+                 .w_qos_hp3(net_wr_qos_hp3),
+                                            
+                 .r_qos_gp0(net_rd_qos_gp0),
+                 .r_qos_gp1(net_rd_qos_gp1),
+                 .r_qos_hp0(net_rd_qos_hp0),
+                 .r_qos_hp1(net_rd_qos_hp1),
+                 .r_qos_hp2(net_rd_qos_hp2),
+                 .r_qos_hp3(net_rd_qos_hp3),
+
+              /* GP Slave ports access */
+                 .wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
+                 .wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
+                 .wr_data_gp0(net_wr_data_gp0),
+                 .wr_addr_gp0(net_wr_addr_gp0),
+                 .wr_bytes_gp0(net_wr_bytes_gp0),
+                 .wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
+                 .wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
+                 .rd_req_ddr_gp0(net_rd_req_ddr_gp0),
+                 .rd_req_ocm_gp0(net_rd_req_ocm_gp0),
+                 .rd_req_reg_gp0(net_rd_req_reg_gp0),
+                 .rd_addr_gp0(net_rd_addr_gp0),
+                 .rd_bytes_gp0(net_rd_bytes_gp0),
+                 .rd_data_ddr_gp0(net_rd_data_ddr_gp0),
+                 .rd_data_ocm_gp0(net_rd_data_ocm_gp0),
+                 .rd_data_reg_gp0(net_rd_data_reg_gp0),
+                 .rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
+                 .rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
+                 .rd_dv_reg_gp0(net_rd_dv_reg_gp0),
+
+                 .wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
+                 .wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
+                 .wr_data_gp1(net_wr_data_gp1), 
+                 .wr_addr_gp1(net_wr_addr_gp1),
+                 .wr_bytes_gp1(net_wr_bytes_gp1),
+                 .wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
+                 .wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
+                 .rd_req_ddr_gp1(net_rd_req_ddr_gp1),
+                 .rd_req_ocm_gp1(net_rd_req_ocm_gp1),
+                 .rd_req_reg_gp1(net_rd_req_reg_gp1),
+                 .rd_addr_gp1(net_rd_addr_gp1),
+                 .rd_bytes_gp1(net_rd_bytes_gp1),
+                 .rd_data_ddr_gp1(net_rd_data_ddr_gp1),
+                 .rd_data_ocm_gp1(net_rd_data_ocm_gp1),
+                 .rd_data_reg_gp1(net_rd_data_reg_gp1),
+                 .rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
+                 .rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
+                 .rd_dv_reg_gp1(net_rd_dv_reg_gp1),
+
+              /* HP Slave ports access */
+                 .wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
+                 .wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
+                 .wr_data_hp0(net_wr_data_hp0),
+                 .wr_addr_hp0(net_wr_addr_hp0),
+                 .wr_bytes_hp0(net_wr_bytes_hp0),
+                 .wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
+                 .wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
+                 .rd_req_ddr_hp0(net_rd_req_ddr_hp0),
+                 .rd_req_ocm_hp0(net_rd_req_ocm_hp0),
+                 .rd_addr_hp0(net_rd_addr_hp0),
+                 .rd_bytes_hp0(net_rd_bytes_hp0),
+                 .rd_data_ddr_hp0(net_rd_data_ddr_hp0),
+                 .rd_data_ocm_hp0(net_rd_data_ocm_hp0),
+                 .rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
+                 .rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
+
+                 .wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
+                 .wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
+                 .wr_data_hp1(net_wr_data_hp1),
+                 .wr_addr_hp1(net_wr_addr_hp1),
+                 .wr_bytes_hp1(net_wr_bytes_hp1),
+                 .wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
+                 .wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
+                 .rd_req_ddr_hp1(net_rd_req_ddr_hp1),
+                 .rd_req_ocm_hp1(net_rd_req_ocm_hp1),
+                 .rd_addr_hp1(net_rd_addr_hp1),
+                 .rd_bytes_hp1(net_rd_bytes_hp1),
+                 .rd_data_ddr_hp1(net_rd_data_ddr_hp1),
+                 .rd_data_ocm_hp1(net_rd_data_ocm_hp1),
+                 .rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
+                 .rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
+
+                 .wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
+                 .wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
+                 .wr_data_hp2(net_wr_data_hp2),
+                 .wr_addr_hp2(net_wr_addr_hp2),
+                 .wr_bytes_hp2(net_wr_bytes_hp2),
+                 .wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
+                 .wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
+                 .rd_req_ddr_hp2(net_rd_req_ddr_hp2),
+                 .rd_req_ocm_hp2(net_rd_req_ocm_hp2),
+                 .rd_addr_hp2(net_rd_addr_hp2),
+                 .rd_bytes_hp2(net_rd_bytes_hp2),
+                 .rd_data_ddr_hp2(net_rd_data_ddr_hp2),
+                 .rd_data_ocm_hp2(net_rd_data_ocm_hp2),
+                 .rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
+                 .rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
+
+                 .wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
+                 .wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
+                 .wr_data_hp3(net_wr_data_hp3),
+                 .wr_addr_hp3(net_wr_addr_hp3),
+                 .wr_bytes_hp3(net_wr_bytes_hp3),
+                 .wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
+                 .wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
+                 .rd_req_ddr_hp3(net_rd_req_ddr_hp3),
+                 .rd_req_ocm_hp3(net_rd_req_ocm_hp3),
+                 .rd_addr_hp3(net_rd_addr_hp3),
+                 .rd_bytes_hp3(net_rd_bytes_hp3),
+                 .rd_data_ddr_hp3(net_rd_data_ddr_hp3),
+                 .rd_data_ocm_hp3(net_rd_data_ocm_hp3),
+                 .rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
+                 .rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
+
+                 /* Goes to port 1 of DDR */
+                 .ddr_wr_ack_port1(ddr_wr_ack_port1),
+                 .ddr_wr_dv_port1(ddr_wr_dv_port1),
+                 .ddr_rd_req_port1(ddr_rd_req_port1),
+                 .ddr_rd_dv_port1 (ddr_rd_dv_port1),
+                 .ddr_wr_addr_port1(ddr_wr_addr_port1),
+                 .ddr_wr_data_port1(ddr_wr_data_port1),
+                 .ddr_wr_bytes_port1(ddr_wr_bytes_port1),
+                 .ddr_rd_addr_port1(ddr_rd_addr_port1),
+                 .ddr_rd_data_port1(ddr_rd_data_port1),
+                 .ddr_rd_bytes_port1(ddr_rd_bytes_port1),
+                 .ddr_wr_qos_port1(ddr_wr_qos_port1),
+                 .ddr_rd_qos_port1(ddr_rd_qos_port1),
+                 
+                /* Goes to port2 of DDR */
+                 .ddr_wr_ack_port2 (ddr_wr_ack_port2),
+                 .ddr_wr_dv_port2  (ddr_wr_dv_port2),
+                 .ddr_rd_req_port2 (ddr_rd_req_port2),
+                 .ddr_rd_dv_port2  (ddr_rd_dv_port2),
+                 .ddr_wr_addr_port2(ddr_wr_addr_port2),
+                 .ddr_wr_data_port2(ddr_wr_data_port2),
+                 .ddr_wr_bytes_port2(ddr_wr_bytes_port2),
+                 .ddr_rd_addr_port2(ddr_rd_addr_port2),
+                 .ddr_rd_data_port2(ddr_rd_data_port2),
+                 .ddr_rd_bytes_port2(ddr_rd_bytes_port2),
+                 .ddr_wr_qos_port2 (ddr_wr_qos_port2),
+                 .ddr_rd_qos_port2 (ddr_rd_qos_port2),
+                
+                /* Goes to port3 of DDR */
+                 .ddr_wr_ack_port3 (ddr_wr_ack_port3),
+                 .ddr_wr_dv_port3  (ddr_wr_dv_port3),
+                 .ddr_rd_req_port3 (ddr_rd_req_port3),
+                 .ddr_rd_dv_port3  (ddr_rd_dv_port3),
+                 .ddr_wr_addr_port3(ddr_wr_addr_port3),
+                 .ddr_wr_data_port3(ddr_wr_data_port3),
+                 .ddr_wr_bytes_port3(ddr_wr_bytes_port3),
+                 .ddr_rd_addr_port3(ddr_rd_addr_port3),
+                 .ddr_rd_data_port3(ddr_rd_data_port3),
+                 .ddr_rd_bytes_port3(ddr_rd_bytes_port3),
+                 .ddr_wr_qos_port3 (ddr_wr_qos_port3),
+                 .ddr_rd_qos_port3 (ddr_rd_qos_port3),
+
+                /* Goes to port 0 of OCM */
+                 .ocm_wr_ack_port1 (ocm_wr_ack_port1),
+                 .ocm_wr_dv_port1  (ocm_wr_dv_port1),
+                 .ocm_rd_req_port1 (ocm_rd_req_port1),
+                 .ocm_rd_dv_port1  (ocm_rd_dv_port1),
+                 .ocm_wr_addr_port1(ocm_wr_addr_port1),
+                 .ocm_wr_data_port1(ocm_wr_data_port1),
+                 .ocm_wr_bytes_port1(ocm_wr_bytes_port1),
+                 .ocm_rd_addr_port1(ocm_rd_addr_port1),
+                 .ocm_rd_data_port1(ocm_rd_data_port1),
+                 .ocm_rd_bytes_port1(ocm_rd_bytes_port1),
+                 .ocm_wr_qos_port1(ocm_wr_qos_port1),
+                 .ocm_rd_qos_port1(ocm_rd_qos_port1), 
+
+                /* Goes to port 0 of REG */
+                 .reg_rd_qos_port1 (reg_rd_qos_port1) ,
+                 .reg_rd_req_port1 (reg_rd_req_port1),
+                 .reg_rd_dv_port1  (reg_rd_dv_port1),
+                 .reg_rd_addr_port1(reg_rd_addr_port1),
+                 .reg_rd_data_port1(reg_rd_data_port1),
+                 .reg_rd_bytes_port1(reg_rd_bytes_port1)
+                 ); 
+
+  processing_system7_vip_v1_0_3_ddrc ddrc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+          
+          /* Goes to port 0 of DDR */
+           .ddr_wr_ack_port0 (ddr_wr_ack_port0),
+           .ddr_wr_dv_port0  (ddr_wr_dv_port0),
+           .ddr_rd_req_port0 (ddr_rd_req_port0),
+           .ddr_rd_dv_port0  (ddr_rd_dv_port0),
+
+           .ddr_wr_addr_port0(net_wr_addr_acp),
+           .ddr_wr_data_port0(net_wr_data_acp),
+           .ddr_wr_bytes_port0(net_wr_bytes_acp),
+
+           .ddr_rd_addr_port0(net_rd_addr_acp),
+           .ddr_rd_bytes_port0(net_rd_bytes_acp),
+           
+           .ddr_rd_data_port0(ddr_rd_data_port0),
+
+           .ddr_wr_qos_port0 (net_wr_qos_acp),
+           .ddr_rd_qos_port0 (net_rd_qos_acp),
+          
+          
+          /* Goes to port 1 of DDR */
+           .ddr_wr_ack_port1 (ddr_wr_ack_port1),
+           .ddr_wr_dv_port1  (ddr_wr_dv_port1),
+           .ddr_rd_req_port1 (ddr_rd_req_port1),
+           .ddr_rd_dv_port1  (ddr_rd_dv_port1),
+           .ddr_wr_addr_port1(ddr_wr_addr_port1),
+           .ddr_wr_data_port1(ddr_wr_data_port1),
+           .ddr_wr_bytes_port1(ddr_wr_bytes_port1),
+           .ddr_rd_addr_port1(ddr_rd_addr_port1),
+           .ddr_rd_data_port1(ddr_rd_data_port1),
+           .ddr_rd_bytes_port1(ddr_rd_bytes_port1),
+           .ddr_wr_qos_port1 (ddr_wr_qos_port1),
+           .ddr_rd_qos_port1 (ddr_rd_qos_port1),
+          
+          /* Goes to port2 of DDR */
+           .ddr_wr_ack_port2 (ddr_wr_ack_port2),
+           .ddr_wr_dv_port2  (ddr_wr_dv_port2),
+           .ddr_rd_req_port2 (ddr_rd_req_port2),
+           .ddr_rd_dv_port2  (ddr_rd_dv_port2),
+           .ddr_wr_addr_port2(ddr_wr_addr_port2),
+           .ddr_wr_data_port2(ddr_wr_data_port2),
+           .ddr_wr_bytes_port2(ddr_wr_bytes_port2),
+           .ddr_rd_addr_port2(ddr_rd_addr_port2),
+           .ddr_rd_data_port2(ddr_rd_data_port2),
+           .ddr_rd_bytes_port2(ddr_rd_bytes_port2),
+           .ddr_wr_qos_port2 (ddr_wr_qos_port2),
+           .ddr_rd_qos_port2 (ddr_rd_qos_port2),
+          
+          /* Goes to port3 of DDR */
+           .ddr_wr_ack_port3 (ddr_wr_ack_port3),
+           .ddr_wr_dv_port3  (ddr_wr_dv_port3),
+           .ddr_rd_req_port3 (ddr_rd_req_port3),
+           .ddr_rd_dv_port3  (ddr_rd_dv_port3),
+           .ddr_wr_addr_port3(ddr_wr_addr_port3),
+           .ddr_wr_data_port3(ddr_wr_data_port3),
+           .ddr_wr_bytes_port3(ddr_wr_bytes_port3),
+           .ddr_rd_addr_port3(ddr_rd_addr_port3),
+           .ddr_rd_data_port3(ddr_rd_data_port3),
+           .ddr_rd_bytes_port3(ddr_rd_bytes_port3),
+           .ddr_wr_qos_port3 (ddr_wr_qos_port3),
+           .ddr_rd_qos_port3 (ddr_rd_qos_port3)
+          
+            );
+
+  processing_system7_vip_v1_0_3_ocmc ocmc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+    
+    /* Goes to port 0 of OCM */
+           .ocm_wr_ack_port0 (ocm_wr_ack_port0),
+           .ocm_wr_dv_port0  (ocm_wr_dv_port0),
+           .ocm_rd_req_port0 (ocm_rd_req_port0),
+           .ocm_rd_dv_port0  (ocm_rd_dv_port0),
+
+           .ocm_wr_addr_port0(net_wr_addr_acp),
+           .ocm_wr_data_port0(net_wr_data_acp),
+           .ocm_wr_bytes_port0(net_wr_bytes_acp),
+
+           .ocm_rd_addr_port0(net_rd_addr_acp),
+           .ocm_rd_bytes_port0(net_rd_bytes_acp),
+           
+           .ocm_rd_data_port0(ocm_rd_data_port0),
+
+           .ocm_wr_qos_port0 (net_wr_qos_acp),
+           .ocm_rd_qos_port0 (net_rd_qos_acp),
+          
+            /* Goes to port 1 of OCM */
+           .ocm_wr_ack_port1 (ocm_wr_ack_port1),
+           .ocm_wr_dv_port1  (ocm_wr_dv_port1),
+           .ocm_rd_req_port1 (ocm_rd_req_port1),
+           .ocm_rd_dv_port1  (ocm_rd_dv_port1),
+           .ocm_wr_addr_port1(ocm_wr_addr_port1),
+           .ocm_wr_data_port1(ocm_wr_data_port1),
+           .ocm_wr_bytes_port1(ocm_wr_bytes_port1),
+           .ocm_rd_addr_port1(ocm_rd_addr_port1),
+           .ocm_rd_data_port1(ocm_rd_data_port1),
+           .ocm_rd_bytes_port1(ocm_rd_bytes_port1),
+           .ocm_wr_qos_port1(ocm_wr_qos_port1),
+           .ocm_rd_qos_port1(ocm_rd_qos_port1) 
+    
+  );
+
+  processing_system7_vip_v1_0_3_regc regc (
+           .rstn(net_rstn),
+           .sw_clk(net_sw_clk),
+    
+            /* Goes to port 0 of REG */
+           .reg_rd_req_port0 (reg_rd_req_port0),
+           .reg_rd_dv_port0  (reg_rd_dv_port0),
+           .reg_rd_addr_port0(net_rd_addr_acp),
+           .reg_rd_bytes_port0(net_rd_bytes_acp),
+           .reg_rd_data_port0(reg_rd_data_port0),
+           .reg_rd_qos_port0 (net_rd_qos_acp),
+          
+            /* Goes to port 1 of REG */
+           .reg_rd_req_port1 (reg_rd_req_port1),
+           .reg_rd_dv_port1  (reg_rd_dv_port1),
+           .reg_rd_addr_port1(reg_rd_addr_port1),
+           .reg_rd_data_port1(reg_rd_data_port1),
+           .reg_rd_bytes_port1(reg_rd_bytes_port1),
+           .reg_rd_qos_port1(reg_rd_qos_port1) 
+    
+  );
+ 
+  /* include axi_gp port instantiations */
+  `include "processing_system7_vip_v1_0_3_axi_gp.v"
+
+  /* include axi_hp port instantiations */
+  `include "processing_system7_vip_v1_0_3_axi_hp.v"
+
+  /* include axi_acp port instantiations */
+  `include "processing_system7_vip_v1_0_3_axi_acp.v"
+
+endmodule
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv
new file mode 100644
index 0000000..beee0f3
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv
@@ -0,0 +1,6479 @@
+//*****************************************************************************
+// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+
+//Generated by MBAC v3.04
+//8-12-2010, 14h 8m 23s
+//--------------------------------------------
+
+//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)
+`define AKRPS ! // ###MBAC###
+
+`timescale 1 ps / 1 ps // ###MBAC###
+
+//Assertion circuit for vunit: inline
+//vunit is bound to module: Axi4LitePC
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_axi4litepc_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);
+  parameter DATA_WIDTH = 64;
+  output [3:1] Axi4LitePC_asr_inline_out;
+  input reset, BVALID, ACLK, RVALID;
+  input [1:0] BRESP;
+  input [1:0] RRESP;
+
+  reg ASR_1, ASR_2, ASR_3;
+
+  assign Axi4LitePC_asr_inline_out={ASR_3, ASR_2, ASR_1};
+
+  //---------------
+  //ASR_1 : assert property ( @(posedge ACLK) ( BVALID |-> BRESP != 2'b1 ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else
+    ASR_1 <= ((BVALID && !((BRESP != 2'b1))));
+
+  //---------------
+  //ASR_2 : assert property ( @(posedge ACLK) ( RVALID |-> RRESP != 2'b1 ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else
+    ASR_2 <= ((RVALID && !((RRESP != 2'b1))));
+
+  //---------------
+  //ASR_3 : assert property ( @(posedge ACLK) ( ( DATA_WIDTH == 32 || DATA_WIDTH == 64 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else
+    ASR_3 <= (!(((DATA_WIDTH == 32) || (DATA_WIDTH == 64))));
+
+endmodule //Axi4LitePC_asr_inline
+/*Instantiation code:
+Axi4LitePC_asr_inline #(DATA_WIDTH) i_Axi4LitePC_asr_inline (Axi4LitePC_asr_inline_out, reset, BVALID, BRESP, ACLK, RVALID, RRESP);
+*/
+//End of circuit(s) for vunit: inline
+
+
+//*****************************************************************************
+// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+
+//RESET_POLARITY_SYMBOL, set to ! (or blank) for active low (high)
+`define AKRPS ! // ###MBAC###
+
+`timescale 1 ps / 1 ps // ###MBAC###
+
+//Assertion circuit for vunit: inline
+//vunit is bound to module: Axi4PC
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_axi4pc_asr_inline (Axi4PC_asr_inline_out, reset, AWVALID, AWBURST, AwAddrIncr, AWADDR, ACLK, AlignMaskW, AWLEN, AWLOCK, AWCACHE, AwSizeInBits, ARESETn, AWREADY, AWID, AWPROT, AWSIZE, AWQOS, AWREGION, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WDATA, WLAST, WSTRB, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, BID, BRESP, ARVALID, ARBURST, ArAddrIncr, ARADDR, AlignMaskR, ARLEN, ARLOCK, ARCACHE, ArSizeInBits, ARREADY, ARID, ARPROT, ARSIZE, ARQOS, ARREGION, RVALID, RREADY, ArCountPending, ArLenPending, RLAST, RidMatch, RRESP, ArExclPending, RDATA, RID, CSYSREQ, CSYSACK, ExclMask, ExclReadAddr, ExclAwMatch, ExclAddr, ExclSize, ExclLen, ExclBurst, ExclCache, ExclProt, ExclRegion, ArLenInBytes, ExclReadData, AWUSER, WUSER, BUSER, ARUSER, RUSER); // ###MBAC###
+  parameter DATA_WIDTH = 64;
+  parameter ID_WIDTH = 4;
+  parameter AWUSER_WIDTH = 32;
+  parameter WUSER_WIDTH = 32;
+  parameter BUSER_WIDTH = 32;
+  parameter ARUSER_WIDTH = 32;
+  parameter RUSER_WIDTH = 32;
+  parameter MAXRBURSTS = 16;
+  parameter MAXWBURSTS = 16;
+  parameter ADDR_WIDTH = 32;
+  parameter EXMON_WIDTH = 4;
+  parameter DATA_MAX = DATA_WIDTH - 1; // ###MBAC###
+  parameter ADDR_MAX = ADDR_WIDTH - 1;
+  parameter STRB_WIDTH = DATA_WIDTH / 8;
+  parameter STRB_MAX = STRB_WIDTH - 1;
+  parameter ID_MAX = ID_WIDTH ? ID_WIDTH - 1 : 0;
+  parameter EXMON_MAX = EXMON_WIDTH - 1;
+  parameter EXMON_HI = {EXMON_WIDTH{1'b1}};
+  parameter AWUSER_MAX = AWUSER_WIDTH ? AWUSER_WIDTH - 1 : 0; // ###MBAC###
+  parameter WUSER_MAX = WUSER_WIDTH ? WUSER_WIDTH - 1 : 0;
+  parameter BUSER_MAX = BUSER_WIDTH ? BUSER_WIDTH - 1 : 0;
+  parameter ARUSER_MAX = ARUSER_WIDTH ? ARUSER_WIDTH - 1 : 0;
+  parameter RUSER_MAX = RUSER_WIDTH ? RUSER_WIDTH - 1 : 0;
+  parameter MAX_AW_WAITS = 16;
+  parameter MAX_AR_WAITS = 16;
+  parameter MAX_W_WAITS  = 16;
+  parameter MAX_R_WAITS  = 16;
+  parameter MAX_B_WAITS  = 16;
+  parameter MAX_CONTINUOUS_RTRANSFERS_WAITS  = 16;
+  parameter MAX_CONTINUOUS_WTRANSFERS_WAITS  = 16;
+  parameter MAX_WLAST_TO_AWVALID_WAITS  = 16;
+  parameter MAX_WRITE_TO_BVALID_WAITS  = 16;
+  parameter LIGHT_WEIGHT  = 0;
+  output [91:1] Axi4PC_asr_inline_out;
+  input reset, AWVALID, ACLK, AWLOCK, ARESETn, AWREADY, i_RecommendOn, i_RecMaxWaitOn, WriteDataNumError, BStrbError, WVALID, WREADY, WLAST, BrespErrorLast, BrespExokError, BVALID, BrespErrorLead, BREADY, ARVALID, ARLOCK, ARREADY, RVALID, RREADY, RLAST, ArExclPending, CSYSREQ, CSYSACK, ExclAwMatch; // ###MBAC###
+  input [1:0] AWBURST;
+  input [ADDR_MAX:0] AwAddrIncr;
+  input [ADDR_MAX:0] AWADDR;
+  input [6:0] AlignMaskW;
+  input [7:0] AWLEN;
+  input [3:0] AWCACHE;
+  input [10:0] AwSizeInBits;
+  input [ID_MAX:0] AWID;
+  input [2:0] AWPROT;
+  input [2:0] AWSIZE;
+  input [3:0] AWQOS;
+  input [3:0] AWREGION;
+  input [DATA_MAX:0] WDATA; // ###MBAC###
+  input [STRB_MAX:0] WSTRB;
+  input [ID_MAX:0] BID; // ###MBAC###
+  input [1:0] BRESP;
+  input [1:0] ARBURST;
+  input [ADDR_MAX:0] ArAddrIncr;
+  input [ADDR_MAX:0] ARADDR;
+  input [6:0] AlignMaskR;
+  input [7:0] ARLEN;
+  input [3:0] ARCACHE;
+  input [10:0] ArSizeInBits;
+  input [ID_MAX:0] ARID;
+  input [2:0] ARPROT;
+  input [2:0] ARSIZE;
+  input [3:0] ARQOS;
+  input [3:0] ARREGION;
+  input [8:0] ArCountPending;
+  input [8:0] ArLenPending;
+  input [31:0] RidMatch;
+  input [1:0] RRESP;
+  input [DATA_MAX:0] RDATA; // ###MBAC###
+  input [ID_MAX:0] RID;
+  input [14:0] ExclMask;
+// ###MBAC###  input [EXMON_MAX:0] ExclAwId;
+// ###MBAC###  input [ADDR_MAX:0] ExclAddr [EXMON_HI:0];
+// ###MBAC###  input [2:0] ExclSize [EXMON_HI:0];
+// ###MBAC###  input [7:0] ExclLen [EXMON_HI:0];
+// ###MBAC###  input [1:0] ExclBurst [EXMON_HI:0];
+// ###MBAC###  input [3:0] ExclCache [EXMON_HI:0];
+// ###MBAC###  input [2:0] ExclProt [EXMON_HI:0];
+// ###MBAC###  input [3:0] ExclRegion [EXMON_HI:0];
+  input [ADDR_MAX:0] ExclAddr;
+  input [2:0] ExclSize;
+  input [7:0] ExclLen;
+  input [1:0] ExclBurst;
+  input [3:0] ExclCache;
+  input [2:0] ExclProt;
+  input [3:0] ExclRegion;
+  input ExclReadAddr;
+  input ExclReadData;
+// ###MBAC###
+  input [15:0] ArLenInBytes;
+  input [AWUSER_MAX:0] AWUSER; // ###MBAC###
+  input [WUSER_MAX:0] WUSER;
+  input [BUSER_MAX:0] BUSER;
+  input [ARUSER_MAX:0] ARUSER;
+  input [RUSER_MAX:0] RUSER;
+// ###MBAC###  input [31:0] RIndex;
+// ###MBAC###  input [31:0] WIndex;
+
+  function integer f_clogb2 (input integer size);
+    integer s;
+    begin
+      s = size;
+      s = s - 1;
+      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+            s = s >> 1;
+    end
+  endfunction // clogb2
+
+  wire [2:0] s1s;
+  reg [2:0] s1sq;
+  reg [ADDR_MAX:0] s2;
+  wire [2:0] s4s;
+  reg [2:0] s4sq;
+  reg [1:0] s5;
+  wire [2:0] s7s;
+  reg [2:0] s7sq;
+  reg [3:0] s8;
+  wire [2:0] s10s;
+  reg [2:0] s10sq;
+  reg [ID_MAX:0] s11;
+  wire [2:0] s13s;
+  reg [2:0] s13sq;
+  reg [7:0] s14;
+  wire [2:0] s16s;
+  reg [2:0] s16sq;
+  wire [2:0] s19s;
+  reg [2:0] s19sq;
+  reg [2:0] s20;
+  wire [2:0] s22s;
+  reg [2:0] s22sq;
+  reg [2:0] s23;
+  wire [2:0] s25s;
+  reg [2:0] s25sq;
+  reg [3:0] s26;
+  wire [2:0] s28s;
+  reg [2:0] s28sq;
+  reg [3:0] s29;
+  wire [2:0] s31s;
+  reg [2:0] s31sq;
+  wire [2:0] s32s;
+  reg [2:0] s32sq;
+  wire [2:0] s34s;
+  reg [2:0] s34sq;
+  reg [DATA_MAX:0] s35;
+  wire [2:0] s37s;
+  reg [2:0] s37sq;
+  wire [2:0] s40s;
+  reg [2:0] s40sq;
+  reg [STRB_MAX:0] s41;
+  wire [2:0] s43s;
+  reg [2:0] s43sq;
+  wire [2:0] s44s;
+  reg [2:0] s44sq;
+  wire [2:0] s46s;
+  reg [2:0] s46sq;
+  reg [ID_MAX:0] s47;
+  wire [2:0] s49s;
+  reg [2:0] s49sq;
+  reg [1:0] s50;
+  wire [2:0] s52s;
+  reg [2:0] s52sq;
+  wire [2:0] s53s;
+  reg [2:0] s53sq;
+  wire [2:0] s55s;
+  reg [2:0] s55sq;
+  reg [ADDR_MAX:0] s56;
+  wire [2:0] s58s;
+  reg [2:0] s58sq;
+  reg [1:0] s59;
+  wire [2:0] s61s;
+  reg [2:0] s61sq;
+  reg [3:0] s62;
+  wire [2:0] s64s;
+  reg [2:0] s64sq;
+  reg [ID_MAX:0] s65;
+  wire [2:0] s67s;
+  reg [2:0] s67sq;
+  reg [7:0] s68;
+  wire [2:0] s70s;
+  reg [2:0] s70sq;
+  wire [2:0] s73s;
+  reg [2:0] s73sq;
+  reg [2:0] s74;
+  wire [2:0] s76s;
+  reg [2:0] s76sq;
+  reg [2:0] s77;
+  wire [2:0] s79s;
+  reg [2:0] s79sq;
+  reg [3:0] s80;
+  wire [2:0] s82s;
+  reg [2:0] s82sq;
+  reg [3:0] s83;
+  wire [2:0] s85s;
+  reg [2:0] s85sq;
+  wire [2:0] s86s;
+  reg [2:0] s86sq;
+  wire [2:0] s88s;
+  reg [2:0] s88sq;
+  reg [DATA_MAX:0] s89;
+  wire [2:0] s91s;
+  reg [2:0] s91sq;
+  reg [ID_MAX:0] s92;
+  wire [2:0] s94s;
+  reg [2:0] s94sq;
+  wire [2:0] s97s;
+  reg [2:0] s97sq;
+  reg [1:0] s98;
+  wire [2:0] s100s;
+  reg [2:0] s100sq;
+  wire [2:0] s101s;
+  reg [2:0] s101sq;
+  reg [31:0] s103;
+  wire [2:0] s105s;
+  reg [2:0] s105sq;
+  reg [WUSER_MAX:0] s106;
+  wire [2:0] s108s;
+  reg [2:0] s108sq;
+  reg [BUSER_MAX:0] s109;
+  wire [2:0] s111s;
+  reg [2:0] s111sq;
+  reg [ARUSER_MAX:0] s112;
+  wire [2:0] s114s;
+  reg [2:0] s114sq;
+  reg [RUSER_MAX:0] s115;
+  wire [2:0] s117s;
+  reg [2:0] s117sq;
+  reg [AWUSER_MAX:0] s118;
+  reg [WUSER_MAX:0] s120;
+  reg [BUSER_MAX:0] s122;
+  reg [ARUSER_MAX:0] s124;
+  reg [RUSER_MAX:0] s126;
+  reg [ID_MAX:0] s128;
+  reg [ID_MAX:0] s130;
+  reg [ID_MAX:0] s132;
+  reg [ID_MAX:0] s134;
+  wire s3, s6, s9, s12, s15, s18, s21, s24, s27, s30, s36, s39, s42, s48, s51, s57, s60, s63, s66, s69, s72, s75, s78, s81, s84, s90, s93, s96, s99, s104, s107, s110, s113, s116, s119, s121, s123, s125, s127, s129, s131, s133, s135;
+  reg ASR_1, ASR_2, ASR_3, ASR_4, ASR_5, ASR_6, ASR_7, ASR_8, ASR_9, ASR_10, ASR_11, ASR_12, ASR_13, ASR_14, s17, ASR_15, ASR_16, ASR_17, ASR_18, ASR_19, ASR_20, ASR_21, ASR_22, ASR_23, ASR_24, ASR_25, s38, ASR_26, ASR_27, ASR_28, ASR_29, ASR_30, ASR_31, ASR_32, ASR_33, ASR_34, ASR_35, ASR_36, ASR_37, ASR_38, ASR_39, ASR_40, ASR_41, ASR_42, ASR_43, ASR_44, ASR_45, ASR_46, ASR_47, ASR_48, ASR_49, ASR_50, ASR_51, s71, ASR_52, ASR_53, ASR_54, ASR_55, ASR_56, ASR_57, ASR_58, ASR_59, ASR_60, ASR_61, ASR_62, ASR_63, ASR_64, s95, ASR_65, ASR_66, ASR_67, ASR_68, ASR_69, ASR_70, ASR_71, ASR_72, ASR_73, ASR_74, ASR_75, ASR_76, ASR_77, ASR_78, ASR_79, ASR_80, ASR_81, ASR_82, ASR_83, ASR_84, ASR_85, ASR_86, ASR_87, ASRX_1, ASRX_2, ASRX_3, ASRX_4;
+
+  assign Axi4PC_asr_inline_out={ASRX_4, ASRX_3, ASRX_2, ASRX_1, ASR_87, ASR_86, ASR_85, ASR_84, ASR_83, ASR_82, ASR_81, ASR_80, ASR_79, ASR_78, ASR_77, ASR_76, ASR_75, ASR_74, ASR_73, ASR_72, ASR_71, ASR_70, ASR_69, ASR_68, ASR_67, ASR_66, ASR_65, ASR_64, ASR_63, ASR_62, ASR_61, ASR_60, ASR_59, ASR_58, ASR_57, ASR_56, ASR_55, ASR_54, ASR_53, ASR_52, ASR_51, ASR_50, ASR_49, ASR_48, ASR_47, ASR_46, ASR_45, ASR_44, ASR_43, ASR_42, ASR_41, ASR_40, ASR_39, ASR_38, ASR_37, ASR_36, ASR_35, ASR_34, ASR_33, ASR_32, ASR_31, ASR_30, ASR_29, ASR_28, ASR_27, ASR_26, ASR_25, ASR_24, ASR_23, ASR_22, ASR_21, ASR_20, ASR_19, ASR_18, ASR_17, ASR_16, ASR_15, ASR_14, ASR_13, ASR_12, ASR_11, ASR_10, ASR_9, ASR_8, ASR_7, ASR_6, ASR_5, ASR_4, ASR_3, ASR_2, ASR_1};
+
+localparam integer L_AW_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);
+localparam integer L_AR_WAIT_WIDTH = f_clogb2(MAX_AW_WAITS+1);
+localparam integer L_W_WAIT_WIDTH  = f_clogb2(MAX_W_WAITS+1);
+localparam integer L_R_WAIT_WIDTH  = f_clogb2(MAX_R_WAITS+1);
+localparam integer L_B_WAIT_WIDTH  = f_clogb2(MAX_B_WAITS+1);
+localparam integer L_WVALID_WAIT_WIDTH  = f_clogb2(MAX_CONTINUOUS_WTRANSFERS_WAITS+1);
+localparam integer L_AWVALID_WAIT_WIDTH  = f_clogb2(MAX_WLAST_TO_AWVALID_WAITS+1);
+localparam integer L_BVALID_WAIT_WIDTH  = f_clogb2(MAX_WRITE_TO_BVALID_WAITS+1);
+localparam integer L_RVALID_WAIT_WIDTH  = f_clogb2(MAX_CONTINUOUS_RTRANSFERS_WAITS+1);
+localparam integer P_W_OUTSTANDING_WIDTH = f_clogb2(MAXWBURSTS);
+localparam integer P_R_OUTSTANDING_WIDTH = f_clogb2(MAXRBURSTS);
+
+genvar AWADDR_bit;
+genvar WSTRB_bit;
+genvar ARADDR_bit;
+genvar AWUSER_bit;
+genvar WUSER_bit;
+genvar BUSER_bit;
+genvar ARUSER_bit;
+genvar RUSER_bit;
+
+generate
+
+  //---------------
+  // BASELINE CHECKS (enabled for all modes)
+  //---------------
+
+  //---------------
+  //ASR_8 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AwSizeInBits <= DATA_WIDTH ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_8<=0; else
+    ASR_8 <= ((AWVALID && !((AwSizeInBits <= DATA_WIDTH))));
+
+  //---------------
+  //ASR_21 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( AWVALID & ! AWREADY ) |-> ##[1:16] ( ! AWVALID | AWREADY ) ) );
+  //---------------
+
+  reg [L_AW_WAIT_WIDTH-1:0]  aw_cnt;
+  wire asr_21_set;
+
+    if (MAX_AW_WAITS > 0) begin : gen_aw_wait
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};
+        end else begin
+          //Valid, not ready, clken
+          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( AWVALID & ! AWREADY )) begin
+            aw_cnt <= aw_cnt + 1;
+          end else begin
+            aw_cnt <= {L_AW_WAIT_WIDTH{1'b0}};
+          end
+        end
+      end
+
+      assign asr_21_set = (aw_cnt == MAX_AW_WAITS) & (AWVALID & ! AWREADY);
+    end else begin : gen_no_aw_wait
+      assign asr_21_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_21<=0; else
+    ASR_21 <= asr_21_set;
+
+  //---------------
+  //ASR_22 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ WriteDataNumError ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_22<=0; else
+    ASR_22 <= ((ARESETn && WriteDataNumError));
+
+  //---------------
+  //ASR_29 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( WVALID & ! WREADY ) |-> ##[1:16] ( ! WVALID | WREADY ) ) );
+  //---------------
+  reg [L_W_WAIT_WIDTH-1:0]  w_cnt;
+  wire asr_29_set;
+
+    if (MAX_W_WAITS > 0) begin : gen_w_wait
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          w_cnt <= {L_W_WAIT_WIDTH{1'b0}};
+        end else begin
+          //Valid, not ready, clken
+          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( WVALID & ! WREADY )) begin
+            w_cnt <= w_cnt + 1;
+          end else begin
+            w_cnt <= {L_W_WAIT_WIDTH{1'b0}};
+          end
+        end
+      end
+
+      assign asr_29_set = (w_cnt == MAX_W_WAITS) & ( WVALID & ! WREADY );
+    end else begin : gen_no_w_wait
+      assign asr_29_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_29<=0; else
+    ASR_29 <= asr_29_set;
+
+  //---------------
+  //ASR_30 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLast ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_30<=0; else
+    ASR_30 <= ((ARESETn && BrespErrorLast));
+
+  //---------------
+  //ASR_33 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespErrorLead ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_33<=0; else
+    ASR_33 <= ((ARESETn && BrespErrorLead));
+
+  //---------------
+  //ASR_37 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( BVALID & ! BREADY ) |-> ##[1:16] ( ! BVALID | BREADY ) ) );
+  //---------------
+  reg [L_B_WAIT_WIDTH-1:0]  b_cnt;
+  wire asr_37_set;
+
+    if (MAX_B_WAITS > 0) begin : gen_b_wait
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          b_cnt <= {L_B_WAIT_WIDTH{1'b0}};
+        end else begin
+          //Valid, not ready, clken
+          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( BVALID & ! BREADY )) begin
+            b_cnt <= b_cnt + 1;
+          end else begin
+            b_cnt <= {L_B_WAIT_WIDTH{1'b0}};
+          end
+        end
+      end
+
+      assign asr_37_set = (b_cnt == MAX_B_WAITS) & ( BVALID & ! BREADY );
+
+    end else begin : gen_no_b_wait
+      assign asr_37_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_37<=0; else
+    ASR_37 <= asr_37_set;
+
+  //---------------
+  //ASR_45 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ArSizeInBits <= DATA_WIDTH ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_45<=0; else
+    ASR_45 <= ((ARVALID && !((ArSizeInBits <= DATA_WIDTH))));
+
+  //---------------
+  //ASR_58 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( ARVALID & ! ARREADY ) |-> ##[1:16] ( ! ARVALID | ARREADY ) ) );
+  //---------------
+  reg [L_AR_WAIT_WIDTH-1:0]  ar_cnt;
+  wire asr_58_set;
+
+    if (MAX_AR_WAITS > 0) begin : gen_ar_wait
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};
+        end else begin
+          //Valid, not ready, clken
+          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( ARVALID & ! ARREADY )) begin
+            ar_cnt <= ar_cnt + 1;
+          end else begin
+            ar_cnt <= {L_AR_WAIT_WIDTH{1'b0}};
+          end
+        end
+      end
+
+      assign asr_58_set = (ar_cnt == MAX_AR_WAITS) & ( ARVALID & ! ARREADY );
+
+    end else begin : gen_no_ar_wait
+      assign asr_58_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_58<=0; else
+    ASR_58 <= asr_58_set;
+
+  //---------------
+  //ASR_59 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY |-> ( ( ( ArCountPending == ArLenPending ) & RLAST ) | ( ( ArCountPending != ArLenPending ) & ~ RLAST ) ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_59<=0; else
+    ASR_59 <= ((ARESETn & RVALID) && !((( (( (ArCountPending == ArLenPending) ) & RLAST) ) | ( (( (ArCountPending != ArLenPending) ) & (~ RLAST)) ))));
+
+  //---------------
+  //ASR_60 : assert property ( @(posedge ACLK) ( ARESETn & RVALID |-> ( RidMatch > 0 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_60<=0; else
+    ASR_60 <= (((ARESETn & RVALID) && !((RidMatch > 0))));
+
+  //---------------
+  //ASR_68 : assert property ( @(posedge ACLK) ( ARESETn & i_RecommendOn & i_RecMaxWaitOn & ( RVALID & ! RREADY ) |-> ##[1:16] ( ! RVALID | RREADY ) ) );
+  //---------------
+  reg [L_R_WAIT_WIDTH-1:0]  r_cnt;
+  wire asr_68_set;
+
+    if (MAX_R_WAITS > 0) begin : gen_r_wait
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          r_cnt <= {L_R_WAIT_WIDTH{1'b0}};
+        end else begin
+          //Valid, not ready, clken
+          if (((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) & ( RVALID & ! RREADY )) begin
+            r_cnt <= r_cnt + 1;
+          end else begin
+            r_cnt <= {L_R_WAIT_WIDTH{1'b0}};
+          end
+        end
+      end
+
+      assign asr_68_set = (r_cnt == MAX_R_WAITS) & ( RVALID & ! RREADY );
+    end else begin : gen_no_r_wait
+      assign asr_68_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_68<=0; else
+    ASR_68 <= asr_68_set;
+
+  //---------------
+  // STALL CHECKS
+  //---------------
+  
+  reg [P_W_OUTSTANDING_WIDTH:0] aw_active;  // Number of AW commands outstanding
+  reg [P_W_OUTSTANDING_WIDTH:0] w_active;  // Number of W bursts outstanding
+  reg [P_W_OUTSTANDING_WIDTH+1:0] aw_w_active;  // Number of AW commands exceeding W bursts 
+  wire aw_push;
+  wire w_push;
+  wire b_pop;
+  
+    if (MAX_CONTINUOUS_WTRANSFERS_WAITS>0 || MAX_WLAST_TO_AWVALID_WAITS>0 || MAX_WRITE_TO_BVALID_WAITS>0) begin : gen_w_active
+      assign aw_push = AWVALID & AWREADY;
+      assign w_push = WVALID & WREADY & WLAST; 
+      assign b_pop = BVALID & BREADY;
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          aw_active <= {P_W_OUTSTANDING_WIDTH+1{1'b0}};
+          w_active <= {P_W_OUTSTANDING_WIDTH+1{1'b0}};
+          aw_w_active <= {P_W_OUTSTANDING_WIDTH+2{1'b0}};
+        end else begin
+          if ((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) begin
+            if (aw_push & !b_pop) begin
+              aw_active <= aw_active + 1;
+            end else if (!aw_push & b_pop) begin
+              aw_active <= aw_active - 1;
+            end
+            if (w_push & !b_pop) begin
+              w_active <= w_active + 1;
+            end else if (!w_push & b_pop) begin
+              w_active <= w_active - 1;
+            end
+            if (aw_push & !w_push) begin
+              aw_w_active <= aw_w_active + 1;
+            end else if (!aw_push & w_push) begin
+              aw_w_active <= aw_w_active - 1;
+            end
+          end
+        end
+      end
+    end // gen_w_active
+  
+  //---------------
+  //ASRX_1 : XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT : Cycles waiting for RVALID, after AR command, exceeds MAX_CONTINUOUS_RTRANSFERS_WAITS
+  //---------------
+
+  reg [L_RVALID_WAIT_WIDTH-1:0]  ar_r_cnt;  // Timer
+  reg [P_R_OUTSTANDING_WIDTH-1:0] ar_active;  // Number of AR commands outstanding
+  wire asrx_1_set;
+  wire ar_push;
+  wire r_pop;
+  wire ar_r_any_active;
+
+    if (MAX_CONTINUOUS_RTRANSFERS_WAITS > 0) begin : gen_ar_r_wait
+      assign ar_push = ARVALID & ARREADY;  // AR command
+      assign r_pop = RVALID & RREADY & RLAST;  // R burst completion
+      assign ar_r_any_active = |ar_active;  // Positive count value
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          ar_r_cnt <= {L_RVALID_WAIT_WIDTH{1'b0}};
+          ar_active <= {P_R_OUTSTANDING_WIDTH{1'b0}};
+        end else begin
+          if ((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) begin
+            if (ar_push & !r_pop) begin
+              ar_active <= ar_active + 1;
+            end else if (!ar_push & r_pop) begin
+              ar_active <= ar_active - 1;
+            end
+            if (ar_r_any_active & ~RVALID) begin  // RVALID stall
+              ar_r_cnt <= ar_r_cnt + 1;
+            end else begin
+              ar_r_cnt <= {L_RVALID_WAIT_WIDTH{1'b0}};
+            end
+          end
+        end
+      end
+
+      assign asrx_1_set = (ar_r_cnt == MAX_CONTINUOUS_RTRANSFERS_WAITS);
+    end else begin : gen_no_ar_r_wait
+      assign asrx_1_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASRX_1<=0; else
+    ASRX_1 <= asrx_1_set;
+
+  //---------------
+  //ASRX_2 : XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT : !WVALID cycles, while AW commands outstanding, exceeds MAX_CONTINUOUS_WTRANSFERS_WAITS
+  //---------------
+
+  reg [L_WVALID_WAIT_WIDTH-1:0]  aw_w_cnt;  // Timer
+  wire asrx_2_set;
+  wire aw_w_any_active;
+
+    if (MAX_CONTINUOUS_WTRANSFERS_WAITS > 0) begin : gen_aw_w_wait
+      assign aw_w_any_active = !aw_w_active[P_W_OUTSTANDING_WIDTH+1] & |aw_w_active[P_W_OUTSTANDING_WIDTH:0];  // Positive count value
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          aw_w_cnt <= {L_WVALID_WAIT_WIDTH{1'b0}};
+        end else begin
+          if ((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) begin
+            if (aw_w_any_active & ~WVALID) begin  // WVALID stalling
+              aw_w_cnt <= aw_w_cnt + 1;
+            end else begin
+              aw_w_cnt <= {L_WVALID_WAIT_WIDTH{1'b0}};
+            end
+          end
+        end
+      end
+
+      assign asrx_2_set = (aw_w_cnt == MAX_CONTINUOUS_WTRANSFERS_WAITS);
+    end else begin : gen_no_aw_w_wait
+      assign asrx_2_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASRX_2<=0; else
+    ASRX_2 <= asrx_2_set;
+
+  //---------------
+  //ASRX_3 : XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT : Cycles waiting for AWVALID, after W burst already started, exceeds MAX_WLAST_TO_AWVALID_WAITS
+  //---------------
+
+  reg [L_AWVALID_WAIT_WIDTH-1:0]  w_aw_cnt;  // Timer
+  wire asrx_3_set;
+  wire w_aw_any_active;
+
+    if (MAX_WLAST_TO_AWVALID_WAITS > 0) begin : gen_w_aw_wait
+      assign w_aw_any_active = aw_w_active[P_W_OUTSTANDING_WIDTH+1];  // Negative count value
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          w_aw_cnt <= {L_AWVALID_WAIT_WIDTH{1'b0}};
+        end else begin
+          if ((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) begin
+            if (w_aw_any_active & ~AWVALID) begin  // AWVALID stall
+              w_aw_cnt <= w_aw_cnt + 1;
+            end else begin
+              w_aw_cnt <= {L_AWVALID_WAIT_WIDTH{1'b0}};
+            end
+          end
+        end
+      end
+
+      assign asrx_3_set = (w_aw_cnt == MAX_WLAST_TO_AWVALID_WAITS);
+    end else begin : gen_no_w_aw_wait
+      assign asrx_3_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASRX_3<=0; else
+    ASRX_3 <= asrx_3_set;
+
+  //---------------
+  //ASRX_4 : XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT : Cycles waiting for BVALID, after AW command or W burst completion, exceeds MAX_WRITE_TO_BVALID_WAITS
+  //---------------
+
+  reg [L_BVALID_WAIT_WIDTH-1:0]  w_b_cnt;  // Timer
+  wire asrx_4_set;
+  wire w_b_any_active;
+
+    if (MAX_WRITE_TO_BVALID_WAITS > 0) begin : gen_w_b_wait
+      assign w_b_any_active = |aw_active & |w_active;  // Both AW and W outstanding counts >0
+      always @(posedge ACLK) begin
+        if (`AKRPS reset) begin
+          w_b_cnt <= {L_BVALID_WAIT_WIDTH{1'b0}};
+        end else begin
+          if ((ARESETn & i_RecommendOn) & i_RecMaxWaitOn) begin
+            if (w_b_any_active & ~BVALID) begin  // BVALID stall
+              w_b_cnt <= w_b_cnt + 1;
+            end else begin
+              w_b_cnt <= {L_BVALID_WAIT_WIDTH{1'b0}};
+            end
+          end
+        end
+      end
+
+      assign asrx_4_set = (w_b_cnt == MAX_WRITE_TO_BVALID_WAITS);
+    end else begin : gen_no_w_b_wait
+      assign asrx_4_set = 1'b0;
+    end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASRX_4<=0; else
+    ASRX_4 <= asrx_4_set;
+
+//==================================================================================================================================================
+
+if (LIGHT_WEIGHT==0) begin : gen_deflt_chks
+  //---------------
+  // DEFAULT CHECKS (disabled in light-weight mode)
+  //---------------
+
+  //---------------
+  //ASR_1 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b1 ) |-> ( AwAddrIncr[ADDR_MAX:12] == AWADDR[ADDR_MAX:12] ) ) );
+  //---------------
+  reg [ADDR_MAX-12:0] AwAddrIncr_q1;
+  reg [ADDR_MAX-12:0] AWADDR_q1;
+  reg                 asr_1_ctrl;
+  always @(posedge ACLK) begin
+    AwAddrIncr_q1 <= AwAddrIncr[ADDR_MAX:12];
+    AWADDR_q1     <= AWADDR[ADDR_MAX:12];
+    asr_1_ctrl   <= (AWVALID & ( (AWBURST == 2'b1) ));
+  end
+
+  always @(posedge ACLK) if (`AKRPS reset) ASR_1<=0; else
+    ASR_1 <= asr_1_ctrl && !(AwAddrIncr_q1 == AWADDR_q1);
+
+  //---------------
+  //ASR_2 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( ( AWADDR[6:0] & AlignMaskW ) == AWADDR[6:0] ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_2<=0; else
+    ASR_2 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !((( (AWADDR[6:0] & AlignMaskW) ) == AWADDR[6:0]))));
+
+  //---------------
+  //ASR_3 : assert property ( @(posedge ACLK) ( AWVALID |-> ( AWBURST != 2'b11 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_3<=0; else
+    ASR_3 <= ((AWVALID && !((AWBURST != 2'b11))));
+
+  //---------------
+  //ASR_4 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWLOCK != 1'b1 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_4<=0; else
+    ASR_4 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWLOCK != 1'b1))));
+
+  //---------------
+  //ASR_5 : assert property ( @(posedge ACLK) ( AWVALID & ~ AWCACHE[1] |-> ( AWCACHE[3:2] == 2'b0 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_5<=0; else
+    ASR_5 <= (((AWVALID & (~ AWCACHE[1])) && !((AWCACHE[3:2] == 2'b0))));
+
+  //---------------
+  //ASR_6 : assert property ( @(posedge ACLK) ( AWVALID & AWLEN > 8'b1111 |-> ( AWBURST != 2'b0 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_6<=0; else
+    ASR_6 <= (((AWVALID & (AWLEN > 8'b1111)) && !((AWBURST != 2'b0))));
+
+  //---------------
+  //ASR_7 : assert property ( @(posedge ACLK) ( AWVALID & ( AWBURST == 2'b10 ) |-> ( AWLEN == 8'b1 || AWLEN == 8'b11 || AWLEN == 8'b111 || AWLEN == 8'b1111 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_7<=0; else
+    ASR_7 <= (((AWVALID & ( (AWBURST == 2'b10) )) && !(((((AWLEN == 8'b1) || (AWLEN == 8'b11)) || (AWLEN == 8'b111)) || (AWLEN == 8'b1111)))));
+
+  //---------------
+  //ASR_9 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! AWVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s1sq<=3'h4; else
+    s1sq<=s1s;
+  assign s1s={1'b1,
+    !(ARESETn),
+    (s1sq[1] && (ARESETn && AWVALID))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_9<=0; else
+    ASR_9 <= (s1s[0]);
+
+  //---------------
+  //ASR_10 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWADDR) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s2<=AWADDR;
+//  assign s3 = s2 == AWADDR;
+//  always @(posedge ACLK) if (`AKRPS reset) s4sq<=3'h4; else
+//    s4sq<=s4s;
+//  assign s4s={1'b1,
+//    ((ARESETn & AWVALID) & (! AWREADY)),
+//    (s4sq[1] && (ARESETn && !(s3)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_10<=0; else
+//    ASR_10 <= (s4s[0]);
+localparam integer L_NUM_AWADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);
+localparam integer L_NUM_AWADDR_BYTE_LANES  = ((L_NUM_AWADDR_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_AWADDR_EQ_LANES    = (L_NUM_AWADDR_BYTE_LANES / 8);
+localparam integer L_NUM_AWADDR_AND1_LANES  = (L_NUM_AWADDR_EQ_LANES + 7) / 8;
+localparam integer L_NUM_AWADDR_AND2_LANES  = (L_NUM_AWADDR_AND1_LANES + 7) / 8;
+
+reg   [ADDR_WIDTH - 1:0]  AWADDR_q;
+reg   [4:0]               s_AWADDR_sq;
+wire  [4:0]               s_AWADDR_s;
+wire                      s_AWADDR_sqaa;
+
+reg [(8*L_NUM_AWADDR_EQ_LANES)-1:0]    AWADDR_eq;
+reg [(8*L_NUM_AWADDR_AND1_LANES)-1:0]  AWADDR_stage_1_eq;
+reg [(8*L_NUM_AWADDR_AND2_LANES)-1:0]  AWADDR_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_AWADDR_sq<=5'h00; 
+    ASR_10 <=0;
+  end else begin
+    s_AWADDR_sq<=s_AWADDR_s;
+    ASR_10 <= (s_AWADDR_s[0]);
+  end
+end
+
+assign s_AWADDR_s={
+  (((ARESETn & AWVALID) & (! AWREADY))),
+  (s_AWADDR_sq[4] && ARESETn),
+  (s_AWADDR_sq[3]),
+  (s_AWADDR_sq[2]),
+  (s_AWADDR_sq[1] & !(s_AWADDR_sqaa))
+  };
+
+assign s_AWADDR_sqaa = &AWADDR_stage_2_eq;
+
+wire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDR_expand;
+wire  [(L_NUM_AWADDR_BYTES*8)-1:0]      AWADDRsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the AWADDR up to the nearest byte
+  for (AWADDR_bit = 0; AWADDR_bit < (L_NUM_AWADDR_BYTES * 8); AWADDR_bit = AWADDR_bit + 1) begin : AWADDR_BIT_LOOP
+    if (AWADDR_bit < ADDR_WIDTH) begin : VAL
+      assign AWADDR_expand[AWADDR_bit] = AWADDR[AWADDR_bit];
+      assign AWADDRsqa_expand[AWADDR_bit] = AWADDR_q[AWADDR_bit];
+    end else begin
+      assign AWADDR_expand[AWADDR_bit] = 1'b0;
+      assign AWADDRsqa_expand[AWADDR_bit] = 1'b0;
+    end
+  end
+
+integer AWADDR_bc;
+integer AWADDR_stage_1;
+integer AWADDR_stage_2;
+
+always @(posedge ACLK) begin
+  AWADDR_q<=AWADDR;
+
+  for (AWADDR_bc = 0; AWADDR_bc < L_NUM_AWADDR_EQ_LANES*8; AWADDR_bc = AWADDR_bc + 1) begin : AWADDR_BC_LOOP
+    if (AWADDR_bc < L_NUM_AWADDR_BYTES) begin
+      AWADDR_eq[AWADDR_bc] <= AWADDR_expand[AWADDR_bc*8 +:8] == AWADDRsqa_expand[AWADDR_bc*8 +: 8];
+    end else begin
+      AWADDR_eq[AWADDR_bc] <= 1'b1;
+    end
+  end
+
+  for (AWADDR_stage_1 = 0; AWADDR_stage_1 < L_NUM_AWADDR_AND1_LANES * 8;AWADDR_stage_1 = AWADDR_stage_1 + 1) begin : AWADDR_S1
+    if (AWADDR_stage_1 < L_NUM_AWADDR_EQ_LANES) begin
+      AWADDR_stage_1_eq[AWADDR_stage_1] <= &AWADDR_eq[AWADDR_stage_1*8 +:8];
+    end else begin
+      AWADDR_stage_1_eq[AWADDR_stage_1] <= 1'b1;
+    end
+  end
+
+  for (AWADDR_stage_2 = 0; AWADDR_stage_2 < L_NUM_AWADDR_AND2_LANES * 8;AWADDR_stage_2 = AWADDR_stage_2 + 1) begin : AWADDR_S2
+    if (AWADDR_stage_2 < L_NUM_AWADDR_AND1_LANES) begin
+      AWADDR_stage_2_eq[AWADDR_stage_2] <= &AWADDR_stage_1_eq[AWADDR_stage_2*8 +:8];
+    end else begin
+      AWADDR_stage_2_eq[AWADDR_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_11 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWBURST) ) );
+  //---------------
+  always @(posedge ACLK)
+    s5<=AWBURST;
+  assign s6 = s5 == AWBURST;
+  always @(posedge ACLK) if (`AKRPS reset) s7sq<=3'h4; else
+    s7sq<=s7s;
+  assign s7s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s7sq[1] && (ARESETn && !(s6)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_11<=0; else
+    ASR_11 <= (s7s[0]);
+
+  //---------------
+  //ASR_12 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWCACHE) ) );
+  //---------------
+  always @(posedge ACLK)
+    s8<=AWCACHE;
+  assign s9 = s8 == AWCACHE;
+  always @(posedge ACLK) if (`AKRPS reset) s10sq<=3'h4; else
+    s10sq<=s10s;
+  assign s10s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s10sq[1] && (ARESETn && !(s9)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_12<=0; else
+    ASR_12 <= (s10s[0]);
+
+  //---------------
+  //ASR_13 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s11<=AWID;
+  assign s12 = s11 == AWID;
+  always @(posedge ACLK) if (`AKRPS reset) s13sq<=3'h4; else
+    s13sq<=s13s;
+  assign s13s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s13sq[1] && (ARESETn && !(s12)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_13<=0; else
+    ASR_13 <= (s13s[0]);
+
+  //---------------
+  //ASR_14 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLEN) ) );
+  //---------------
+  always @(posedge ACLK)
+    s14<=AWLEN;
+  assign s15 = s14 == AWLEN;
+  always @(posedge ACLK) if (`AKRPS reset) s16sq<=3'h4; else
+    s16sq<=s16s;
+  assign s16s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s16sq[1] && (ARESETn && !(s15)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_14<=0; else
+    ASR_14 <= (s16s[0]);
+
+  //---------------
+  //ASR_15 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWLOCK) ) );
+  //---------------
+  always @(posedge ACLK)
+    s17<=AWLOCK;
+  assign s18 = s17 == AWLOCK;
+  always @(posedge ACLK) if (`AKRPS reset) s19sq<=3'h4; else
+    s19sq<=s19s;
+  assign s19s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s19sq[1] && (ARESETn && !(s18)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_15<=0; else
+    ASR_15 <= (s19s[0]);
+
+  //---------------
+  //ASR_16 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWPROT) ) );
+  //---------------
+  always @(posedge ACLK)
+    s20<=AWPROT;
+  assign s21 = s20 == AWPROT;
+  always @(posedge ACLK) if (`AKRPS reset) s22sq<=3'h4; else
+    s22sq<=s22s;
+  assign s22s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s22sq[1] && (ARESETn && !(s21)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_16<=0; else
+    ASR_16 <= (s22s[0]);
+
+  //---------------
+  //ASR_17 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWSIZE) ) );
+  //---------------
+  always @(posedge ACLK)
+    s23<=AWSIZE;
+  assign s24 = s23 == AWSIZE;
+  always @(posedge ACLK) if (`AKRPS reset) s25sq<=3'h4; else
+    s25sq<=s25s;
+  assign s25s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s25sq[1] && (ARESETn && !(s24)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_17<=0; else
+    ASR_17 <= (s25s[0]);
+
+  //---------------
+  //ASR_18 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWQOS) ) );
+  //---------------
+  always @(posedge ACLK)
+    s26<=AWQOS;
+  assign s27 = s26 == AWQOS;
+  always @(posedge ACLK) if (`AKRPS reset) s28sq<=3'h4; else
+    s28sq<=s28s;
+  assign s28s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s28sq[1] && (ARESETn && !(s27)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_18<=0; else
+    ASR_18 <= (s28s[0]);
+
+  //---------------
+  //ASR_19 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWREGION) ) );
+  //---------------
+  always @(posedge ACLK)
+    s29<=AWREGION;
+  assign s30 = s29 == AWREGION;
+  always @(posedge ACLK) if (`AKRPS reset) s31sq<=3'h4; else
+    s31sq<=s31s;
+  assign s31s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s31sq[1] && (ARESETn && !(s30)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_19<=0; else
+    ASR_19 <= (s31s[0]);
+
+  //---------------
+  //ASR_20 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> AWVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s32sq<=3'h4; else
+    s32sq<=s32s;
+  assign s32s={1'b1,
+    ((ARESETn & AWVALID) & (! AWREADY)),
+    (s32sq[1] && (ARESETn && !(AWVALID)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_20<=0; else
+    ASR_20 <= (s32s[0]);
+
+  //---------------
+  //ASR_23 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BStrbError ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_23<=0; else
+    ASR_23 <= ((ARESETn && BStrbError));
+
+  //---------------
+  //ASR_24 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! WVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s34sq<=3'h4; else
+    s34sq<=s34s;
+  assign s34s={1'b1,
+    !(ARESETn),
+    (s34sq[1] && (ARESETn && WVALID))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_24<=0; else
+    ASR_24 <= (s34s[0]);
+
+  //---------------
+  //ASR_25 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WDATA) ) );
+//  //---------------
+//  always @(posedge ACLK)
+//    s35<=WDATA;
+//  assign s36 = s35 == WDATA;
+//  always @(posedge ACLK) if (`AKRPS reset) s37sq<=3'h4; else
+//    s37sq<=s37s;
+//  assign s37s={1'b1,
+//    ((ARESETn & WVALID) & (! WREADY)),
+//    (s37sq[1] && (ARESETn && !(s36)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_25<=0; else
+//    ASR_25 <= (s37s[0]);
+
+localparam integer L_NUM_WDATA_BYTES       = ((DATA_WIDTH + 7) / 8);
+localparam integer L_NUM_WDATA_BYTE_LANES  = ((L_NUM_WDATA_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_WDATA_EQ_LANES    = (L_NUM_WDATA_BYTE_LANES / 8);
+localparam integer L_NUM_WDATA_AND1_LANES  = (L_NUM_WDATA_EQ_LANES + 7) / 8;
+localparam integer L_NUM_WDATA_AND2_LANES  = (L_NUM_WDATA_AND1_LANES + 7) / 8;
+
+reg   [DATA_WIDTH - 1:0]  WDATA_q;
+reg   [4:0]               s_WDATA_sq;
+wire  [4:0]               s_WDATA_s;
+wire                      s_WDATA_sqaa;
+
+reg [(8*L_NUM_WDATA_EQ_LANES)-1:0]    WDATA_eq;
+reg [(8*L_NUM_WDATA_AND1_LANES)-1:0]  WDATA_stage_1_eq;
+reg [(8*L_NUM_WDATA_AND2_LANES)-1:0]  WDATA_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_WDATA_sq<=5'h00; 
+    ASR_25 <=0;
+  end else begin
+    s_WDATA_sq<=s_WDATA_s;
+    ASR_25 <= (s_WDATA_s[0]);
+  end
+end
+
+assign s_WDATA_s={
+  (((ARESETn & WVALID) & (! WREADY))),
+  (s_WDATA_sq[4] && ARESETn),
+  (s_WDATA_sq[3]),
+  (s_WDATA_sq[2]),
+  (s_WDATA_sq[1] & !(s_WDATA_sqaa))
+  };
+
+assign s_WDATA_sqaa = &WDATA_stage_2_eq;
+
+integer WDATA_bc;
+integer WDATA_stage_1;
+integer WDATA_stage_2;
+
+always @(posedge ACLK) begin
+  WDATA_q<=WDATA;
+
+  for (WDATA_bc = 0; WDATA_bc < L_NUM_WDATA_EQ_LANES*8; WDATA_bc = WDATA_bc + 1) begin : WDATA_BC_LOOP
+    if (WDATA_bc < L_NUM_WDATA_BYTES) begin
+      WDATA_eq[WDATA_bc] <= WDATA_q[WDATA_bc*8 +:8] == WDATA[WDATA_bc*8 +: 8];
+    end else begin
+      WDATA_eq[WDATA_bc] <= 1'b1;
+    end
+  end
+
+  for (WDATA_stage_1 = 0; WDATA_stage_1 < L_NUM_WDATA_AND1_LANES * 8;WDATA_stage_1 = WDATA_stage_1 + 1) begin : WDATA_S1
+    if (WDATA_stage_1 < L_NUM_WDATA_EQ_LANES) begin
+      WDATA_stage_1_eq[WDATA_stage_1] <= &WDATA_eq[WDATA_stage_1*8 +:8];
+    end else begin
+      WDATA_stage_1_eq[WDATA_stage_1] <= 1'b1;
+    end
+  end
+
+  for (WDATA_stage_2 = 0; WDATA_stage_2 < L_NUM_WDATA_AND2_LANES * 8;WDATA_stage_2 = WDATA_stage_2 + 1) begin : WDATA_S2
+    if (WDATA_stage_2 < L_NUM_WDATA_AND1_LANES) begin
+      WDATA_stage_2_eq[WDATA_stage_2] <= &WDATA_stage_1_eq[WDATA_stage_2*8 +:8];
+    end else begin
+      WDATA_stage_2_eq[WDATA_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+
+  //---------------
+  //ASR_26 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WLAST) ) );
+  //---------------
+  always @(posedge ACLK)
+    s38<=WLAST;
+  assign s39 = s38 == WLAST;
+  always @(posedge ACLK) if (`AKRPS reset) s40sq<=3'h4; else
+    s40sq<=s40s;
+  assign s40s={1'b1,
+    ((ARESETn & WVALID) & (! WREADY)),
+    (s40sq[1] && (ARESETn && !(s39)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_26<=0; else
+    ASR_26 <= (s40s[0]);
+
+  //---------------
+  //ASR_27 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WSTRB) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s41<=WSTRB;
+//  assign s42 = s41 == WSTRB;
+//  always @(posedge ACLK) if (`AKRPS reset) s43sq<=3'h4; else
+//    s43sq<=s43s;
+//  assign s43s={1'b1,
+//    ((ARESETn & WVALID) & (! WREADY)),
+//    (s43sq[1] && (ARESETn && !(s42)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_27<=0; else
+//    ASR_27 <= (s43s[0]);
+localparam integer L_NUM_WSTRB_BYTES       = (((DATA_WIDTH/8) + 7) / 8);
+localparam integer L_NUM_WSTRB_BYTE_LANES  = ((L_NUM_WSTRB_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_WSTRB_EQ_LANES    = (L_NUM_WSTRB_BYTE_LANES / 8);
+localparam integer L_NUM_WSTRB_AND1_LANES  = (L_NUM_WSTRB_EQ_LANES + 7) / 8;
+localparam integer L_NUM_WSTRB_AND2_LANES  = (L_NUM_WSTRB_AND1_LANES + 7) / 8;
+
+reg   [(DATA_WIDTH/8) - 1:0] WSTRB_q;
+reg   [4:0]               s_WSTRB_sq;
+wire  [4:0]               s_WSTRB_s;
+wire                      s_WSTRB_sqaa;
+
+reg [(8*L_NUM_WSTRB_EQ_LANES)-1:0]    WSTRB_eq;
+reg [(8*L_NUM_WSTRB_AND1_LANES)-1:0]  WSTRB_stage_1_eq;
+reg [(8*L_NUM_WSTRB_AND2_LANES)-1:0]  WSTRB_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_WSTRB_sq<=5'h00; 
+    ASR_27 <=0;
+  end else begin
+    s_WSTRB_sq<=s_WSTRB_s;
+    ASR_27 <= (s_WSTRB_s[0]);
+  end
+end
+
+assign s_WSTRB_s={
+  (((ARESETn & WVALID) & (! WREADY))),
+  (s_WSTRB_sq[4] && ARESETn),
+  (s_WSTRB_sq[3]),
+  (s_WSTRB_sq[2]),
+  (s_WSTRB_sq[1] & !(s_WSTRB_sqaa))
+  };
+
+assign s_WSTRB_sqaa = &WSTRB_stage_2_eq;
+
+wire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRB_expand;
+wire  [(L_NUM_WSTRB_BYTES*8)-1:0]      WSTRBsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the WSTRB up to the nearest byte
+  for (WSTRB_bit = 0; WSTRB_bit < (L_NUM_WSTRB_BYTES * 8); WSTRB_bit = WSTRB_bit + 1) begin : WSTRB_BIT_LOOP
+    if (WSTRB_bit < (DATA_WIDTH/8)) begin : VAL
+      assign WSTRB_expand[WSTRB_bit] = WSTRB[WSTRB_bit];
+      assign WSTRBsqa_expand[WSTRB_bit] = WSTRB_q[WSTRB_bit];
+    end else begin
+      assign WSTRB_expand[WSTRB_bit] = 1'b0;
+      assign WSTRBsqa_expand[WSTRB_bit] = 1'b0;
+    end
+  end
+
+integer WSTRB_bc;
+integer WSTRB_stage_1;
+integer WSTRB_stage_2;
+
+always @(posedge ACLK) begin
+  WSTRB_q<=WSTRB;
+
+  for (WSTRB_bc = 0; WSTRB_bc < L_NUM_WSTRB_EQ_LANES*8; WSTRB_bc = WSTRB_bc + 1) begin : WSTRB_BC_LOOP
+    if (WSTRB_bc < L_NUM_WSTRB_BYTES) begin
+      WSTRB_eq[WSTRB_bc] <= WSTRB_expand[WSTRB_bc*8 +:8] == WSTRBsqa_expand[WSTRB_bc*8 +: 8];
+    end else begin
+      WSTRB_eq[WSTRB_bc] <= 1'b1;
+    end
+  end
+
+  for (WSTRB_stage_1 = 0; WSTRB_stage_1 < L_NUM_WSTRB_AND1_LANES * 8;WSTRB_stage_1 = WSTRB_stage_1 + 1) begin : WSTRB_S1
+    if (WSTRB_stage_1 < L_NUM_WSTRB_EQ_LANES) begin
+      WSTRB_stage_1_eq[WSTRB_stage_1] <= &WSTRB_eq[WSTRB_stage_1*8 +:8];
+    end else begin
+      WSTRB_stage_1_eq[WSTRB_stage_1] <= 1'b1;
+    end
+  end
+
+  for (WSTRB_stage_2 = 0; WSTRB_stage_2 < L_NUM_WSTRB_AND2_LANES * 8;WSTRB_stage_2 = WSTRB_stage_2 + 1) begin : WSTRB_S2
+    if (WSTRB_stage_2 < L_NUM_WSTRB_AND1_LANES) begin
+      WSTRB_stage_2_eq[WSTRB_stage_2] <= &WSTRB_stage_1_eq[WSTRB_stage_2*8 +:8];
+    end else begin
+      WSTRB_stage_2_eq[WSTRB_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_28 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> WVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s44sq<=3'h4; else
+    s44sq<=s44s;
+  assign s44s={1'b1,
+    ((ARESETn & WVALID) & (! WREADY)),
+    (s44sq[1] && (ARESETn && !(WVALID)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_28<=0; else
+    ASR_28 <= (s44s[0]);
+
+  //---------------
+  //ASR_31 : assert property ( @(posedge ACLK) ( ARESETn |-> ~ BrespExokError ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_31<=0; else
+    ASR_31 <= ((ARESETn && BrespExokError));
+
+  //---------------
+  //ASR_32 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! BVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s46sq<=3'h4; else
+    s46sq<=s46s;
+  assign s46s={1'b1,
+    !(ARESETn),
+    (s46sq[1] && (ARESETn && BVALID))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_32<=0; else
+    ASR_32 <= (s46s[0]);
+
+  //---------------
+  //ASR_34 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s47<=BID;
+  assign s48 = s47 == BID;
+  always @(posedge ACLK) if (`AKRPS reset) s49sq<=3'h4; else
+    s49sq<=s49s;
+  assign s49s={1'b1,
+    ((ARESETn & BVALID) & (! BREADY)),
+    (s49sq[1] && (ARESETn && !(s48)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_34<=0; else
+    ASR_34 <= (s49s[0]);
+
+  //---------------
+  //ASR_35 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BRESP) ) );
+  //---------------
+  always @(posedge ACLK)
+    s50<=BRESP;
+  assign s51 = s50 == BRESP;
+  always @(posedge ACLK) if (`AKRPS reset) s52sq<=3'h4; else
+    s52sq<=s52s;
+  assign s52s={1'b1,
+    ((ARESETn & BVALID) & (! BREADY)),
+    (s52sq[1] && (ARESETn && !(s51)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_35<=0; else
+    ASR_35 <= (s52s[0]);
+
+  //---------------
+  //ASR_36 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> BVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s53sq<=3'h4; else
+    s53sq<=s53s;
+  assign s53s={1'b1,
+    ((ARESETn & BVALID) & (! BREADY)),
+    (s53sq[1] && (ARESETn && !(BVALID)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_36<=0; else
+    ASR_36 <= (s53s[0]);
+
+  //---------------
+  //ASR_38 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b1 ) |-> ( ArAddrIncr[ADDR_MAX:12] == ARADDR[ADDR_MAX:12] ) ) );
+  //---------------
+  reg [ADDR_MAX-12:0] ArAddrIncr_q1;
+  reg [ADDR_MAX-12:0] ARADDR_q1;
+  reg                 asr_38_ctrl;
+  
+  always @(posedge ACLK) begin
+    ArAddrIncr_q1 <= ArAddrIncr[ADDR_MAX:12];
+    ARADDR_q1     <= ARADDR[ADDR_MAX:12];
+    asr_38_ctrl   <= (ARVALID & ( (ARBURST == 2'b1) ));
+  end
+  
+  always @(posedge ACLK) if (`AKRPS reset) ASR_38<=0; else
+    ASR_38 <= asr_38_ctrl && !(ArAddrIncr_q1 == ARADDR_q1);
+
+  //---------------
+  //ASR_39 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ( ARADDR[6:0] & AlignMaskR ) == ARADDR[6:0] ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_39<=0; else
+    ASR_39 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !((( (ARADDR[6:0] & AlignMaskR) ) == ARADDR[6:0]))));
+
+  //---------------
+  //ASR_40 : assert property ( @(posedge ACLK) ( ARVALID |-> ( ARBURST != 2'b11 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_40<=0; else
+    ASR_40 <= ((ARVALID && !((ARBURST != 2'b11))));
+
+  //---------------
+  //ASR_41 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARLOCK != 1'b1 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_41<=0; else
+    ASR_41 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARLOCK != 1'b1))));
+
+  //---------------
+  //ASR_42 : assert property ( @(posedge ACLK) ( ARVALID & ~ ARCACHE[1] |-> ( ARCACHE[3:2] == 2'b0 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_42<=0; else
+    ASR_42 <= (((ARVALID & (~ ARCACHE[1])) && !((ARCACHE[3:2] == 2'b0))));
+
+  //---------------
+  //ASR_43 : assert property ( @(posedge ACLK) ( ARVALID & ARLEN > 8'b1111 |-> ( ARBURST != 2'b0 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_43<=0; else
+    ASR_43 <= (((ARVALID & (ARLEN > 8'b1111)) && !((ARBURST != 2'b0))));
+
+  //---------------
+  //ASR_44 : assert property ( @(posedge ACLK) ( ARVALID & ( ARBURST == 2'b10 ) |-> ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_44<=0; else
+    ASR_44 <= (((ARVALID & ( (ARBURST == 2'b10) )) && !(((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)))));
+
+  //---------------
+  //ASR_46 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! ARVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s55sq<=3'h4; else
+    s55sq<=s55s;
+  assign s55s={1'b1,
+    !(ARESETn),
+    (s55sq[1] && (ARESETn && ARVALID))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_46<=0; else
+    ASR_46 <= (s55s[0]);
+
+  //---------------
+  //ASR_47 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARADDR) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s56<=ARADDR;
+//  assign s57 = s56 == ARADDR;
+//  always @(posedge ACLK) if (`AKRPS reset) s58sq<=3'h4; else
+//    s58sq<=s58s;
+//  assign s58s={1'b1,
+//    ((ARESETn & ARVALID) & (! ARREADY)),
+//    (s58sq[1] && (ARESETn && !(s57)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_47<=0; else
+//    ASR_47 <= (s58s[0]);
+localparam integer L_NUM_ARADDR_BYTES       = ((ADDR_WIDTH + 7) / 8);
+localparam integer L_NUM_ARADDR_BYTE_LANES  = ((L_NUM_ARADDR_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_ARADDR_EQ_LANES    = (L_NUM_ARADDR_BYTE_LANES / 8);
+localparam integer L_NUM_ARADDR_AND1_LANES  = (L_NUM_ARADDR_EQ_LANES + 7) / 8;
+localparam integer L_NUM_ARADDR_AND2_LANES  = (L_NUM_ARADDR_AND1_LANES + 7) / 8;
+
+reg   [ADDR_WIDTH - 1:0] ARADDR_q;
+reg   [4:0]               s_ARADDR_sq;
+wire  [4:0]               s_ARADDR_s;
+wire                      s_ARADDR_sqaa;
+
+reg [(8*L_NUM_ARADDR_EQ_LANES)-1:0]    ARADDR_eq;
+reg [(8*L_NUM_ARADDR_AND1_LANES)-1:0]  ARADDR_stage_1_eq;
+reg [(8*L_NUM_ARADDR_AND2_LANES)-1:0]  ARADDR_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_ARADDR_sq<=5'h00; 
+    ASR_47 <=0;
+  end else begin
+    s_ARADDR_sq<=s_ARADDR_s;
+    ASR_47 <= (s_ARADDR_s[0]);
+  end
+end
+
+assign s_ARADDR_s={
+  (((ARESETn & ARVALID) & (! ARREADY))),
+  (s_ARADDR_sq[4] && ARESETn),
+  (s_ARADDR_sq[3]),
+  (s_ARADDR_sq[2]),
+  (s_ARADDR_sq[1] & !(s_ARADDR_sqaa))
+  };
+
+assign s_ARADDR_sqaa = &ARADDR_stage_2_eq;
+
+wire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDR_expand;
+wire  [(L_NUM_ARADDR_BYTES*8)-1:0]      ARADDRsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the ARADDR up to the nearest byte
+  for (ARADDR_bit = 0; ARADDR_bit < (L_NUM_ARADDR_BYTES * 8); ARADDR_bit = ARADDR_bit + 1) begin : ARADDR_BIT_LOOP
+    if (ARADDR_bit < ADDR_WIDTH) begin : VAL
+      assign ARADDR_expand[ARADDR_bit] = ARADDR[ARADDR_bit];
+      assign ARADDRsqa_expand[ARADDR_bit] = ARADDR_q[ARADDR_bit];
+    end else begin
+      assign ARADDR_expand[ARADDR_bit] = 1'b0;
+      assign ARADDRsqa_expand[ARADDR_bit] = 1'b0;
+    end
+  end
+
+integer ARADDR_bc;
+integer ARADDR_stage_1;
+integer ARADDR_stage_2;
+
+always @(posedge ACLK) begin
+  ARADDR_q<=ARADDR;
+
+  for (ARADDR_bc = 0; ARADDR_bc < L_NUM_ARADDR_EQ_LANES*8; ARADDR_bc = ARADDR_bc + 1) begin : ARADDR_BC_LOOP
+    if (ARADDR_bc < L_NUM_ARADDR_BYTES) begin
+      ARADDR_eq[ARADDR_bc] <= ARADDR_expand[ARADDR_bc*8 +:8] == ARADDRsqa_expand[ARADDR_bc*8 +: 8];
+    end else begin
+      ARADDR_eq[ARADDR_bc] <= 1'b1;
+    end
+  end
+
+  for (ARADDR_stage_1 = 0; ARADDR_stage_1 < L_NUM_ARADDR_AND1_LANES * 8;ARADDR_stage_1 = ARADDR_stage_1 + 1) begin : ARADDR_S1
+    if (ARADDR_stage_1 < L_NUM_ARADDR_EQ_LANES) begin
+      ARADDR_stage_1_eq[ARADDR_stage_1] <= &ARADDR_eq[ARADDR_stage_1*8 +:8];
+    end else begin
+      ARADDR_stage_1_eq[ARADDR_stage_1] <= 1'b1;
+    end
+  end
+
+  for (ARADDR_stage_2 = 0; ARADDR_stage_2 < L_NUM_ARADDR_AND2_LANES * 8;ARADDR_stage_2 = ARADDR_stage_2 + 1) begin : ARADDR_S2
+    if (ARADDR_stage_2 < L_NUM_ARADDR_AND1_LANES) begin
+      ARADDR_stage_2_eq[ARADDR_stage_2] <= &ARADDR_stage_1_eq[ARADDR_stage_2*8 +:8];
+    end else begin
+      ARADDR_stage_2_eq[ARADDR_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_48 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARBURST) ) );
+  //---------------
+  always @(posedge ACLK)
+    s59<=ARBURST;
+  assign s60 = s59 == ARBURST;
+  always @(posedge ACLK) if (`AKRPS reset) s61sq<=3'h4; else
+    s61sq<=s61s;
+  assign s61s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s61sq[1] && (ARESETn && !(s60)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_48<=0; else
+    ASR_48 <= (s61s[0]);
+
+  //---------------
+  //ASR_49 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARCACHE) ) );
+  //---------------
+  always @(posedge ACLK)
+    s62<=ARCACHE;
+  assign s63 = s62 == ARCACHE;
+  always @(posedge ACLK) if (`AKRPS reset) s64sq<=3'h4; else
+    s64sq<=s64s;
+  assign s64s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s64sq[1] && (ARESETn && !(s63)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_49<=0; else
+    ASR_49 <= (s64s[0]);
+
+  //---------------
+  //ASR_50 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s65<=ARID;
+  assign s66 = s65 == ARID;
+  always @(posedge ACLK) if (`AKRPS reset) s67sq<=3'h4; else
+    s67sq<=s67s;
+  assign s67s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s67sq[1] && (ARESETn && !(s66)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_50<=0; else
+    ASR_50 <= (s67s[0]);
+
+  //---------------
+  //ASR_51 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLEN) ) );
+  //---------------
+  always @(posedge ACLK)
+    s68<=ARLEN;
+  assign s69 = s68 == ARLEN;
+  always @(posedge ACLK) if (`AKRPS reset) s70sq<=3'h4; else
+    s70sq<=s70s;
+  assign s70s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s70sq[1] && (ARESETn && !(s69)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_51<=0; else
+    ASR_51 <= (s70s[0]);
+
+  //---------------
+  //ASR_52 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARLOCK) ) );
+  //---------------
+  always @(posedge ACLK)
+    s71<=ARLOCK;
+  assign s72 = s71 == ARLOCK;
+  always @(posedge ACLK) if (`AKRPS reset) s73sq<=3'h4; else
+    s73sq<=s73s;
+  assign s73s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s73sq[1] && (ARESETn && !(s72)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_52<=0; else
+    ASR_52 <= (s73s[0]);
+
+  //---------------
+  //ASR_53 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARPROT) ) );
+  //---------------
+  always @(posedge ACLK)
+    s74<=ARPROT;
+  assign s75 = s74 == ARPROT;
+  always @(posedge ACLK) if (`AKRPS reset) s76sq<=3'h4; else
+    s76sq<=s76s;
+  assign s76s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s76sq[1] && (ARESETn && !(s75)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_53<=0; else
+    ASR_53 <= (s76s[0]);
+
+  //---------------
+  //ASR_54 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARSIZE) ) );
+  //---------------
+  always @(posedge ACLK)
+    s77<=ARSIZE;
+  assign s78 = s77 == ARSIZE;
+  always @(posedge ACLK) if (`AKRPS reset) s79sq<=3'h4; else
+    s79sq<=s79s;
+  assign s79s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s79sq[1] && (ARESETn && !(s78)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_54<=0; else
+    ASR_54 <= (s79s[0]);
+
+  //---------------
+  //ASR_55 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARQOS) ) );
+  //---------------
+  always @(posedge ACLK)
+    s80<=ARQOS;
+  assign s81 = s80 == ARQOS;
+  always @(posedge ACLK) if (`AKRPS reset) s82sq<=3'h4; else
+    s82sq<=s82s;
+  assign s82s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s82sq[1] && (ARESETn && !(s81)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_55<=0; else
+    ASR_55 <= (s82s[0]);
+
+  //---------------
+  //ASR_56 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARREGION) ) );
+  //---------------
+  always @(posedge ACLK)
+    s83<=ARREGION;
+  assign s84 = s83 == ARREGION;
+  always @(posedge ACLK) if (`AKRPS reset) s85sq<=3'h4; else
+    s85sq<=s85s;
+  assign s85s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s85sq[1] && (ARESETn && !(s84)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_56<=0; else
+    ASR_56 <= (s85s[0]);
+
+  //---------------
+  //ASR_57 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> ARVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s86sq<=3'h4; else
+    s86sq<=s86s;
+  assign s86s={1'b1,
+    ((ARESETn & ARVALID) & (! ARREADY)),
+    (s86sq[1] && (ARESETn && !(ARVALID)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_57<=0; else
+    ASR_57 <= (s86s[0]);
+
+  //---------------
+  //ASR_61 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & RREADY & ( RRESP == 2'b1 ) |-> ( ArExclPending ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_61<=0; else
+    ASR_61 <= (((((ARESETn & RVALID) & RREADY) & ( (RRESP == 2'b1) )) && !(ArExclPending)));
+
+  //---------------
+  //ASR_62 : assert property ( @(posedge ACLK) ( ! ( ARESETn ) ##1 ARESETn |-> ! RVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s88sq<=3'h4; else
+    s88sq<=s88s;
+  assign s88s={1'b1,
+    !(ARESETn),
+    (s88sq[1] && (ARESETn && RVALID))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_62<=0; else
+    ASR_62 <= (s88s[0]);
+
+  //---------------
+  //ASR_63 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RDATA) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s89<=RDATA;
+//  assign s90 = s89 == RDATA;
+//  always @(posedge ACLK) if (`AKRPS reset) s91sq<=3'h4; else
+//    s91sq<=s91s;
+//  assign s91s={1'b1,
+//    ((ARESETn & RVALID) & (! RREADY)),
+//    (s91sq[1] && (ARESETn && !(s90)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_63<=0; else
+//    ASR_63 <= (s91s[0]);
+localparam integer L_NUM_RDATA_BYTES       = ((DATA_WIDTH + 7) / 8);
+localparam integer L_NUM_RDATA_BYTE_LANES  = ((L_NUM_RDATA_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_RDATA_EQ_LANES    = (L_NUM_RDATA_BYTE_LANES / 8);
+localparam integer L_NUM_RDATA_AND1_LANES  = (L_NUM_RDATA_EQ_LANES + 7) / 8;
+localparam integer L_NUM_RDATA_AND2_LANES  = (L_NUM_RDATA_AND1_LANES + 7) / 8;
+
+reg   [DATA_WIDTH - 1:0]  RDATA_q;
+reg   [4:0]               s_RDATA_sq;
+wire  [4:0]               s_RDATA_s;
+wire                      s_RDATA_sqaa;
+
+reg [(8*L_NUM_RDATA_EQ_LANES)-1:0]    RDATA_eq;
+reg [(8*L_NUM_RDATA_AND1_LANES)-1:0]  RDATA_stage_1_eq;
+reg [(8*L_NUM_RDATA_AND2_LANES)-1:0]  RDATA_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_RDATA_sq<=5'h00; 
+    ASR_63 <=0;
+  end else begin
+    s_RDATA_sq<=s_RDATA_s;
+    ASR_63 <= (s_RDATA_s[0]);
+  end
+end
+
+assign s_RDATA_s={
+  (((ARESETn & RVALID) & (! RREADY))),
+  (s_RDATA_sq[4] && ARESETn),
+  (s_RDATA_sq[3]),
+  (s_RDATA_sq[2]),
+  (s_RDATA_sq[1] & !(s_RDATA_sqaa))
+  };
+
+assign s_RDATA_sqaa = &RDATA_stage_2_eq;
+
+integer RDATA_bc;
+integer RDATA_stage_1;
+integer RDATA_stage_2;
+
+always @(posedge ACLK) begin
+  RDATA_q<=RDATA;
+
+  for (RDATA_bc = 0; RDATA_bc < L_NUM_RDATA_EQ_LANES*8; RDATA_bc = RDATA_bc + 1) begin : RDATA_BC_LOOP
+    if (RDATA_bc < L_NUM_RDATA_BYTES) begin
+      RDATA_eq[RDATA_bc] <= RDATA_q[RDATA_bc*8 +:8] == RDATA[RDATA_bc*8 +: 8];
+    end else begin
+      RDATA_eq[RDATA_bc] <= 1'b1;
+    end
+  end
+
+  for (RDATA_stage_1 = 0; RDATA_stage_1 < L_NUM_RDATA_AND1_LANES * 8;RDATA_stage_1 = RDATA_stage_1 + 1) begin : RDATA_S1
+    if (RDATA_stage_1 < L_NUM_RDATA_EQ_LANES) begin
+      RDATA_stage_1_eq[RDATA_stage_1] <= &RDATA_eq[RDATA_stage_1*8 +:8];
+    end else begin
+      RDATA_stage_1_eq[RDATA_stage_1] <= 1'b1;
+    end
+  end
+
+  for (RDATA_stage_2 = 0; RDATA_stage_2 < L_NUM_RDATA_AND2_LANES * 8;RDATA_stage_2 = RDATA_stage_2 + 1) begin : RDATA_S2
+    if (RDATA_stage_2 < L_NUM_RDATA_AND1_LANES) begin
+      RDATA_stage_2_eq[RDATA_stage_2] <= &RDATA_stage_1_eq[RDATA_stage_2*8 +:8];
+    end else begin
+      RDATA_stage_2_eq[RDATA_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_64 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s92<=RID;
+  assign s93 = s92 == RID;
+  always @(posedge ACLK) if (`AKRPS reset) s94sq<=3'h4; else
+    s94sq<=s94s;
+  assign s94s={1'b1,
+    ((ARESETn & RVALID) & (! RREADY)),
+    (s94sq[1] && (ARESETn && !(s93)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_64<=0; else
+    ASR_64 <= (s94s[0]);
+
+  //---------------
+  //ASR_65 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RLAST) ) );
+  //---------------
+  always @(posedge ACLK)
+    s95<=RLAST;
+  assign s96 = s95 == RLAST;
+  always @(posedge ACLK) if (`AKRPS reset) s97sq<=3'h4; else
+    s97sq<=s97s;
+  assign s97s={1'b1,
+    ((ARESETn & RVALID) & (! RREADY)),
+    (s97sq[1] && (ARESETn && !(s96)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_65<=0; else
+    ASR_65 <= (s97s[0]);
+
+  //---------------
+  //ASR_66 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RRESP) ) );
+  //---------------
+  always @(posedge ACLK)
+    s98<=RRESP;
+  assign s99 = s98 == RRESP;
+  always @(posedge ACLK) if (`AKRPS reset) s100sq<=3'h4; else
+    s100sq<=s100s;
+  assign s100s={1'b1,
+    ((ARESETn & RVALID) & (! RREADY)),
+    (s100sq[1] && (ARESETn && !(s99)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_66<=0; else
+    ASR_66 <= (s100s[0]);
+
+  //---------------
+  //ASR_67 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> RVALID ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) s101sq<=3'h4; else
+    s101sq<=s101s;
+  assign s101s={1'b1,
+    ((ARESETn & RVALID) & (! RREADY)),
+    (s101sq[1] && (ARESETn && !(RVALID)))};
+  always @(posedge ACLK) if (`AKRPS reset) ASR_67<=0; else
+    ASR_67 <= (s101s[0]);
+
+  //---------------
+  //ASR_69 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b0 || ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ( ARADDR[10:0] & ExclMask ) == ARADDR[10:0] ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_69<=0; else
+    ASR_69 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( (((((ARLEN == 8'b0) || (ARLEN == 8'b1)) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((( (ARADDR[10:0] & ExclMask) ) == ARADDR[10:0]))));
+
+  //---------------
+  //ASR_70 : assert property ( @(posedge ACLK) ( ARVALID & ( ARLOCK == 1'b1 ) |-> ( ( ARLEN == 8'b0 ) || ( ARLEN == 8'b1 ) || ( ARLEN == 8'b11 ) || ( ARLEN == 8'b111 ) || ( ARLEN == 8'b1111 ) ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_70<=0; else
+    ASR_70 <= (((ARVALID & ( (ARLOCK == 1'b1) )) && !(((((( (ARLEN == 8'b0) ) || ( (ARLEN == 8'b1) )) || ( (ARLEN == 8'b11) )) || ( (ARLEN == 8'b111) )) || ( (ARLEN == 8'b1111) )))));
+
+  //---------------
+  //ASR_71 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) & ExclReadAddr[ExclAwId] & ExclAwMatch |-> ( ( ExclAddr[ExclAwId] == AWADDR ) & ( ExclSize[ExclAwId] == AWSIZE ) & ( ExclLen[ExclAwId] == AWLEN ) & ( ExclBurst[ExclAwId] == AWBURST ) & ( ExclCache[ExclAwId] == AWCACHE ) & ( ExclProt[ExclAwId] == AWPROT ) & ( ExclRegion[ExclAwId] == AWREGION ) ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_71<=0; else
+    ASR_71 <= (((((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) & ExclReadAddr) & ExclAwMatch) && !(((((((( (ExclAddr == AWADDR) ) & ( (ExclSize == AWSIZE) )) & ( (ExclLen == AWLEN) )) & ( (ExclBurst == AWBURST) )) & ( (ExclCache == AWCACHE) )) & ( (ExclProt == AWPROT) )) & ( (ExclRegion == AWREGION) ))))); // ###MBAC###
+
+  //---------------
+  //ASR_72 : assert property ( @(posedge ACLK) ( ( ARVALID & ( ARLOCK == 1'b1 ) & ( ARLEN == 8'b1 || ARLEN == 8'b11 || ARLEN == 8'b111 || ARLEN == 8'b1111 ) ) |-> ( ArLenInBytes <= 128 ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_72<=0; else
+    ASR_72 <= ((((ARVALID & ( (ARLOCK == 1'b1) )) & ( ((((ARLEN == 8'b1) || (ARLEN == 8'b11)) || (ARLEN == 8'b111)) || (ARLEN == 8'b1111)) )) && !((ArLenInBytes <= 128))));
+
+  //---------------
+  //ASR_73 : assert property ( @(posedge ACLK) ( i_RecommendOn & AWVALID & AWREADY & ( AWLOCK == 1'b1 ) |-> ( ExclAwMatch && ExclReadAddr[ExclAwId] && ExclReadData[ExclAwId] ) ) );
+  //---------------
+  always @(posedge ACLK) if (`AKRPS reset) ASR_73<=0; else
+    ASR_73 <= (((((i_RecommendOn & AWVALID) & AWREADY) & ( (AWLOCK == 1'b1) )) && !(((ExclAwMatch && ExclReadAddr) && ExclReadData)))); // ###MBAC###
+
+  //---------------
+  //ASR_74 : assert property ( @(posedge ACLK) ( ARESETn & AWVALID & ! AWREADY ##1 ARESETn |-> $stable(AWUSER) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s103<=AWUSER;
+//  assign s104 = s103 == AWUSER;
+//  always @(posedge ACLK) if (`AKRPS reset) s105sq<=3'h4; else
+//    s105sq<=s105s;
+//  assign s105s={1'b1,
+//    ((ARESETn & AWVALID) & (! AWREADY)),
+//    (s105sq[1] && (ARESETn && !(s104)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_74<=0; else
+//    ASR_74 <= (s105s[0]);
+localparam integer L_NUM_AWUSER_BYTES       = ((AWUSER_WIDTH + 7) / 8);
+localparam integer L_NUM_AWUSER_BYTE_LANES  = ((L_NUM_AWUSER_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_AWUSER_EQ_LANES    = (L_NUM_AWUSER_BYTE_LANES / 8);
+localparam integer L_NUM_AWUSER_AND1_LANES  = (L_NUM_AWUSER_EQ_LANES + 7) / 8;
+localparam integer L_NUM_AWUSER_AND2_LANES  = (L_NUM_AWUSER_AND1_LANES + 7) / 8;
+
+reg   [AWUSER_WIDTH - 1:0] AWUSER_q;
+reg   [4:0]               s_AWUSER_sq;
+wire  [4:0]               s_AWUSER_s;
+wire                      s_AWUSER_sqaa;
+
+reg [(8*L_NUM_AWUSER_EQ_LANES)-1:0]    AWUSER_eq;
+reg [(8*L_NUM_AWUSER_AND1_LANES)-1:0]  AWUSER_stage_1_eq;
+reg [(8*L_NUM_AWUSER_AND2_LANES)-1:0]  AWUSER_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_AWUSER_sq<=5'h00; 
+    ASR_74 <=0;
+  end else begin
+    s_AWUSER_sq<=s_AWUSER_s;
+    ASR_74 <= (s_AWUSER_s[0]);
+  end
+end
+
+assign s_AWUSER_s={
+  (((ARESETn & AWVALID) & (! AWREADY))),
+  (s_AWUSER_sq[4] && ARESETn),
+  (s_AWUSER_sq[3]),
+  (s_AWUSER_sq[2]),
+  (s_AWUSER_sq[1] & !(s_AWUSER_sqaa))
+  };
+
+assign s_AWUSER_sqaa = &AWUSER_stage_2_eq;
+
+wire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSER_expand;
+wire  [(L_NUM_AWUSER_BYTES*8)-1:0]      AWUSERsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the AWUSER up to the nearest byte
+  for (AWUSER_bit = 0; AWUSER_bit < (L_NUM_AWUSER_BYTES * 8); AWUSER_bit = AWUSER_bit + 1) begin : AWUSER_BIT_LOOP
+    if (AWUSER_bit < AWUSER_WIDTH) begin : VAL
+      assign AWUSER_expand[AWUSER_bit] = AWUSER[AWUSER_bit];
+      assign AWUSERsqa_expand[AWUSER_bit] = AWUSER_q[AWUSER_bit];
+    end else begin
+      assign AWUSER_expand[AWUSER_bit] = 1'b0;
+      assign AWUSERsqa_expand[AWUSER_bit] = 1'b0;
+    end
+  end
+
+integer AWUSER_bc;
+integer AWUSER_stage_1;
+integer AWUSER_stage_2;
+
+always @(posedge ACLK) begin
+  AWUSER_q<=AWUSER;
+
+  for (AWUSER_bc = 0; AWUSER_bc < L_NUM_AWUSER_EQ_LANES*8; AWUSER_bc = AWUSER_bc + 1) begin : AWUSER_BC_LOOP
+    if (AWUSER_bc < L_NUM_AWUSER_BYTES) begin
+      AWUSER_eq[AWUSER_bc] <= AWUSER_expand[AWUSER_bc*8 +:8] == AWUSERsqa_expand[AWUSER_bc*8 +: 8];
+    end else begin
+      AWUSER_eq[AWUSER_bc] <= 1'b1;
+    end
+  end
+
+  for (AWUSER_stage_1 = 0; AWUSER_stage_1 < L_NUM_AWUSER_AND1_LANES * 8;AWUSER_stage_1 = AWUSER_stage_1 + 1) begin : AWUSER_S1
+    if (AWUSER_stage_1 < L_NUM_AWUSER_EQ_LANES) begin
+      AWUSER_stage_1_eq[AWUSER_stage_1] <= &AWUSER_eq[AWUSER_stage_1*8 +:8];
+    end else begin
+      AWUSER_stage_1_eq[AWUSER_stage_1] <= 1'b1;
+    end
+  end
+
+  for (AWUSER_stage_2 = 0; AWUSER_stage_2 < L_NUM_AWUSER_AND2_LANES * 8;AWUSER_stage_2 = AWUSER_stage_2 + 1) begin : AWUSER_S2
+    if (AWUSER_stage_2 < L_NUM_AWUSER_AND1_LANES) begin
+      AWUSER_stage_2_eq[AWUSER_stage_2] <= &AWUSER_stage_1_eq[AWUSER_stage_2*8 +:8];
+    end else begin
+      AWUSER_stage_2_eq[AWUSER_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+
+  //---------------
+  //ASR_75 : assert property ( @(posedge ACLK) ( ARESETn & WVALID & ! WREADY ##1 ARESETn |-> $stable(WUSER) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s106<=WUSER;
+//  assign s107 = s106 == WUSER;
+//  always @(posedge ACLK) if (`AKRPS reset) s108sq<=3'h4; else
+//    s108sq<=s108s;
+//  assign s108s={1'b1,
+//    ((ARESETn & WVALID) & (! WREADY)),
+//    (s108sq[1] && (ARESETn && !(s107)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_75<=0; else
+//    ASR_75 <= (s108s[0]);
+localparam integer L_NUM_WUSER_BYTES       = ((WUSER_WIDTH + 7) / 8);
+localparam integer L_NUM_WUSER_BYTE_LANES  = ((L_NUM_WUSER_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_WUSER_EQ_LANES    = (L_NUM_WUSER_BYTE_LANES / 8);
+localparam integer L_NUM_WUSER_AND1_LANES  = (L_NUM_WUSER_EQ_LANES + 7) / 8;
+localparam integer L_NUM_WUSER_AND2_LANES  = (L_NUM_WUSER_AND1_LANES + 7) / 8;
+
+reg   [WUSER_WIDTH - 1:0] WUSER_q;
+reg   [4:0]               s_WUSER_sq;
+wire  [4:0]               s_WUSER_s;
+wire                      s_WUSER_sqaa;
+
+reg [(8*L_NUM_WUSER_EQ_LANES)-1:0]    WUSER_eq;
+reg [(8*L_NUM_WUSER_AND1_LANES)-1:0]  WUSER_stage_1_eq;
+reg [(8*L_NUM_WUSER_AND2_LANES)-1:0]  WUSER_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_WUSER_sq<=5'h00; 
+    ASR_75 <=0;
+  end else begin
+    s_WUSER_sq<=s_WUSER_s;
+    ASR_75 <= (s_WUSER_s[0]);
+  end
+end
+
+assign s_WUSER_s={
+  (((ARESETn & WVALID) & (! WREADY))),
+  (s_WUSER_sq[4] && ARESETn),
+  (s_WUSER_sq[3]),
+  (s_WUSER_sq[2]),
+  (s_WUSER_sq[1] & !(s_WUSER_sqaa))
+  };
+
+assign s_WUSER_sqaa = &WUSER_stage_2_eq;
+
+wire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSER_expand;
+wire  [(L_NUM_WUSER_BYTES*8)-1:0]      WUSERsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the WUSER up to the nearest byte
+  for (WUSER_bit = 0; WUSER_bit < (L_NUM_WUSER_BYTES * 8); WUSER_bit = WUSER_bit + 1) begin : WUSER_BIT_LOOP
+    if (WUSER_bit < WUSER_WIDTH) begin : VAL
+      assign WUSER_expand[WUSER_bit] = WUSER[WUSER_bit];
+      assign WUSERsqa_expand[WUSER_bit] = WUSER_q[WUSER_bit];
+    end else begin
+      assign WUSER_expand[WUSER_bit] = 1'b0;
+      assign WUSERsqa_expand[WUSER_bit] = 1'b0;
+    end
+  end
+
+integer WUSER_bc;
+integer WUSER_stage_1;
+integer WUSER_stage_2;
+
+always @(posedge ACLK) begin
+  WUSER_q<=WUSER;
+
+  for (WUSER_bc = 0; WUSER_bc < L_NUM_WUSER_EQ_LANES*8; WUSER_bc = WUSER_bc + 1) begin : WUSER_BC_LOOP
+    if (WUSER_bc < L_NUM_WUSER_BYTES) begin
+      WUSER_eq[WUSER_bc] <= WUSER_expand[WUSER_bc*8 +:8] == WUSERsqa_expand[WUSER_bc*8 +: 8];
+    end else begin
+      WUSER_eq[WUSER_bc] <= 1'b1;
+    end
+  end
+
+  for (WUSER_stage_1 = 0; WUSER_stage_1 < L_NUM_WUSER_AND1_LANES * 8;WUSER_stage_1 = WUSER_stage_1 + 1) begin : WUSER_S1
+    if (WUSER_stage_1 < L_NUM_WUSER_EQ_LANES) begin
+      WUSER_stage_1_eq[WUSER_stage_1] <= &WUSER_eq[WUSER_stage_1*8 +:8];
+    end else begin
+      WUSER_stage_1_eq[WUSER_stage_1] <= 1'b1;
+    end
+  end
+
+  for (WUSER_stage_2 = 0; WUSER_stage_2 < L_NUM_WUSER_AND2_LANES * 8;WUSER_stage_2 = WUSER_stage_2 + 1) begin : WUSER_S2
+    if (WUSER_stage_2 < L_NUM_WUSER_AND1_LANES) begin
+      WUSER_stage_2_eq[WUSER_stage_2] <= &WUSER_stage_1_eq[WUSER_stage_2*8 +:8];
+    end else begin
+      WUSER_stage_2_eq[WUSER_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+
+  //---------------
+  //ASR_76 : assert property ( @(posedge ACLK) ( ARESETn & BVALID & ! BREADY ##1 ARESETn |-> $stable(BUSER) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s109<=BUSER;
+//  assign s110 = s109 == BUSER;
+//  always @(posedge ACLK) if (`AKRPS reset) s111sq<=3'h4; else
+//    s111sq<=s111s;
+//  assign s111s={1'b1,
+//    ((ARESETn & BVALID) & (! BREADY)),
+//    (s111sq[1] && (ARESETn && !(s110)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_76<=0; else
+//    ASR_76 <= (s111s[0]);
+localparam integer L_NUM_BUSER_BYTES       = ((BUSER_WIDTH + 7) / 8);
+localparam integer L_NUM_BUSER_BYTE_LANES  = ((L_NUM_BUSER_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_BUSER_EQ_LANES    = (L_NUM_BUSER_BYTE_LANES / 8);
+localparam integer L_NUM_BUSER_AND1_LANES  = (L_NUM_BUSER_EQ_LANES + 7) / 8;
+localparam integer L_NUM_BUSER_AND2_LANES  = (L_NUM_BUSER_AND1_LANES + 7) / 8;
+
+reg   [BUSER_WIDTH - 1:0] BUSER_q;
+reg   [4:0]               s_BUSER_sq;
+wire  [4:0]               s_BUSER_s;
+wire                      s_BUSER_sqaa;
+
+reg [(8*L_NUM_BUSER_EQ_LANES)-1:0]    BUSER_eq;
+reg [(8*L_NUM_BUSER_AND1_LANES)-1:0]  BUSER_stage_1_eq;
+reg [(8*L_NUM_BUSER_AND2_LANES)-1:0]  BUSER_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_BUSER_sq<=5'h00; 
+    ASR_76 <=0;
+  end else begin
+    s_BUSER_sq<=s_BUSER_s;
+    ASR_76 <= (s_BUSER_s[0]);
+  end
+end
+
+assign s_BUSER_s={
+  (((ARESETn & BVALID) & (! BREADY))),
+  (s_BUSER_sq[4] && ARESETn),
+  (s_BUSER_sq[3]),
+  (s_BUSER_sq[2]),
+  (s_BUSER_sq[1] & !(s_BUSER_sqaa))
+  };
+
+assign s_BUSER_sqaa = &BUSER_stage_2_eq;
+
+wire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSER_expand;
+wire  [(L_NUM_BUSER_BYTES*8)-1:0]      BUSERsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the BUSER up to the nearest byte
+  for (BUSER_bit = 0; BUSER_bit < (L_NUM_BUSER_BYTES * 8); BUSER_bit = BUSER_bit + 1) begin : BUSER_BIT_LOOP
+    if (BUSER_bit < BUSER_WIDTH) begin : VAL
+      assign BUSER_expand[BUSER_bit] = BUSER[BUSER_bit];
+      assign BUSERsqa_expand[BUSER_bit] = BUSER_q[BUSER_bit];
+    end else begin
+      assign BUSER_expand[BUSER_bit] = 1'b0;
+      assign BUSERsqa_expand[BUSER_bit] = 1'b0;
+    end
+  end
+
+integer BUSER_bc;
+integer BUSER_stage_1;
+integer BUSER_stage_2;
+
+always @(posedge ACLK) begin
+  BUSER_q<=BUSER;
+
+  for (BUSER_bc = 0; BUSER_bc < L_NUM_BUSER_EQ_LANES*8; BUSER_bc = BUSER_bc + 1) begin : BUSER_BC_LOOP
+    if (BUSER_bc < L_NUM_BUSER_BYTES) begin
+      BUSER_eq[BUSER_bc] <= BUSER_expand[BUSER_bc*8 +:8] == BUSERsqa_expand[BUSER_bc*8 +: 8];
+    end else begin
+      BUSER_eq[BUSER_bc] <= 1'b1;
+    end
+  end
+
+  for (BUSER_stage_1 = 0; BUSER_stage_1 < L_NUM_BUSER_AND1_LANES * 8;BUSER_stage_1 = BUSER_stage_1 + 1) begin : BUSER_S1
+    if (BUSER_stage_1 < L_NUM_BUSER_EQ_LANES) begin
+      BUSER_stage_1_eq[BUSER_stage_1] <= &BUSER_eq[BUSER_stage_1*8 +:8];
+    end else begin
+      BUSER_stage_1_eq[BUSER_stage_1] <= 1'b1;
+    end
+  end
+
+  for (BUSER_stage_2 = 0; BUSER_stage_2 < L_NUM_BUSER_AND2_LANES * 8;BUSER_stage_2 = BUSER_stage_2 + 1) begin : BUSER_S2
+    if (BUSER_stage_2 < L_NUM_BUSER_AND1_LANES) begin
+      BUSER_stage_2_eq[BUSER_stage_2] <= &BUSER_stage_1_eq[BUSER_stage_2*8 +:8];
+    end else begin
+      BUSER_stage_2_eq[BUSER_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_77 : assert property ( @(posedge ACLK) ( ARESETn & ARVALID & ! ARREADY ##1 ARESETn |-> $stable(ARUSER) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s112<=ARUSER;
+//  assign s113 = s112 == ARUSER;
+//  always @(posedge ACLK) if (`AKRPS reset) s114sq<=3'h4; else
+//    s114sq<=s114s;
+//  assign s114s={1'b1,
+//    ((ARESETn & ARVALID) & (! ARREADY)),
+//    (s114sq[1] && (ARESETn && !(s113)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_77<=0; else
+//    ASR_77 <= (s114s[0]);
+localparam integer L_NUM_ARUSER_BYTES       = ((ARUSER_WIDTH + 7) / 8);
+localparam integer L_NUM_ARUSER_BYTE_LANES  = ((L_NUM_ARUSER_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_ARUSER_EQ_LANES    = (L_NUM_ARUSER_BYTE_LANES / 8);
+localparam integer L_NUM_ARUSER_AND1_LANES  = (L_NUM_ARUSER_EQ_LANES + 7) / 8;
+localparam integer L_NUM_ARUSER_AND2_LANES  = (L_NUM_ARUSER_AND1_LANES + 7) / 8;
+
+reg   [ARUSER_WIDTH - 1:0] ARUSER_q;
+reg   [4:0]               s_ARUSER_sq;
+wire  [4:0]               s_ARUSER_s;
+wire                      s_ARUSER_sqaa;
+
+reg [(8*L_NUM_ARUSER_EQ_LANES)-1:0]    ARUSER_eq;
+reg [(8*L_NUM_ARUSER_AND1_LANES)-1:0]  ARUSER_stage_1_eq;
+reg [(8*L_NUM_ARUSER_AND2_LANES)-1:0]  ARUSER_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_ARUSER_sq<=5'h00; 
+    ASR_77 <=0;
+  end else begin
+    s_ARUSER_sq<=s_ARUSER_s;
+    ASR_77 <= (s_ARUSER_s[0]);
+  end
+end
+
+assign s_ARUSER_s={
+  (((ARESETn & ARVALID) & (! ARREADY))),
+  (s_ARUSER_sq[4] && ARESETn),
+  (s_ARUSER_sq[3]),
+  (s_ARUSER_sq[2]),
+  (s_ARUSER_sq[1] & !(s_ARUSER_sqaa))
+  };
+
+assign s_ARUSER_sqaa = &ARUSER_stage_2_eq;
+
+wire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSER_expand;
+wire  [(L_NUM_ARUSER_BYTES*8)-1:0]      ARUSERsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the ARUSER up to the nearest byte
+  for (ARUSER_bit = 0; ARUSER_bit < (L_NUM_ARUSER_BYTES * 8); ARUSER_bit = ARUSER_bit + 1) begin : ARUSER_BIT_LOOP
+    if (ARUSER_bit < ARUSER_WIDTH) begin : VAL
+      assign ARUSER_expand[ARUSER_bit] = ARUSER[ARUSER_bit];
+      assign ARUSERsqa_expand[ARUSER_bit] = ARUSER_q[ARUSER_bit];
+    end else begin
+      assign ARUSER_expand[ARUSER_bit] = 1'b0;
+      assign ARUSERsqa_expand[ARUSER_bit] = 1'b0;
+    end
+  end
+
+integer ARUSER_bc;
+integer ARUSER_stage_1;
+integer ARUSER_stage_2;
+
+always @(posedge ACLK) begin
+  ARUSER_q<=ARUSER;
+
+  for (ARUSER_bc = 0; ARUSER_bc < L_NUM_ARUSER_EQ_LANES*8; ARUSER_bc = ARUSER_bc + 1) begin : ARUSER_BC_LOOP
+    if (ARUSER_bc < L_NUM_ARUSER_BYTES) begin
+      ARUSER_eq[ARUSER_bc] <= ARUSER_expand[ARUSER_bc*8 +:8] == ARUSERsqa_expand[ARUSER_bc*8 +: 8];
+    end else begin
+      ARUSER_eq[ARUSER_bc] <= 1'b1;
+    end
+  end
+
+  for (ARUSER_stage_1 = 0; ARUSER_stage_1 < L_NUM_ARUSER_AND1_LANES * 8;ARUSER_stage_1 = ARUSER_stage_1 + 1) begin : ARUSER_S1
+    if (ARUSER_stage_1 < L_NUM_ARUSER_EQ_LANES) begin
+      ARUSER_stage_1_eq[ARUSER_stage_1] <= &ARUSER_eq[ARUSER_stage_1*8 +:8];
+    end else begin
+      ARUSER_stage_1_eq[ARUSER_stage_1] <= 1'b1;
+    end
+  end
+
+  for (ARUSER_stage_2 = 0; ARUSER_stage_2 < L_NUM_ARUSER_AND2_LANES * 8;ARUSER_stage_2 = ARUSER_stage_2 + 1) begin : ARUSER_S2
+    if (ARUSER_stage_2 < L_NUM_ARUSER_AND1_LANES) begin
+      ARUSER_stage_2_eq[ARUSER_stage_2] <= &ARUSER_stage_1_eq[ARUSER_stage_2*8 +:8];
+    end else begin
+      ARUSER_stage_2_eq[ARUSER_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_78 : assert property ( @(posedge ACLK) ( ARESETn & RVALID & ! RREADY ##1 ARESETn |-> $stable(RUSER) ) );
+  //---------------
+//  always @(posedge ACLK)
+//    s115<=RUSER;
+//  assign s116 = s115 == RUSER;
+//  always @(posedge ACLK) if (`AKRPS reset) s117sq<=3'h4; else
+//    s117sq<=s117s;
+//  assign s117s={1'b1,
+//    ((ARESETn & RVALID) & (! RREADY)),
+//    (s117sq[1] && (ARESETn && !(s116)))};
+//  always @(posedge ACLK) if (`AKRPS reset) ASR_78<=0; else
+//    ASR_78 <= (s117s[0]);
+localparam integer L_NUM_RUSER_BYTES       = ((RUSER_WIDTH + 7) / 8);
+localparam integer L_NUM_RUSER_BYTE_LANES  = ((L_NUM_RUSER_BYTES + 7) / 8) * 8;
+localparam integer L_NUM_RUSER_EQ_LANES    = (L_NUM_RUSER_BYTE_LANES / 8);
+localparam integer L_NUM_RUSER_AND1_LANES  = (L_NUM_RUSER_EQ_LANES + 7) / 8;
+localparam integer L_NUM_RUSER_AND2_LANES  = (L_NUM_RUSER_AND1_LANES + 7) / 8;
+
+reg   [RUSER_WIDTH - 1:0] RUSER_q;
+reg   [4:0]               s_RUSER_sq;
+wire  [4:0]               s_RUSER_s;
+wire                      s_RUSER_sqaa;
+
+reg [(8*L_NUM_RUSER_EQ_LANES)-1:0]    RUSER_eq;
+reg [(8*L_NUM_RUSER_AND1_LANES)-1:0]  RUSER_stage_1_eq;
+reg [(8*L_NUM_RUSER_AND2_LANES)-1:0]  RUSER_stage_2_eq;
+
+always @(posedge ACLK) begin
+  if (`AKRPS reset) begin
+    s_RUSER_sq<=5'h00; 
+    ASR_78 <=0;
+  end else begin
+    s_RUSER_sq<=s_RUSER_s;
+    ASR_78 <= (s_RUSER_s[0]);
+  end
+end
+
+assign s_RUSER_s={
+  (((ARESETn & RVALID) & (! RREADY))),
+  (s_RUSER_sq[4] && ARESETn),
+  (s_RUSER_sq[3]),
+  (s_RUSER_sq[2]),
+  (s_RUSER_sq[1] & !(s_RUSER_sqaa))
+  };
+
+assign s_RUSER_sqaa = &RUSER_stage_2_eq;
+
+wire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSER_expand;
+wire  [(L_NUM_RUSER_BYTES*8)-1:0]      RUSERsqa_expand;
+  ///////////////////////////////////////////////////////////////////////////////////////////
+  //Expand the RUSER up to the nearest byte
+  for (RUSER_bit = 0; RUSER_bit < (L_NUM_RUSER_BYTES * 8); RUSER_bit = RUSER_bit + 1) begin : RUSER_BIT_LOOP
+    if (RUSER_bit < RUSER_WIDTH) begin : VAL
+      assign RUSER_expand[RUSER_bit] = RUSER[RUSER_bit];
+      assign RUSERsqa_expand[RUSER_bit] = RUSER_q[RUSER_bit];
+    end else begin
+      assign RUSER_expand[RUSER_bit] = 1'b0;
+      assign RUSERsqa_expand[RUSER_bit] = 1'b0;
+    end
+  end
+
+integer RUSER_bc;
+integer RUSER_stage_1;
+integer RUSER_stage_2;
+
+always @(posedge ACLK) begin
+  RUSER_q<=RUSER;
+
+  for (RUSER_bc = 0; RUSER_bc < L_NUM_RUSER_EQ_LANES*8; RUSER_bc = RUSER_bc + 1) begin : RUSER_BC_LOOP
+    if (RUSER_bc < L_NUM_RUSER_BYTES) begin
+      RUSER_eq[RUSER_bc] <= RUSER_expand[RUSER_bc*8 +:8] == RUSERsqa_expand[RUSER_bc*8 +: 8];
+    end else begin
+      RUSER_eq[RUSER_bc] <= 1'b1;
+    end
+  end
+
+  for (RUSER_stage_1 = 0; RUSER_stage_1 < L_NUM_RUSER_AND1_LANES * 8;RUSER_stage_1 = RUSER_stage_1 + 1) begin : RUSER_S1
+    if (RUSER_stage_1 < L_NUM_RUSER_EQ_LANES) begin
+      RUSER_stage_1_eq[RUSER_stage_1] <= &RUSER_eq[RUSER_stage_1*8 +:8];
+    end else begin
+      RUSER_stage_1_eq[RUSER_stage_1] <= 1'b1;
+    end
+  end
+
+  for (RUSER_stage_2 = 0; RUSER_stage_2 < L_NUM_RUSER_AND2_LANES * 8;RUSER_stage_2 = RUSER_stage_2 + 1) begin : RUSER_S2
+    if (RUSER_stage_2 < L_NUM_RUSER_AND1_LANES) begin
+      RUSER_stage_2_eq[RUSER_stage_2] <= &RUSER_stage_1_eq[RUSER_stage_2*8 +:8];
+    end else begin
+      RUSER_stage_2_eq[RUSER_stage_2] <= 1'b1;
+    end
+  end
+
+end
+
+  //---------------
+  //ASR_79 : assert property ( @(posedge ACLK) ( ARESETn & ( AWUSER_WIDTH == 0 ) |-> $stable(AWUSER) ) );
+  //---------------
+  always @(posedge ACLK)
+    s118<=AWUSER;
+  assign s119 = s118 == AWUSER;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_79<=0; else
+    ASR_79 <= (((ARESETn & ( (AWUSER_WIDTH == 0) )) && !(s119)));
+
+  //---------------
+  //ASR_80 : assert property ( @(posedge ACLK) ( ARESETn & ( WUSER_WIDTH == 0 ) |-> $stable(WUSER) ) );
+  //---------------
+  always @(posedge ACLK)
+    s120<=WUSER;
+  assign s121 = s120 == WUSER;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_80<=0; else
+    ASR_80 <= (((ARESETn & ( (WUSER_WIDTH == 0) )) && !(s121)));
+
+  //---------------
+  //ASR_81 : assert property ( @(posedge ACLK) ( ARESETn & ( BUSER_WIDTH == 0 ) |-> $stable(BUSER) ) );
+  //---------------
+  always @(posedge ACLK)
+    s122<=BUSER;
+  assign s123 = s122 == BUSER;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_81<=0; else
+    ASR_81 <= (((ARESETn & ( (BUSER_WIDTH == 0) )) && !(s123)));
+
+  //---------------
+  //ASR_82 : assert property ( @(posedge ACLK) ( ARESETn & ( ARUSER_WIDTH == 0 ) |-> $stable(ARUSER) ) );
+  //---------------
+  always @(posedge ACLK)
+    s124<=ARUSER;
+  assign s125 = s124 == ARUSER;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_82<=0; else
+    ASR_82 <= (((ARESETn & ( (ARUSER_WIDTH == 0) )) && !(s125)));
+
+  //---------------
+  //ASR_83 : assert property ( @(posedge ACLK) ( ARESETn & ( RUSER_WIDTH == 0 ) |-> $stable(RUSER) ) );
+  //---------------
+  always @(posedge ACLK)
+    s126<=RUSER;
+  assign s127 = s126 == RUSER;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_83<=0; else
+    ASR_83 <= (((ARESETn & ( (RUSER_WIDTH == 0) )) && !(s127)));
+
+  //---------------
+  //ASR_84 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(AWID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s128<=AWID;
+  assign s129 = s128 == AWID;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_84<=0; else
+    ASR_84 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s129)));
+
+  //---------------
+  //ASR_85 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(BID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s130<=BID;
+  assign s131 = s130 == BID;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_85<=0; else
+    ASR_85 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s131)));
+
+  //---------------
+  //ASR_86 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(ARID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s132<=ARID;
+  assign s133 = s132 == ARID;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_86<=0; else
+    ASR_86 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s133)));
+
+  //---------------
+  //ASR_87 : assert property ( @(posedge ACLK) ( ARESETn & ( ID_WIDTH == 0 ) |-> $stable(RID) ) );
+  //---------------
+  always @(posedge ACLK)
+    s134<=RID;
+  assign s135 = s134 == RID;
+  always @(posedge ACLK) if (`AKRPS reset) ASR_87<=0; else
+    ASR_87 <= (((ARESETn & ( (ID_WIDTH == 0) )) && !(s135)));
+
+end else begin : gen_ltwt_chks
+  
+  always @(posedge ACLK) begin
+    ASR_1  <= 1'b0;
+    ASR_2  <= 1'b0;
+    ASR_3  <= 1'b0;
+    ASR_4  <= 1'b0;
+    ASR_5  <= 1'b0;
+    ASR_6  <= 1'b0;
+    ASR_7  <= 1'b0;
+    ASR_9  <= 1'b0;
+    ASR_10 <= 1'b0;
+    ASR_11 <= 1'b0;
+    ASR_12 <= 1'b0;
+    ASR_13 <= 1'b0;
+    ASR_14 <= 1'b0;
+    ASR_15 <= 1'b0;
+    ASR_16 <= 1'b0;
+    ASR_17 <= 1'b0;
+    ASR_18 <= 1'b0;
+    ASR_19 <= 1'b0;
+    ASR_20 <= 1'b0;
+    ASR_23 <= 1'b0;
+    ASR_24 <= 1'b0;
+    ASR_25 <= 1'b0;
+    ASR_26 <= 1'b0;
+    ASR_27 <= 1'b0;
+    ASR_28 <= 1'b0;
+    ASR_31 <= 1'b0;
+    ASR_32 <= 1'b0;
+    ASR_34 <= 1'b0;
+    ASR_35 <= 1'b0;
+    ASR_36 <= 1'b0;
+    ASR_38 <= 1'b0;
+    ASR_39 <= 1'b0;
+    ASR_40 <= 1'b0;
+    ASR_41 <= 1'b0;
+    ASR_42 <= 1'b0;
+    ASR_43 <= 1'b0;
+    ASR_44 <= 1'b0;
+    ASR_46 <= 1'b0;
+    ASR_47 <= 1'b0;
+    ASR_48 <= 1'b0;
+    ASR_49 <= 1'b0;
+    ASR_50 <= 1'b0;
+    ASR_51 <= 1'b0;
+    ASR_52 <= 1'b0;
+    ASR_53 <= 1'b0;
+    ASR_54 <= 1'b0;
+    ASR_55 <= 1'b0;
+    ASR_56 <= 1'b0;
+    ASR_57 <= 1'b0;
+    ASR_61 <= 1'b0;
+    ASR_62 <= 1'b0;
+    ASR_63 <= 1'b0;
+    ASR_64 <= 1'b0;
+    ASR_65 <= 1'b0;
+    ASR_66 <= 1'b0;
+    ASR_67 <= 1'b0;
+    ASR_69 <= 1'b0;
+    ASR_70 <= 1'b0;
+    ASR_71 <= 1'b0;
+    ASR_72 <= 1'b0;
+    ASR_73 <= 1'b0;
+    ASR_74 <= 1'b0;
+    ASR_75 <= 1'b0;
+    ASR_76 <= 1'b0;
+    ASR_77 <= 1'b0;
+    ASR_78 <= 1'b0;
+    ASR_79 <= 1'b0;
+    ASR_80 <= 1'b0;
+    ASR_81 <= 1'b0;
+    ASR_82 <= 1'b0;
+    ASR_83 <= 1'b0;
+    ASR_84 <= 1'b0;
+    ASR_85 <= 1'b0;
+    ASR_86 <= 1'b0;
+    ASR_87 <= 1'b0;
+  end
+end
+endgenerate
+endmodule //Axi4PC_asr_inline
+
+
+// (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//*****************************************************************************
+// Notes            : The assertion ASR_23 is not implemented for WDATA before
+//                    AWADDR, since that would require storing all WSTRB in a
+//                    burst.
+//
+//                    The following assertions use FIFOs to store AW and W
+//                    signals, and can be disabled to improve frequency and
+//                    reduce area: ASR_22, ASR_23, ASR_30, ASR_31, ASR_33.
+//
+//                    The following assertions use FIFOs to store AW and W
+//                    signals, and can be disabled to improve frequency and
+//                    reduce area: ASR_59, ASR_60, ASR_61, ASR_63, ASR_73.
+//                    In particular, ASR_59 is timing critical.
+//*****************************************************************************
+
+`timescale 1ps/1ps
+`default_nettype none
+
+`define AXI4PC_TYPES
+// ALEN Encoding
+`define AXI4PC_ALEN_1            8'b00000000
+`define AXI4PC_ALEN_2            8'b00000001
+`define AXI4PC_ALEN_3            8'b00000010
+`define AXI4PC_ALEN_4            8'b00000011
+`define AXI4PC_ALEN_5            8'b00000100
+`define AXI4PC_ALEN_6            8'b00000101
+`define AXI4PC_ALEN_7            8'b00000110
+`define AXI4PC_ALEN_8            8'b00000111
+`define AXI4PC_ALEN_9            8'b00001000
+`define AXI4PC_ALEN_10           8'b00001001
+`define AXI4PC_ALEN_11           8'b00001010
+`define AXI4PC_ALEN_12           8'b00001011
+`define AXI4PC_ALEN_13           8'b00001100
+`define AXI4PC_ALEN_14           8'b00001101
+`define AXI4PC_ALEN_15           8'b00001110
+`define AXI4PC_ALEN_16           8'b00001111
+
+// ASIZE Encoding
+`define AXI4PC_ASIZE_8           3'b000
+`define AXI4PC_ASIZE_16          3'b001
+`define AXI4PC_ASIZE_32          3'b010
+`define AXI4PC_ASIZE_64          3'b011
+`define AXI4PC_ASIZE_128         3'b100
+`define AXI4PC_ASIZE_256         3'b101
+`define AXI4PC_ASIZE_512         3'b110
+`define AXI4PC_ASIZE_1024        3'b111
+
+// ABURST Encoding
+`define AXI4PC_ABURST_FIXED      2'b00
+`define AXI4PC_ABURST_INCR       2'b01 
+`define AXI4PC_ABURST_WRAP       2'b10 
+
+// ALOCK Encoding
+`define AXI4PC_ALOCK_EXCL        1'b1
+
+// RRESP / BRESP Encoding
+`define AXI4PC_RESP_OKAY         2'b00
+`define AXI4PC_RESP_EXOKAY       2'b01
+`define AXI4PC_RESP_SLVERR       2'b10
+`define AXI4PC_RESP_DECERR       2'b11
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_core #(
+  parameter integer C_ERROR_COUNT = 160,
+  parameter integer C_AXI_ID_WIDTH = 1,
+  parameter integer C_AXI_DATA_WIDTH = 32,
+  parameter integer C_AXI_ADDR_WIDTH = 32,
+  parameter integer C_AXI_AWUSER_WIDTH = 1,
+  parameter integer C_AXI_WUSER_WIDTH  = 1,
+  parameter integer C_AXI_BUSER_WIDTH  = 1,
+  parameter integer C_AXI_ARUSER_WIDTH = 1,
+  parameter integer C_AXI_RUSER_WIDTH  = 1,
+  parameter integer C_AXI_PROTOCOL = 0,
+  parameter integer MAXRBURSTS = 16,
+  parameter integer MAXWBURSTS = 16,
+  parameter integer EXMON_WIDTH = 4,
+  parameter integer RecommendOn = 1,
+  parameter integer RecommendWaitOn = 1,
+  parameter integer MAX_AW_WAITS = 16,
+  parameter integer MAX_AR_WAITS = 16,
+  parameter integer MAX_W_WAITS = 16,
+  parameter integer MAX_R_WAITS = 16,
+  parameter integer MAX_B_WAITS = 16,
+  parameter integer MAX_CONTINUOUS_RTRANSFERS_WAITS  = 16,
+  parameter integer MAX_CONTINUOUS_WTRANSFERS_WAITS = 16,
+  parameter integer MAX_WLAST_TO_AWVALID_WAITS  = 16,
+  parameter integer MAX_WRITE_TO_BVALID_WAITS  = 16,
+  parameter integer LIGHT_WEIGHT  = 0,
+  parameter integer C_HAS_WSTRB                    = 1,
+  parameter integer C_PC_SUPPORTS_NARROW_BURST     = 1,
+  parameter integer C_PC_HAS_SYSTEM_RESET = 0,
+  parameter integer C_PC_MAX_BURST_LENGTH          = 256,
+  parameter integer C_INDEX_WIDTH       = 1 ,
+  parameter integer C_NUM_RTHREADS       = 1 ,
+  parameter integer C_NUM_WTHREADS       = 1 
+) (
+   output wire [C_ERROR_COUNT-1:0]     pc_status,
+   input wire                          resetn,
+
+   input wire [C_INDEX_WIDTH-1:0]      arid_index,
+   input wire [C_INDEX_WIDTH-1:0]      rid_index,
+   input wire                          rid_mismatch,
+   input wire                          rcam_overflow,
+   input wire [C_INDEX_WIDTH-1:0]      awid_index,
+   input wire [C_INDEX_WIDTH-1:0]      bid_index,
+   input wire                          bid_mismatch,
+   input wire                          wcam_overflow,
+
+   input wire                          ACLK,
+   input wire                          ARST_N,
+   input wire [C_AXI_ID_WIDTH-1:0]     AWID,
+   input wire [C_AXI_ADDR_WIDTH-1:0]   AWADDR,
+   input wire [7:0]                    AWLEN,
+   input wire [2:0]                    AWSIZE,
+   input wire [1:0]                    AWBURST,
+   input wire [0:0]                    AWLOCK,
+   input wire [3:0]                    AWCACHE,
+   input wire [2:0]                    AWPROT,
+   input wire [3:0]                    AWQOS,
+   input wire [3:0]                    AWREGION,
+   input wire [C_AXI_AWUSER_WIDTH-1:0] AWUSER,
+   input wire                          AWVALID,
+   input wire                          AWREADY,
+   input wire                          WLAST,
+   input wire [C_AXI_DATA_WIDTH-1:0]   WDATA,
+   input wire [C_AXI_DATA_WIDTH/8-1:0] WSTRB,
+   input wire [C_AXI_WUSER_WIDTH-1:0]  WUSER,
+   input wire                          WVALID,
+   input wire                          WREADY,
+   input wire [C_AXI_ID_WIDTH-1:0]     BID,
+   input wire [1:0]                    BRESP,
+   input wire [C_AXI_BUSER_WIDTH-1:0]  BUSER,
+   input wire                          BVALID,
+   input wire                          BREADY,
+   input wire [C_AXI_ID_WIDTH-1:0]     ARID,
+   input wire [C_AXI_ADDR_WIDTH-1:0]   ARADDR,
+   input wire [7:0]                    ARLEN,
+   input wire [2:0]                    ARSIZE,
+   input wire [1:0]                    ARBURST,
+   input wire [0:0]                    ARLOCK,
+   input wire [3:0]                    ARCACHE,
+   input wire [2:0]                    ARPROT,
+   input wire [3:0]                    ARQOS,
+   input wire [3:0]                    ARREGION,
+   input wire [C_AXI_ARUSER_WIDTH-1:0] ARUSER,
+   input wire                          ARVALID,
+   input wire                          ARREADY,
+   input wire [C_AXI_ID_WIDTH-1:0]     RID,
+   input wire                          RLAST,
+   input wire [C_AXI_DATA_WIDTH-1:0]   RDATA,
+   input wire [1:0]                    RRESP,
+   input wire [C_AXI_RUSER_WIDTH-1:0]  RUSER,
+   input wire                          RVALID,
+   input wire                          RREADY
+  );
+
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Log2.
+  function integer log2;
+    input integer value;
+    integer a;
+    begin
+      a = value;
+      
+      for (log2=0; a>1; log2=log2+1) begin
+        a = a >> 1;
+      end
+    end
+  endfunction
+
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+
+  localparam WEXCL           = 0;
+  localparam WALENLO         = WEXCL + 1;
+  localparam WALENHI         = WALENLO + 7;
+
+  localparam WADDRLO         = 0;
+  localparam WADDRHI         = 6;
+  localparam WASIZELO        = WADDRHI + 1;
+  localparam WASIZEHI        = WASIZELO + 2;
+
+  localparam STRB_WIDTH      = C_AXI_DATA_WIDTH/8;
+  localparam LOG2_STRB_WIDTH = log2(STRB_WIDTH);
+  localparam ID_MAX          = C_AXI_ID_WIDTH? C_AXI_ID_WIDTH-1:0;
+    
+  localparam integer P_RTHREAD_SIZE = f_ceil_log2(C_NUM_RTHREADS);
+  localparam integer P_MAXRBURSTS_LOG = f_ceil_log2(MAXRBURSTS);
+  localparam integer P_WTHREAD_SIZE = f_ceil_log2(C_NUM_WTHREADS);
+  localparam integer P_MAXWBURSTS_LOG = f_ceil_log2(MAXWBURSTS);
+
+  localparam ADDRLO          = 0;
+  localparam ADDRHI          = 6;
+  localparam EXCL            = ADDRHI + 1;
+  localparam ALENLO          = EXCL + 1;
+  localparam ALENHI          = ALENLO + 7;
+  localparam ASIZELO         = ALENHI + 1;
+  localparam ASIZEHI         = ASIZELO + 2;
+  localparam BURSTLO         = ASIZEHI + 1;
+  localparam BURSTHI         = BURSTLO + 1;
+  localparam LP_ADDR_WIDTH   = (C_AXI_ADDR_WIDTH > 12) ? C_AXI_ADDR_WIDTH : 13;
+  localparam LP_EXMON_WIDTH  = (EXMON_WIDTH == 0) ? 1 : EXMON_WIDTH;
+
+  wire internal_AWLOCK;
+  wire internal_ARLOCK;
+  
+  assign internal_AWLOCK = (EXMON_WIDTH == 0) ? 1'b0 : AWLOCK;
+  assign internal_ARLOCK = (EXMON_WIDTH == 0) ? 1'b0 : ARLOCK;
+
+
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+
+  wire [91:1]                 Axi4PC_asr_inline_out;
+  wire [3:1]                  Axi4LitePC_asr_inline_out;
+  reg  [11:1]                 xilinx_inline_out;
+  wire [5:1]                  Axi4PC_aux;
+
+  reg  [6:0]                  AlignMaskR;
+  reg  [6:0]                  AlignMaskW;
+  reg  [14:0]                 ExclMask;
+  reg  [LP_ADDR_WIDTH-1:0]    ArAddrIncr;
+  reg  [LP_ADDR_WIDTH-1:0]    AwAddrIncr;
+  reg  [15:0]                 ArLenInBytes;
+  reg  [10:0]                 ArSizeInBits;
+  reg  [10:0]                 AwSizeInBits;
+  wire                        ArExclPending;
+  wire                        WriteDataNumError;
+  reg                         BStrbError;
+  wire [8:0]                  ArCountPending;
+  wire [8:0]                  ArLenPending;
+  reg                         RidMatch_index;
+  wire [31:0]                 RidMatch;
+  wire                        i_RecommendOn;
+  wire                        i_RecMaxWaitOn;
+  reg  [LP_EXMON_WIDTH-1:0]   ExclAwId;
+  wire                        ExclIdOverflow;
+  wire [LP_ADDR_WIDTH-1:0]    ExclAddr_indexed;
+  wire [2:0]                  ExclSize_indexed;
+  wire [7:0]                  ExclLen_indexed;
+  wire [1:0]                  ExclBurst_indexed;
+  wire [3:0]                  ExclCache_indexed;
+  wire [2:0]                  ExclProt_indexed;
+  wire [3:0]                  ExclRegion_indexed;
+  wire                        ExclReadAddr_indexed;
+  wire                        ExclReadData_indexed;
+
+  genvar                      i;                    // FIFO generation variable
+
+  // Write FIFO signals
+  reg  [8:0]                  WCountIn;
+  reg                         WDataNumError1;
+  reg                         BrespErrorLead;
+
+  // Read FIFO signals
+  reg  [BURSTHI:0]            RBurstCam_index;
+  wire [BURSTHI:0]            RBurstCam;
+//  reg  [BURSTHI:0]            RBurstCam1;
+  reg  [8:0]                  RCountCam_index;
+  wire [8:0]                  RCountCam;
+  reg  [8:0]                  RCountCam1;
+
+  reg  [8:0]                  RCount[0:C_NUM_RTHREADS-1];
+  reg  [0:C_NUM_RTHREADS-1]    RCountIncr;
+  reg  [BURSTHI:0]            Burst;
+  wire [(LIGHT_WEIGHT?7:BURSTHI):0] RDataOut[0:C_NUM_RTHREADS-1];
+  wire [C_NUM_RTHREADS-1:0]    REmpty;
+  wire [C_NUM_RTHREADS-1:0]    RFull;
+//  reg  [11:0]                 Bcount1;
+//  reg  [11:0]                 Bcount;
+//  reg  [16:0]                 Bshift1;
+//  reg  [15:0]                 Bshift;
+  wire [LP_ADDR_WIDTH-1:0] lp_awaddr = {LP_ADDR_WIDTH{1'b0}} | AWADDR[C_AXI_ADDR_WIDTH-1:0];
+  wire [LP_ADDR_WIDTH-1:0] lp_araddr = {LP_ADDR_WIDTH{1'b0}} | ARADDR[C_AXI_ADDR_WIDTH-1:0];
+
+  wire [P_WTHREAD_SIZE-1:0]       AWIDOut;
+  wire [7:0]                      AWLENOut;
+  wire [6:0]                      AWStrbAddrOut;
+  wire [2:0]                      AWStrbsizeOut;
+  wire                            AWEmpty;
+  wire                            AWFull;
+  wire [8:0]                      WCheckCountOut;
+  wire [C_AXI_DATA_WIDTH/8-1:0]   WCheckstrbOut;
+  wire                            WCheckEmpty;
+  wire                            WCheckFull;
+  reg  [C_AXI_DATA_WIDTH/8-1:0]   WSTRBq;
+  wire [C_AXI_DATA_WIDTH/8-1:0]   WstrbIn;
+  reg                             first_strb;
+  wire                            wcheckPop;
+  reg  [log2(MAXWBURSTS):0]       AWXferCount[C_NUM_WTHREADS-1:0];
+  reg                             AWXferCountOverflow;
+  wire                            AWPush;
+  wire                            WLastPush;
+  
+  wire [C_NUM_RTHREADS-1:0]       cmd_push;
+  wire [C_NUM_RTHREADS-1:0]       cmd_pop;
+
+  wire  reset_i;
+  wire  resetn_out;
+  wire  checker_main_resetn;
+  (* shreg_extract="no", iob="false", equivalent_register_removal = "no" *) reg [2:0] reset_resync;
+
+  assign reset_i = ~resetn;
+  assign resetn_out = (C_PC_HAS_SYSTEM_RESET == 1) ? reset_resync[2] : ARST_N;
+  
+  always @(posedge ACLK or posedge reset_i) begin
+    if (reset_i) begin
+      reset_resync <= 3'b000;
+    end else begin
+      reset_resync <= {reset_resync[1:0], 1'b1};
+    end
+  end
+
+  assign checker_main_resetn = resetn_out & ARST_N;
+ 
+  // Reset Pulse Width Assertion Check 
+
+  wire  sys_resetn;
+  assign sys_resetn = (C_PC_HAS_SYSTEM_RESET == 1) ? (resetn) : 1'b0;
+  reg aresetn_i_q;
+  wire rising_edge_rst;
+  wire falling_edge_rst;
+  wire reset_pulse_violation;
+  reg reset_pulse_violation_i;
+  reg [4:0] count_clk ;
+  reg en_chk_r;
+
+
+  always @(posedge ACLK) begin
+    if(sys_resetn == 1'b0) begin
+      count_clk <= 'h0;
+    end else if (en_chk_r && count_clk < 15 ) begin
+      count_clk <= count_clk + 1'h1;
+    end else if (en_chk_r == 0) begin 
+      count_clk <= 'h0;
+    end
+  end
+
+  always @(posedge ACLK) begin
+    if(sys_resetn == 1'b0) begin
+      aresetn_i_q <= 1'b0; 
+    end else begin
+      aresetn_i_q <= ARST_N;
+    end
+  end
+  
+  assign falling_edge_rst = ( (~ARST_N) & aresetn_i_q );
+
+  always @(posedge ACLK) begin
+    if(ARST_N == 1'b1) begin
+      en_chk_r <= 1'b0; 
+    end else if (falling_edge_rst)begin
+      en_chk_r <= 1'b1;
+    end
+  end
+
+  assign rising_edge_rst = ( (ARST_N) & (~aresetn_i_q) );
+
+  always @(posedge ACLK)begin
+    if(sys_resetn == 1'b0) begin
+      reset_pulse_violation_i <= 1'b0;
+    end else if(rising_edge_rst && en_chk_r && count_clk < 15)begin
+      reset_pulse_violation_i <= 1'b1;
+    end
+  end
+
+  assign reset_pulse_violation = reset_pulse_violation_i;
+
+  // End Of Reset Pulse Width Check
+  // New Metadata Checks //doen't work in light weight mode 
+
+  reg ASR_102; 
+  reg ASR_103; 
+  wire [1:0] strb_asr;
+  always @(posedge ACLK) begin 
+    if (!ARST_N || !sys_resetn || !AWVALID ) begin
+      ASR_102 <= 0;
+      ASR_103 <= 0;
+    end else begin
+      ASR_102 <= (C_HAS_WSTRB ==0) && (AWADDR%(C_AXI_DATA_WIDTH/8) !=0);
+      ASR_103 <= (C_HAS_WSTRB ==0) && (C_PC_SUPPORTS_NARROW_BURST == 1) && (AwSizeInBits < C_AXI_DATA_WIDTH);
+    end 
+  end
+
+  assign strb_asr = {ASR_103, ASR_102};
+
+
+  // End Metadata Checks
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Rewritten auxillary code to meet timing derived from Axi4PC.sv
+  /////////////////////////////////////////////////////////////////////////////
+
+  //---------------------------------------------------------------------------
+  // RDataMask
+  //---------------------------------------------------------------------------
+//  always @(posedge ACLK)
+//  begin : p_ByteCountShiftSeq
+//    if (!checker_main_resetn) begin
+//      Bcount1    <= 12'b0;
+//      Bcount     <= 12'b0;
+//      Bshift1    <= 17'b0;
+//      RBurstCam1 <= {BURSTHI+1{1'b0}};
+//      RCountCam1 <= 9'b0;
+//      Bshift     <= 16'b0;
+//    end else begin
+//      Bcount1    <= ByteCount(RBurstCam, RCountCam);
+//      Bcount     <= Bcount1;
+//      Bshift1    <= ByteShift1(RBurstCam, RCountCam);
+//      RBurstCam1 <= RBurstCam;
+//      RCountCam1 <= RCountCam;
+//      Bshift     <= ByteShift2(RBurstCam1, RCountCam1, Bshift1);
+//    end
+//  end
+
+  always @(lp_araddr or internal_ARLOCK or ARBURST or ARLEN or ARSIZE) begin
+    if (LIGHT_WEIGHT==0) begin
+      Burst[ADDRHI:ADDRLO]     = lp_araddr[ADDRHI:ADDRLO];
+      Burst[EXCL]              = (internal_ARLOCK == `AXI4PC_ALOCK_EXCL);
+      Burst[BURSTHI:BURSTLO]   = ARBURST;
+      Burst[ALENHI:ALENLO]     = ARLEN;
+      Burst[ASIZEHI:ASIZELO]   = ARSIZE;
+    end else begin
+      Burst                    = ARLEN;
+    end
+  end
+
+genvar gen_thread;
+generate
+  for (gen_thread=0; gen_thread 0) // clk edge
+    begin
+      // exclusive read address transfer
+      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&
+          !ExclIdFull)
+      begin
+        ExclId[ExclIdWrPtr] <= ARID;
+        ExclIdValid[ExclIdWrPtr] <= 1'b1;
+        ExclIdDelta <= ~ExclIdDelta;
+      end
+      // exclusive write
+      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&
+          ExclAwMatch)
+      begin
+        ExclIdValid[ExclAwId] <= 1'b0;
+        ExclIdDelta <= ~ExclIdDelta;
+      end
+    end // else: !if(!checker_main_resetn)
+  end // block: p_ExclIdSeq
+
+  // Lookup table is full when all valid bits are set
+  assign ExclIdFull = &ExclIdValid;
+
+  // Lookup table overflows when it is full and another exclusive read happens
+  // with an ID that does not match any already being monitored
+  assign ExclIdOverflow = ExclIdFull &&
+                          ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&
+                          !ExclArMatch;
+
+  // New IDs are written to the highest location
+  // that does not have the valid flag set 
+  always @(ExclIdValid)
+  begin : p_ExclIdFreePtrComb
+    integer i;  // loop counter
+    ExclIdFreePtr = 0;
+    for (i = 0; i <= EXMON_HI; i = i + 1)
+    begin
+      if (ExclIdValid[i] == 1'b0)
+      begin
+        ExclIdFreePtr = i;
+      end
+    end
+  end // p_ExclIdFreePtrComb
+
+  // If the ID is already being monitored then reuse the location
+  // New IDs are written to the highest location
+  // that does not have the valid flag set 
+  assign ExclIdWrPtr = ExclArMatch ? ExclArId : ExclIdFreePtr;
+
+  // Write address ID comparator
+//  always @(AWVALID or AWID or ExclIdValid or ExclIdDelta or ExclId)
+  always @( * )
+  begin : p_ExclAwMatchComb
+    integer i;  // loop counter
+    ExclAwMatch = 1'b0;
+    ExclAwId = {LP_EXMON_WIDTH{1'b0}};
+    if (AWVALID)
+    begin
+      for (i = 0; i <= EXMON_HI; i = i + 1)
+      begin
+        if (ExclIdValid[i] && (AWID == ExclId[i]))
+        begin
+          ExclAwMatch = 1'b1;
+          ExclAwId = i;
+        end
+      end
+    end
+  end // p_ExclAwMatchComb
+
+  // Read address ID comparator
+//  always @(ARVALID or ARID or ExclIdValid or ExclIdDelta or ExclId)
+  always @( * )
+  begin : p_ExclArMatchComb
+    integer i;  // loop counter
+    ExclArMatch = 1'b0;
+    ExclArId = {LP_EXMON_WIDTH{1'b0}};
+    if (ARVALID)
+    begin
+      for (i = 0; i <= EXMON_HI; i = i + 1)
+      begin
+        if (ExclIdValid[i] && (ARID == ExclId[i]))
+        begin
+          ExclArMatch = 1'b1;
+          ExclArId = i;
+        end
+      end
+    end
+  end // p_ExclArMatchComb
+
+  // Read data ID comparator
+  always @( * )
+  begin : p_ExclRMatchComb
+    integer i;  // loop counter
+    ExclRMatch = 1'b0;
+    ExclRId = {LP_EXMON_WIDTH{1'b0}};
+    if (RVALID)
+    begin
+      for (i = 0; i <= EXMON_HI; i = i + 1)
+      begin
+        if (ExclIdValid[i] && (RID == ExclId[i]))
+        begin
+          ExclRMatch = 1'b1;
+          ExclRId = i;
+        end
+      end
+    end
+  end // p_ExclRMatchComb
+
+  // INDEX:        - Exclusive Access Storage
+  // =====
+  // Store exclusive control info on each read for checking against write
+
+  always @(posedge ACLK)
+  begin : p_ExclCtrlSeq
+    integer i;  // loop counter
+
+    if (LIGHT_WEIGHT || !checker_main_resetn)
+      for (i = 0; i <= EXMON_HI; i = i + 1)
+      begin
+        ExclReadAddr[i] <= 1'b0;
+        ExclReadData[i] <= 1'b0;
+        ExclAddr[i]     <= {LP_ADDR_WIDTH{1'b0}};
+        ExclSize[i]     <= 3'b000;
+        ExclLen[i]      <= {8{1'b0}};
+        ExclBurst[i]    <= 2'b00;
+        ExclCache[i]    <= {4{1'b0}};
+        ExclProt[i]     <= {3{1'b0}};
+        ExclQos[i]      <= {4{1'b0}};
+        ExclRegion[i]   <= {4{1'b0}};
+        ExclUser[i]     <= {ARUSER_MAX+1{1'b0}};
+      end
+    else if (EXMON_WIDTH > 0) // clk edge
+    begin
+      // exclusive read address transfer
+      if (ARVALID && ARREADY && (internal_ARLOCK == `AXI4PC_ALOCK_EXCL) &&
+          !ExclIdFull)
+      begin
+        ExclReadAddr[ExclIdWrPtr] <= 1'b1; // set exclusive read addr flag for ARID
+        ExclReadData[ExclIdWrPtr] <= 1'b0; // reset exclusive read data flag for ARID
+        ExclAddr[ExclIdWrPtr]     <= lp_araddr;
+        ExclSize[ExclIdWrPtr]     <= ARSIZE;
+        ExclLen[ExclIdWrPtr]      <= ARLEN;
+        ExclBurst[ExclIdWrPtr]    <= ARBURST;
+        ExclCache[ExclIdWrPtr]    <= ARCACHE;
+        ExclProt[ExclIdWrPtr]     <= ARPROT;
+        ExclQos[ExclIdWrPtr]      <= ARQOS;
+        ExclRegion[ExclIdWrPtr]   <= ARREGION;
+        ExclUser[ExclIdWrPtr]     <= ARUSER;
+      end
+      // exclusive write
+      if (AWVALID && AWREADY && (internal_AWLOCK == `AXI4PC_ALOCK_EXCL) &&
+          ExclAwMatch)
+      begin
+        ExclReadAddr[ExclAwId] <= 1'b0; // reset exclusive address flag for AWID
+        ExclReadData[ExclAwId] <= 1'b0; // reset exclusive read data flag for AWID
+      end
+      // completion of exclusive read data transaction
+      if ((RVALID && RREADY && RLAST && ExclReadAddr[ExclRId] &&
+           ExclRMatch) &&
+           // check the read CAM that this is part of an exclusive transfer
+           RBurstCam[EXCL] // ### Rewritten
+         )
+        ExclReadData[ExclRId]  <= 1'b1; // set exclusive read data flag for RID
+    end // else: !if(!checker_main_resetn)
+  end // block: p_ExclCtrlSeq
+
+//------------------------------------------------------------------------------
+// INDEX:   4) Content addressable memories (CAMs)
+//------------------------------------------------------------------------------
+
+  assign WriteDataNumError = WDataNumError1;
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Instantiation
+  /////////////////////////////////////////////////////////////////////////////
+
+  assign i_RecommendOn  = (RecommendOn == 0)     ? 1'b0 : 1'b1;
+  assign i_RecMaxWaitOn = (RecommendWaitOn == 0) ? 1'b0 : 1'b1;
+
+  assign ExclAddr_indexed     = ExclAddr[ExclAwId];
+  assign ExclSize_indexed     = ExclSize[ExclAwId];
+  assign ExclLen_indexed      = ExclLen[ExclAwId];
+  assign ExclBurst_indexed    = ExclBurst[ExclAwId];
+  assign ExclCache_indexed    = ExclCache[ExclAwId];
+  assign ExclProt_indexed     = ExclProt[ExclAwId];
+  assign ExclRegion_indexed   = ExclRegion[ExclAwId];
+  assign ExclReadAddr_indexed = ExclReadAddr[ExclAwId];
+  assign ExclReadData_indexed = ExclReadData[ExclAwId];
+
+  axi_protocol_checker_v2_0_1_axi4pc_asr_inline #
+  (
+     .DATA_WIDTH   (C_AXI_DATA_WIDTH),
+     .ID_WIDTH     (C_AXI_ID_WIDTH),
+     .AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
+     .WUSER_WIDTH  (C_AXI_WUSER_WIDTH),
+     .BUSER_WIDTH  (C_AXI_BUSER_WIDTH),
+     .ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
+     .RUSER_WIDTH  (C_AXI_RUSER_WIDTH),
+     .MAXRBURSTS   (MAXRBURSTS),
+     .MAXWBURSTS   (MAXWBURSTS),
+     .ADDR_WIDTH   (LP_ADDR_WIDTH),
+     .DATA_MAX     (DATA_MAX),
+     .ADDR_MAX     (LP_ADDR_WIDTH - 1),
+     .STRB_WIDTH   (STRB_WIDTH),
+     .STRB_MAX     (STRB_MAX),
+     .ID_MAX       (ID_MAX),
+     .AWUSER_MAX   (AWUSER_MAX),
+     .WUSER_MAX    (WUSER_MAX),
+     .BUSER_MAX    (BUSER_MAX),
+     .ARUSER_MAX   (ARUSER_MAX),
+     .RUSER_MAX    (RUSER_MAX),
+     .MAX_AW_WAITS (MAX_AW_WAITS),
+     .MAX_AR_WAITS (MAX_AR_WAITS),
+     .MAX_W_WAITS  (MAX_W_WAITS),
+     .MAX_R_WAITS  (MAX_R_WAITS),
+     .MAX_B_WAITS  (MAX_B_WAITS),
+     .MAX_CONTINUOUS_RTRANSFERS_WAITS  (MAX_CONTINUOUS_RTRANSFERS_WAITS),
+     .MAX_CONTINUOUS_WTRANSFERS_WAITS  (MAX_CONTINUOUS_WTRANSFERS_WAITS),
+     .MAX_WLAST_TO_AWVALID_WAITS  (MAX_WLAST_TO_AWVALID_WAITS),
+     .MAX_WRITE_TO_BVALID_WAITS  (MAX_WRITE_TO_BVALID_WAITS),
+     .LIGHT_WEIGHT (LIGHT_WEIGHT)
+   )
+  i_Axi4PC_asr_inline
+  (
+     .Axi4PC_asr_inline_out (Axi4PC_asr_inline_out),
+     .reset                 (resetn_out),
+     .AWVALID               (AWVALID),
+     .AWBURST               (AWBURST),
+     .AwAddrIncr            (AwAddrIncr),
+     .AWADDR                (lp_awaddr),
+     .ACLK                  (ACLK),
+     .AlignMaskW            (AlignMaskW),
+     .AWLEN                 (AWLEN),
+     .AWLOCK                (internal_AWLOCK),
+     .AWCACHE               (AWCACHE),
+     .AwSizeInBits          (AwSizeInBits),
+     .ARESETn               (ARST_N),
+     .AWREADY               (AWREADY),
+     .AWID                  (AWID),
+     .AWPROT                (AWPROT),
+     .AWSIZE                (AWSIZE),
+     .AWQOS                 (AWQOS),
+     .AWREGION              (AWREGION),
+     .i_RecommendOn         (i_RecommendOn),
+     .i_RecMaxWaitOn        (i_RecMaxWaitOn),
+     .WriteDataNumError     (WriteDataNumError),
+     .BStrbError            (BStrbError),
+     .WVALID                (WVALID),
+     .WREADY                (WREADY),
+     .WDATA                 (WDATA),
+     .WLAST                 (WLAST),
+     .WSTRB                 (WSTRB),
+     .BrespErrorLast        (1'b0),
+     .BrespExokError        (1'b0),
+     .BVALID                (BVALID),
+     .BrespErrorLead        (BrespErrorLead),
+     .BREADY                (BREADY),
+     .BID                   (BID),
+     .BRESP                 (BRESP),
+     .ARVALID               (ARVALID),
+     .ARBURST               (ARBURST),
+     .ArAddrIncr            (ArAddrIncr),
+     .ARADDR                (lp_araddr),
+     .AlignMaskR            (AlignMaskR),
+     .ARLEN                 (ARLEN),
+     .ARLOCK                (internal_ARLOCK),
+     .ARCACHE               (ARCACHE),
+     .ArSizeInBits          (ArSizeInBits),
+     .ARREADY               (ARREADY),
+     .ARID                  (ARID),
+     .ARPROT                (ARPROT),
+     .ARSIZE                (ARSIZE),
+     .ARQOS                 (ARQOS),
+     .ARREGION              (ARREGION),
+     .RVALID                (RVALID),
+     .RREADY                (RREADY),
+     .ArCountPending        (ArCountPending),
+     .ArLenPending          (ArLenPending),
+     .RLAST                 (RLAST),
+     .RidMatch              (RidMatch),
+     .RRESP                 (RRESP),
+     .ArExclPending         (ArExclPending),
+     .RDATA                 (RDATA),
+     .RID                   (RID),
+     .CSYSREQ               (1'b0),
+     .CSYSACK               (1'b0),
+     .ExclMask              (ExclMask),
+     .ExclReadAddr          (ExclReadAddr_indexed),
+     .ExclAwMatch           (ExclAwMatch),
+     .ExclAddr              (ExclAddr_indexed),
+     .ExclSize              (ExclSize_indexed),
+     .ExclLen               (ExclLen_indexed),
+     .ExclBurst             (ExclBurst_indexed),
+     .ExclCache             (ExclCache_indexed),
+     .ExclProt              (ExclProt_indexed),
+     .ExclRegion            (ExclRegion_indexed),
+     .ArLenInBytes          (ArLenInBytes),
+     .ExclReadData          (ExclReadData_indexed),
+     .AWUSER                (AWUSER),
+     .WUSER                 (WUSER),
+     .BUSER                 (BUSER),
+     .ARUSER                (ARUSER),
+     .RUSER                 (RUSER)
+   );
+
+
+  generate
+    if (C_AXI_PROTOCOL == 2) begin : LITE
+      axi_protocol_checker_v2_0_1_axi4litepc_asr_inline #
+      (
+         .DATA_WIDTH (C_AXI_DATA_WIDTH)
+       )
+      i_Axi4LitePC_asr_inline
+      (
+         .Axi4LitePC_asr_inline_out (Axi4LitePC_asr_inline_out),
+         .reset                     (resetn_out),
+         .BVALID                    (BVALID),
+         .BRESP                     (BRESP),
+         .ACLK                      (ACLK),
+         .RVALID                    (RVALID),
+         .RRESP                     (RRESP)
+       );
+    end else begin : NO_LITE
+      assign Axi4LitePC_asr_inline_out = 3'b000;
+    end
+  endgenerate
+  
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Error output masking and latching
+  /////////////////////////////////////////////////////////////////////////////
+
+  reg  [C_ERROR_COUNT-1:0] pc_status_i;
+  wire [C_ERROR_COUNT-1:0] pc_status_masked;
+
+  assign pc_status_masked = {strb_asr, reset_pulse_violation, Axi4PC_asr_inline_out[91:88], xilinx_inline_out, Axi4LitePC_asr_inline_out, Axi4PC_aux, Axi4PC_asr_inline_out[78:1]};
+
+  always @(posedge ACLK)
+  begin : p_errorSeq
+    if (!checker_main_resetn) begin
+      pc_status_i <= {C_ERROR_COUNT {1'b0}};
+    end else begin
+      pc_status_i <= pc_status_masked | pc_status_i;
+    end
+  end
+
+  assign pc_status = pc_status_i;
+
+  assign AWPush = AWREADY & AWVALID;
+  assign WLastPush = WVALID & WREADY & WLAST;
+
+  /////////////////////////////////////////////////////////////////////////////
+  //AW-W checks
+  axi_protocol_checker_v2_0_1_syn_fifo # (
+    .C_DATA_WIDTH (WASIZEHI+1+8+P_WTHREAD_SIZE),
+    .C_ADDR_WIDTH (log2(MAXWBURSTS))
+   ) AWCMD (
+    .clk      (ACLK),
+    .rst      (!checker_main_resetn),
+    .data_in  ({awid_index[P_WTHREAD_SIZE-1:0], AWLEN, AWSIZE, ((LIGHT_WEIGHT==0)?lp_awaddr[WADDRHI:WADDRLO]:{WADDRHI-WADDRLO+1{1'b0}})}),
+    .rd       (wcheckPop),
+    .wr       (AWPush),
+    .data_out ({AWIDOut, AWLENOut,AWStrbsizeOut, AWStrbAddrOut}),
+    .empty    (AWEmpty),
+    .full     (AWFull)
+  );
+  
+  axi_protocol_checker_v2_0_1_syn_fifo # (
+    .C_DATA_WIDTH (9+STRB_MAX+1),
+    .C_ADDR_WIDTH (log2(MAXWBURSTS))
+   ) WCHECK (
+    .clk      (ACLK),
+    .rst      (!checker_main_resetn),
+    .data_in  ({WCountIn, ((LIGHT_WEIGHT==0)?WstrbIn:{C_AXI_DATA_WIDTH/8{1'b0}})}),
+    .rd       (wcheckPop),
+    .wr       (WLastPush),
+    .data_out ({WCheckCountOut, WCheckstrbOut}),
+    .empty    (WCheckEmpty),
+    .full     (WCheckFull)
+  );
+
+  assign WstrbIn = (first_strb) ? WSTRB : WSTRBq;
+  assign wcheckPop = (!WCheckEmpty & !AWEmpty);
+
+  always @(posedge ACLK) begin : p_wstrb
+    if (LIGHT_WEIGHT || !checker_main_resetn | (WVALID & WREADY & WLAST)) begin
+      WSTRBq <= {C_AXI_DATA_WIDTH/8{1'b0}};
+      first_strb <= 1'b1;
+    end else if (WVALID & WREADY & first_strb) begin
+      first_strb <= 1'b0;
+      WSTRBq <= WSTRB;
+    end
+  end
+
+integer id_cnt;
+
+localparam L_CHECK_PIPE_WIDTH = 7;
+
+reg   [STRB_MAX:0] StrbMask_q1;  
+reg   [STRB_MAX:0] StrbMask_q2;  
+reg   [STRB_MAX:0] StrbMask_q3_n;  
+
+reg          [6:0] StrbAddr_q1;
+reg          [6:0] StrbAddr_q2;
+reg          [2:0] StrbSize_q1;
+reg          [2:0] StrbSize_q2;
+reg   [STRB_MAX:0] Strb_q1;
+reg   [STRB_MAX:0] Strb_q2;
+reg   [STRB_MAX:0] Strb_q3;
+reg          [L_CHECK_PIPE_WIDTH-1:0] wchechPop_shift;
+reg                CheckStrbAssert;
+reg          [6:0] mask_shift_stage_1;
+reg          [6:0] mask_shift_stage_2;
+reg          [6:0] mask_shift_stage_2_q1;
+
+always @(posedge ACLK) begin
+  StrbAddr_q1 <= AWStrbAddrOut;
+  StrbAddr_q2 <= StrbAddr_q1;
+  StrbSize_q1 <= AWStrbsizeOut;
+  StrbSize_q2 <= StrbSize_q1;
+  Strb_q1 <= WCheckstrbOut;
+  Strb_q2 <= Strb_q1;
+  Strb_q3 <= Strb_q2;
+
+  mask_shift_stage_1 <= (AWStrbAddrOut & ((STRB_1 << AWStrbsizeOut) -  STRB_1));
+  mask_shift_stage_2 <= (AWStrbAddrOut & ((STRB_MAX << AWStrbsizeOut) & STRB_MAX));
+  mask_shift_stage_2_q1 <= mask_shift_stage_2;
+  // The basic strobe for an aligned address
+  StrbMask_q1 <= (STRB_1 << (STRB_1 << AWStrbsizeOut)) - STRB_1;
+  // Zero the unaligned byte lanes
+  // Note: the number of unaligned byte lanes is given by:
+  // (StrbAddr & ((1 << StrbSize) - 1)), i.e. the unaligned part of the
+  // address with respect to the transfer size
+  //
+  // Note! {{STRB_MAX{1'b0}}, 1'b1} gives 1 in the correct vector length
+  StrbMask_q2 <= StrbMask_q1 &                    // Mask off unaligned byte lanes
+    (StrbMask_q1 << mask_shift_stage_1);          // shift the strb mask left by the number of unaligned byte lanes
+
+  StrbMask_q3_n <= ~(StrbMask_q2 << mask_shift_stage_2_q1);
+
+end
+
+localparam integer L_NUM_CHKSTRB_NIBS       = (((C_AXI_DATA_WIDTH/8) + 3) / 4);
+localparam integer L_NUM_CHKSTRB_NIB_LANES  = ((L_NUM_CHKSTRB_NIBS + 3) / 4) * 4;
+localparam integer L_NUM_CHKSTRB_EQ_LANES    = (L_NUM_CHKSTRB_NIB_LANES / 4);
+localparam integer L_NUM_CHKSTRB_AND1_LANES  = (L_NUM_CHKSTRB_EQ_LANES + 3) / 4;
+localparam integer L_NUM_CHKSTRB_AND2_LANES  = (L_NUM_CHKSTRB_AND1_LANES + 3) / 4;
+
+reg [(4*L_NUM_CHKSTRB_EQ_LANES)-1:0]    CHKSTRB_eq;
+reg [(4*L_NUM_CHKSTRB_AND1_LANES)-1:0]  CHKSTRB_stage_1_eq;
+reg [(4*L_NUM_CHKSTRB_AND2_LANES)-1:0]  CHKSTRB_stage_2_eq;
+
+//assign s_CHKSTRB_sqaa = &CHKSTRB_stage_2_eq;
+
+integer CHKSTRB_bc;
+integer CHKSTRB_stage_1;
+integer CHKSTRB_stage_2;
+
+always @(posedge ACLK) begin
+  for (CHKSTRB_bc = 0; CHKSTRB_bc < L_NUM_CHKSTRB_EQ_LANES*4; CHKSTRB_bc = CHKSTRB_bc + 1) begin : CHKSTRB_BC_LOOP
+    if (CHKSTRB_bc < ((C_AXI_DATA_WIDTH/8)/4)) begin
+      CHKSTRB_eq[CHKSTRB_bc] <= |(Strb_q3[CHKSTRB_bc*4 +:4] & StrbMask_q3_n[CHKSTRB_bc*4 +: 4]);
+    end else begin
+      CHKSTRB_eq[CHKSTRB_bc] <= 1'b0;
+    end
+  end
+
+  for (CHKSTRB_stage_1 = 0; CHKSTRB_stage_1 < L_NUM_CHKSTRB_AND1_LANES * 4;CHKSTRB_stage_1 = CHKSTRB_stage_1 + 1) begin : CHKSTRB_S1
+    if (CHKSTRB_stage_1 < L_NUM_CHKSTRB_EQ_LANES) begin
+      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= |CHKSTRB_eq[CHKSTRB_stage_1*4 +:4];
+    end else begin
+      CHKSTRB_stage_1_eq[CHKSTRB_stage_1] <= 1'b0;
+    end
+  end
+
+  for (CHKSTRB_stage_2 = 0; CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND2_LANES * 4;CHKSTRB_stage_2 = CHKSTRB_stage_2 + 1) begin : CHKSTRB_S2
+    if (CHKSTRB_stage_2 < L_NUM_CHKSTRB_AND1_LANES) begin
+      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= |CHKSTRB_stage_1_eq[CHKSTRB_stage_2*4 +:4];
+    end else begin
+      CHKSTRB_stage_2_eq[CHKSTRB_stage_2] <= 1'b0;
+    end
+  end
+
+end
+
+
+always @(posedge ACLK) begin : bstrb_check
+  if (LIGHT_WEIGHT || !checker_main_resetn) begin
+    BStrbError <= 1'b0;
+    wchechPop_shift <= {L_CHECK_PIPE_WIDTH{1'b0}};
+    CheckStrbAssert <= 1'b0;
+  end else begin
+    wchechPop_shift <= {wchechPop_shift[(L_CHECK_PIPE_WIDTH-2):0], wcheckPop};
+    BStrbError <= wchechPop_shift[(L_CHECK_PIPE_WIDTH-1)] & CheckStrbAssert;
+    CheckStrbAssert <= |CHKSTRB_stage_2_eq;
+  end
+end
+
+  always @(posedge ACLK) begin : p_check
+    if (!checker_main_resetn) begin
+      WDataNumError1 <= 1'b0;
+      for (id_cnt = 0; id_cnt <= C_NUM_WTHREADS; id_cnt = id_cnt + 1) begin
+        AWXferCount[id_cnt] <= {log2(MAXWBURSTS) + 1{1'b0}};
+      end
+      BrespErrorLead <= 1'b0;
+      AWXferCountOverflow <= 1'b0;
+    end else begin
+      WDataNumError1 <= 1'b0;
+      AWXferCountOverflow <= 1'b0;
+      //Trigger Error of B->{AW or W}
+      if (BVALID & !(wcheckPop & (bid_index == AWIDOut) & !bid_mismatch)) begin
+        BrespErrorLead <= bid_mismatch | (AWXferCount[bid_index] == 0);
+      end else begin
+        BrespErrorLead <= 1'b0;
+      end
+      ////////////////////////////////////////////////////////////////
+      //Count the number of AWID's and BID's
+      if (wcheckPop) begin
+        WDataNumError1 <= (WCheckCountOut != {1'b0,AWLENOut});
+      end
+      if (wcheckPop & !(BVALID & BREADY & (bid_index == AWIDOut))) begin
+        AWXferCount[AWIDOut] <= AWXferCount[AWIDOut] + 1;
+        AWXferCountOverflow <= AWXferCount[AWIDOut] == {1'b1,{log2(MAXWBURSTS){1'b0}}};
+      end
+      if (BVALID & BREADY & !(wcheckPop & (bid_index == AWIDOut))) begin
+        AWXferCount[bid_index] <= AWXferCount[bid_index] - 1;
+      end
+    end
+  end
+
+//////////////////////////////////////////////////////////////////////////////////////////////////
+//Xilinx Checks
+wire [2:0]  awready_s;
+wire [2:0]  wready_s;
+wire [2:0]  bready_s;
+wire [2:0]  arready_s;
+wire [2:0]  rready_s;
+
+reg  [2:0]  awready_sq;
+reg  [2:0]  wready_sq;
+reg  [2:0]  bready_sq;
+reg  [2:0]  arready_sq;
+reg  [2:0]  rready_sq;
+
+always @(posedge ACLK) begin : xil_check
+  if (LIGHT_WEIGHT || !resetn_out) begin
+    xilinx_inline_out <= 11'h000;
+    awready_sq <= 3'h4;
+    wready_sq <= 3'h4;
+    bready_sq <= 3'h4;
+    arready_sq <= 3'h4;
+    rready_sq <= 3'h4;
+  end else begin
+    xilinx_inline_out[1] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && (AwSizeInBits < C_AXI_DATA_WIDTH));
+    xilinx_inline_out[2] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && (ArSizeInBits < C_AXI_DATA_WIDTH));
+    xilinx_inline_out[3] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (AWVALID && (AWLEN > 0) && !(AWCACHE[1]));
+    xilinx_inline_out[4] <= (C_PC_SUPPORTS_NARROW_BURST == 0) && (ARVALID && (ARLEN > 0) && !(ARCACHE[1]));
+    xilinx_inline_out[5] <= (AWVALID && !(AWLEN <= (C_PC_MAX_BURST_LENGTH - 1)));
+    xilinx_inline_out[6] <= (ARVALID && !(ARLEN <= (C_PC_MAX_BURST_LENGTH - 1)));
+
+    //////////////////////////////////////////////////////////////////////////////////////////////////
+    //Xilinx xREADY checks : xREADY is LOW for the first cycle after ARESETn goes HIGH.
+    awready_sq  <= awready_s;
+    wready_sq   <= wready_s;
+    bready_sq   <= bready_s;
+    arready_sq  <= arready_s;
+    rready_sq   <= rready_s;
+
+    xilinx_inline_out[7] <= (awready_s[0]);
+    xilinx_inline_out[8] <= ( wready_s[0]);
+    xilinx_inline_out[9] <= ( bready_s[0]);
+    xilinx_inline_out[10] <= (arready_s[0]);
+    xilinx_inline_out[11] <= ( rready_s[0]);
+  end
+end
+
+assign awready_s  = {1'b1, !(ARST_N), (awready_sq[1] && (ARST_N && AWREADY))};
+assign wready_s   = {1'b1, !(ARST_N), ( wready_sq[1] && (ARST_N &&  WREADY))};
+assign bready_s   = {1'b1, !(ARST_N), ( bready_sq[1] && (ARST_N &&  BREADY))};
+assign arready_s  = {1'b1, !(ARST_N), (arready_sq[1] && (ARST_N && ARREADY))};
+assign rready_s   = {1'b1, !(ARST_N), ( rready_sq[1] && (ARST_N &&  RREADY))};
+
+endmodule
+`default_nettype wire
+
+
+
+//*****************************************************************************
+// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+// Design Name      : axi_protocol_checker_v2_0_1_syn_fifo
+// Function         : synchronous FIFO
+// Reference        : None
+// Revision History : Initial version
+//*****************************************************************************
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_syn_fifo #
+  (
+   parameter C_DATA_WIDTH = 8,
+   parameter C_ADDR_WIDTH = 4
+   )
+  (
+   input  wire                    clk,
+   input  wire                    rst,
+
+   input  wire [C_DATA_WIDTH-1:0] data_in,
+   input  wire                    rd,
+   input  wire                    wr,
+   output wire [C_DATA_WIDTH-1:0] data_out,
+   output wire                    empty,
+   output wire                    full
+  );
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+
+  localparam RAM_SIZE = (1 << C_ADDR_WIDTH);
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+
+  reg [C_ADDR_WIDTH-1:0] wr_ptr;
+  reg [C_ADDR_WIDTH-1:0] rd_ptr;
+  reg [C_ADDR_WIDTH:0]   cnt;
+
+  (* ram_style="distributed" *)
+  reg [C_DATA_WIDTH-1:0] data_ram[RAM_SIZE-1:0];
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Code
+  /////////////////////////////////////////////////////////////////////////////
+
+  assign full  = (cnt == RAM_SIZE);
+  assign empty = (cnt == 0);
+
+  always @(posedge clk)
+  begin : COUNTER
+    if (rst) begin
+      cnt <= 0;
+    end else if (rd && !wr && (cnt != 0)) begin
+      cnt <= cnt - 1; // Just read: decrement
+    end else if (wr && !rd && (cnt != RAM_SIZE)) begin
+      cnt <= cnt + 1; // Just write: increment
+    end
+  end
+
+  always @(posedge clk)
+  begin : WRITE_PTR
+    if (rst) begin
+      wr_ptr <= 0;
+    end else if (wr) begin
+      wr_ptr <= wr_ptr + 1;
+    end
+  end
+
+  always @(posedge clk)
+  begin : READ_PTR
+    if (rst) begin
+      rd_ptr <= 0;
+    end else if (rd) begin
+      rd_ptr <= rd_ptr + 1;
+    end
+  end
+
+  // Distributed RAM
+  always @(posedge clk)
+  begin
+    if (wr)
+      data_ram[wr_ptr] <= data_in;
+  end
+
+  assign data_out = data_ram[rd_ptr];
+
+endmodule
+
+`default_nettype wire
+
+
+// (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+
+
+`timescale 1ps/1ps
+`default_nettype none
+`ifndef AXI4PC_MESSAGES
+  `define AXI4PC_MESSAGES
+  `define AUXM_ADDR_WIDTH           "AXI_AUXM_ADDR_WIDTH. Parameter ADDR_WIDTH must be between 32 and 64 bits inclusive"
+  `define AUXM_AXI4LITE_DATA_WIDTH  "AXI4LITE_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be either 32 or 64."
+  `define AUXM_DATA_WIDTH           "AXI_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be 32, 64, 128, 256, 512 or 1024"
+  `define AUXM_EXCL_OVERFLOW        "AXI_AUXM_EXCL_OVERFLOW. Exclusive access monitor overflow, increase EXMON_WIDTH parameter."
+  `define AUXM_EXMON_WIDTH          "AXI_AUXM_EXMON_WIDTH. Parameter EXMON_WIDTH must be greater than or equal to 1"
+  `define AUXM_MAXRBURSTS           "AXI_AUXM_MAXRBURSTS. Parameter MAXRBURSTS must be greater than or equal to 1"
+  `define AUXM_MAXWBURSTS           "AXI_AUXM_MAXWBURSTS. Parameter MAXWBURSTS must be greater than or equal to 1"
+  `define AUXM_RCAM_OVERFLOW        "AXI_AUXM_RCAM_OVERFLOW. Read CAM overflow, increase Maximum outstanding READ Transactions per ID (MAX_RD_BURSTS) parameter."
+  `define AUXM_RCAM_UNDERFLOW       "AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow."
+  `define AUXM_WCAM_OVERFLOW        "AXI_AUXM_WCAM_OVERFLOW. Write CAM overflow, increase Maximum outstanding WRITE Transactions per ID (MAX_WR_BURSTS) parameter."
+  `define AUXM_WCAM_UNDERFLOW       "AXI_AUXM_WCAM_UNDERFLOW. Write CAM underflow"
+  `define ERRL_CACTIVE_X            "AXI_ERRL_CACTIVE_X: When not in reset, a value of X on CACTIVE is not permitted. Spec: section A9.2."
+  `define ERRL_CSYSACK_FALL         "AXI_ERRL_CSYSACK_FALL: When CSYSACK transitions from high to low, CSYSREQ must be low. Spec: figure A9-1."
+  `define ERRL_CSYSACK_RISE         "AXI_ERRL_CSYSACK_RISE: When CSYSACK transitions from low to high, CSYSREQ must be high. Spec: figure A9-1."
+  `define ERRL_CSYSACK_X            "AXI_ERRL_CSYSACK_X: When not in reset, a value of X on CSYSACK is not permitted. Spec: section A9.2."
+  `define ERRL_CSYSREQ_FALL         "AXI_ERRL_CSYSREQ_FALL: When CSYSREQ transitions from high to low, CSYSACK must be high. Spec: figure A9-1."
+  `define ERRL_CSYSREQ_RISE         "AXI_ERRL_CSYSREQ_RISE: When CSYSREQ transitions from low to high, CSYSACK must be low. Spec: figure A9-1."
+  `define ERRL_CSYSREQ_X            "AXI_ERRL_CSYSREQ_X: When not in reset, a value of X on CSYSREQ is not permitted. Spec: section A9.2."
+  `define ERRM_ARADDR_BOUNDARY      "AXI_ERRM_ARADDR_BOUNDARY: A burst must not cross a 4kbyte boundary. Spec: section A3.4.1."
+  `define ERRM_ARADDR_STABLE        "AXI_ERRM_ARADDR_STABLE: ARADDR must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARADDR_WRAP_ALIGN    "AXI_ERRM_ARADDR_WRAP_ALIGN: For a wrapping burst, the start address must be aligned to the size of each transfer. Spec: section A3.4.1."
+  `define ERRM_ARADDR_X             "AXI_ERRM_ARADDR_X: When ARVALID is high, a value of X on ARADDR is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARBURST              "AXI_ERRM_ARBURST: When ARVALID is high, a value of 2'b11 on ARBURST is not permitted. Spec: table A3-3."
+  `define ERRM_ARBURST_STABLE       "AXI_ERRM_ARBURST_STABLE: ARBURST must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARBURST_X            "AXI_ERRM_ARBURST_X: When ARVALID is high, a value of X on ARBURST is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARCACHE              "AXI_ERRM_ARCACHE: When AWVALID is high, a reserved value on ARCACHE is not allowed. Spec: table A4-5."
+  `define ERRM_ARCACHE_STABLE       "AXI_ERRM_ARCACHE_STABLE: ARCACHE must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARCACHE_X            "AXI_ERRM_ARCACHE_X: When ARVALID is high, a value of X on ARCACHE is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARID_STABLE          "AXI_ERRM_ARID_STABLE: ARID must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARID_TIEOFF          "AXI_ERRM_ARID_TIEOFF: ARID must be stable when ID_WIDTH is set to 0." 
+  `define ERRM_ARID_X               "AXI_ERRM_ARID_X: When ARVALID is high, a value of X on ARID is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARLEN_FIXED          "AXI_ERRM_ARLEN_FIXED: Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section A3.4.1."
+  `define ERRM_ARLEN_LOCK           "AXI_ERRM_ARLEN_LOCK: Exclusive access transactions cannot have a length greater than 16 beats. Spec: section A7.2.4."
+  `define ERRM_ARLEN_STABLE         "AXI_ERRM_ARLEN_STABLE: ARLEN must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARLEN_WRAP           "AXI_ERRM_ARLEN_WRAP: For a wrapping burst, the length of the burst must be 2, 4, 8 or 16 transfers. Spec: section A3.4.1."
+  `define ERRM_ARLEN_X              "AXI_ERRM_ARLEN_X: When ARVALID is high, a value of X on ARLEN is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARLOCK_STABLE        "AXI_ERRM_ARLOCK_STABLE: ARLOCK must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARLOCK_X             "AXI_ERRM_ARLOCK_X: When ARVALID is high, a value of X on ARLOCK is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARPROT_STABLE        "AXI_ERRM_ARPROT_STABLE: ARPROT must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARPROT_X             "AXI_ERRM_ARPROT_X: When ARVALID is high, a value of X on ARPROT is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARQOS_STABLE         "AXI_ERRM_ARQOS_STABLE: ARQOS must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARQOS_X              "AXI_ERRM_ARQOS_X: When ARVALID is high, a value of X on ARQOS is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARREGION_STABLE      "AXI_ERRM_ARREGION_STABLE: ARREGION must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARREGION_X           "AXI_ERRM_ARREGION_X: When ARVALID is high, a value of X on ARREGION is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARSIZE               "AXI_ERRM_ARSIZE: The size of any transfer must not exceed the data bus width of either agent in the transaction. Spec: section A3.4.1."
+  `define ERRM_ARSIZE_STABLE        "AXI_ERRM_ARSIZE_STABLE: ARSIZE must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARSIZE_X             "AXI_ERRM_ARSIZE_X: When ARVALID is high, a value of X on ARSIZE is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARUSER_STABLE        "AXI_ERRM_ARUSER_STABLE: ARUSER must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1."
+  `define ERRM_ARUSER_TIEOFF        "AXI_ERRM_ARUSER_TIEOFF: ARUSER must be stable when ARUSER_WIDTH is set to 0." 
+  `define ERRM_ARUSER_X             "AXI_ERRM_ARUSER_X: When ARVALID is high, a value of X on ARUSER is not permitted. Spec: section A3.2.2."
+  `define ERRM_ARVALID_RESET        "AXI_ERRM_ARVALID_RESET: The earliest point after reset that a master is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. Spec: Figure A3-1."
+  `define ERRM_ARVALID_STABLE       "AXI_ERRM_ARVALID_STABLE: Once ARVALID is asserted, it must remain asserted until ARREADY is high. Spec: section A3.2.1."
+  `define ERRM_ARVALID_X            "AXI_ERRM_ARVALID_X: When not in reset, a value of X on ARVALID is not permitted. Spec: section A3.1.2."
+  `define ERRM_AWADDR_BOUNDARY      "AXI_ERRM_AWADDR_BOUNDARY: A burst must not cross a 4kbyte boundary. Spec: section A3.4.1."
+  `define ERRM_AWADDR_STABLE        "AXI_ERRM_AWADDR_STABLE: AWADDR must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWADDR_WRAP_ALIGN    "AXI_ERRM_AWADDR_WRAP_ALIGN: For a wrapping burst, the start address must be aligned to the size of each transfer. Spec: section A3.4.1."
+  `define ERRM_AWADDR_X             "AXI_ERRM_AWADDR_X: When AWVALID is high, a value of X on AWADDR is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWBURST              "AXI_ERRM_AWBURST: When AWVALID is high, a value of 2'b11 on AWBURST is reserved. Spec: table A3-3."
+  `define ERRM_AWBURST_STABLE       "AXI_ERRM_AWBURST_STABLE: AWBURST must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWBURST_X            "AXI_ERRM_AWBURST_X: When AWVALID is high, a value of X on AWBURST is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWCACHE              "AXI_ERRM_AWCACHE: When AWVALID is high, a reserved value on AWCACHE is not allowed. Spec: table A4-5."
+  `define ERRM_AWCACHE_STABLE       "AXI_ERRM_AWCACHE_STABLE: AWCACHE must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWCACHE_X            "AXI_ERRM_AWCACHE_X: When AWVALID is high, a value of X on AWCACHE is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWID_STABLE          "AXI_ERRM_AWID_STABLE: AWID must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWID_TIEOFF          "AXI_ERRM_AWID_TIEOFF: AWID must be stable when ID_WIDTH is set to 0." 
+  `define ERRM_AWID_X               "AXI_ERRM_AWID_X: When AWVALID is high, a value of X on AWID is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWLEN_FIXED          "AXI_ERRM_AWLEN_FIXED: Transactions of burst type FIXED cannot have a length greater than 16 beats. Spec: section A3.4.1."
+  `define ERRM_AWLEN_LOCK           "AXI_ERRM_AWLEN_LOCK: Exclusive access transactions cannot have a length greater than 16 beats. Spec: section A7.2.4."
+  `define ERRM_AWLEN_STABLE         "AXI_ERRM_AWLEN_STABLE: AWLEN must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWLEN_WRAP           "AXI_ERRM_AWLEN_WRAP: For a wrapping burst, the length of the burst must be 2, 4, 8 or 16 transfers. Spec: section A3.4.1."
+  `define ERRM_AWLEN_X              "AXI_ERRM_AWLEN_X: When AWVALID is high, a value of X on AWLEN is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWLOCK_STABLE        "AXI_ERRM_AWLOCK_STABLE: AWLOCK must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWLOCK_X             "AXI_ERRM_AWLOCK_X: When AWVALID is high, a value of X on AWLOCK is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWPROT_STABLE        "AXI_ERRM_AWPROT_STABLE: AWPROT must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWPROT_X             "AXI_ERRM_AWPROT_X: When AWVALID is high, a value of X on AWPROT is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWQOS_STABLE         "AXI_ERRM_AWQOS_STABLE: AWQOS must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWQOS_X              "AXI_ERRM_AWQOS_X: When AWVALID is high, a value of X on AWQOS is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWREGION_STABLE      "AXI_ERRM_AWREGION_STABLE: AWREGION must remain stable when ARVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWREGION_X           "AXI_ERRM_AWREGION_X: When AWVALID is high, a value of X on AWREGION is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWSIZE               "AXI_ERRM_AWSIZE: The size of any transfer must not exceed the data bus width of either agent in the transaction. Spec: section A3.4.1."
+  `define ERRM_AWSIZE_STABLE        "AXI_ERRM_AWSIZE_STABLE: AWSIZE must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWSIZE_X             "AXI_ERRM_AWSIZE_X: When AWVALID is high, a value of X on AWSIZE is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWUSER_STABLE        "AXI_ERRM_AWUSER_STABLE: AWUSER must remain stable when AWVALID is asserted and AWREADY low. Spec: section A3.2.1."
+  `define ERRM_AWUSER_TIEOFF        "AXI_ERRM_AWUSER_TIEOFF: AWUSER must be stable when AWUSER_WIDTH is set to 0." 
+  `define ERRM_AWUSER_X             "AXI_ERRM_AWUSER_X: When AWVALID is high, a value of X on AWUSER is not permitted. Spec: section A3.2.2."
+  `define ERRM_AWVALID_RESET        "AXI_ERRM_AWVALID_RESET: The earliest point after reset that a master is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. Spec: Figure A3-1."
+  `define ERRM_AWVALID_STABLE       "AXI_ERRM_AWVALID_STABLE: Once AWVALID is asserted, it must remain asserted until AWREADY is high. Spec: section A3.2.2."
+  `define ERRM_AWVALID_X            "AXI_ERRM_AWVALID_X: When not in reset, a value of X on AWVALID is not permitted. Spec: section A3.1.2."
+  `define ERRM_BREADY_X             "AXI_ERRM_BREADY_X: When not in reset, a value of X on BREADY is not permitted. Spec: section A3.1.2."
+  `define ERRM_EXCL_ALIGN           "AXI_ERRM_EXCL_ALIGN: The address of an exclusive access must be aligned to the total number of bytes in the transaction. Spec: section A7.2.4."
+  `define ERRM_EXCL_LEN             "AXI_ERRM_EXCL_LEN: The number of bytes to be transferred in an exclusive access burst must be a power of 2. Spec: section A7.2.4."
+  `define ERRM_EXCL_MAX             "AXI_ERRM_EXCL_MAX: The maximum number of bytes that can be transferred in an exclusive burst is 128. Spec: section A7.2.4."
+  `define ERRM_RREADY_X             "AXI_ERRM_RREADY_X: When not in reset, a value of X on RREADY is not permitted. Spec: section A3.1.2."
+  `define ERRM_WDATA_NUM            "AXI_ERRM_WDATA_NUM: The number of write data items must match AWLEN for the corresponding address. Spec: section A3.4.1."
+  `define ERRM_WDATA_STABLE         "AXI_ERRM_WDATA_STABLE: WDATA must remain stable when WVALID is asserted and WREADY low. Spec: section A3.2.1."
+  `define ERRM_WDATA_X              "AXI_ERRM_WDATA_X: When WVALID is high, a value of X on active byte lanes of WDATA is not permitted. Spec: section A3.2.2."
+  `define ERRM_WLAST_STABLE         "AXI_ERRM_WLAST_STABLE: WLAST must remain stable when WVALID is asserted and WREADY low. Spec: section A3.2.1."
+  `define ERRM_WLAST_X              "AXI_ERRM_WLAST_X: When WVALID is high, a value of X on WLAST is not permitted. Spec: section A3.2.2."
+  `define ERRM_WSTRB                "AXI_ERRM_WSTRB: Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. Spec: section A3.4.3."
+  `define ERRM_WSTRB_STABLE         "AXI_ERRM_WSTRB_STABLE: WSTRB must remain stable when WVALID is asserted and WREADY low. Spec: section A3.2.1."
+  `define ERRM_WSTRB_X              "AXI_ERRM_WSTRB_X: When WVALID is high, a value of X on WSTRB is not permitted. Spec: section A3.2.2."
+  `define ERRM_WUSER_STABLE         "AXI_ERRM_WUSER_STABLE: WUSER must remain stable when WVALID is asserted and WREADY low. Spec: section A3.2.1."
+  `define ERRM_WUSER_TIEOFF         "AXI_ERRM_WUSER_TIEOFF: WUSER must be stable when WUSER_WIDTH is set to 0." 
+  `define ERRM_WUSER_X              "AXI_ERRM_WUSER_X: When WVALID is high, a value of X on WUSER is not permitted. Spec: section A3.2.2."
+  `define ERRM_WVALID_RESET         "AXI_ERRM_WVALID_RESET: The earliest point after reset that a master is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. Spec: Figure A3-1."
+  `define ERRM_WVALID_STABLE        "AXI_ERRM_WVALID_STABLE: Once WVALID is asserted, it must remain asserted until WREADY is high. Spec: section A3.2.2."
+  `define ERRM_WVALID_X             "AXI_ERRM_WVALID_X: When not in reset, a value of X on WVALID is not permitted. Spec: section A3.2.2."
+  `define ERRS_ARREADY_X            "AXI_ERRS_ARREADY_X: When not in reset, a value of X on ARREADY is not permitted. Spec: section A3.1.2."
+  `define ERRS_AWREADY_X            "AXI_ERRS_AWREADY_X: When not in reset, a value of X on AWREADY is not permitted. Spec: section A3.1.2."
+  `define ERRS_AXI4LITE_BRESP_EXOKAY   "AXI4LITE_ERRS_BRESP_EXOKAY: A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section B1.1.1."
+  `define ERRS_AXI4LITE_RRESP_EXOKAY   "AXI4LITE_ERRS_RRESP_EXOKAY: A slave must not give an EXOKAY response on an Axi4Lite interface. Spec: section B1.1.1."
+  `define ERRS_BID_STABLE           "AXI_ERRS_BID_STABLE: BID must remain stable when BVALID is asserted and BREADY low. Spec: section A3.2.1."
+  `define ERRS_BID_TIEOFF           "AXI_ERRS_BID_TIEOFF: BID must be stable when ID_WIDTH is set to 0." 
+  `define ERRS_BID_X                "AXI_ERRS_BID_X: When BVALID is high, a value of X on BID is not permitted. Spec: section A3.2.2."
+  `define ERRS_BRESP_ALL_DONE_EOS   "AXI_ERRS_BRESP_ALL_DONE_EOS: All write transaction addresses must have been matched with corresponding write response."
+  `define ERRS_BRESP_AW             "AXI_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7."
+  `define ERRS_BRESP_EXOKAY         "AXI_ERRS_BRESP_EXOKAY: An EXOKAY write response can only be given to an exclusive write access. Spec: section A7.2."
+  `define ERRS_BRESP_STABLE         "AXI_ERRS_BRESP_STABLE: BRESP must remain stable when BVALID is asserted and BREADY low. Spec: section A3.2.1."
+  `define ERRS_BRESP_WLAST          "AXI_ERRS_BRESP_WLAST: A slave must only give a write response after the last write data item is transferred. Spec: section A3.3.1 and figure A3-7."
+  `define ERRS_BRESP_X              "AXI_ERRS_BRESP_X: When BVALID is high, a value of X on BRESP is not permitted.  Spec: section A3.2.2."
+  `define ERRS_BUSER_STABLE         "AXI_ERRS_BUSER_STABLE: BUSER must remain stable when BVALID is asserted and BREADY low. Spec: section A3.2.1."
+  `define ERRS_BUSER_TIEOFF         "AXI_ERRS_BUSER_TIEOFF: BUSER must be stable when BUSER_WIDTH is set to 0." 
+  `define ERRS_BUSER_X              "AXI_ERRS_BUSER_X: When BVALID is high, a value of X on BUSER is not permitted. Spec: section A3.2.2."
+  `define ERRS_BVALID_RESET         "AXI_ERRS_BVALID_RESET: The earliest point after reset that a master is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. Spec: Figure A3-1."
+  `define ERRS_BVALID_STABLE        "AXI_ERRS_BVALID_STABLE: Once BVALID is asserted, it must remain asserted until BREADY is high. Spec: section A3.2.2."
+  `define ERRS_BVALID_X             "AXI_ERRS_BVALID_X: When not in reset, a value of X on BVALID is not permitted. Spec: section A3.2.2."
+  `define ERRS_RDATA_NUM            "AXI_ERRS_RDATA_NUM: The number of read data items must match the corresponding ARLEN. Spec: section A3.4.1."
+  `define ERRS_RDATA_STABLE         "AXI_ERRS_RDATA_STABLE: RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1."
+  `define ERRS_RDATA_X              "AXI_ERRS_RDATA_X: When RVALID is high, a value of X on RDATA valid byte lanes is not permitted. Spec: section A3.2.2."
+  `define ERRS_RID                  "AXI_ERRS_RID: A slave can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1."
+  `define ERRS_RID_STABLE           "AXI_ERRS_RID_STABLE: RID must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1."
+  `define ERRS_RID_TIEOFF           "AXI_ERRS_RID_TIEOFF: RID must be stable when ID_WIDTH is set to 0." 
+  `define ERRS_RID_X                "AXI_ERRS_RID_X: When RVALID is high, a value of X on RID is not permitted. Spec: section A3.2.2."
+  `define ERRS_RLAST_ALL_DONE_EOS   "AXI_ERRS_RLAST_ALL_DONE_EOS: All outstanding read bursts must have completed a the end of the simulation."
+  `define ERRS_RLAST_STABLE         "AXI_ERRS_RLAST_STABLE: RLAST must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1."
+  `define ERRS_RLAST_X              "AXI_ERRS_RLAST_X: When RVALID is high, a value of X on RLAST is not permitted. Spec: section A3.2.2."
+  `define ERRS_RRESP_EXOKAY         "AXI_ERRS_RRESP_EXOKAY: An EXOKAY read response can only be given to an exclusive read access. Spec: section A7.2.3."
+  `define ERRS_RRESP_STABLE         "AXI_ERRS_RRESP_STABLE: RRESP must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1."
+  `define ERRS_RRESP_X              "AXI_ERRS_RRESP_X: When RVALID is high, a value of X on RRESP is not permitted. Spec: section A3.2.2."
+  `define ERRS_RUSER_STABLE         "AXI_ERRS_RUSER_STABLE: RUSER must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1."
+  `define ERRS_RUSER_TIEOFF         "AXI_ERRS_RUSER_TIEOFF: RUSER must be stable when RUSER_WIDTH is set to 0." 
+  `define ERRS_RUSER_X              "AXI_ERRS_RUSER_X: When RVALID is high, a value of X on RUSER is not permitted.  Spec: section A3.2.2."
+  `define ERRS_RVALID_RESET         "AXI_ERRS_RVALID_RESET: The earliest point after reset that a master is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. Spec: Figure A3-1."
+  `define ERRS_RVALID_STABLE        "AXI_ERRS_RVALID_STABLE: Once RVALID is asserted, it must remain asserted until RREADY is high. Spec: section A3.2.1."
+  `define ERRS_RVALID_X             "AXI_ERRS_RVALID_X: When not in reset, a value of X on RVALID is not permitted. Spec: section A3.1.2."
+  `define ERRS_WREADY_X             "AXI_ERRS_WREADY_X: When not in reset, a value of X on WREADY is not permitted. Spec: section A3.2.2."
+  `define RECM_BREADY_MAX_WAIT      "AXI_RECM_BREADY_MAX_WAIT: BREADY should be asserted within MAXWAITS cycles of BVALID being asserted."
+  `define RECM_EXCL_MATCH           "AXI_RECM_EXCL_MATCH: The address payload of an exclusive write should be the same as the preceding exclusive read with the same ID. Spec: section A7.2.4."
+  `define RECM_EXCL_PAIR            "AXI_RECM_EXCL_PAIR: An exclusive write should have an earlier outstanding completed exclusive read with the same ID. Spec: section A7.2.2."
+  `define RECM_RREADY_MAX_WAIT      "AXI_RECM_RREADY_MAX_WAIT. RREADY should be asserted within MAXWAITS cycles of RVALID being asserted."
+  `define RECS_ARREADY_MAX_WAIT     "AXI_RECS_ARREADY_MAX_WAIT. ARREADY should be asserted within MAXWAITS cycles of ARVALID being asserted."
+  `define RECS_AWREADY_MAX_WAIT     "AXI_RECS_AWREADY_MAX_WAIT. AWREADY should be asserted within MAXWAITS cycles of AWVALID being asserted."
+  `define RECS_WREADY_MAX_WAIT      "AXI_RECS_WREADY_MAX_WAIT. WREADY should be asserted within MAXWAITS cycles of WVALID being asserted."
+  `define XILINX_ARREADY_RESET               "XILINX_ARREADY_RESET. ARREADY must be low for the first clock edge that ARESETn goes high."
+  `define XILINX_AR_MAX_BURST                "XILINX_AR_MAX_BURST. AR MASTER has issued a burst longer than the declared MAXIMUM."
+  `define XILINX_AR_SUPPORTS_NARROW_BURST    "XILINX_AR_SUPPORTS_NARROW_BURST. AR Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts."
+  `define XILINX_AR_SUPPORTS_NARROW_CACHE    "XILINX_AR_SUPPORTS_NARROW_CACHE. AR Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts."
+  `define XILINX_AWREADY_RESET               "XILINX_AWREADY_RESET. AWREADY must be low for the first clock edge that ARESETn goes high."
+  `define XILINX_AW_MAX_BURST                "XILINX_AW_MAX_BURST. AW MASTER has issued a burst longer than the declared MAXIMUM."
+  `define XILINX_AW_SUPPORTS_NARROW_BURST    "XILINX_AW_SUPPORTS_NARROW_BURST. AW Narrow burst issued from MASTER. Connection has been declared to NOT support narrow bursts."
+  `define XILINX_AW_SUPPORTS_NARROW_CACHE    "XILINX_AW_SUPPORTS_NARROW_CACHE. AW Non-modifiable burst issued from MASTER. Connection has been declared to NOT support narrow bursts."
+  `define XILINX_BREADY_RESET                "XILINX_BREADY_RESET. BREADY must be low for the first clock edge that ARESETn goes high."
+  `define XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT  "XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT. WVALID should be asserted within MAXWAITS cycles of either AW command transfer or previous W transfer while there are outstanding AW commands."
+  `define XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT       "XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT. AWVALID should be asserted within MAXWAITS cycles of WLAST transfer or previous AW transfer if there are yet more WLAST transfers outstanding."
+  `define XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT  "XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT. RVALID should be asserted within MAXWAITS cycles of either AR command transfer or previous R transfer while there are outstanding AR commands."
+  `define XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT        "XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT. BVALID should be asserted within MAXWAITS cycles of AW command transfer or WLAST transfer (whichever is later), or previous B transfer if there are yet more AW and WLAST transfers outstanding."
+  `define XILINX_RREADY_RESET                "XILINX_RREADY_RESET. RREADY must be low for the first clock edge that ARESETn goes high."
+  `define XILINX_WREADY_RESET                "XILINX_WREADY_RESET. WREADY must be low for the first clock edge that ARESETn goes high."
+  `define XILINX_ARESETN_PULSE_WIDTH  "XILINX_ARESETN_PULSE_WIDTH. ARESETn must be low for atleast 16 ACLKn cycles."
+  `define XILINX_AXI4_ERRM_NO_STRB_ADDRESS "XILINX_AXI4_ERRM_NO_STRB_ADDRESS. When there is no WSTRB, address must be aligned with data width"
+  `define XILINX_AXI4_ERRM_SUPPORTS_NARROW_BURST_SIZE "XILINX_AXI4_ERRM_SUPPORTS_NARROW_BURST_SIZE. When there is support narrow burst along with WSTRB, then AWSIZE has to be greater than or equal to data width"
+`endif
+
+`define REPORTER_MACRO(ERR_BIT, NET_NAME, MSG_TEXT, SEV_NUM) \
+  always@(posedge NET_NAME) begin \
+    if ((SEV_NUM != 0) && (NET_NAME === 1'b1)) begin \
+      $display("%t : %m : BIT(%d) : %s : %s", $time, ERR_BIT, (SEV_NUM == 0) ? "INFO" : (SEV_NUM == 1) ? "WARNING" : "ERROR" , MSG_TEXT); \
+      if (SEV_NUM == 3) $stop;\
+      if (SEV_NUM == 4) $finish;\
+    end else if ((NET_NAME !== 1'b1) && (NET_NAME !== 1'b0)) begin \
+      $display("%t : %m : BIT(%d) :   ERROR : Invalid state %b", $time, ERR_BIT, NET_NAME); \
+    end \
+  end
+
+`define REPORT_XCHECK(MSG,SEV_NUM) \
+      if(SEV_NUM == 1) $info(MSG); \
+      else if (SEV_NUM == 2) $warning(MSG); \
+      else if (SEV_NUM == 3) $error(MSG); \
+      else if (SEV_NUM == 4) $fatal(1,MSG); \
+
+
+
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_reporter #(
+  parameter integer C_PC_MESSAGE_LEVEL             = 2,
+  parameter integer C_PC_STATUS_WIDTH              = 104,
+  parameter integer C_AXI_PROTOCOL                 = 0,
+  parameter integer C_AXI_ID_WIDTH                 = 1,
+  parameter integer C_AXI_DATA_WIDTH               = 32,
+  parameter integer C_AXI_ADDR_WIDTH               = 32,
+  parameter integer C_AXI_AWUSER_WIDTH             = 1,
+  parameter integer C_AXI_WUSER_WIDTH              = 1,
+  parameter integer C_AXI_BUSER_WIDTH              = 1,
+  parameter integer C_AXI_ARUSER_WIDTH             = 1,
+  parameter integer C_AXI_RUSER_WIDTH              = 1,
+  parameter integer C_PC_MAXRBURSTS                = 8,
+  parameter integer C_PC_MAXWBURSTS                = 8,
+  parameter integer C_ENABLE_MARK_DEBUG            = 1
+) (
+  input  wire                             aclk,
+  input  wire [C_PC_STATUS_WIDTH-1:0]     pc_status,
+  ///
+  input wire                                        ARST_N,
+  input wire [C_AXI_ID_WIDTH-1:0]                   AWID,
+  input wire [C_AXI_ADDR_WIDTH-1:0]                 AWADDR,
+  input wire [7:0]                                  AWLEN,
+  input wire [2:0]                                  AWSIZE,
+  input wire [1:0]                                  AWBURST,
+  input wire [0:0]                                  AWLOCK,
+  input wire [3:0]                                  AWCACHE,
+  input wire [2:0]                                  AWPROT,
+  input wire [3:0]                                  AWQOS,
+  input wire [3:0]                                  AWREGION,
+  input wire [C_AXI_AWUSER_WIDTH-1:0]               AWUSER,
+  input wire                                        AWVALID,
+  input wire                                        AWREADY,
+  input wire                                        WLAST,
+  input wire [C_AXI_DATA_WIDTH-1:0]                 WDATA,
+  input wire [C_AXI_DATA_WIDTH/8-1:0]               WSTRB,
+  input wire [C_AXI_WUSER_WIDTH-1:0]                WUSER,
+  input wire                                        WVALID,
+  input wire                                        WREADY,
+  input wire [C_AXI_ID_WIDTH-1:0]                   BID,
+  input wire [1:0]                                  BRESP,
+  input wire [C_AXI_BUSER_WIDTH-1:0]                BUSER,
+  input wire                                        BVALID,
+  input wire                                        BREADY,
+  input wire [C_AXI_ID_WIDTH-1:0]                   ARID,
+  input wire [C_AXI_ADDR_WIDTH-1:0]                 ARADDR,
+  input wire [7:0]                                  ARLEN,
+  input wire [2:0]                                  ARSIZE,
+  input wire [1:0]                                  ARBURST,
+  input wire [0:0]                                  ARLOCK,
+  input wire [3:0]                                  ARCACHE,
+  input wire [2:0]                                  ARPROT,
+  input wire [3:0]                                  ARQOS,
+  input wire [3:0]                                  ARREGION,
+  input wire [C_AXI_ARUSER_WIDTH-1:0]               ARUSER,
+  input wire                                        ARVALID,
+  input wire                                        ARREADY,
+  input wire [C_AXI_ID_WIDTH-1:0]                   RID,
+  input wire                                        RLAST,
+  input wire [C_AXI_DATA_WIDTH-1:0]                 RDATA,
+  input wire [1:0]                                  RRESP,
+  input wire [C_AXI_RUSER_WIDTH-1:0]                RUSER,
+  input wire                                        RVALID,
+  input wire                                        RREADY
+);
+
+`define ASSIGN_MARKED_DEBUG(ERR_BIT, DISPLAY_NETNAME) \
+  reg DISPLAY_NETNAME;\
+  always@(posedge aclk) DISPLAY_NETNAME <= pc_status[ERR_BIT];
+
+ typedef struct packed {
+   bit [7-1:0]     addr;
+   bit             excl;
+   bit [8-1:0]     len ;
+   bit [3-1:0]     size;
+   bit [2-1:0]     burst;
+   bit [C_AXI_ID_WIDTH-1:0]  id;
+ } t_cmd_message;
+
+  // Read CAMs
+  typedef struct packed {
+    t_cmd_message       cmd;
+    bit          [8:0]  Count;
+  } t_rburst_xfer;
+  
+  t_rburst_xfer RCam[0:C_PC_MAXRBURSTS];
+
+ reg  [C_AXI_DATA_WIDTH-1:0] WdataMask;
+ wire [C_AXI_DATA_WIDTH-1:0] RdataMask;
+
+  integer unsigned   RIndex = 1;
+  integer unsigned   RIndexNext = 1;
+  integer unsigned   RidMatch;
+  wire               RPop;
+  wire               RPush;
+  wire               nROutstanding;  // flag for an empty cmd
+  reg                RIdCamDelta;    // flag indicates that RidCam has changed
+
+  wire ACLKEN = 1;
+
+
+`ASSIGN_MARKED_DEBUG(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          )
+`ASSIGN_MARKED_DEBUG(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        )
+`ASSIGN_MARKED_DEBUG(02, PC_02_AXI_ERRM_AWBURST                  )
+`ASSIGN_MARKED_DEBUG(03, PC_03_AXI_ERRM_AWLEN_LOCK               )
+`ASSIGN_MARKED_DEBUG(04, PC_04_AXI_ERRM_AWCACHE                  )
+`ASSIGN_MARKED_DEBUG(05, PC_05_AXI_ERRM_AWLEN_FIXED              )
+`ASSIGN_MARKED_DEBUG(06, PC_06_AXI_ERRM_AWLEN_WRAP               )
+`ASSIGN_MARKED_DEBUG(07, PC_07_AXI_ERRM_AWSIZE                   )
+`ASSIGN_MARKED_DEBUG(08, PC_08_AXI_ERRM_AWVALID_RESET            )
+`ASSIGN_MARKED_DEBUG(09, PC_09_AXI_ERRM_AWADDR_STABLE            )
+`ASSIGN_MARKED_DEBUG(10, PC_10_AXI_ERRM_AWBURST_STABLE           )
+`ASSIGN_MARKED_DEBUG(11, PC_11_AXI_ERRM_AWCACHE_STABLE           )
+`ASSIGN_MARKED_DEBUG(12, PC_12_AXI_ERRM_AWID_STABLE              )
+`ASSIGN_MARKED_DEBUG(13, PC_13_AXI_ERRM_AWLEN_STABLE             )
+`ASSIGN_MARKED_DEBUG(14, PC_14_AXI_ERRM_AWLOCK_STABLE            )
+`ASSIGN_MARKED_DEBUG(15, PC_15_AXI_ERRM_AWPROT_STABLE            )
+`ASSIGN_MARKED_DEBUG(16, PC_16_AXI_ERRM_AWSIZE_STABLE            )
+`ASSIGN_MARKED_DEBUG(17, PC_17_AXI_ERRM_AWQOS_STABLE             )
+`ASSIGN_MARKED_DEBUG(18, PC_18_AXI_ERRM_AWREGION_STABLE          )
+`ASSIGN_MARKED_DEBUG(19, PC_19_AXI_ERRM_AWVALID_STABLE           )
+`ASSIGN_MARKED_DEBUG(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         )
+`ASSIGN_MARKED_DEBUG(21, PC_21_AXI_ERRM_WDATA_NUM                )
+`ASSIGN_MARKED_DEBUG(22, PC_22_AXI_ERRM_WSTRB                    )
+`ASSIGN_MARKED_DEBUG(23, PC_23_AXI_ERRM_WVALID_RESET             )
+`ASSIGN_MARKED_DEBUG(24, PC_24_AXI_ERRM_WDATA_STABLE             )
+`ASSIGN_MARKED_DEBUG(25, PC_25_AXI_ERRM_WLAST_STABLE             )
+`ASSIGN_MARKED_DEBUG(26, PC_26_AXI_ERRM_WSTRB_STABLE             )
+`ASSIGN_MARKED_DEBUG(27, PC_27_AXI_ERRM_WVALID_STABLE            )
+`ASSIGN_MARKED_DEBUG(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          )
+`ASSIGN_MARKED_DEBUG(29, PC_29_AXI_ERRS_BRESP_WLAST              )
+`ASSIGN_MARKED_DEBUG(30, PC_30_AXI_ERRS_BRESP_EXOKAY             )
+`ASSIGN_MARKED_DEBUG(31, PC_31_AXI_ERRS_BVALID_RESET             )
+`ASSIGN_MARKED_DEBUG(32, PC_32_AXI_ERRS_BRESP_AW                 )
+`ASSIGN_MARKED_DEBUG(33, PC_33_AXI_ERRS_BID_STABLE               )
+`ASSIGN_MARKED_DEBUG(34, PC_34_AXI_ERRS_BRESP_STABLE             )
+`ASSIGN_MARKED_DEBUG(35, PC_35_AXI_ERRS_BVALID_STABLE            )
+`ASSIGN_MARKED_DEBUG(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          )
+`ASSIGN_MARKED_DEBUG(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          )
+`ASSIGN_MARKED_DEBUG(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        )
+`ASSIGN_MARKED_DEBUG(39, PC_39_AXI_ERRM_ARBURST                  )
+`ASSIGN_MARKED_DEBUG(40, PC_40_AXI_ERRM_ARLEN_LOCK               )
+`ASSIGN_MARKED_DEBUG(41, PC_41_AXI_ERRM_ARCACHE                  )
+`ASSIGN_MARKED_DEBUG(42, PC_42_AXI_ERRM_ARLEN_FIXED              )
+`ASSIGN_MARKED_DEBUG(43, PC_43_AXI_ERRM_ARLEN_WRAP               )
+`ASSIGN_MARKED_DEBUG(44, PC_44_AXI_ERRM_ARSIZE                   )
+`ASSIGN_MARKED_DEBUG(45, PC_45_AXI_ERRM_ARVALID_RESET            )
+`ASSIGN_MARKED_DEBUG(46, PC_46_AXI_ERRM_ARADDR_STABLE            )
+`ASSIGN_MARKED_DEBUG(47, PC_47_AXI_ERRM_ARBURST_STABLE           )
+`ASSIGN_MARKED_DEBUG(48, PC_48_AXI_ERRM_ARCACHE_STABLE           )
+`ASSIGN_MARKED_DEBUG(49, PC_49_AXI_ERRM_ARID_STABLE              )
+`ASSIGN_MARKED_DEBUG(50, PC_50_AXI_ERRM_ARLEN_STABLE             )
+`ASSIGN_MARKED_DEBUG(51, PC_51_AXI_ERRM_ARLOCK_STABLE            )
+`ASSIGN_MARKED_DEBUG(52, PC_52_AXI_ERRM_ARPROT_STABLE            )
+`ASSIGN_MARKED_DEBUG(53, PC_53_AXI_ERRM_ARSIZE_STABLE            )
+`ASSIGN_MARKED_DEBUG(54, PC_54_AXI_ERRM_ARQOS_STABLE             )
+`ASSIGN_MARKED_DEBUG(55, PC_55_AXI_ERRM_ARREGION_STABLE          )
+`ASSIGN_MARKED_DEBUG(56, PC_56_AXI_ERRM_ARVALID_STABLE           )
+`ASSIGN_MARKED_DEBUG(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         )
+`ASSIGN_MARKED_DEBUG(58, PC_58_AXI_ERRS_RDATA_NUM                )
+`ASSIGN_MARKED_DEBUG(59, PC_59_AXI_ERRS_RID                      )
+`ASSIGN_MARKED_DEBUG(60, PC_60_AXI_ERRS_RRESP_EXOKAY             )
+`ASSIGN_MARKED_DEBUG(61, PC_61_AXI_ERRS_RVALID_RESET             )
+`ASSIGN_MARKED_DEBUG(62, PC_62_AXI_ERRS_RDATA_STABLE             )
+`ASSIGN_MARKED_DEBUG(63, PC_63_AXI_ERRS_RID_STABLE               )
+`ASSIGN_MARKED_DEBUG(64, PC_64_AXI_ERRS_RLAST_STABLE             )
+`ASSIGN_MARKED_DEBUG(65, PC_65_AXI_ERRS_RRESP_STABLE             )
+`ASSIGN_MARKED_DEBUG(66, PC_66_AXI_ERRS_RVALID_STABLE            )
+`ASSIGN_MARKED_DEBUG(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          )
+`ASSIGN_MARKED_DEBUG(68, PC_68_AXI_ERRM_EXCL_ALIGN               )
+`ASSIGN_MARKED_DEBUG(69, PC_69_AXI_ERRM_EXCL_LEN                 )
+`ASSIGN_MARKED_DEBUG(70, PC_70_AXI_RECM_EXCL_MATCH               )
+`ASSIGN_MARKED_DEBUG(71, PC_71_AXI_ERRM_EXCL_MAX                 )
+`ASSIGN_MARKED_DEBUG(72, PC_72_AXI_RECM_EXCL_PAIR                )
+`ASSIGN_MARKED_DEBUG(73, PC_73_AXI_ERRM_AWUSER_STABLE            )
+`ASSIGN_MARKED_DEBUG(74, PC_74_AXI_ERRM_WUSER_STABLE             )
+`ASSIGN_MARKED_DEBUG(75, PC_75_AXI_ERRS_BUSER_STABLE             )
+`ASSIGN_MARKED_DEBUG(76, PC_76_AXI_ERRM_ARUSER_STABLE            )
+`ASSIGN_MARKED_DEBUG(77, PC_77_AXI_ERRS_RUSER_STABLE             )
+`ASSIGN_MARKED_DEBUG(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            )
+`ASSIGN_MARKED_DEBUG(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           )
+`ASSIGN_MARKED_DEBUG(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            )
+`ASSIGN_MARKED_DEBUG(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           )
+`ASSIGN_MARKED_DEBUG(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            )
+`ASSIGN_MARKED_DEBUG(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        )
+`ASSIGN_MARKED_DEBUG(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        )
+`ASSIGN_MARKED_DEBUG(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          )
+`ASSIGN_MARKED_DEBUG(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   )
+`ASSIGN_MARKED_DEBUG(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   )
+`ASSIGN_MARKED_DEBUG(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   )
+`ASSIGN_MARKED_DEBUG(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   )
+`ASSIGN_MARKED_DEBUG(90, PC_90_XILINX_AW_MAX_BURST               )
+`ASSIGN_MARKED_DEBUG(91, PC_91_XILINX_AR_MAX_BURST               )
+`ASSIGN_MARKED_DEBUG(92, PC_92_XILINX_AWREADY_RESET              )
+`ASSIGN_MARKED_DEBUG(93, PC_93_XILINX_WREADY_RESET               )
+`ASSIGN_MARKED_DEBUG(94, PC_94_XILINX_BREADY_RESET               )
+`ASSIGN_MARKED_DEBUG(95, PC_95_XILINX_ARREADY_RESET              )
+`ASSIGN_MARKED_DEBUG(96, PC_96_XILINX_RREADY_RESET               )
+`ASSIGN_MARKED_DEBUG(97, PC_97_XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT               )
+`ASSIGN_MARKED_DEBUG(98, PC_98_XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT               )
+`ASSIGN_MARKED_DEBUG(99, PC_99_XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT               )
+`ASSIGN_MARKED_DEBUG(100, PC_100_XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT               )
+`ASSIGN_MARKED_DEBUG(101, PC_101_XILINX_ARESETN_PULSE_WIDTH      )
+`ASSIGN_MARKED_DEBUG(102, PC_102_XILINX_AXI4_ERRM_NO_STRB_ADDRESS      )
+`ASSIGN_MARKED_DEBUG(103, PC_103_XILINX_AXI4_ERRM_NO_SUPPORTS_NARROW_LENGTH_SIZE )
+
+// synthesis translate_off
+
+  // INDEX:        - ByteCount
+  // =====
+  // Inputs: Burst (Burst data structure)
+  //         Beat  (Data beat number)
+  // Returns: Byte Count of valid byte lanes.
+  //----------------------------------------------------------------------------
+  function [7:0] ByteCount;
+    input t_cmd_message Burst;         // burst vector
+    input [9:0]        Beat;           // beat number in the burst (1-256)
+    reg   [6:0]        axaddr;
+    reg   [2:0]        axsize;
+    reg   [7:0]        axlen;
+    reg   [1:0]        axburst;
+    integer bus_data_bytes;
+    integer unaligned_byte_shift;
+  begin
+    axaddr  = Burst.addr;
+    axsize  = Burst.size;
+    axlen   = Burst.len;
+    axburst = Burst.burst;
+
+    bus_data_bytes = C_AXI_DATA_WIDTH/8;
+
+    // Number of bytes that the data needs to be shifted when
+    // the address is unaligned
+    unaligned_byte_shift =
+      axaddr &              // Byte address
+      ((1<>axsize;
+
+    // The address may increment with each beat. The increment will be zero
+    // for a FIXED burst.
+    addr_trans_bus_inc = addr_trans_bus + beat_addr_inc;
+
+    // Modify the byte shift for wrapping bursts
+    if (axburst == 2)
+    begin
+      // The upper address of the transfer before wrapping
+      wrap_point = length + (addr_trans_bus & ~(length - 1));
+      // If adding the beat number to the transfer address causes it to
+      // pass the upper wrap address then wrap to the lower address.
+      if (addr_trans_bus_inc >= wrap_point)
+      begin
+        addr_trans_bus_inc = addr_trans_bus_inc - length;
+      end
+    end
+
+    // Address calculation may exceed the number of transfers that can fit
+    // in the data bus for INCR bursts. So the calculation is truncated to
+    // make the byte shift wrap round to zero. 
+    addr_trans_bus_inc = addr_trans_bus_inc & ((bus_data_bytes-1)>>axsize);
+
+    // Number of bytes that the data needs to be shifted when
+    // the transfer size is less than the data bus width
+    transfer_byte_shift = (1<= RidMatch)
+          begin
+              RCam[i].cmd <= RCam[i+1].cmd;
+              RCam[i].Count <= RCam[i+1].Count;
+              RIdCamDelta  <= ~RIdCamDelta;
+          end //for (i=1; i ! $isunknown(AWADDR);
+  endproperty
+  axi4_errm_awaddr_x: assert property (AXI4_ERRM_AWADDR_X) else
+   `REPORT_XCHECK(`ERRM_AWADDR_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWBURST_X
+  // =====
+  property AXI4_ERRM_AWBURST_X;
+    @(posedge aclk) ARST_N & AWVALID  |-> ! $isunknown(AWBURST);
+  endproperty
+  axi4_errm_awburst_x: assert property (AXI4_ERRM_AWBURST_X) else
+   `REPORT_XCHECK(`ERRM_AWBURST_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWCACHE_X
+  // =====
+  property AXI4_ERRM_AWCACHE_X;
+    @(posedge aclk) ARST_N & AWVALID  |-> ! $isunknown(AWCACHE);
+  endproperty
+  axi4_errm_awcache_x: assert property (AXI4_ERRM_AWCACHE_X) else
+   `REPORT_XCHECK(`ERRM_AWCACHE_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWID_X
+  // =====
+  property AXI4_ERRM_AWID_X;
+    @(posedge aclk) ARST_N & AWVALID |-> ! $isunknown(AWID);
+  endproperty
+  axi4_errm_awid_x: assert property (AXI4_ERRM_AWID_X) else
+   `REPORT_XCHECK(`ERRM_AWID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWLEN_X
+  // =====
+  property AXI4_ERRM_AWLEN_X;
+    @(posedge aclk) ARST_N & AWVALID  |-> ! $isunknown(AWLEN);
+  endproperty
+  axi4_errm_awlen_x: assert property (AXI4_ERRM_AWLEN_X) else
+   `REPORT_XCHECK(`ERRM_AWLEN_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWLOCK_X
+  // =====
+  property AXI4_ERRM_AWLOCK_X;
+    @(posedge aclk) ARST_N & AWVALID |-> ! $isunknown(AWLOCK);
+  endproperty
+  axi4_errm_awlock_x: assert property (AXI4_ERRM_AWLOCK_X) else
+   `REPORT_XCHECK(`ERRM_AWLOCK_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWPROT_X
+  // =====
+  property AXI4_ERRM_AWPROT_X;
+    @(posedge aclk) ARST_N & AWVALID |-> ! $isunknown(AWPROT);
+  endproperty
+  axi4_errm_awprot_x: assert property (AXI4_ERRM_AWPROT_X) else
+   `REPORT_XCHECK(`ERRM_AWPROT_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWSIZE_X
+  // =====
+  property AXI4_ERRM_AWSIZE_X;
+    @(posedge aclk) ARST_N & AWVALID |-> ! $isunknown(AWSIZE);
+  endproperty
+  axi4_errm_awsize_x: assert property (AXI4_ERRM_AWSIZE_X) else
+   `REPORT_XCHECK(`ERRM_AWSIZE_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWQOS_X
+  // =====
+  property AXI4_ERRM_AWQOS_X;
+    @(posedge aclk) ARST_N & AWVALID |-> ! $isunknown(AWQOS);
+  endproperty
+  axi4_errm_awqos_x: assert property (AXI4_ERRM_AWQOS_X) else
+   `REPORT_XCHECK(`ERRM_AWQOS_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWREGION_X
+  // =====
+  property AXI4_ERRM_AWREGION_X;
+    @(posedge aclk) 
+      ARST_N & AWVALID
+      |-> ! $isunknown(AWREGION);
+  endproperty
+  axi4_errm_awregion_x: assert property (AXI4_ERRM_AWREGION_X) else
+   `REPORT_XCHECK(`ERRM_AWREGION_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_AWVALID_X
+  // =====
+  property AXI4_ERRM_AWVALID_X;
+    @(posedge aclk) ARST_N |-> ! $isunknown(AWVALID);
+  endproperty
+  axi4_errm_awvalid_x: assert property (AXI4_ERRM_AWVALID_X) else
+   `REPORT_XCHECK(`ERRM_AWVALID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_AWREADY_X
+  // =====
+  property AXI4_ERRS_AWREADY_X;
+    @(posedge aclk) ARST_N |-> ! $isunknown(AWREADY);
+  endproperty
+  axi4_errs_awready_x: assert property (AXI4_ERRS_AWREADY_X) else
+   `REPORT_XCHECK(`ERRS_AWREADY_X,C_PC_MESSAGE_LEVEL)
+
+
+
+
+  // INDEX:        - AXI4_ERRM_WDATA_X
+  // =====
+  property AXI4_ERRM_WDATA_X;
+    @(posedge aclk)
+      ARST_N & WVALID & !($isunknown(WdataMask))
+      |-> ! $isunknown(WDATA & WdataMask);
+  endproperty
+  axi4_errm_wdata_x: assert property (AXI4_ERRM_WDATA_X) else
+   `REPORT_XCHECK(`ERRM_WDATA_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_WLAST_X
+  // =====
+  property AXI4_ERRM_WLAST_X;
+    @(posedge aclk)
+      ARST_N & WVALID
+      |-> ! $isunknown(WLAST);
+  endproperty
+  axi4_errm_wlast_x: assert property (AXI4_ERRM_WLAST_X) else
+   `REPORT_XCHECK(`ERRM_WLAST_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_WSTRB_X
+  // =====
+  property AXI4_ERRM_WSTRB_X;
+    @(posedge aclk)
+      ARST_N & WVALID
+      |-> ! $isunknown(WSTRB);
+  endproperty
+  axi4_errm_wstrb_x: assert property (AXI4_ERRM_WSTRB_X) else
+   `REPORT_XCHECK(`ERRM_WSTRB_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_WVALID_X
+  // =====
+  property AXI4_ERRM_WVALID_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(WVALID);
+  endproperty
+  axi4_errm_wvalid_x: assert property (AXI4_ERRM_WVALID_X) else
+   `REPORT_XCHECK(`ERRM_WVALID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_WREADY_X
+  // =====
+  property AXI4_ERRS_WREADY_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(WREADY);
+  endproperty
+  axi4_errs_wready_x: assert property (AXI4_ERRS_WREADY_X) else
+   `REPORT_XCHECK(`ERRS_WREADY_X,C_PC_MESSAGE_LEVEL)
+
+
+
+  // INDEX:        - AXI4_ERRM_BREADY_X
+  // =====
+  property AXI4_ERRM_BREADY_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(BREADY);
+  endproperty
+  axi4_errm_bready_x: assert property (AXI4_ERRM_BREADY_X) else
+   `REPORT_XCHECK(`ERRM_BREADY_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_BID_X
+  // =====
+  property AXI4_ERRS_BID_X;
+    @(posedge aclk) 
+      ARST_N & BVALID
+      |-> ! $isunknown(BID);
+  endproperty
+  axi4_errs_bid_x: assert property (AXI4_ERRS_BID_X) else
+   `REPORT_XCHECK(`ERRS_BID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_BRESP_X
+  // =====
+  property AXI4_ERRS_BRESP_X;
+    @(posedge aclk) 
+      ARST_N & BVALID
+      |-> ! $isunknown(BRESP);
+  endproperty
+  axi4_errs_bresp_x: assert property (AXI4_ERRS_BRESP_X) else
+   `REPORT_XCHECK(`ERRS_BRESP_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_BVALID_X
+  // =====
+  property AXI4_ERRS_BVALID_X;
+    @(posedge aclk) 
+      ARST_N
+      |-> ! $isunknown(BVALID);
+  endproperty
+  axi4_errs_bvalid_x: assert property (AXI4_ERRS_BVALID_X) else
+   `REPORT_XCHECK(`ERRS_BVALID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARADDR_X
+  // =====
+  property AXI4_ERRM_ARADDR_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARADDR);
+  endproperty
+  axi4_errm_araddr_x: assert property (AXI4_ERRM_ARADDR_X) else
+   `REPORT_XCHECK(`ERRM_ARADDR_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARBURST_X
+  // =====
+  property AXI4_ERRM_ARBURST_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARBURST);
+  endproperty
+  axi4_errm_arburst_x: assert property (AXI4_ERRM_ARBURST_X) else
+   `REPORT_XCHECK(`ERRM_ARBURST_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARCACHE_X
+  // =====
+  property AXI4_ERRM_ARCACHE_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARCACHE);
+  endproperty
+  axi4_errm_arcache_x: assert property (AXI4_ERRM_ARCACHE_X) else
+   `REPORT_XCHECK(`ERRM_ARCACHE_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARID_X
+  // =====
+  property AXI4_ERRM_ARID_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARID);
+  endproperty
+  axi4_errm_arid_x: assert property (AXI4_ERRM_ARID_X) else
+   `REPORT_XCHECK(`ERRM_ARID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARLEN_X
+  // =====
+  property AXI4_ERRM_ARLEN_X;
+    @(posedge aclk) 
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARLEN);
+  endproperty
+  axi4_errm_arlen_x: assert property (AXI4_ERRM_ARLEN_X) else
+   `REPORT_XCHECK(`ERRM_ARLEN_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARLOCK_X
+  // =====
+  property AXI4_ERRM_ARLOCK_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARLOCK);
+  endproperty
+  axi4_errm_arlock_x: assert property (AXI4_ERRM_ARLOCK_X) else
+   `REPORT_XCHECK(`ERRM_ARLOCK_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARPROT_X
+  // =====
+  property AXI4_ERRM_ARPROT_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARPROT);
+  endproperty
+  axi4_errm_arprot_x: assert property (AXI4_ERRM_ARPROT_X) else
+   `REPORT_XCHECK(`ERRM_ARPROT_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARSIZE_X
+  // =====
+  property AXI4_ERRM_ARSIZE_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARSIZE);
+  endproperty
+  axi4_errm_arsize_x: assert property (AXI4_ERRM_ARSIZE_X) else
+   `REPORT_XCHECK(`ERRM_ARSIZE_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARQOS_X
+  // =====
+  property AXI4_ERRM_ARQOS_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARQOS);
+  endproperty
+  axi4_errm_arqos_x: assert property (AXI4_ERRM_ARQOS_X) else
+   `REPORT_XCHECK(`ERRM_ARQOS_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARREGION_X
+  // =====
+  property AXI4_ERRM_ARREGION_X;
+    @(posedge aclk)
+      ARST_N & ARVALID
+      |-> ! $isunknown(ARREGION);
+  endproperty
+  axi4_errm_arregion_x: assert property (AXI4_ERRM_ARREGION_X) else
+   `REPORT_XCHECK(`ERRM_ARREGION_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_ARVALID_X
+  // =====
+  property AXI4_ERRM_ARVALID_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(ARVALID);
+  endproperty
+  axi4_errm_arvalid_x: assert property (AXI4_ERRM_ARVALID_X) else
+   `REPORT_XCHECK(`ERRM_ARVALID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_ARREADY_X
+  // =====
+  property AXI4_ERRS_ARREADY_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(ARREADY);
+  endproperty
+  axi4_errs_arready_x: assert property (AXI4_ERRS_ARREADY_X) else
+   `REPORT_XCHECK(`ERRS_ARREADY_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_RDATA_X
+  // =====
+  property AXI4_ERRS_RDATA_X;
+    @(posedge aclk)
+      ARST_N & RVALID
+      |-> ! $isunknown(RDATA | ~RdataMask);
+  endproperty
+  axi4_errs_rdata_x: assert property (AXI4_ERRS_RDATA_X) else
+    `REPORT_XCHECK(`ERRS_RDATA_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRM_RREADY_X
+  // =====
+  property AXI4_ERRM_RREADY_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(RREADY);
+  endproperty
+  axi4_errm_rready_x: assert property (AXI4_ERRM_RREADY_X) else
+   `REPORT_XCHECK(`ERRM_RREADY_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_RID_X
+  // =====
+  property AXI4_ERRS_RID_X;
+    @(posedge aclk)
+      ARST_N & RVALID
+      |-> ! $isunknown(RID);
+  endproperty
+  axi4_errs_rid_x: assert property (AXI4_ERRS_RID_X) else
+    `REPORT_XCHECK(`ERRS_RID_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_RLAST_X
+  // =====
+  property AXI4_ERRS_RLAST_X;
+    @(posedge aclk)
+      ARST_N & RVALID
+      |-> ! $isunknown(RLAST);
+  endproperty
+  axi4_errs_rlast_x: assert property (AXI4_ERRS_RLAST_X) else
+   `REPORT_XCHECK(`ERRS_RLAST_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_RRESP_X
+  // =====
+  property AXI4_ERRS_RRESP_X;
+    @(posedge aclk) 
+      ARST_N & RVALID
+      |-> ! $isunknown(RRESP);
+  endproperty
+  axi4_errs_rresp_x: assert property (AXI4_ERRS_RRESP_X) else
+   `REPORT_XCHECK(`ERRS_RRESP_X,C_PC_MESSAGE_LEVEL)
+
+
+  // INDEX:        - AXI4_ERRS_RVALID_X
+  // =====
+  property AXI4_ERRS_RVALID_X;
+    @(posedge aclk)
+      ARST_N
+      |-> ! $isunknown(RVALID);
+  endproperty
+  axi4_errs_rvalid_x: assert property (AXI4_ERRS_RVALID_X) else
+   `REPORT_XCHECK(`ERRS_RVALID_X,C_PC_MESSAGE_LEVEL)
+
+`REPORTER_MACRO(00, PC_00_AXI_ERRM_AWADDR_BOUNDARY          , `ERRM_AWADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(01, PC_01_AXI_ERRM_AWADDR_WRAP_ALIGN        , `ERRM_AWADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(02, PC_02_AXI_ERRM_AWBURST                  , `ERRM_AWBURST                  , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(03, PC_03_AXI_ERRM_AWLEN_LOCK               , `ERRM_AWLEN_LOCK               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(04, PC_04_AXI_ERRM_AWCACHE                  , `ERRM_AWCACHE                  , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(05, PC_05_AXI_ERRM_AWLEN_FIXED              , `ERRM_AWLEN_FIXED              , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(06, PC_06_AXI_ERRM_AWLEN_WRAP               , `ERRM_AWLEN_WRAP               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(07, PC_07_AXI_ERRM_AWSIZE                   , `ERRM_AWSIZE                   , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(08, PC_08_AXI_ERRM_AWVALID_RESET            , `ERRM_AWVALID_RESET            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(09, PC_09_AXI_ERRM_AWADDR_STABLE            , `ERRM_AWADDR_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(10, PC_10_AXI_ERRM_AWBURST_STABLE           , `ERRM_AWBURST_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(11, PC_11_AXI_ERRM_AWCACHE_STABLE           , `ERRM_AWCACHE_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(12, PC_12_AXI_ERRM_AWID_STABLE              , `ERRM_AWID_STABLE              , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(13, PC_13_AXI_ERRM_AWLEN_STABLE             , `ERRM_AWLEN_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(14, PC_14_AXI_ERRM_AWLOCK_STABLE            , `ERRM_AWLOCK_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(15, PC_15_AXI_ERRM_AWPROT_STABLE            , `ERRM_AWPROT_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(16, PC_16_AXI_ERRM_AWSIZE_STABLE            , `ERRM_AWSIZE_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(17, PC_17_AXI_ERRM_AWQOS_STABLE             , `ERRM_AWQOS_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(18, PC_18_AXI_ERRM_AWREGION_STABLE          , `ERRM_AWREGION_STABLE          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(19, PC_19_AXI_ERRM_AWVALID_STABLE           , `ERRM_AWVALID_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(20, PC_20_AXI_RECS_AWREADY_MAX_WAIT         , `RECS_AWREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(21, PC_21_AXI_ERRM_WDATA_NUM                , `ERRM_WDATA_NUM                , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(22, PC_22_AXI_ERRM_WSTRB                    , `ERRM_WSTRB                    , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(23, PC_23_AXI_ERRM_WVALID_RESET             , `ERRM_WVALID_RESET             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(24, PC_24_AXI_ERRM_WDATA_STABLE             , `ERRM_WDATA_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(25, PC_25_AXI_ERRM_WLAST_STABLE             , `ERRM_WLAST_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(26, PC_26_AXI_ERRM_WSTRB_STABLE             , `ERRM_WSTRB_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(27, PC_27_AXI_ERRM_WVALID_STABLE            , `ERRM_WVALID_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(28, PC_28_AXI_RECS_WREADY_MAX_WAIT          , `RECS_WREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(29, PC_29_AXI_ERRS_BRESP_WLAST              , `ERRS_BRESP_WLAST              , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(30, PC_30_AXI_ERRS_BRESP_EXOKAY             , `ERRS_BRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(31, PC_31_AXI_ERRS_BVALID_RESET             , `ERRS_BVALID_RESET             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(32, PC_32_AXI_ERRS_BRESP_AW                 , `ERRS_BRESP_AW                 , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(33, PC_33_AXI_ERRS_BID_STABLE               , `ERRS_BID_STABLE               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(34, PC_34_AXI_ERRS_BRESP_STABLE             , `ERRS_BRESP_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(35, PC_35_AXI_ERRS_BVALID_STABLE            , `ERRS_BVALID_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(36, PC_36_AXI_RECM_BREADY_MAX_WAIT          , `RECM_BREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(37, PC_37_AXI_ERRM_ARADDR_BOUNDARY          , `ERRM_ARADDR_BOUNDARY          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(38, PC_38_AXI_ERRM_ARADDR_WRAP_ALIGN        , `ERRM_ARADDR_WRAP_ALIGN        , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(39, PC_39_AXI_ERRM_ARBURST                  , `ERRM_ARBURST                  , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(40, PC_40_AXI_ERRM_ARLEN_LOCK               , `ERRM_ARLEN_LOCK               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(41, PC_41_AXI_ERRM_ARCACHE                  , `ERRM_ARCACHE                  , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(42, PC_42_AXI_ERRM_ARLEN_FIXED              , `ERRM_ARLEN_FIXED              , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(43, PC_43_AXI_ERRM_ARLEN_WRAP               , `ERRM_ARLEN_WRAP               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(44, PC_44_AXI_ERRM_ARSIZE                   , `ERRM_ARSIZE                   , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(45, PC_45_AXI_ERRM_ARVALID_RESET            , `ERRM_ARVALID_RESET            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(46, PC_46_AXI_ERRM_ARADDR_STABLE            , `ERRM_ARADDR_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(47, PC_47_AXI_ERRM_ARBURST_STABLE           , `ERRM_ARBURST_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(48, PC_48_AXI_ERRM_ARCACHE_STABLE           , `ERRM_ARCACHE_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(49, PC_49_AXI_ERRM_ARID_STABLE              , `ERRM_ARID_STABLE              , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(50, PC_50_AXI_ERRM_ARLEN_STABLE             , `ERRM_ARLEN_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(51, PC_51_AXI_ERRM_ARLOCK_STABLE            , `ERRM_ARLOCK_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(52, PC_52_AXI_ERRM_ARPROT_STABLE            , `ERRM_ARPROT_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(53, PC_53_AXI_ERRM_ARSIZE_STABLE            , `ERRM_ARSIZE_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(54, PC_54_AXI_ERRM_ARQOS_STABLE             , `ERRM_ARQOS_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(55, PC_55_AXI_ERRM_ARREGION_STABLE          , `ERRM_ARREGION_STABLE          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(56, PC_56_AXI_ERRM_ARVALID_STABLE           , `ERRM_ARVALID_STABLE           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(57, PC_57_AXI_RECS_ARREADY_MAX_WAIT         , `RECS_ARREADY_MAX_WAIT         , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(58, PC_58_AXI_ERRS_RDATA_NUM                , `ERRS_RDATA_NUM                , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(59, PC_59_AXI_ERRS_RID                      , `ERRS_RID                      , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(60, PC_60_AXI_ERRS_RRESP_EXOKAY             , `ERRS_RRESP_EXOKAY             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(61, PC_61_AXI_ERRS_RVALID_RESET             , `ERRS_RVALID_RESET             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(62, PC_62_AXI_ERRS_RDATA_STABLE             , `ERRS_RDATA_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(63, PC_63_AXI_ERRS_RID_STABLE               , `ERRS_RID_STABLE               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(64, PC_64_AXI_ERRS_RLAST_STABLE             , `ERRS_RLAST_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(65, PC_65_AXI_ERRS_RRESP_STABLE             , `ERRS_RRESP_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(66, PC_66_AXI_ERRS_RVALID_STABLE            , `ERRS_RVALID_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(67, PC_67_AXI_RECM_RREADY_MAX_WAIT          , `RECM_RREADY_MAX_WAIT          , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(68, PC_68_AXI_ERRM_EXCL_ALIGN               , `ERRM_EXCL_ALIGN               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(69, PC_69_AXI_ERRM_EXCL_LEN                 , `ERRM_EXCL_LEN                 , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(70, PC_70_AXI_RECM_EXCL_MATCH               , `RECM_EXCL_MATCH               , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(71, PC_71_AXI_ERRM_EXCL_MAX                 , `ERRM_EXCL_MAX                 , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(72, PC_72_AXI_RECM_EXCL_PAIR                , `RECM_EXCL_PAIR                , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(73, PC_73_AXI_ERRM_AWUSER_STABLE            , `ERRM_AWUSER_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(74, PC_74_AXI_ERRM_WUSER_STABLE             , `ERRM_WUSER_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(75, PC_75_AXI_ERRS_BUSER_STABLE             , `ERRS_BUSER_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(76, PC_76_AXI_ERRM_ARUSER_STABLE            , `ERRM_ARUSER_STABLE            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(77, PC_77_AXI_ERRS_RUSER_STABLE             , `ERRS_RUSER_STABLE             , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(78, PC_78_AXI_AUXM_RCAM_OVERFLOW            , `AUXM_RCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(79, PC_79_AXI_AUXM_RCAM_UNDERFLOW           , `AUXM_RCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(80, PC_80_AXI_AUXM_WCAM_OVERFLOW            , `AUXM_WCAM_OVERFLOW            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(81, PC_81_AXI_AUXM_WCAM_UNDERFLOW           , `AUXM_WCAM_UNDERFLOW           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(82, PC_82_AXI_AUXM_EXCL_OVERFLOW            , `AUXM_EXCL_OVERFLOW            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(83, PC_83_AXI4LITE_ERRS_BRESP_EXOKAY        , `ERRS_AXI4LITE_BRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(84, PC_84_AXI4LITE_ERRS_RRESP_EXOKAY        , `ERRS_AXI4LITE_RRESP_EXOKAY    , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(85, PC_85_AXI4LITE_AUXM_DATA_WIDTH          , `AUXM_AXI4LITE_DATA_WIDTH      , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(86, PC_86_XILINX_AW_SUPPORTS_NARROW_BURST   , `XILINX_AW_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(87, PC_87_XILINX_AR_SUPPORTS_NARROW_BURST   , `XILINX_AR_SUPPORTS_NARROW_BURST, C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(88, PC_88_XILINX_AW_SUPPORTS_NARROW_CACHE   , `XILINX_AW_SUPPORTS_NARROW_CACHE, ((C_PC_MESSAGE_LEVEL > 1) ? 1 : C_PC_MESSAGE_LEVEL))
+`REPORTER_MACRO(89, PC_89_XILINX_AR_SUPPORTS_NARROW_CACHE   , `XILINX_AR_SUPPORTS_NARROW_CACHE, ((C_PC_MESSAGE_LEVEL > 1) ? 1 : C_PC_MESSAGE_LEVEL))
+`REPORTER_MACRO(90, PC_90_XILINX_AW_MAX_BURST               , `XILINX_AW_MAX_BURST            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(91, PC_91_XILINX_AR_MAX_BURST               , `XILINX_AR_MAX_BURST            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(92, PC_92_XILINX_AWREADY_RESET              , `XILINX_AWREADY_RESET           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(93, PC_93_XILINX_WREADY_RESET               , `XILINX_WREADY_RESET            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(94, PC_94_XILINX_BREADY_RESET               , `XILINX_BREADY_RESET            , 1)
+`REPORTER_MACRO(95, PC_95_XILINX_ARREADY_RESET              , `XILINX_ARREADY_RESET           , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(96, PC_96_XILINX_RREADY_RESET               , `XILINX_RREADY_RESET            , 1)
+`REPORTER_MACRO(97, PC_97_XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT               , `XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(98, PC_98_XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT               , `XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(99, PC_99_XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT               , `XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(100, PC_100_XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT               , `XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT            , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(101, PC_101_XILINX_ARESETN_PULSE_WIDTH , `XILINX_ARESETN_PULSE_WIDTH , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(102, PC_102_XILINX_AXI4_ERRM_NO_STRB_ADDRESS, `XILINX_AXI4_ERRM_NO_STRB_ADDRESS , C_PC_MESSAGE_LEVEL)
+`REPORTER_MACRO(103, PC_103_XILINX_AXI4_ERRM_NO_SUPPORTS_NARROW_LENGTH_SIZE, `XILINX_AXI4_ERRM_SUPPORTS_NARROW_BURST_SIZE , C_PC_MESSAGE_LEVEL)
+
+// synthesis translate_on
+
+endmodule
+`ifdef AXI4PC_MESSAGES
+  `undef AXI4PC_MESSAGES
+  `undef ERRM_AWADDR_BOUNDARY      
+  `undef ERRM_AWADDR_WRAP_ALIGN    
+  `undef ERRM_AWBURST              
+  `undef ERRM_AWCACHE              
+  `undef ERRM_ARCACHE              
+  `undef ERRM_AWLEN_WRAP           
+  `undef ERRM_AWSIZE               
+  `undef ERRM_AWVALID_RESET        
+  `undef ERRM_AWADDR_STABLE        
+  `undef ERRM_AWBURST_STABLE       
+  `undef ERRM_AWCACHE_STABLE       
+  `undef ERRM_AWID_STABLE          
+  `undef ERRM_AWLEN_STABLE         
+  `undef ERRM_AWLOCK_STABLE        
+  `undef ERRM_AWPROT_STABLE        
+  `undef ERRM_AWSIZE_STABLE        
+  `undef ERRM_AWQOS_STABLE         
+  `undef ERRM_AWREGION_STABLE      
+  `undef ERRM_AWVALID_STABLE       
+  `undef ERRM_AWADDR_X             
+  `undef ERRM_AWBURST_X            
+  `undef ERRM_AWCACHE_X            
+  `undef ERRM_AWID_X               
+  `undef ERRM_AWLEN_X              
+  `undef ERRM_AWLOCK_X             
+  `undef ERRM_AWPROT_X             
+  `undef ERRM_AWSIZE_X             
+  `undef ERRM_AWQOS_X              
+  `undef ERRM_AWREGION_X           
+  `undef ERRM_AWVALID_X            
+  `undef ERRS_AWREADY_X            
+  `undef ERRM_WDATA_NUM            
+  `undef ERRM_WSTRB                
+  `undef ERRM_WVALID_RESET         
+  `undef ERRM_WDATA_STABLE         
+  `undef ERRM_WLAST_STABLE         
+  `undef ERRM_WSTRB_STABLE         
+  `undef ERRM_WVALID_STABLE        
+  `undef ERRM_WDATA_X              
+  `undef ERRM_WLAST_X              
+  `undef ERRM_WSTRB_X              
+  `undef ERRM_WVALID_X             
+  `undef ERRS_WREADY_X             
+  `undef ERRS_BRESP_WLAST          
+  `undef ERRS_BRESP_ALL_DONE_EOS   
+  `undef ERRS_BRESP_EXOKAY         
+  `undef ERRS_BVALID_RESET         
+  `undef ERRS_BRESP_AW             
+  `undef ERRS_BID_STABLE           
+  `undef ERRS_BRESP_STABLE         
+  `undef ERRS_BVALID_STABLE        
+  `undef ERRM_BREADY_X             
+  `undef ERRS_BID_X                
+  `undef ERRS_BRESP_X              
+  `undef ERRS_BVALID_X             
+  `undef ERRM_ARADDR_BOUNDARY      
+  `undef ERRM_ARADDR_WRAP_ALIGN    
+  `undef ERRM_ARBURST              
+  `undef ERRM_ARLEN_FIXED          
+  `undef ERRM_AWLEN_FIXED          
+  `undef ERRM_AWLEN_LOCK           
+  `undef ERRM_ARLEN_LOCK           
+  `undef ERRM_ARLEN_WRAP           
+  `undef ERRM_ARSIZE               
+  `undef ERRM_ARVALID_RESET        
+  `undef ERRM_ARADDR_STABLE        
+  `undef ERRM_ARBURST_STABLE       
+  `undef ERRM_ARCACHE_STABLE       
+  `undef ERRM_ARID_STABLE          
+  `undef ERRM_ARLEN_STABLE         
+  `undef ERRM_ARLOCK_STABLE        
+  `undef ERRM_ARPROT_STABLE        
+  `undef ERRM_ARSIZE_STABLE        
+  `undef ERRM_ARQOS_STABLE         
+  `undef ERRM_ARREGION_STABLE      
+  `undef ERRM_ARVALID_STABLE       
+  `undef ERRM_ARADDR_X             
+  `undef ERRM_ARBURST_X            
+  `undef ERRM_ARCACHE_X            
+  `undef ERRM_ARID_X               
+  `undef ERRM_ARLEN_X              
+  `undef ERRM_ARLOCK_X             
+  `undef ERRM_ARPROT_X             
+  `undef ERRM_ARSIZE_X             
+  `undef ERRM_ARQOS_X              
+  `undef ERRM_ARREGION_X           
+  `undef ERRM_ARVALID_X            
+  `undef ERRS_ARREADY_X            
+  `undef ERRS_RDATA_NUM            
+  `undef ERRS_RLAST_ALL_DONE_EOS   
+  `undef ERRS_RID                  
+  `undef ERRS_RRESP_EXOKAY         
+  `undef ERRS_RVALID_RESET         
+  `undef ERRS_RDATA_STABLE         
+  `undef ERRS_RID_STABLE           
+  `undef ERRS_RLAST_STABLE         
+  `undef ERRS_RRESP_STABLE         
+  `undef ERRS_RVALID_STABLE        
+  `undef ERRS_RDATA_X              
+  `undef ERRM_RREADY_X             
+  `undef ERRS_RID_X                
+  `undef ERRS_RLAST_X              
+  `undef ERRS_RRESP_X              
+  `undef ERRS_RVALID_X             
+  `undef ERRL_CSYSACK_FALL         
+  `undef ERRL_CSYSACK_RISE         
+  `undef ERRL_CSYSREQ_FALL         
+  `undef ERRL_CSYSREQ_RISE         
+  `undef ERRL_CACTIVE_X            
+  `undef ERRL_CSYSACK_X            
+  `undef ERRL_CSYSREQ_X            
+  `undef ERRM_EXCL_ALIGN           
+  `undef ERRM_EXCL_LEN             
+  `undef ERRM_EXCL_MAX             
+  `undef ERRM_AWUSER_STABLE        
+  `undef ERRM_WUSER_STABLE         
+  `undef ERRS_BUSER_STABLE         
+  `undef ERRM_ARUSER_STABLE        
+  `undef ERRS_RUSER_STABLE         
+  `undef ERRM_AWUSER_X             
+  `undef ERRM_WUSER_X              
+  `undef ERRS_BUSER_X              
+  `undef ERRM_ARUSER_X             
+  `undef ERRS_RUSER_X              
+  `undef ERRM_AWUSER_TIEOFF
+  `undef ERRM_WUSER_TIEOFF
+  `undef ERRS_BUSER_TIEOFF
+  `undef ERRM_ARUSER_TIEOFF
+  `undef ERRS_RUSER_TIEOFF
+  `undef ERRM_AWID_TIEOFF 
+  `undef ERRS_BID_TIEOFF 
+  `undef ERRM_ARID_TIEOFF 
+  `undef ERRS_RID_TIEOFF 
+  `undef AUXM_DATA_WIDTH           
+  `undef AUXM_ADDR_WIDTH           
+  `undef AUXM_EXMON_WIDTH          
+  `undef AUXM_MAXRBURSTS           
+  `undef AUXM_MAXWBURSTS           
+  `undef AUXM_RCAM_OVERFLOW        
+  `undef AUXM_RCAM_UNDERFLOW       
+  `undef AUXM_WCAM_OVERFLOW        
+  `undef AUXM_WCAM_UNDERFLOW       
+  `undef AUXM_EXCL_OVERFLOW        
+  `undef RECM_EXCL_PAIR            
+  `undef RECS_AWREADY_MAX_WAIT     
+  `undef RECS_WREADY_MAX_WAIT      
+  `undef RECM_BREADY_MAX_WAIT      
+  `undef RECS_ARREADY_MAX_WAIT     
+  `undef RECM_RREADY_MAX_WAIT      
+  `undef RECM_EXCL_MATCH           
+  `undef ERRS_AXI4LITE_BRESP_EXOKAY 
+  `undef ERRS_AXI4LITE_RRESP_EXOKAY 
+  `undef AUXM_AXI4LITE_DATA_WIDTH
+  `undef XILINX_AW_SUPPORTS_NARROW_BURST 
+  `undef XILINX_AR_SUPPORTS_NARROW_BURST 
+  `undef XILINX_AW_SUPPORTS_NARROW_CACHE 
+  `undef XILINX_AR_SUPPORTS_NARROW_CACHE 
+  `undef XILINX_AW_MAX_BURST
+  `undef XILINX_AR_MAX_BURST
+  `undef XILINX_AWREADY_RESET
+  `undef XILINX_WREADY_RESET 
+  `undef XILINX_BREADY_RESET 
+  `undef XILINX_ARREADY_RESET
+  `undef XILINX_RREADY_RESET 
+  `undef XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT
+  `undef XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT
+  `undef XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT
+  `undef XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT
+  `undef XILINX_ARESETN_PULSE_WIDTH
+  `undef XILINX_AXI4_ERRM_NO_STRB_ADDRESS
+  `undef XILINX_AXI4_ERRM_SUPPORTS_NARROW_BURST_SIZE
+`endif
+
+`default_nettype wire
+
+
+
+//  (c) Copyright 2017 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Verilog-standard:  System Verilog 2012
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+`include "sc_util_v1_0_2_constants.vh"
+  
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_protocol_checker_v2_0_1_threadcam # (
+  parameter integer C_NUM_THREADS       = 1                ,
+  parameter integer C_INDEX_WIDTH       = 1                ,  // = clog2(C_NUM_THREADS)
+  parameter integer C_ID_WIDTH          = 0                ,
+  parameter integer C_NUM_OUTSTANDING   = 32
+) (
+  input  wire                                        aclk,
+  input  wire                                        aclken,
+  input  wire                                        areset,
+
+// Generic address channel SI
+  input  wire [(C_ID_WIDTH==0?1:C_ID_WIDTH)-1:0]     s_aid,
+  input  wire                                        s_avalid,
+  input  wire                                        s_aready,
+
+// Response monitor ports
+  input  wire [(C_ID_WIDTH==0?1:C_ID_WIDTH)-1:0]     m_rid,
+  input  wire                                        m_rlast,
+  input  wire                                        m_rvalid,
+  input  wire                                        m_rready,
+  
+// CAM results
+  output wire [C_INDEX_WIDTH-1:0]                    aid_index,
+  output wire [C_INDEX_WIDTH-1:0]                    rid_index,
+  output wire                                        rid_mismatch,
+  output wire                                        cam_overflow,
+  
+// Reverse ID lookup
+  input  wire [C_INDEX_WIDTH-1:0]                    rev_index,
+  output wire [(C_ID_WIDTH==0?1:C_ID_WIDTH)-1:0]     rev_id
+);
+
+import sc_util_v1_0_2_pkg::*;
+
+localparam integer P_ACCEPTANCE_SIZE = $clog2(C_NUM_OUTSTANDING<2?2:C_NUM_OUTSTANDING);
+localparam integer P_BYPASS = 0;
+localparam integer P_FULLY_PIPELINED = 1;
+localparam integer P_PIPELINED_REG_STALL = 2;
+localparam integer P_ID_WIDTH = (C_ID_WIDTH==0) ? 1 : C_ID_WIDTH;
+
+function [P_ID_WIDTH-1:0] f_mux_id
+  (
+   input [C_NUM_THREADS*P_ID_WIDTH-1:0] id_array,
+   input [C_INDEX_WIDTH-1:0] sel
+   );
+  integer i;
+  reg [C_NUM_THREADS*P_ID_WIDTH-1:0] carry;
+  begin
+    carry[P_ID_WIDTH-1:0] = {P_ID_WIDTH{(sel==0)?1'b1:1'b0}} & id_array[P_ID_WIDTH-1:0];
+    if (C_NUM_THREADS>1) begin
+      for (i=1;i16?16:C_AXI_ID_WIDTH) > C_PC_MAXRBURSTS) ? (C_PC_MAXRBURSTS+1) : 2**C_AXI_ID_WIDTH;
+localparam integer P_NUM_WTHREADS = (2**(C_AXI_ID_WIDTH>16?16:C_AXI_ID_WIDTH) > C_PC_MAXWBURSTS) ? (C_PC_MAXWBURSTS+1) : 2**C_AXI_ID_WIDTH;
+localparam integer P_INDEX_WIDTH = f_ceil_log2(P_NUM_RTHREADS>P_NUM_WTHREADS ? P_NUM_RTHREADS : P_NUM_WTHREADS);
+
+  function integer f_ceil_log2
+    (
+     input integer x
+     );
+    integer acc;
+    begin
+      acc=0;
+      while ((2**acc) < x)
+        acc = acc + 1;
+      f_ceil_log2 = acc;
+    end
+  endfunction
+
+  reg   resetn_q;
+  wire  reset_i;
+  wire  resetn_out;
+  wire  thread_cam_reset;
+  (* shreg_extract="no", iob="false", equivalent_register_removal = "no" *) reg [2:0] reset_resync;
+
+  assign reset_i = ~system_resetn;
+  assign resetn_out = (C_PC_HAS_SYSTEM_RESET == 1) ? reset_resync[2] : resetn_q;
+  
+  always @(posedge aclk or posedge reset_i) begin
+    if (reset_i) begin
+      reset_resync <= 3'b000;
+    end else begin
+      reset_resync <= {reset_resync[1:0], 1'b1};
+    end
+  end
+
+  assign thread_cam_reset = !(resetn_out & resetn_q);
+
+reg  [C_AXI_ID_WIDTH-1:0]     awid_q;
+reg  [C_AXI_ADDR_WIDTH-1:0]   awaddr_q;
+reg  [7:0]                    awlen_q;
+reg  [2:0]                    awsize_q;
+reg  [1:0]                    awburst_q;
+reg  [0:0]                    awlock_q;
+reg  [3:0]                    awcache_q;
+reg  [2:0]                    awprot_q;
+reg  [3:0]                    awqos_q;
+reg  [3:0]                    awregion_q;
+reg  [C_AXI_AWUSER_WIDTH-1:0] awuser_q;
+reg                           awvalid_q;
+reg                           awready_q;
+reg                           wlast_q;
+reg  [C_AXI_DATA_WIDTH-1:0]   wdata_q;
+reg  [C_AXI_DATA_WIDTH/8-1:0] wstrb_q;
+reg  [C_AXI_WUSER_WIDTH-1:0]  wuser_q;
+reg                           wvalid_q;
+reg                           wready_q;
+reg  [C_AXI_ID_WIDTH-1:0]     bid_q;
+reg  [1:0]                    bresp_q;
+reg  [C_AXI_BUSER_WIDTH-1:0]  buser_q;
+reg                           bvalid_q;
+reg                           bready_q;
+reg  [C_AXI_ID_WIDTH-1:0]     arid_q;
+reg  [C_AXI_ADDR_WIDTH-1:0]   araddr_q;
+reg  [7:0]                    arlen_q;
+reg  [2:0]                    arsize_q;
+reg  [1:0]                    arburst_q;
+reg  [0:0]                    arlock_q;
+reg  [3:0]                    arcache_q;
+reg  [2:0]                    arprot_q;
+reg  [3:0]                    arqos_q;
+reg  [3:0]                    arregion_q;
+reg  [C_AXI_ARUSER_WIDTH-1:0] aruser_q;
+reg                           arvalid_q;
+reg                           arready_q;
+reg  [C_AXI_ID_WIDTH-1:0]     rid_q;
+reg                           rlast_q;
+reg  [C_AXI_DATA_WIDTH-1:0]   rdata_q;
+reg  [1:0]                    rresp_q;
+reg  [C_AXI_RUSER_WIDTH-1:0]  ruser_q;
+reg                           rvalid_q;
+reg                           rready_q;
+
+reg                           resetn_qq;
+reg  [C_AXI_ID_WIDTH-1:0]     awid_qq;
+reg  [C_AXI_ADDR_WIDTH-1:0]   awaddr_qq;
+reg  [7:0]                    awlen_qq;
+reg  [2:0]                    awsize_qq;
+reg  [1:0]                    awburst_qq;
+reg  [0:0]                    awlock_qq;
+reg  [3:0]                    awcache_qq;
+reg  [2:0]                    awprot_qq;
+reg  [3:0]                    awqos_qq;
+reg  [3:0]                    awregion_qq;
+reg  [C_AXI_AWUSER_WIDTH-1:0] awuser_qq;
+reg                           awvalid_qq;
+reg                           awready_qq;
+reg                           wlast_qq;
+reg  [C_AXI_DATA_WIDTH-1:0]   wdata_qq;
+reg  [C_AXI_DATA_WIDTH/8-1:0] wstrb_qq;
+reg  [C_AXI_WUSER_WIDTH-1:0]  wuser_qq;
+reg                           wvalid_qq;
+reg                           wready_qq;
+reg  [C_AXI_ID_WIDTH-1:0]     bid_qq;
+reg  [1:0]                    bresp_qq;
+reg  [C_AXI_BUSER_WIDTH-1:0]  buser_qq;
+reg                           bvalid_qq;
+reg                           bready_qq;
+reg  [C_AXI_ID_WIDTH-1:0]     arid_qq;
+reg  [C_AXI_ADDR_WIDTH-1:0]   araddr_qq;
+reg  [7:0]                    arlen_qq;
+reg  [2:0]                    arsize_qq;
+reg  [1:0]                    arburst_qq;
+reg  [0:0]                    arlock_qq;
+reg  [3:0]                    arcache_qq;
+reg  [2:0]                    arprot_qq;
+reg  [3:0]                    arqos_qq;
+reg  [3:0]                    arregion_qq;
+reg  [C_AXI_ARUSER_WIDTH-1:0] aruser_qq;
+reg                           arvalid_qq;
+reg                           arready_qq;
+reg  [C_AXI_ID_WIDTH-1:0]     rid_qq;
+reg                           rlast_qq;
+reg  [C_AXI_DATA_WIDTH-1:0]   rdata_qq;
+reg  [1:0]                    rresp_qq;
+reg  [C_AXI_RUSER_WIDTH-1:0]  ruser_qq;
+reg                           rvalid_qq;
+reg                           rready_qq;
+
+wire [P_INDEX_WIDTH-1:0] arid_index    ;
+wire [P_INDEX_WIDTH-1:0] rid_index     ;
+wire                     rid_mismatch  ;
+wire                     rcam_overflow ;
+wire [P_INDEX_WIDTH-1:0] awid_index    ;
+wire [P_INDEX_WIDTH-1:0] bid_index     ;
+wire                     bid_mismatch  ;
+wire                     wcam_overflow ;
+reg  [P_INDEX_WIDTH-1:0] arid_index_q;
+reg  [P_INDEX_WIDTH-1:0] rid_index_q;
+reg                      rid_mismatch_q;
+reg                      rcam_overflow_q;
+reg  [P_INDEX_WIDTH-1:0] awid_index_q;
+reg  [P_INDEX_WIDTH-1:0] bid_index_q;
+reg                      bid_mismatch_q;
+reg                      wcam_overflow_q;
+
+reg                           pc_asserted_i;
+reg [159:0]                   pc_snapshot;
+wire [C_PC_STATUS_WIDTH-1:0]  pc_status_i;
+
+always @(posedge aclk) begin
+  resetn_q    <= aresetn;
+  awid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_awid     : {C_AXI_ID_WIDTH{1'b0}};
+  awaddr_q    <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_awaddr : {C_AXI_ADDR_WIDTH{1'b0}};
+  awlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_awlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_awlen | 8'h00) : 8'h00;
+  awsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_awsize   : LP_AXI_SIZE;
+  awburst_q   <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awburst  : 2'b01;
+  awlock_q    <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awlock[0] : 1'b0;
+  awcache_q   <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awcache  : 4'h0;
+  awprot_q    <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_awprot : {3{1'b0}};
+  awqos_q     <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awqos    : 4'h0;
+  awregion_q  <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awregion : 4'h0;
+  awuser_q    <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_awuser   : {C_AXI_AWUSER_WIDTH{1'b0}};
+  awvalid_q   <= pc_axi_awvalid;
+  awready_q   <= pc_axi_awready;
+  wlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_wlast    : 1'b1;
+  wdata_q     <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_wdata : {C_AXI_DATA_WIDTH{1'b0}};
+  wstrb_q     <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_wstrb : {C_AXI_DATA_WIDTH/8{1'b0}};
+  wuser_q     <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_wuser    : {C_AXI_WUSER_WIDTH{1'b0}};
+  wvalid_q    <= pc_axi_wvalid;
+  wready_q    <= pc_axi_wready;
+  bid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_bid      : {C_AXI_ID_WIDTH{1'b0}};
+  bresp_q     <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_bresp : {2{1'b0}};
+  buser_q     <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_buser    : {C_AXI_BUSER_WIDTH{1'b0}};
+  bvalid_q    <= pc_axi_bvalid;
+  bready_q    <= pc_axi_bready;
+  arid_q      <= (C_AXI_PROTOCOL != 2) ? pc_axi_arid     : {C_AXI_ID_WIDTH{1'b0}};
+  araddr_q    <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_araddr : {C_AXI_ADDR_WIDTH{1'b0}};
+  arlen_q     <= (C_AXI_PROTOCOL == 0) ? pc_axi_arlen : (C_AXI_PROTOCOL == 1) ? (pc_axi_arlen| 8'h00) : 8'h00;
+  arsize_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_arsize   : LP_AXI_SIZE;
+  arburst_q   <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_arburst  : 2'b01;
+  arlock_q    <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_arlock[0] : 1'b0;
+  arcache_q   <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_arcache  : 4'h0;
+  arprot_q    <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_arprot : {3{1'b0}};
+  arqos_q     <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_arqos    : 4'h0;
+  arregion_q  <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_arregion : 4'h0;
+  aruser_q    <= (C_AXI_PROTOCOL != 2) ? pc_axi_aruser   : {C_AXI_ARUSER_WIDTH{1'b0}};
+  arvalid_q   <= pc_axi_arvalid;
+  arready_q   <= pc_axi_arready;
+  rid_q       <= (C_AXI_PROTOCOL != 2) ? pc_axi_rid      : {C_AXI_ID_WIDTH{1'b0}};
+  rlast_q     <= (C_AXI_PROTOCOL != 2) ? pc_axi_rlast    : 1'b1;
+  rdata_q     <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_rdata : {C_AXI_DATA_WIDTH{1'b0}};
+  rresp_q     <= (C_PC_LIGHT_WEIGHT == 0) ? pc_axi_rresp : {2{1'b0}};
+  ruser_q     <= (C_PC_LIGHT_WEIGHT == 0 && C_AXI_PROTOCOL != 2) ? pc_axi_ruser    : {C_AXI_RUSER_WIDTH{1'b0}};
+  rvalid_q    <= pc_axi_rvalid;
+  rready_q    <= pc_axi_rready;
+  
+  resetn_qq    <= resetn_q   ;
+  awid_qq      <= awid_q     ;
+  awaddr_qq    <= awaddr_q   ;
+  awlen_qq     <= awlen_q    ;
+  awsize_qq    <= awsize_q   ;
+  awburst_qq   <= awburst_q  ;
+  awlock_qq    <= awlock_q   ;
+  awcache_qq   <= awcache_q  ;
+  awprot_qq    <= awprot_q   ;
+  awqos_qq     <= awqos_q    ;
+  awregion_qq  <= awregion_q ;
+  awuser_qq    <= awuser_q   ;
+  awvalid_qq   <= awvalid_q  ;
+  awready_qq   <= awready_q  ;
+  wlast_qq     <= wlast_q    ;
+  wdata_qq     <= wdata_q    ;
+  wstrb_qq     <= wstrb_q    ;
+  wuser_qq     <= wuser_q    ;
+  wvalid_qq    <= wvalid_q   ;
+  wready_qq    <= wready_q   ;
+  bid_qq       <= bid_q      ;
+  bresp_qq     <= bresp_q    ;
+  buser_qq     <= buser_q    ;
+  bvalid_qq    <= bvalid_q   ;
+  bready_qq    <= bready_q   ;
+  arid_qq      <= arid_q     ;
+  araddr_qq    <= araddr_q   ;
+  arlen_qq     <= arlen_q    ;
+  arsize_qq    <= arsize_q   ;
+  arburst_qq   <= arburst_q  ;
+  arlock_qq    <= arlock_q   ;
+  arcache_qq   <= arcache_q  ;
+  arprot_qq    <= arprot_q   ;
+  arqos_qq     <= arqos_q    ;
+  arregion_qq  <= arregion_q ;
+  aruser_qq    <= aruser_q   ;
+  arvalid_qq   <= arvalid_q  ;
+  arready_qq   <= arready_q  ;
+  rid_qq       <= rid_q      ;
+  rlast_qq     <= rlast_q    ;
+  rdata_qq     <= rdata_q    ;
+  rresp_qq     <= rresp_q    ;
+  ruser_qq     <= ruser_q    ;
+  rvalid_qq    <= rvalid_q   ;
+  rready_qq    <= rready_q   ;
+  
+  arid_index_q    <= arid_index     ;
+  rid_index_q     <= rid_index      ;
+  rid_mismatch_q  <= rid_mismatch   ;
+  rcam_overflow_q <= rcam_overflow  ;
+  awid_index_q    <= awid_index     ;
+  bid_index_q     <= bid_index      ;
+  bid_mismatch_q  <= bid_mismatch   ;
+  wcam_overflow_q <= wcam_overflow  ;
+  
+  pc_asserted_i <= |pc_status_i;
+  if (~pc_asserted_i) begin  // Capture first asserted check(s)
+    pc_snapshot <= pc_status_i;
+  end
+end
+
+assign pc_status = pc_status_i;
+assign pc_asserted = pc_asserted_i;
+
+  axi_protocol_checker_v2_0_1_threadcam #( 
+    .C_NUM_THREADS   (P_NUM_RTHREADS      ) ,
+    .C_INDEX_WIDTH   (P_INDEX_WIDTH  ) ,
+    .C_ID_WIDTH      (C_AXI_ID_WIDTH       ) ,
+    .C_NUM_OUTSTANDING (C_PC_MAXRBURSTS       ) 
+  )
+  r_threadcam ( 
+    .aclk       (aclk  ),
+    .aclken     (1'b1 ),
+    .areset     (thread_cam_reset ),
+    .s_aid      ( arid_q ) ,
+    .s_avalid   ( arvalid_q   ) ,
+    .s_aready   ( arready_q   ) ,
+    .m_rid      ( rid_q ) ,
+    .m_rlast    ( rlast_q  ) ,
+    .m_rvalid   ( rvalid_q ) ,
+    .m_rready   ( rready_q ) ,
+    .aid_index  (arid_index),
+    .rid_index  (rid_index),
+    .rid_mismatch (rid_mismatch),
+    .cam_overflow (rcam_overflow ),
+    .rev_index  ({P_INDEX_WIDTH{1'b0}}),
+    .rev_id     ( )
+  );
+
+  axi_protocol_checker_v2_0_1_threadcam #( 
+    .C_NUM_THREADS   (P_NUM_WTHREADS      ) ,
+    .C_INDEX_WIDTH   (P_INDEX_WIDTH  ) ,
+    .C_ID_WIDTH      (C_AXI_ID_WIDTH       ) ,
+    .C_NUM_OUTSTANDING (C_PC_MAXWBURSTS       ) 
+  )
+  w_threadcam ( 
+    .aclk       (aclk  ),
+    .aclken     (1'b1 ),
+    .areset     (thread_cam_reset ),
+    .s_aid      ( awid_q ) ,
+    .s_avalid   ( awvalid_q   ) ,
+    .s_aready   ( awready_q   ) ,
+    .m_rid      ( bid_q ) ,
+    .m_rlast    ( 1'b1  ) ,
+    .m_rvalid   ( bvalid_q ) ,
+    .m_rready   ( bready_q ) ,
+    .aid_index  (awid_index),
+    .rid_index  (bid_index),
+    .rid_mismatch (bid_mismatch),
+    .cam_overflow (wcam_overflow ),
+    .rev_index  ({P_INDEX_WIDTH{1'b0}}),
+    .rev_id     ( )
+  );
+
+axi_protocol_checker_v2_0_1_core #(
+  .C_AXI_PROTOCOL             (C_AXI_PROTOCOL),
+  .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),
+  .C_AXI_DATA_WIDTH           (C_AXI_DATA_WIDTH),
+  .C_AXI_ADDR_WIDTH           (C_AXI_ADDR_WIDTH),
+  .C_AXI_AWUSER_WIDTH         (C_AXI_AWUSER_WIDTH),
+  .C_AXI_WUSER_WIDTH          (C_AXI_WUSER_WIDTH),
+  .C_AXI_BUSER_WIDTH          (C_AXI_BUSER_WIDTH),
+  .C_AXI_ARUSER_WIDTH         (C_AXI_ARUSER_WIDTH),
+  .C_AXI_RUSER_WIDTH          (C_AXI_RUSER_WIDTH),
+  .C_HAS_WSTRB                (C_HAS_WSTRB),
+  .C_PC_SUPPORTS_NARROW_BURST (C_PC_SUPPORTS_NARROW_BURST),
+  .C_PC_MAX_BURST_LENGTH      (C_PC_MAX_BURST_LENGTH),
+  .MAXRBURSTS                 (C_PC_MAXRBURSTS),
+  .MAXWBURSTS                 (C_PC_MAXWBURSTS),
+  .EXMON_WIDTH                (C_PC_EXMON_WIDTH),
+  .MAX_AW_WAITS               (C_PC_AW_MAXWAITS),
+  .MAX_AR_WAITS               (C_PC_AR_MAXWAITS),
+  .MAX_W_WAITS                (C_PC_W_MAXWAITS),
+  .MAX_R_WAITS                (C_PC_R_MAXWAITS),
+  .MAX_B_WAITS                (C_PC_B_MAXWAITS),
+  .MAX_CONTINUOUS_RTRANSFERS_WAITS  (C_PC_MAX_CONTINUOUS_RTRANSFERS_WAITS),
+  .MAX_CONTINUOUS_WTRANSFERS_WAITS  (C_PC_MAX_CONTINUOUS_WTRANSFERS_WAITS),
+  .MAX_WLAST_TO_AWVALID_WAITS       (C_PC_MAX_WLAST_TO_AWVALID_WAITS),
+  .MAX_WRITE_TO_BVALID_WAITS        (C_PC_MAX_WRITE_TO_BVALID_WAITS),
+  .LIGHT_WEIGHT               (C_PC_LIGHT_WEIGHT),
+  .C_PC_HAS_SYSTEM_RESET      (C_PC_HAS_SYSTEM_RESET),
+  .C_ERROR_COUNT              (C_PC_STATUS_WIDTH),
+  .C_INDEX_WIDTH              (P_INDEX_WIDTH) ,
+  .C_NUM_RTHREADS             (P_NUM_RTHREADS) ,
+  .C_NUM_WTHREADS             (P_NUM_WTHREADS) 
+  ) CORE (
+    .pc_status        (pc_status_i),
+    .resetn           (system_resetn),
+    
+    .arid_index    (arid_index_q),
+    .rid_index     (rid_index_q),
+    .rid_mismatch  (rid_mismatch_q),
+    .rcam_overflow (rcam_overflow_q),
+    .awid_index    (awid_index_q),
+    .bid_index     (bid_index_q),
+    .bid_mismatch  (bid_mismatch_q),
+    .wcam_overflow (wcam_overflow_q),
+    
+    .ACLK      (aclk),
+    .ARST_N    ( resetn_qq   ),
+    .AWID      ( awid_qq     ),
+    .AWADDR    ( awaddr_qq   ),
+    .AWLEN     ( awlen_qq    ),
+    .AWSIZE    ( awsize_qq   ),
+    .AWBURST   ( awburst_qq  ),
+    .AWLOCK    ( awlock_qq   ),
+    .AWCACHE   ( awcache_qq  ),
+    .AWPROT    ( awprot_qq   ),
+    .AWQOS     ( awqos_qq    ),
+    .AWREGION  ( awregion_qq ),
+    .AWUSER    ( awuser_qq   ),
+    .AWVALID   ( awvalid_qq  ),
+    .AWREADY   ( awready_qq  ),
+    .WLAST     ( wlast_qq    ),
+    .WDATA     ( wdata_qq    ),
+    .WSTRB     ( wstrb_qq    ),
+    .WUSER     ( wuser_qq    ),
+    .WVALID    ( wvalid_qq   ),
+    .WREADY    ( wready_qq   ),
+    .BID       ( bid_qq      ),
+    .BRESP     ( bresp_qq    ),
+    .BUSER     ( buser_qq    ),
+    .BVALID    ( bvalid_qq   ),
+    .BREADY    ( bready_qq   ),
+    .ARID      ( arid_qq     ),
+    .ARADDR    ( araddr_qq   ),
+    .ARLEN     ( arlen_qq    ),
+    .ARSIZE    ( arsize_qq   ),
+    .ARBURST   ( arburst_qq  ),
+    .ARLOCK    ( arlock_qq   ),
+    .ARCACHE   ( arcache_qq  ),
+    .ARPROT    ( arprot_qq   ),
+    .ARQOS     ( arqos_qq    ),
+    .ARREGION  ( arregion_qq ),
+    .ARUSER    ( aruser_qq   ),
+    .ARVALID   ( arvalid_qq  ),
+    .ARREADY   ( arready_qq  ),
+    .RID       ( rid_qq      ),
+    .RLAST     ( rlast_qq    ),
+    .RDATA     ( rdata_qq    ),
+    .RRESP     ( rresp_qq    ),
+    .RUSER     ( ruser_qq    ),
+    .RVALID    ( rvalid_qq   ),
+    .RREADY    ( rready_qq   )
+);
+
+wire [P_NUM_REPORTED_CHECKS-1:0] pc_status_ii;
+assign pc_status_ii = pc_status_i;
+axi_protocol_checker_v2_0_1_reporter #(
+  .C_PC_MESSAGE_LEVEL         (C_PC_MESSAGE_LEVEL),
+  .C_PC_STATUS_WIDTH          (P_NUM_REPORTED_CHECKS),
+  .C_AXI_PROTOCOL             (C_AXI_PROTOCOL),
+  .C_AXI_ID_WIDTH             (C_AXI_ID_WIDTH),
+  .C_AXI_DATA_WIDTH           (C_AXI_DATA_WIDTH),
+  .C_AXI_ADDR_WIDTH           (C_AXI_ADDR_WIDTH),
+  .C_AXI_AWUSER_WIDTH         (C_AXI_AWUSER_WIDTH),
+  .C_AXI_WUSER_WIDTH          (C_AXI_WUSER_WIDTH),
+  .C_AXI_BUSER_WIDTH          (C_AXI_BUSER_WIDTH),
+  .C_AXI_ARUSER_WIDTH         (C_AXI_ARUSER_WIDTH),
+  .C_AXI_RUSER_WIDTH          (C_AXI_RUSER_WIDTH),
+  .C_PC_MAXRBURSTS            (C_PC_MAXRBURSTS),
+  .C_PC_MAXWBURSTS            (C_PC_MAXWBURSTS),
+  .C_ENABLE_MARK_DEBUG        (C_ENABLE_MARK_DEBUG)
+) REP (
+  .aclk         (aclk),
+  .pc_status    (pc_status_ii),  // Port width must match number of defined checks
+  .ARST_N      ( aresetn   ),
+  .AWID         ( awid_q ),
+  .AWADDR       ( awaddr_q ),
+  .AWLEN        ( awlen_q ),
+  .AWSIZE       ( awsize_q ),
+  .AWBURST      ( awburst_q ),
+  .AWLOCK       ( awlock_q ),
+  .AWCACHE      ( awcache_q ),
+  .AWPROT       ( awprot_q ),
+  .AWQOS        ( awqos_q ),
+  .AWREGION     ( awregion_q ),
+  .AWUSER       ( awuser_q ),
+  .AWVALID      ( awvalid_q ),
+  .AWREADY      ( awready_q ),
+  .WLAST        ( wlast_q ),
+  .WDATA        ( wdata_q ),
+  .WSTRB        ( wstrb_q ),
+  .WUSER        ( wuser_q ),
+  .WVALID       ( wvalid_q ),
+  .WREADY       ( wready_q ),
+  .BID          ( bid_q ),
+  .BRESP        ( bresp_q ),
+  .BUSER        ( buser_q ),
+  .BVALID       ( bvalid_q ),
+  .BREADY       ( bready_q ),
+  .ARID         ( arid_q ),
+  .ARADDR       ( araddr_q ),
+  .ARLEN        ( arlen_q ),
+  .ARSIZE       ( arsize_q ),
+  .ARBURST      ( arburst_q ),
+  .ARLOCK       ( arlock_q ),
+  .ARCACHE      ( arcache_q ),
+  .ARPROT       ( arprot_q ),
+  .ARQOS        ( arqos_q ),
+  .ARREGION     ( arregion_q ),
+  .ARUSER       ( aruser_q ),
+  .ARVALID      ( arvalid_q ),
+  .ARREADY      ( arready_q ),
+  .RID          ( rid_q ),
+  .RLAST        ( rlast_q ),
+  .RDATA        ( rdata_q ),
+  .RRESP        ( rresp_q ),
+  .RUSER        ( ruser_q ),
+  .RVALID       ( rvalid_q ),
+  .RREADY       ( rready_q   )
+);
+
+// AXI Status Interface
+  
+  reg s_axi_arready_i;
+  reg s_axi_rvalid_i;
+  reg [31:0] s_axi_rdata_i;
+  assign s_axi_arready = s_axi_arready_i;
+  assign s_axi_rvalid  = s_axi_rvalid_i;
+  assign s_axi_rdata   = s_axi_rdata_i;
+  assign s_axi_rresp   = 2'b0;
+  
+  always @(posedge aclk) begin
+    if (~aresetn) begin
+      s_axi_arready_i <= 1'b0;
+      s_axi_rvalid_i <= 1'b0;
+    end else if (C_ENABLE_CONTROL!=0) begin
+      if (s_axi_rready & s_axi_rvalid_i) begin
+        s_axi_rvalid_i <= 1'b0;
+      end else if (s_axi_arready_i & s_axi_arvalid) begin
+        s_axi_arready_i <= 1'b0;
+        s_axi_rvalid_i <= 1'b1;
+      end else if (~s_axi_rvalid_i) begin
+        s_axi_arready_i <= 1'b1;
+      end
+    end
+  end
+
+  always @(posedge aclk) begin
+    if (C_ENABLE_CONTROL!=0 && ~s_axi_rvalid_i) begin
+      casex (s_axi_araddr)
+        10'b01_xxxx_00xx: s_axi_rdata_i <= pc_status_i[31:0];
+        10'b01_xxxx_01xx: s_axi_rdata_i <= pc_status_i[63:32];
+        10'b01_xxxx_10xx: s_axi_rdata_i <= pc_status_i[95:64];
+        10'b01_xxxx_11xx: s_axi_rdata_i <= pc_status_i[C_PC_STATUS_WIDTH-1:96];
+        10'b10_xxxx_00xx: s_axi_rdata_i <= pc_snapshot[31:0];
+        10'b10_xxxx_01xx: s_axi_rdata_i <= pc_snapshot[63:32];
+        10'b10_xxxx_10xx: s_axi_rdata_i <= pc_snapshot[95:64];
+        10'b10_xxxx_11xx: s_axi_rdata_i <= pc_snapshot[C_PC_STATUS_WIDTH-1:96];
+        default:          s_axi_rdata_i <= pc_asserted_i;  // s_axi_araddr==0x0
+      endcase
+    end
+  end
+
+endmodule // axi_protocol_checker_v2_0_1_top
+
+`default_nettype wire
+
+
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v
new file mode 100644
index 0000000..98caca1
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v
@@ -0,0 +1,409 @@
+//-----------------------------------------------------------------------------
+//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+//--
+//-- This file contains confidential and proprietary information
+//-- of Xilinx, Inc. and is protected under U.S. and
+//-- international copyright and other intellectual property
+//-- laws.
+//--
+//-- DISCLAIMER
+//-- This disclaimer is not a license and does not grant any
+//-- rights to the materials distributed herewith. Except as
+//-- otherwise provided in a valid license issued to you by
+//-- Xilinx, and to the maximum extent permitted by applicable
+//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//-- (2) Xilinx shall not be liable (whether in contract or tort,
+//-- including negligence, or under any other theory of
+//-- liability) for any loss or damage of any kind or nature
+//-- related to, arising under or in connection with these
+//-- materials, including for any direct, or any indirect,
+//-- special, incidental, or consequential loss or damage
+//-- (including loss of data, profits, goodwill, or any type of
+//-- loss or damage suffered as a result of any action brought
+//-- by a third party) even if such damage or loss was
+//-- reasonably foreseeable or Xilinx had been advised of the
+//-- possibility of the same.
+//--
+//-- CRITICAL APPLICATIONS
+//-- Xilinx products are not designed or intended to be fail-
+//-- safe, or for use in any application requiring fail-safe
+//-- performance, such as life-support or safety devices or
+//-- systems, Class III medical devices, nuclear facilities,
+//-- applications related to the deployment of airbags, or any
+//-- other applications that could lead to death, personal
+//-- injury, or severe property or environmental damage
+//-- (individually and collectively, "Critical
+//-- Applications"). Customer assumes the sole risk and
+//-- liability of any use of Xilinx products in Critical
+//-- Applications, subject only to applicable laws and
+//-- regulations governing limitations on product liability.
+//--
+//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//-- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: ACP Transaction Checker
+// 
+// Check for optimized ACP transactions and flag if they are broken.
+// 
+// 
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   atc
+//     aw_atc
+//     w_atc
+//     b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+module processing_system7_v5_5_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32,
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+                       // Width of ARUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+                       // Width of WUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+                       // Width of RUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+                       // Width of BUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ACLK,
+   input  wire                                  ARESETN,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output wire [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [4-1:0]                          S_AXI_ARLEN,
+   input  wire [3-1:0]                          S_AXI_ARSIZE,
+   input  wire [2-1:0]                          S_AXI_ARBURST,
+   input  wire [2-1:0]                          S_AXI_ARLOCK,
+   input  wire [4-1:0]                          S_AXI_ARCACHE,
+   input  wire [3-1:0]                          S_AXI_ARPROT,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire                                  S_AXI_ARVALID,
+   output wire                                  S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_RDATA,
+   output wire [2-1:0]                          S_AXI_RRESP,
+   output wire                                  S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire                                  S_AXI_RVALID,
+   input  wire                                  S_AXI_RREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_ARID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_ARADDR,
+   output wire [4-1:0]                          M_AXI_ARLEN,
+   output wire [3-1:0]                          M_AXI_ARSIZE,
+   output wire [2-1:0]                          M_AXI_ARBURST,
+   output wire [2-1:0]                          M_AXI_ARLOCK,
+   output wire [4-1:0]                          M_AXI_ARCACHE,
+   output wire [3-1:0]                          M_AXI_ARPROT,
+   output wire [C_AXI_ARUSER_WIDTH-1:0]         M_AXI_ARUSER,
+   output wire                                  M_AXI_ARVALID,
+   input  wire                                  M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_RDATA,
+   input  wire [2-1:0]                          M_AXI_RRESP,
+   input  wire                                  M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0]          M_AXI_RUSER,
+   input  wire                                  M_AXI_RVALID,
+   output wire                                  M_AXI_RREADY,
+   
+   output wire                                  ERROR_TRIGGER,
+   output wire [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  localparam C_FIFO_DEPTH_LOG            = 4;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Internal reset.
+  reg                                   ARESET;
+  
+  // AW->W command queue signals.
+  wire                                  cmd_w_valid;
+  wire                                  cmd_w_check;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id;
+  wire                                  cmd_w_ready;
+  
+  // W->B command queue signals.
+  wire                                  cmd_b_push;
+  wire                                  cmd_b_error;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id;
+  wire                                  cmd_b_full;
+  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr;
+  wire                                  cmd_b_ready;
+  
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Internal Reset
+  /////////////////////////////////////////////////////////////////////////////
+  always @ (posedge ACLK) begin
+    ARESET <= !ARESETN;
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Write Channels (AW/W/B)
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Write Address Channel.
+  processing_system7_v5_5_aw_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+   .C_AXI_AWUSER_WIDTH          (C_AXI_AWUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_addr_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (Out)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+   
+    // Slave Interface Write Address Ports
+    .S_AXI_AWID                 (S_AXI_AWID),
+    .S_AXI_AWADDR               (S_AXI_AWADDR),
+    .S_AXI_AWLEN                (S_AXI_AWLEN),
+    .S_AXI_AWSIZE               (S_AXI_AWSIZE),
+    .S_AXI_AWBURST              (S_AXI_AWBURST),
+    .S_AXI_AWLOCK               (S_AXI_AWLOCK),
+    .S_AXI_AWCACHE              (S_AXI_AWCACHE),
+    .S_AXI_AWPROT               (S_AXI_AWPROT),
+    .S_AXI_AWUSER               (S_AXI_AWUSER),
+    .S_AXI_AWVALID              (S_AXI_AWVALID),
+    .S_AXI_AWREADY              (S_AXI_AWREADY),
+    
+    // Master Interface Write Address Port
+    .M_AXI_AWID                 (M_AXI_AWID),
+    .M_AXI_AWADDR               (M_AXI_AWADDR),
+    .M_AXI_AWLEN                (M_AXI_AWLEN),
+    .M_AXI_AWSIZE               (M_AXI_AWSIZE),
+    .M_AXI_AWBURST              (M_AXI_AWBURST),
+    .M_AXI_AWLOCK               (M_AXI_AWLOCK),
+    .M_AXI_AWCACHE              (M_AXI_AWCACHE),
+    .M_AXI_AWPROT               (M_AXI_AWPROT),
+    .M_AXI_AWUSER               (M_AXI_AWUSER),
+    .M_AXI_AWVALID              (M_AXI_AWVALID),
+    .M_AXI_AWREADY              (M_AXI_AWREADY)
+   );
+   
+  // Write Data channel.
+  processing_system7_v5_5_w_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+   .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH)
+    ) write_data_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    
+    // Command Interface (Out)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    
+    // Slave Interface Write Data Ports
+    .S_AXI_WID                  (S_AXI_WID),
+    .S_AXI_WDATA                (S_AXI_WDATA),
+    .S_AXI_WSTRB                (S_AXI_WSTRB),
+    .S_AXI_WLAST                (S_AXI_WLAST),
+    .S_AXI_WUSER                (S_AXI_WUSER),
+    .S_AXI_WVALID               (S_AXI_WVALID),
+    .S_AXI_WREADY               (S_AXI_WREADY),
+    
+    // Master Interface Write Data Ports
+    .M_AXI_WID                  (M_AXI_WID),
+    .M_AXI_WDATA                (M_AXI_WDATA),
+    .M_AXI_WSTRB                (M_AXI_WSTRB),
+    .M_AXI_WLAST                (M_AXI_WLAST),
+    .M_AXI_WUSER                (M_AXI_WUSER),
+    .M_AXI_WVALID               (M_AXI_WVALID),
+    .M_AXI_WREADY               (M_AXI_WREADY)
+   );
+   
+  // Write Response channel.
+  processing_system7_v5_5_b_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_response_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+    
+    // Slave Interface Write Response Ports
+    .S_AXI_BID                  (S_AXI_BID),
+    .S_AXI_BRESP                (S_AXI_BRESP),
+    .S_AXI_BUSER                (S_AXI_BUSER),
+    .S_AXI_BVALID               (S_AXI_BVALID),
+    .S_AXI_BREADY               (S_AXI_BREADY),
+    
+    // Master Interface Write Response Ports
+    .M_AXI_BID                  (M_AXI_BID),
+    .M_AXI_BRESP                (M_AXI_BRESP),
+    .M_AXI_BUSER                (M_AXI_BUSER),
+    .M_AXI_BVALID               (M_AXI_BVALID),
+    .M_AXI_BREADY               (M_AXI_BREADY),
+    
+    // Trigger detection
+    .ERROR_TRIGGER              (ERROR_TRIGGER),
+    .ERROR_TRANSACTION_ID       (ERROR_TRANSACTION_ID)
+   );
+  
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Read Channels (AR/R)
+  /////////////////////////////////////////////////////////////////////////////
+  // Read Address Port
+  assign M_AXI_ARID     = S_AXI_ARID;
+  assign M_AXI_ARADDR   = S_AXI_ARADDR;
+  assign M_AXI_ARLEN    = S_AXI_ARLEN;
+  assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
+  assign M_AXI_ARBURST  = S_AXI_ARBURST;
+  assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
+  assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
+  assign M_AXI_ARPROT   = S_AXI_ARPROT;
+  assign M_AXI_ARUSER   = S_AXI_ARUSER;
+  assign M_AXI_ARVALID  = S_AXI_ARVALID;
+  assign S_AXI_ARREADY  = M_AXI_ARREADY;
+   
+  // Read Data Port
+  assign S_AXI_RID      = M_AXI_RID;
+  assign S_AXI_RDATA    = M_AXI_RDATA;
+  assign S_AXI_RRESP    = M_AXI_RRESP;
+  assign S_AXI_RLAST    = M_AXI_RLAST;
+  assign S_AXI_RUSER    = M_AXI_RUSER;
+  assign S_AXI_RVALID   = M_AXI_RVALID;
+  assign M_AXI_RREADY   = S_AXI_RREADY;
+  
+  
+endmodule
+`default_nettype wire
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v
new file mode 100644
index 0000000..25bbc9d
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v
@@ -0,0 +1,298 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Address Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   aw_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_aw_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   output reg                                   cmd_w_valid,
+   output wire                                  cmd_w_check,
+   output wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   input  wire                                  cmd_w_ready,
+   input  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   input  wire                                  cmd_b_ready,
+   
+   // Slave Interface Write Address Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for burst types.
+  localparam [2-1:0] C_FIX_BURST         = 2'b00;
+  localparam [2-1:0] C_INCR_BURST        = 2'b01;
+  localparam [2-1:0] C_WRAP_BURST        = 2'b10;
+  
+  // Constants for size.
+  localparam [3-1:0] C_OPTIMIZED_SIZE    = 3'b011;
+  
+  // Constants for length.
+  localparam [4-1:0] C_OPTIMIZED_LEN     = 4'b0011;
+
+  // Constants for cacheline address.
+  localparam [4-1:0] C_NO_ADDR_OFFSET    = 5'b0;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction properties.
+  wire                                access_is_incr;
+  wire                                access_is_wrap;
+  wire                                access_is_coherent;
+  wire                                access_optimized_size;
+  wire                                incr_addr_boundary;
+  wire                                incr_is_optimized;
+  wire                                wrap_is_optimized;
+  wire                                access_is_optimized;
+  
+  // Command FIFO.
+  wire                                cmd_w_push;
+  reg                                 cmd_full;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  wire [C_FIFO_DEPTH_LOG-1:0]         all_addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Decode:
+  //
+  // Detect if transaction is of correct typ, size and length to qualify as
+  // an optimized transaction that has to be checked for errors.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction burst type.
+  assign access_is_incr         = ( S_AXI_AWBURST == C_INCR_BURST );
+  assign access_is_wrap         = ( S_AXI_AWBURST == C_WRAP_BURST );
+  
+  // Transaction has to be Coherent.
+  assign access_is_coherent     = ( S_AXI_AWUSER[0]  == 1'b1 ) &
+                                  ( S_AXI_AWCACHE[1] == 1'b1 );
+  
+  // Transaction cacheline boundary address.
+  assign incr_addr_boundary     = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
+  
+  // Transaction length & size.
+  assign access_optimized_size  = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & 
+                                  ( S_AXI_AWLEN  == C_OPTIMIZED_LEN  );
+  
+  // Transaction is optimized.
+  assign incr_is_optimized      = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
+  assign wrap_is_optimized      = access_is_wrap & access_is_coherent & access_optimized_size;
+  assign access_is_optimized    = ( incr_is_optimized | wrap_is_optimized );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command FIFO:
+  //
+  // Since supported write interleaving is only 1, it is safe to use only a 
+  // simple SRL based FIFO as a command queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+    
+  // Determine when transaction infromation is pushed to the FIFO.
+  assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        addr_ptr <= addr_ptr + 1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        addr_ptr <= addr_ptr - 1;
+      end
+    end
+  end
+  
+  // Total number of buffered commands.
+  assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_full    <= 1'b0;
+      cmd_w_valid <= 1'b0;
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        cmd_w_valid <= 1'b1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        cmd_w_valid <= ( addr_ptr != 0 );
+      end
+      if ( cmd_w_push & ~cmd_b_ready ) begin
+        // Going to full.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
+      end else if ( ~cmd_w_push & cmd_b_ready ) begin
+        // Pop in middle of queue doesn't affect full status.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_w_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {access_is_optimized, S_AXI_AWID};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_AWVALID   = S_AXI_AWVALID & ~cmd_full;
+  
+  // Return ready with push back.
+  assign S_AXI_AWREADY   = M_AXI_AWREADY & ~cmd_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Address Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_AWID      = S_AXI_AWID; 
+  assign M_AXI_AWADDR    = S_AXI_AWADDR;
+  assign M_AXI_AWLEN     = S_AXI_AWLEN;
+  assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+  assign M_AXI_AWBURST   = S_AXI_AWBURST;
+  assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+  assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+  assign M_AXI_AWPROT    = S_AXI_AWPROT;
+  assign M_AXI_AWUSER    = S_AXI_AWUSER;
+  
+  
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v
new file mode 100644
index 0000000..36f280f
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v
@@ -0,0 +1,413 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Response Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_b_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   input  wire                                  cmd_b_push,
+   input  wire                                  cmd_b_error,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   output wire                                  cmd_b_ready,
+   output wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   output reg                                   cmd_b_full,
+   
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output reg  [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   
+   // Trigger detection
+   output reg                                   ERROR_TRIGGER,
+   output reg  [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY         = 2'b00;
+  localparam [2-1:0] C_RESP_EXOKAY       = 2'b01;
+  localparam [2-1:0] C_RESP_SLVERROR     = 2'b10;
+  localparam [2-1:0] C_RESP_DECERR       = 2'b11;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Command Queue.
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  reg                                 cmd_b_valid;
+  wire                                cmd_b_ready_i;
+  wire                                inject_error;
+  wire [C_AXI_ID_WIDTH-1:0]           current_id;
+  
+  // Search command.
+  wire                                found_match;
+  wire                                use_match;
+  wire                                matching_id;
+  
+  // Manage valid command.
+  wire                                write_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             updated_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             next_valid_cmd;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         search_addr_ptr;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         collapsed_addr_ptr;
+  
+  // Pipelined data
+  reg  [C_AXI_ID_WIDTH-1:0]           M_AXI_BID_I;
+  reg  [2-1:0]                        M_AXI_BRESP_I;
+  reg  [C_AXI_BUSER_WIDTH-1:0]        M_AXI_BUSER_I;
+  reg                                 M_AXI_BVALID_I;
+  wire                                M_AXI_BREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue:
+  //
+  // Keep track of depth of Queue to generate full flag.
+  // 
+  // Also generate valid to mark pressence of commands in Queue.
+  // 
+  // Maintain Queue and extract data from currently searched entry.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        // Pushing data increase length/addr.
+        addr_ptr <= addr_ptr + 1;
+      end else if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        addr_ptr <= collapsed_addr_ptr;
+      end
+    end
+  end
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_full  <= 1'b0;
+      cmd_b_valid <= 1'b0;
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        cmd_b_full  <= ( addr_ptr == C_FIFO_DEPTH-3 );
+        cmd_b_valid <= 1'b1;
+      end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
+        cmd_b_full  <= 1'b0;
+        cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_b_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {cmd_b_error, cmd_b_id};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {inject_error, current_id} = data_srl[search_addr_ptr];
+  
+  // Assign outputs.
+  assign cmd_b_addr = collapsed_addr_ptr;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Search Command Queue:
+  //
+  // Search for matching valid command in queue.
+  // 
+  // A command is found when an valid entry with correct ID is found. The queue
+  // is search from the oldest entry, i.e. from a high value.
+  // When new commands are pushed the search address has to be updated to always 
+  // start the search from the oldest available.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Handle search addr.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        search_addr_ptr <= collapsed_addr_ptr;
+        
+      end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
+        // Skip non valid command.
+        search_addr_ptr <= search_addr_ptr - 1;
+        
+      end else if ( cmd_b_push ) begin
+        search_addr_ptr <= search_addr_ptr + 1;
+        
+      end
+    end
+  end
+  
+  // Check if searched command is valid and match ID (for existing response on MI side).
+  assign matching_id  = ( M_AXI_BID_I == current_id );
+  assign found_match  = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
+  assign use_match    = found_match & S_AXI_BREADY;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Track Used Commands:
+  //
+  // Actions that affect Valid Command:
+  // * When a new command is pushed
+  //   => Shift valid vector one step
+  // * When a command is used
+  //   => Clear corresponding valid bit
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Valid command status is updated when a command is used or a new one is pushed.
+  assign write_valid_cmd  = cmd_b_push | cmd_b_ready_i;
+  
+  // Update the used command valid bit.
+  always @ *
+  begin
+    updated_valid_cmd                   = valid_cmd;
+    updated_valid_cmd[search_addr_ptr]  = ~use_match;
+  end
+  
+  // Shift valid vector when command is pushed.
+  always @ *
+  begin
+    if ( cmd_b_push ) begin
+      next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
+    end else begin
+      next_valid_cmd = updated_valid_cmd;
+    end
+  end
+  
+  // Valid signals for next cycle.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      valid_cmd <= {C_FIFO_WIDTH{1'b0}};
+    end else if ( write_valid_cmd ) begin
+      valid_cmd <= next_valid_cmd;
+    end
+  end
+  
+  // Detect oldest available command in Queue.
+  always @ *
+  begin
+    // Default to empty.
+    collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
+    
+    for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
+      if ( next_valid_cmd[index] ) begin
+        collapsed_addr_ptr = index;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Pipe incoming data:
+  // 
+  // The B channel is piped to improve timing and avoid impact in search
+  // mechanism due to late arriving signals.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Clock data.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      M_AXI_BID_I     <= {C_AXI_ID_WIDTH{1'b0}};
+      M_AXI_BRESP_I   <= 2'b00;
+      M_AXI_BUSER_I   <= {C_AXI_BUSER_WIDTH{1'b0}};
+      M_AXI_BVALID_I  <= 1'b0;
+    end else begin
+      if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
+        M_AXI_BVALID_I  <= 1'b0;
+      end
+      if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
+        M_AXI_BID_I     <= M_AXI_BID;
+        M_AXI_BRESP_I   <= M_AXI_BRESP;
+        M_AXI_BUSER_I   <= M_AXI_BUSER;
+        M_AXI_BVALID_I  <= 1'b1;
+      end
+    end
+  end
+  
+  // Generate ready to get new transaction.
+  assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Inject Error:
+  //
+  // BRESP is modified according to command information.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Inject error in response.
+  always @ *
+  begin
+    if ( inject_error ) begin
+      S_AXI_BRESP = C_RESP_SLVERROR;
+    end else begin
+      S_AXI_BRESP = M_AXI_BRESP_I;
+    end
+  end
+  
+  // Handle interrupt generation.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      ERROR_TRIGGER        <= 1'b0;
+      ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
+    end else begin
+      if ( inject_error & cmd_b_ready_i ) begin
+        ERROR_TRIGGER        <= 1'b1;
+        ERROR_TRANSACTION_ID <= M_AXI_BID_I;
+      end else begin
+        ERROR_TRIGGER        <= 1'b0;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Response is passed forward when a matching entry has been found in queue.
+  // Both ready and valid are set when the command is completed.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign S_AXI_BVALID   = M_AXI_BVALID_I & cmd_b_valid & found_match;
+  
+  // Return ready with push back.
+  assign M_AXI_BREADY_I = cmd_b_valid & use_match;
+  
+  // Command has been handled.
+  assign cmd_b_ready_i  = M_AXI_BVALID_I & cmd_b_valid & use_match;
+  assign cmd_b_ready    = cmd_b_ready_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write Response Propagation:
+  //
+  // All information is simply forwarded on from MI- to SI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign S_AXI_BID    = M_AXI_BID_I;
+  assign S_AXI_BUSER  = M_AXI_BUSER_I;
+  
+  
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v
new file mode 100644
index 0000000..0c776b3
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v
@@ -0,0 +1,310 @@
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:      trace_buffer.v
+// Description:   Trace port buffer 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7
+//							 |	
+//							 --trace_buffer
+//-----------------------------------------------------------------------------
+
+
+module processing_system7_v5_5_trace_buffer #
+  (
+   parameter integer FIFO_SIZE = 128,
+	parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+   parameter integer C_DELAY_CLKS = 12
+   )
+  (
+   input wire TRACE_CLK,
+   input wire RST,
+   input wire TRACE_VALID_IN,
+   input wire [3:0] TRACE_ATID_IN,
+   input wire [31:0] TRACE_DATA_IN,
+   output wire TRACE_VALID_OUT,
+   output wire [3:0] TRACE_ATID_OUT,
+   output wire [31:0] TRACE_DATA_OUT
+  );
+
+//------------------------------------------------------------
+// Architecture section
+//------------------------------------------------------------
+
+// function called clogb2 that returns an integer which has the 
+// value of the ceiling of the log base 2.
+
+function integer clogb2 (input integer bit_depth);
+ integer i;
+ integer temp_log;
+ begin
+  temp_log = 0;
+  for(i=bit_depth; i > 0; i = i>>1)
+  clogb2 = temp_log;
+  temp_log=temp_log+1;		
+ end
+endfunction
+
+localparam DEPTH  = clogb2(FIFO_SIZE-1);
+
+wire [31:0] reset_zeros;
+reg  [31:0] trace_pedge; // write enable for FIFO
+reg  [31:0] ti;
+reg  [31:0] tom;
+
+reg  [3:0] atid;
+
+reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory 
+
+reg  [4:0]  dly_ctr;
+reg  [DEPTH-1:0]  fifo_wp;
+reg  [DEPTH-1:0]  fifo_rp;
+
+reg         fifo_re;
+wire        fifo_empty;
+wire        fifo_full;
+reg         fifo_full_reg;
+
+assign reset_zeros = 32'h0;  
+
+
+// Pipeline Stage for Traceport ATID ports
+  always @(posedge TRACE_CLK) begin
+    // process pedge_ti
+    // rising clock edge
+    if((RST == 1'b1)) begin
+      atid <= reset_zeros;
+    end
+    else begin	 
+      atid <= TRACE_ATID_IN;
+	 end
+  end
+
+  assign TRACE_ATID_OUT = atid;
+  
+  /////////////////////////////////////////////
+  // Generate FIFO data based on TRACE_VALID_IN
+  /////////////////////////////////////////////
+  generate
+    if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
+  /////////////////////////////////////////////
+        
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+				if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
+					trace_fifo[fifo_wp]  <= TRACE_DATA_IN;
+				end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(TRACE_VALID_IN ) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+  /////////////////////////////////////////////
+  // Generate FIFO data based on data edge
+  /////////////////////////////////////////////
+    end else begin : gen_data_edge_detector
+  /////////////////////////////////////////////
+
+
+		  // purpose: check for pos edge on any trace input
+		  always @(posedge TRACE_CLK) begin
+			 // process pedge_ti
+			 // rising clock edge
+			 if((RST == 1'b1)) begin
+				ti          <= reset_zeros;
+				trace_pedge <= reset_zeros;
+			 end
+			 else begin
+				ti          <= TRACE_DATA_IN;
+				trace_pedge <= (~ti & TRACE_DATA_IN);
+				//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) &  ~ti;
+				// posedge only
+			 end
+		  end
+		  
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+			 if(|(trace_pedge)  == 1'b1 && fifo_full_reg != 1'b1) begin
+				trace_fifo[fifo_wp]  <= trace_pedge;
+			 end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(|(trace_pedge)  == 1'b1) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+    end
+  endgenerate
+
+
+  always @(posedge TRACE_CLK) begin
+    tom <= trace_fifo[fifo_rp] ;
+  end
+
+
+//  // fifo write pointer
+//  always @(posedge TRACE_CLK) begin
+//      // process
+//    if(RST == 1'b1) begin
+//      fifo_wp <= {DEPTH{1'b0}};
+//    end
+//    else if(|(trace_pedge)  == 1'b1) begin
+//      if(fifo_wp == (FIFO_SIZE - 1)) begin
+//        fifo_wp <= {DEPTH{1'b0}};
+//      end
+//      else begin
+//        fifo_wp <= fifo_wp + 1;
+//      end
+//    end
+//  end
+
+
+  // fifo read pointer update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_rp <= {DEPTH{1'b0}};
+      fifo_re <= 1'b0;
+    end
+    else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
+      fifo_re <= 1'b1;
+      if(fifo_rp == (FIFO_SIZE - 1)) begin
+        fifo_rp <= {DEPTH{1'b0}};
+      end
+      else begin
+        fifo_rp <= fifo_rp + 1;
+      end
+    end
+    else begin
+      fifo_re <= 1'b0;
+    end
+  end
+  
+  // delay counter update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      dly_ctr <= 5'h0;
+    end
+    else if (fifo_re == 1'b1) begin
+      dly_ctr <= C_DELAY_CLKS-1;
+    end
+    else if(dly_ctr != 5'h0) begin
+      dly_ctr <= dly_ctr - 1;
+    end
+  end
+
+  // fifo empty update
+  assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
+
+  // fifo full update
+  assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
+
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_full_reg <= 1'b0;
+    end
+    else if (fifo_empty) begin
+      fifo_full_reg <= 1'b0;
+	 end else begin	
+      fifo_full_reg <= fifo_full;
+    end
+  end  
+  
+//  always @(posedge TRACE_CLK) begin
+//    if(RST == 1'b1) begin
+//      fifo_full_reg <= 1'b0;
+//    end
+//    else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
+//      fifo_full_reg <= 1'b1;
+//    end
+//	 else begin
+//        fifo_full_reg <= 1'b0;
+//    end
+//  end  
+//  
+  assign TRACE_DATA_OUT     = tom;
+  
+  assign TRACE_VALID_OUT    = fifo_re;  
+  
+  
+
+
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v
new file mode 100644
index 0000000..8b19a70
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v
@@ -0,0 +1,244 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   w_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_w_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_WUSER_WIDTH                = 1
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface (In)
+   input  wire                                  cmd_w_valid,
+   input  wire                                  cmd_w_check,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   output wire                                  cmd_w_ready,
+   
+   // Command Interface (Out)
+   output wire                                  cmd_b_push,
+   output wire                                  cmd_b_error,
+   output reg  [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   input  wire                                  cmd_b_full,
+   
+   // Slave Interface Write Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detecttion.
+  wire                                any_strb_deasserted;
+  wire                                incoming_strb_issue;
+  reg                                 first_word;
+  reg                                 strb_issue;
+  
+  // Data flow.
+  wire                                data_pop;
+  wire                                cmd_b_push_blocked;
+  reg                                 cmd_b_push_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Detect error:
+  //
+  // Detect and accumulate error when a transaction shall be scanned for
+  // potential issues.
+  // Accumulation of error is restarted for each ne transaction. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Check stobe information
+  assign any_strb_deasserted  = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
+  assign incoming_strb_issue  = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
+  
+  // Keep track of first word in a transaction.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      first_word  <= 1'b1;
+    end else if ( data_pop ) begin
+      first_word  <= S_AXI_WLAST;
+    end
+  end
+  
+  // Keep track of error status.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      strb_issue  <= 1'b0;
+      cmd_b_id    <= {C_AXI_ID_WIDTH{1'b0}};
+    end else if ( data_pop ) begin
+      if ( first_word ) begin
+        strb_issue  <= incoming_strb_issue;
+      end else begin
+        strb_issue  <= incoming_strb_issue | strb_issue;
+      end
+      cmd_b_id    <= cmd_w_id;
+    end
+  end
+  
+  assign cmd_b_error  = strb_issue;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Control command queue to B:
+  //
+  // Push command to B queue when all data for the transaction has flowed  
+  // through.
+  // Delay pipelined command until there is room in the Queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detect when data is popped.
+  assign data_pop   = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; 
+  
+  // Push command when last word in transfered (pipelined).
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_push_i  <= 1'b0;
+    end else begin
+      cmd_b_push_i  <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
+    end
+  end
+  
+  // Detect if pipelined push is blocked.
+  assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
+  
+  // Assign output.
+  assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full or there is no valid command information 
+  // from AW. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_WVALID   = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // Return ready with push back.
+  assign S_AXI_WREADY   = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // End of burst.
+  assign cmd_w_ready    = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_WID      = S_AXI_WID;
+  assign M_AXI_WDATA    = S_AXI_WDATA;
+  assign M_AXI_WSTRB    = S_AXI_WSTRB;
+  assign M_AXI_WLAST    = S_AXI_WLAST;
+  assign M_AXI_WUSER    = S_AXI_WUSER;
+  
+  
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv
new file mode 100644
index 0000000..25c9dd1
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/a16a/hdl/axi_vip_v1_1_vl_rfs.sv
@@ -0,0 +1,728 @@
+//  (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// AXI VIP wrapper
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axi_vip
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_vip_v1_1_1_top #
+  (
+   parameter C_AXI_PROTOCOL                      = 0,
+   parameter C_AXI_INTERFACE_MODE                = 1,  //master, slave and bypass
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_WDATA_WIDTH           = 32,
+   parameter integer C_AXI_RDATA_WIDTH           = 32,
+   parameter integer C_AXI_WID_WIDTH             = 0,
+   parameter integer C_AXI_RID_WIDTH             = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 0,
+   parameter integer C_AXI_ARUSER_WIDTH          = 0,
+   parameter integer C_AXI_WUSER_WIDTH           = 0,
+   parameter integer C_AXI_RUSER_WIDTH           = 0,
+   parameter integer C_AXI_BUSER_WIDTH           = 0,
+   parameter integer C_AXI_SUPPORTS_NARROW       = 1,
+   parameter integer C_AXI_HAS_BURST             = 1,
+   parameter integer C_AXI_HAS_LOCK              = 1,
+   parameter integer C_AXI_HAS_CACHE             = 1,
+   parameter integer C_AXI_HAS_REGION            = 1,
+   parameter integer C_AXI_HAS_PROT              = 1,
+   parameter integer C_AXI_HAS_QOS               = 1,
+   parameter integer C_AXI_HAS_WSTRB             = 1,
+   parameter integer C_AXI_HAS_BRESP             = 1,
+   parameter integer C_AXI_HAS_RRESP             = 1,
+   parameter integer C_AXI_HAS_ARESETN           = 1
+   )
+  (
+   //NOTE:  C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
+   //Please refer xgui tcl and coreinfo.yml
+   
+   // System Signals
+   input wire aclk,
+   input wire aclken,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_awaddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_awlen,
+   input  wire [3-1:0]                                             s_axi_awsize,
+   input  wire [2-1:0]                                             s_axi_awburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_awlock,
+   input  wire [4-1:0]                                             s_axi_awcache,
+   input  wire [3-1:0]                                             s_axi_awprot,
+   input  wire [4-1:0]                                             s_axi_awregion,
+   input  wire [4-1:0]                                             s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    s_axi_awuser,
+   input  wire                                                     s_axi_awvalid,
+   output wire                                                     s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_wid,
+   input  wire [C_AXI_WDATA_WIDTH-1:0]                             s_axi_wdata,
+   input  wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                                                     s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      s_axi_wuser,
+   input  wire                                                     s_axi_wvalid,
+   output wire                                                     s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_bid,
+   output wire [2-1:0]                                             s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,
+   output wire                                                     s_axi_bvalid,
+   input  wire                                                     s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_araddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_arlen,
+   input  wire [3-1:0]                                             s_axi_arsize,
+   input  wire [2-1:0]                                             s_axi_arburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_arlock,
+   input  wire [4-1:0]                                             s_axi_arcache,
+   input  wire [3-1:0]                                             s_axi_arprot,
+   input  wire [4-1:0]                                             s_axi_arregion,
+   input  wire [4-1:0]                                             s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    s_axi_aruser,
+   input  wire                                                     s_axi_arvalid,
+   output wire                                                     s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_rid,
+   output wire [C_AXI_RDATA_WIDTH-1:0]                             s_axi_rdata,
+   output wire [2-1:0]                                             s_axi_rresp,
+   output wire                                                     s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,
+   output wire                                                     s_axi_rvalid,
+   input  wire                                                     s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]                              m_axi_awaddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_awlen,
+   output wire [3-1:0]                                             m_axi_awsize,
+   output wire [2-1:0]                                             m_axi_awburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_awlock,
+   output wire [4-1:0]                                             m_axi_awcache,
+   output wire [3-1:0]                                             m_axi_awprot,
+   output wire [4-1:0]                                             m_axi_awregion,
+   output wire [4-1:0]                                             m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    m_axi_awuser,
+   output wire                                                     m_axi_awvalid,
+   input  wire                                                     m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_wid,
+   output wire [C_AXI_WDATA_WIDTH-1:0]                             m_axi_wdata,
+   output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                                                     m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,
+   output wire                                                     m_axi_wvalid,
+   input  wire                                                     m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_bid,
+   input  wire [2-1:0]                                             m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      m_axi_buser,
+   input  wire                                                     m_axi_bvalid,
+   output wire                                                     m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_arid,
+   output wire [ C_AXI_ADDR_WIDTH-1:0]                             m_axi_araddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_arlen,
+   output wire [3-1:0]                                             m_axi_arsize,
+   output wire [2-1:0]                                             m_axi_arburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_arlock,
+   output wire [4-1:0]                                             m_axi_arcache,
+   output wire [3-1:0]                                             m_axi_arprot,
+   output wire [4-1:0]                                             m_axi_arregion,
+   output wire [4-1:0]                                             m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    m_axi_aruser,
+   output wire                                                     m_axi_arvalid,
+   input  wire                                                     m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_rid,
+   input  wire [C_AXI_RDATA_WIDTH-1:0]                             m_axi_rdata,
+   input  wire [2-1:0]                                             m_axi_rresp,
+   input  wire                                                     m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      m_axi_ruser,
+   input  wire                                                     m_axi_rvalid,
+   output wire                                                     m_axi_rready
+  );
+   
+  /**********************************************************************************************
+  * NOTE:  
+  *   C_AXI_INTERFACE_MODE =0 -- MASTER MODE, 
+  *   C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE 
+  *   C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
+  *   Please refer xgui tcl and coreinfo.yml
+  *   User can change PASS_THROUGH VIP to run time master mode or run time slave mode during 
+  *   the simulation 
+  *********************************************************************************************/
+
+  /**********************************************************************************************
+  * Master_mode means that either the dut is statically being configured to be in master mode
+  * or it statically being configured to be pass-through mode and switched to be in master mode
+  * in run time. 
+   
+  * Slave mode means that either the dut is statically being configured to be in slave mode
+  * or it statically being configured to be pass-through mode and switched to be in slave mode
+  * in run time. 
+
+   * Pass-through mode means that either the dut is statically being configured to be in
+   * pass-through mode or it statically being configured to be pass-through mode and switched
+   * to be in master/slave mode and then switch back to be in pass-through mode in run time
+  *********************************************************************************************/
+
+  logic runtime_master =0;
+  logic runtime_slave =0;
+
+  wire run_slave_mode;
+  wire run_master_mode;
+  wire run_passth_mode;
+  wire compile_master_mode;
+  wire compile_slave_mode;
+  wire master_mode;
+  wire slave_mode;
+
+  assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
+  assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
+  assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
+
+  assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;   
+  assign compile_slave_mode  = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
+
+  assign master_mode = compile_master_mode || run_master_mode; 
+  assign slave_mode = compile_slave_mode || run_slave_mode;
+
+  // Slave Interface Write Address Ports Internal
+  assign IF.AWID        = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.AWADDR      = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
+  assign IF.AWLEN       = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.AWSIZE      = slave_mode? s_axi_awsize : {3{1'bz}};
+  assign IF.AWBURST     = slave_mode? s_axi_awburst : {2{1'bz}};
+  assign IF.AWLOCK      = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.AWCACHE     = slave_mode? s_axi_awcache : {4{1'bz}};
+  assign IF.AWPROT      = slave_mode? s_axi_awprot : {3{1'bz}};
+  assign IF.AWREGION    = slave_mode? s_axi_awregion : {4{1'bz}};
+  assign IF.AWQOS       = slave_mode? s_axi_awqos : {4{1'bz}};
+  assign IF.AWUSER      = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
+  assign IF.AWVALID     = slave_mode? s_axi_awvalid : {1'bz};
+  assign s_axi_awready  = slave_mode? IF.AWREADY : {1'b0};
+
+  // Slave Interface Write Data Ports  
+  assign IF.WID         = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.WDATA       = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
+  assign IF.WSTRB       = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
+  assign IF.WLAST       = slave_mode? s_axi_wlast: {1'bz};
+  assign IF.WUSER       = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
+  assign IF.WVALID      = slave_mode? s_axi_wvalid : {1'bz}; 
+  assign s_axi_wready   = slave_mode? IF.WREADY : {1'b0};
+
+  // Slave Interface Write Response Ports
+  assign s_axi_bid      = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign s_axi_bresp    = slave_mode? IF.BRESP : {2{1'b0}};
+  assign s_axi_buser    = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
+  assign s_axi_bvalid   = slave_mode? IF.BVALID : {1{1'b0}};
+  assign IF.BREADY      = slave_mode? s_axi_bready :{1{1'bz}};
+
+  // Slave Interface Read Address Ports 
+  assign IF.ARID        = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.ARADDR      = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
+  assign IF.ARLEN       = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.ARSIZE      = slave_mode? s_axi_arsize : {3{1'bz}};
+  assign IF.ARBURST     = slave_mode? s_axi_arburst : {2{1'bz}};
+  assign IF.ARLOCK      = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.ARCACHE     = slave_mode? s_axi_arcache : {4{1'bz}};
+  assign IF.ARPROT      = slave_mode? s_axi_arprot : {3{1'bz}};
+  assign IF.ARREGION    = slave_mode? s_axi_arregion :{4{1'bz}} ;
+  assign IF.ARQOS       = slave_mode? s_axi_arqos : {4{1'bz}};
+  assign IF.ARUSER      = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
+  assign IF.ARVALID     = slave_mode? s_axi_arvalid : {1'bz};
+  assign s_axi_arready  = slave_mode? IF.ARREADY : {1'b0};
+
+  //Slave Interface Read Data Ports 
+  assign s_axi_rid      = slave_mode?  IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign s_axi_rdata    = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
+  assign s_axi_rresp    = slave_mode? IF.RRESP : {2{1'b0}};
+  assign s_axi_rlast    = slave_mode? IF.RLAST : {{1'b0}};
+  assign s_axi_ruser    = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
+  assign s_axi_rvalid   = slave_mode? IF.RVALID : {{1'b0}};
+  assign IF.RREADY      = slave_mode? s_axi_rready:{{1'bz}};
+
+  // Master Interface Write Address Port 
+  assign m_axi_awid     = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_awaddr   = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_awlen    = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_awsize   = master_mode? IF.AWSIZE : {3{1'b0}};
+  assign m_axi_awburst  = master_mode? IF.AWBURST : {2{1'b0}};
+  assign m_axi_awlock   = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_awcache  = master_mode? IF.AWCACHE : {4{1'b0}};
+  assign m_axi_awprot   = master_mode? IF.AWPROT : {3{1'b0}};
+  assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
+  assign m_axi_awqos    = master_mode? IF.AWQOS : {4{1'b0}};
+  assign m_axi_awuser   = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
+  assign m_axi_awvalid  = master_mode? IF.AWVALID :{1'b0};
+  assign IF.AWREADY     = master_mode? m_axi_awready :{1'bz};
+
+  // Master Interface Write Data Ports Internal
+  assign m_axi_wid      = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_wdata    = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
+  assign m_axi_wstrb    = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
+  assign m_axi_wlast    = master_mode? IF.WLAST : {1'b0};
+  assign m_axi_wuser    = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
+  assign m_axi_wvalid   = master_mode? IF.WVALID : {1'b0};
+  assign IF.WREADY      = master_mode? m_axi_wready : {1'bz};
+
+  // Master Interface Write Response Ports Internal
+  assign IF.BID        = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.BRESP      = master_mode? m_axi_bresp : {2{1'bz}};
+  assign IF.BUSER      = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
+  assign IF.BVALID     = master_mode? m_axi_bvalid : 1'bz;
+  assign m_axi_bready  = master_mode? IF.BREADY : 1'b0;
+
+  // Master Interface Read Address Port Internal
+  assign m_axi_arid     = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign m_axi_araddr   = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_arlen    = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_arsize   = master_mode? IF.ARSIZE : {3{1'b0}};
+  assign m_axi_arburst  = master_mode? IF.ARBURST : {2{1'b0}};
+  assign m_axi_arlock   = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_arcache  = master_mode?IF.ARCACHE : {4{1'b0}};
+  assign m_axi_arprot   = master_mode? IF.ARPROT : {3{1'b0}};
+  assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
+  assign m_axi_arqos    = master_mode? IF.ARQOS : {4{1'b0}};
+  assign m_axi_aruser   = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
+  assign m_axi_arvalid  = master_mode? IF.ARVALID :{1'b0};
+  assign IF.ARREADY     = master_mode? m_axi_arready : {1{1'bz}};
+
+  // Master Interface Read Data Ports Internal
+  assign IF.RID        = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.RDATA      = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
+  assign IF.RRESP      = master_mode? m_axi_rresp : {2{1'bz}};
+  assign IF.RLAST      = master_mode? m_axi_rlast : {1{1'bz}};
+  assign IF.RUSER      = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
+  assign IF.RVALID     = master_mode? m_axi_rvalid : {1{1'bz}};
+  assign m_axi_rready  = master_mode? IF.RREADY : {1{1'b0}};
+
+  axi_vip_if #(
+    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),
+    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
+    .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
+    .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
+    .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
+    .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), 
+    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), 
+    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
+    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
+    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
+    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
+    .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
+    .C_AXI_HAS_BURST(C_AXI_HAS_BURST),
+    .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
+    .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
+    .C_AXI_HAS_REGION(C_AXI_HAS_REGION),
+    .C_AXI_HAS_PROT(C_AXI_HAS_PROT),
+    .C_AXI_HAS_QOS(C_AXI_HAS_QOS),
+    .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
+    .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
+    .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
+    .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
+  ) IF (
+    .ACLK(aclk),
+    .ARESET_N(aresetn),
+    .ACLKEN(aclken)
+  );  
+
+`ifdef XILINX_SIMULATOR 
+  generate 
+    if(C_AXI_WID_WIDTH <16) begin
+      axi_protocol_checker_v2_0_1_top #(
+            .C_AXI_PROTOCOL(C_AXI_PROTOCOL), 
+            .C_AXI_ID_WIDTH(C_AXI_WID_WIDTH ==0 ? 1: C_AXI_WID_WIDTH  ) ,
+            .C_AXI_DATA_WIDTH(C_AXI_WDATA_WIDTH) ,
+            .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH) ,
+            .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ==0 ? 1: C_AXI_AWUSER_WIDTH ) ,
+            .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ==0 ?1 : C_AXI_WUSER_WIDTH ) ,
+            .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ==0 ? 1: C_AXI_BUSER_WIDTH) ,
+            .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ==0 ? 1: C_AXI_ARUSER_WIDTH) ,
+            .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ==0 ? 1:C_AXI_RUSER_WIDTH )  ,
+            .C_HAS_WSTRB(C_AXI_HAS_WSTRB),
+            .C_PC_MAXRBURSTS            ( 64),
+            .C_PC_MAXWBURSTS            ( 64),
+            .C_PC_EXMON_WIDTH           ( 0),
+            .C_PC_AW_MAXWAITS               ( 0),
+            .C_PC_AR_MAXWAITS               ( 0),
+            .C_PC_W_MAXWAITS                ( 0),
+            .C_PC_R_MAXWAITS                ( 0),
+            .C_PC_B_MAXWAITS                ( 0),
+            .C_PC_MESSAGE_LEVEL             ( 2),
+            .C_PC_SUPPORTS_NARROW_BURST     (C_AXI_SUPPORTS_NARROW),
+            .C_PC_MAX_BURST_LENGTH          ( 256),
+            .C_PC_HAS_SYSTEM_RESET          ( 0),
+            .C_PC_STATUS_WIDTH              ( 97)
+      ) PC (
+            .pc_status(),
+            .pc_asserted(), 
+            .system_resetn(aresetn),
+        //AXI CLK
+            .aclk(aclk),
+        //AXI Reset
+            .aresetn(aresetn),
+        //AXI Write Address
+            .pc_axi_awid(IF.awid_internal),
+            .pc_axi_awaddr(IF.AWADDR),
+            .pc_axi_awlen(IF.awlen_internal[(C_AXI_PROTOCOL ==1 ?3: 7):0]),
+            .pc_axi_awsize(IF.awsize_internal),
+            .pc_axi_awburst(IF.awburst_internal),
+            .pc_axi_awlock(IF.awlock_internal[(C_AXI_PROTOCOL ==1 ?1: 0):0]  ),
+            .pc_axi_awcache(IF.awcache_internal),
+            .pc_axi_awprot(IF.AWPROT),
+            .pc_axi_awqos(IF.awqos_internal),
+            .pc_axi_awregion(IF.awregion_internal),
+            .pc_axi_awuser(IF.AWUSER),
+            .pc_axi_awvalid(IF.awvalid_internal),
+            .pc_axi_awready(IF.awready_internal),
+        //AXI Write Data
+            .pc_axi_wid(IF.wid_internal),
+            .pc_axi_wlast(IF.wlast_internal),
+            .pc_axi_wdata(IF.WDATA),
+            .pc_axi_wstrb(IF.WSTRB),
+            .pc_axi_wuser(IF.WUSER),
+            .pc_axi_wvalid(IF.wvalid_internal),
+            .pc_axi_wready(IF.wready_internal),
+        //AXI Write Response
+            .pc_axi_bid(IF.bid_internal),
+            .pc_axi_bresp(IF.BRESP),
+            .pc_axi_buser(IF.BUSER),
+            .pc_axi_bvalid(IF.bvalid_internal),
+            .pc_axi_bready(IF.bready_internal),
+        //AXI Read Address
+            .pc_axi_arid(IF.arid_internal),
+            .pc_axi_araddr(IF.ARADDR),
+            .pc_axi_arlen(IF.arlen_internal[(C_AXI_PROTOCOL ==1 ?3: 7):0]  ),
+            .pc_axi_arsize(IF.arsize_internal),
+            .pc_axi_arburst(IF.arburst_internal),
+            .pc_axi_arlock(IF.arlock_internal[(C_AXI_PROTOCOL ==1 ?1: 0):0] ),
+            .pc_axi_arcache(IF.arcache_internal),
+            .pc_axi_arprot(IF.ARPROT),
+            .pc_axi_arqos(IF.arqos_internal),
+            .pc_axi_arregion(IF.arregion_internal),
+            .pc_axi_aruser(IF.ARUSER ),
+            .pc_axi_arvalid(IF.arvalid_internal),
+            .pc_axi_arready(IF.arready_internal),
+        //AXI Read Data
+           .pc_axi_rid(IF.rid_internal),
+           .pc_axi_rlast(IF.rlast_internal),
+           .pc_axi_rdata(IF.RDATA),
+           .pc_axi_rresp (IF.RRESP ),
+           .pc_axi_ruser(IF.RUSER ),
+           .pc_axi_rvalid(IF.rvalid_internal),
+           .pc_axi_rready(IF.rready_internal)
+      );
+    end  
+  endgenerate
+`endif
+  //synthesis translate_off
+  initial begin
+    `ifdef XILINX_SIMULATOR 
+      if(C_AXI_WID_WIDTH >=16) begin
+       $display("INFO: ID width is %0d bigger than 16, AXI protocol Checker will not be instantiated in this case ",C_AXI_WID_WIDTH);
+      end
+    `endif
+    $display("XilinxAXIVIP: Found at Path: %m");
+  end
+
+  //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode  
+  generate
+    initial begin
+      if(C_AXI_INTERFACE_MODE ==0) begin
+        IF.set_intf_master;
+      end else if(C_AXI_INTERFACE_MODE ==2) begin
+        IF.set_intf_slave;
+      end else if(C_AXI_INTERFACE_MODE ==1) begin
+        $display("This AXI VIP is in passthrough mode");
+      end else begin
+        $fatal(0,"This AXI VIP's mode is out of range");
+      end
+    end  
+  endgenerate
+
+  /*
+   Function: set_passthrough_mode
+   Sets AXI VIP passthrough into run time passthrough mode
+  */
+  function void set_passthrough_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 0;
+      IF.set_intf_monitor();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction: set_passthrough_mode
+
+  /*
+   Function: set_master_mode
+   Sets AXI VIP passthrough into run time master mode
+  */
+  function void set_master_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 1;
+      runtime_slave = 0;
+      IF.set_intf_master();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
+    end
+  endfunction : set_master_mode
+
+  /*
+   Function: set_slave_mode
+   Sets AXI VIP passthrough into run time slave mode
+  */
+  function void set_slave_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 1;
+      IF.set_intf_slave();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete  non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction : set_slave_mode
+
+  /*
+  Function: set_xilinx_slave_ready_check
+  Sets xilinx_slave_ready_check_enable of IF to be 1
+  */
+  function void set_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 1;
+  endfunction
+
+  /*
+   Function: clr_xilinx_slave_ready_check
+   Sets xilinx_slave_ready_check_enable of IF to be 0
+  */
+  function void clr_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 0;
+  endfunction
+
+ `ifndef XILINX_SIMULATOR
+  /*
+   Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Sets max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_aw_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_aw_wait_cycles = new_num;
+  endfunction : set_max_aw_wait_cycles
+
+  /*
+   Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Sets max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_ar_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_ar_wait_cycles = new_num;
+  endfunction : set_max_ar_wait_cycles
+
+  /*
+   Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
+   Sets max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_r_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_r_wait_cycles = new_num;
+  endfunction : set_max_r_wait_cycles
+
+  /*
+   Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
+   Sets max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_b_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_b_wait_cycles = new_num;
+  endfunction : set_max_b_wait_cycles
+
+  /*
+   Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
+   Sets max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_w_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_w_wait_cycles = new_num;
+  endfunction : set_max_w_wait_cycles
+
+  /*
+   Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlast_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
+  endfunction : set_max_wlast_wait_cycles
+
+  /*
+   Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_rtransfers_wait_cycles = new_num;
+  endfunction : set_max_rtransfers_wait_cycles
+
+  /*
+   Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wtransfers_wait_cycles = new_num;
+  endfunction : set_max_wtransfers_wait_cycles
+
+  /*
+   Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlcmd_wait_cycles = new_num;
+  endfunction : set_max_wlcmd_wait_cycles
+
+  /*
+   Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Returns max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_aw_wait_cycles();
+    return(IF.PC.max_aw_wait_cycles);
+  endfunction : get_max_aw_wait_cycles
+
+  /*
+   Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Returns max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_ar_wait_cycles();
+    return(IF.PC.max_ar_wait_cycles);
+  endfunction : get_max_ar_wait_cycles
+
+  /*
+   Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
+   Returns max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_r_wait_cycles();
+    return(IF.PC.max_r_wait_cycles);
+  endfunction : get_max_r_wait_cycles
+
+  /*
+   Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
+   Returns max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_b_wait_cycles();
+    return(IF.PC.max_b_wait_cycles);
+  endfunction : get_max_b_wait_cycles
+
+  /*
+   Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
+   Returns max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_w_wait_cycles();
+    return(IF.PC.max_w_wait_cycles);
+  endfunction :get_max_w_wait_cycles
+
+  /*
+   Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlast_wait_cycles();
+    return(IF.PC.max_wlast_to_awvalid_wait_cycles);
+  endfunction :get_max_wlast_wait_cycles
+
+  /*
+   Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_rtransfers_wait_cycles();
+    return(IF.PC.max_rtransfers_wait_cycles);
+  endfunction :get_max_rtransfers_wait_cycles
+
+  /*
+   Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wtransfers_wait_cycles();
+    return(IF.PC.max_wtransfers_wait_cycles);
+  endfunction :get_max_wtransfers_wait_cycles
+
+  /*
+   Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlcmd_wait_cycles();
+    return(IF.PC.max_wlcmd_wait_cycles);
+  endfunction :get_max_wlcmd_wait_cycles
+
+  /*
+   Function:  set_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
+  */
+  function void set_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 1;
+  endfunction : set_fatal_to_warnings
+
+  /*
+   Function:   clr_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
+  */
+  function void clr_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 0;
+  endfunction : clr_fatal_to_warnings
+`endif
+  //synthesis translate_on
+
+endmodule // axi_vip_v1_1_1_top
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh
new file mode 100644
index 0000000..d3d4a0e
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh
@@ -0,0 +1,138 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXI Infrastructure Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//
+// Tasks:
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+localparam G_AXI_AWADDR_INDEX   = 0;
+localparam G_AXI_AWADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_AWPROT_INDEX   = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
+localparam G_AXI_AWPROT_WIDTH   = 3;
+localparam G_AXI_AWSIZE_INDEX   = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
+localparam G_AXI_AWSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_AWBURST_INDEX  = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
+localparam G_AXI_AWBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_AWCACHE_INDEX  = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
+localparam G_AXI_AWCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWLEN_INDEX    = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
+localparam G_AXI_AWLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_AWLOCK_INDEX   = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
+localparam G_AXI_AWLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_AWID_INDEX     = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
+localparam G_AXI_AWID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_AWQOS_INDEX    = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
+localparam G_AXI_AWQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
+localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_AWUSER_INDEX   = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
+localparam G_AXI_AWUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
+localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
+localparam G_AXI_ARADDR_INDEX   = 0;
+localparam G_AXI_ARADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_ARPROT_INDEX   = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
+localparam G_AXI_ARPROT_WIDTH   = 3;
+localparam G_AXI_ARSIZE_INDEX   = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
+localparam G_AXI_ARSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_ARBURST_INDEX  = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
+localparam G_AXI_ARBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_ARCACHE_INDEX  = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
+localparam G_AXI_ARCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARLEN_INDEX    = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
+localparam G_AXI_ARLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_ARLOCK_INDEX   = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
+localparam G_AXI_ARLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_ARID_INDEX     = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
+localparam G_AXI_ARID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_ARQOS_INDEX    = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
+localparam G_AXI_ARQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
+localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_ARUSER_INDEX   = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
+localparam G_AXI_ARUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
+localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
+// Write channel widths
+localparam G_AXI_WDATA_INDEX    = 0;
+localparam G_AXI_WDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_WSTRB_INDEX    = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
+localparam G_AXI_WSTRB_WIDTH    = C_AXI_DATA_WIDTH / 8;
+localparam G_AXI_WLAST_INDEX    = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
+localparam G_AXI_WLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_WID_INDEX      = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
+localparam G_AXI_WID_WIDTH      = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_WUSER_INDEX    = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
+localparam G_AXI_WUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
+localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
+// Write Response channel Widths
+localparam G_AXI_BRESP_INDEX    = 0;
+localparam G_AXI_BRESP_WIDTH    = 2;
+localparam G_AXI_BID_INDEX      = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
+localparam G_AXI_BID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_BUSER_INDEX    = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
+localparam G_AXI_BUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
+localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
+// Read channel widths
+localparam G_AXI_RDATA_INDEX    = 0;
+localparam G_AXI_RDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_RRESP_INDEX    = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
+localparam G_AXI_RRESP_WIDTH    = 2;
+localparam G_AXI_RLAST_INDEX    = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
+localparam G_AXI_RLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_RID_INDEX      = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
+localparam G_AXI_RID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_RUSER_INDEX    = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
+localparam G_AXI_RUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
+localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
new file mode 100644
index 0000000..d6ec7f8
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
@@ -0,0 +1,670 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axis to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axi2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+  input  wire [3-1:0]                               s_axi_awsize,
+  input  wire [2-1:0]                               s_axi_awburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+  input  wire [4-1:0]                               s_axi_awcache,
+  input  wire [3-1:0]                               s_axi_awprot,
+  input  wire [4-1:0]                               s_axi_awregion,
+  input  wire [4-1:0]                               s_axi_awqos,
+  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,
+  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,
+  input  wire                                       s_axi_wlast,
+  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,
+  output wire [2-1:0]                               s_axi_bresp,
+  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,
+
+   // Slave Interface Read Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+  input  wire [3-1:0]                               s_axi_arsize,
+  input  wire [2-1:0]                               s_axi_arburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+  input  wire [4-1:0]                               s_axi_arcache,
+  input  wire [3-1:0]                               s_axi_arprot,
+  input  wire [4-1:0]                               s_axi_arregion,
+  input  wire [4-1:0]                               s_axi_arqos,
+  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,
+  output wire [2-1:0]                               s_axi_rresp,
+  output wire                                       s_axi_rlast,
+  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,
+
+  // payloads
+  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,
+  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,
+  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,
+  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,
+  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
+assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
+
+assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
+assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
+
+assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
+
+assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
+assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
+
+assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
+assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;
+    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
+    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
+    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;
+    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;
+    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;
+    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;
+
+    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;
+    end
+    else begin : gen_no_axi3_wid_packing
+    end
+
+    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
+
+    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;
+    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
+    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
+    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;
+    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;
+    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;
+    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;
+
+    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
+    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
+      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
+    end 
+    else begin : gen_no_region_signals
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
+      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;
+      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
+      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
+      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
+    end 
+    else begin : gen_no_user_signals
+      assign s_axi_buser = 'b0;
+      assign s_axi_ruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign s_axi_bid = 'b0;
+    assign s_axi_buser = 'b0;
+
+    assign s_axi_rlast = 1'b1;
+    assign s_axi_rid   = 'b0;
+    assign s_axi_ruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+// Description: SRL based FIFO for AXIS/AXI Channels.
+//--------------------------------------------------------------------------
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axic_srl_fifo #(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY     = "virtex7",
+  parameter integer C_PAYLOAD_WIDTH = 1,
+  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                        aclk,    // Clock
+  input  wire                        aresetn,  // Reset
+  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data
+  input  wire                        s_valid, // Input data valid
+  output reg                         s_ready, // Input data ready
+  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data
+  output reg                         m_valid, // Output data valid
+  input  wire                        m_ready  // Output data ready
+);
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+function integer f_clogb2 (input integer size);
+  integer s;
+  begin
+    s = size;
+    s = s - 1;
+    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+          s = s >> 1;
+  end
+endfunction // clogb2
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;
+wire [4-1:0]                        fifo_addr;
+wire                                push;
+wire                                pop ;
+reg                                 areset_r1;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin 
+  areset_r1 <= ~aresetn;
+end
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin
+    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
+  end
+  else begin
+    fifo_index <= push & ~pop ? fifo_index + 1'b1 :
+                  ~push & pop ? fifo_index - 1'b1 : 
+                  fifo_index;
+  end
+end
+
+assign push = s_valid & s_ready;
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    s_ready <= 1'b0;
+  end
+  else begin 
+    s_ready <= areset_r1 ? 1'b1 : 
+               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
+               ~push & pop ? 1'b1 : 
+               s_ready;
+  end
+end
+
+assign pop = m_valid & m_ready;
+               
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    m_valid <= 1'b0;
+  end
+  else begin 
+    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
+               push & ~pop ? 1'b1 : 
+               m_valid;
+  end
+end
+
+generate 
+  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
+    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
+  end
+  else begin : gen_fifo_addr
+    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+  end
+endgenerate
+
+
+generate
+  genvar i;
+  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
+    SRL16E 
+    u_srl_fifo(
+      .Q   ( m_payload[i] ) ,
+      .A0  ( fifo_addr[0]     ) ,
+      .A1  ( fifo_addr[1]     ) ,
+      .A2  ( fifo_addr[2]     ) ,
+      .A3  ( fifo_addr[3]     ) ,
+      .CE  ( push              ) ,
+      .CLK ( aclk              ) ,
+      .D   ( s_payload[i] ) 
+    );
+  end
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axi to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_vector2axi #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+  output wire [3-1:0]                               m_axi_awsize,
+  output wire [2-1:0]                               m_axi_awburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+  output wire [4-1:0]                               m_axi_awcache,
+  output wire [3-1:0]                               m_axi_awprot,
+  output wire [4-1:0]                               m_axi_awregion,
+  output wire [4-1:0]                               m_axi_awqos,
+  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,
+  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,
+  output wire                                       m_axi_wlast,
+  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,
+  input  wire [2-1:0]                               m_axi_bresp,
+  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,
+
+   // Slave Interface Read Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+  output wire [3-1:0]                               m_axi_arsize,
+  output wire [2-1:0]                               m_axi_arburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+  output wire [4-1:0]                               m_axi_arcache,
+  output wire [3-1:0]                               m_axi_arprot,
+  output wire [4-1:0]                               m_axi_arregion,
+  output wire [4-1:0]                               m_axi_arqos,
+  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,
+  input  wire [2-1:0]                               m_axi_rresp,
+  input  wire                                       m_axi_rlast,
+  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,
+
+  // payloads
+  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,
+  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,
+  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,
+  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,
+  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
+assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
+
+assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
+assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
+
+assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
+
+assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
+assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
+
+assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
+assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;
+    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
+    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
+    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;
+    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;
+    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;
+    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;
+
+    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;
+    end
+    else begin : gen_no_axi3_wid_packing
+      assign m_axi_wid = 1'b0;
+    end
+
+    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
+
+    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;
+    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
+    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
+    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;
+    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;
+    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;
+    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;
+
+    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
+    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
+      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
+    end 
+    else begin : gen_no_region_signals
+      assign m_axi_awregion = 'b0;
+      assign m_axi_arregion = 'b0;
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
+      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;
+      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;
+      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
+      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;
+    end 
+    else begin : gen_no_user_signals
+      assign m_axi_awuser = 'b0;
+      assign m_axi_wuser = 'b0;
+      assign m_axi_aruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_awburst = 'b0;
+    assign m_axi_awcache = 'b0;
+    assign m_axi_awlen = 'b0;
+    assign m_axi_awlock = 'b0;
+    assign m_axi_awid = 'b0;
+    assign m_axi_awqos = 'b0;
+
+    assign m_axi_wlast = 1'b1;
+    assign m_axi_wid = 'b0;
+
+
+    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_arburst = 'b0;
+    assign m_axi_arcache = 'b0;
+    assign m_axi_arlen = 'b0;
+    assign m_axi_arlock = 'b0;
+    assign m_axi_arid = 'b0;
+    assign m_axi_arqos = 'b0;
+
+    assign m_axi_awregion = 'b0;
+    assign m_axi_arregion = 'b0;
+
+    assign m_axi_awuser = 'b0;
+    assign m_axi_wuser = 'b0;
+    assign m_axi_aruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/sim/system.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/sim/system.v
new file mode 100644
index 0000000..355463b
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/sim/system.v
@@ -0,0 +1,115 @@
+//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
+//Date        : Sat May 25 13:08:00 2019
+//Host        : LB-201810041430 running 64-bit major release  (build 9200)
+//Command     : generate_target system.bd
+//Design      : system
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "system.hwdef" *) 
+module system
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb);
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
+
+  wire [14:0]processing_system7_0_DDR_ADDR;
+  wire [2:0]processing_system7_0_DDR_BA;
+  wire processing_system7_0_DDR_CAS_N;
+  wire processing_system7_0_DDR_CKE;
+  wire processing_system7_0_DDR_CK_N;
+  wire processing_system7_0_DDR_CK_P;
+  wire processing_system7_0_DDR_CS_N;
+  wire [3:0]processing_system7_0_DDR_DM;
+  wire [31:0]processing_system7_0_DDR_DQ;
+  wire [3:0]processing_system7_0_DDR_DQS_N;
+  wire [3:0]processing_system7_0_DDR_DQS_P;
+  wire processing_system7_0_DDR_ODT;
+  wire processing_system7_0_DDR_RAS_N;
+  wire processing_system7_0_DDR_RESET_N;
+  wire processing_system7_0_DDR_WE_N;
+  wire processing_system7_0_FCLK_CLK0;
+  wire processing_system7_0_FIXED_IO_DDR_VRN;
+  wire processing_system7_0_FIXED_IO_DDR_VRP;
+  wire [53:0]processing_system7_0_FIXED_IO_MIO;
+  wire processing_system7_0_FIXED_IO_PS_CLK;
+  wire processing_system7_0_FIXED_IO_PS_PORB;
+  wire processing_system7_0_FIXED_IO_PS_SRSTB;
+
+  system_processing_system7_0_0 processing_system7_0
+       (.DDR_Addr(DDR_addr[14:0]),
+        .DDR_BankAddr(DDR_ba[2:0]),
+        .DDR_CAS_n(DDR_cas_n),
+        .DDR_CKE(DDR_cke),
+        .DDR_CS_n(DDR_cs_n),
+        .DDR_Clk(DDR_ck_p),
+        .DDR_Clk_n(DDR_ck_n),
+        .DDR_DM(DDR_dm[3:0]),
+        .DDR_DQ(DDR_dq[31:0]),
+        .DDR_DQS(DDR_dqs_p[3:0]),
+        .DDR_DQS_n(DDR_dqs_n[3:0]),
+        .DDR_DRSTB(DDR_reset_n),
+        .DDR_ODT(DDR_odt),
+        .DDR_RAS_n(DDR_ras_n),
+        .DDR_VRN(FIXED_IO_ddr_vrn),
+        .DDR_VRP(FIXED_IO_ddr_vrp),
+        .DDR_WEB(DDR_we_n),
+        .FCLK_CLK0(processing_system7_0_FCLK_CLK0),
+        .MIO(FIXED_IO_mio[53:0]),
+        .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
+        .M_AXI_GP0_ARREADY(1'b0),
+        .M_AXI_GP0_AWREADY(1'b0),
+        .M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_BRESP({1'b0,1'b0}),
+        .M_AXI_GP0_BVALID(1'b0),
+        .M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_RLAST(1'b0),
+        .M_AXI_GP0_RRESP({1'b0,1'b0}),
+        .M_AXI_GP0_RVALID(1'b0),
+        .M_AXI_GP0_WREADY(1'b0),
+        .PS_CLK(FIXED_IO_ps_clk),
+        .PS_PORB(FIXED_IO_ps_porb),
+        .PS_SRSTB(FIXED_IO_ps_srstb));
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.hwdef b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.hwdef
new file mode 100644
index 0000000..c702c25
Binary files /dev/null and b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.hwdef differ
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v
new file mode 100644
index 0000000..355463b
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/synth/system.v
@@ -0,0 +1,115 @@
+//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
+//Date        : Sat May 25 13:08:00 2019
+//Host        : LB-201810041430 running 64-bit major release  (build 9200)
+//Command     : generate_target system.bd
+//Design      : system
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "system.hwdef" *) 
+module system
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb);
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
+  (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
+  (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
+
+  wire [14:0]processing_system7_0_DDR_ADDR;
+  wire [2:0]processing_system7_0_DDR_BA;
+  wire processing_system7_0_DDR_CAS_N;
+  wire processing_system7_0_DDR_CKE;
+  wire processing_system7_0_DDR_CK_N;
+  wire processing_system7_0_DDR_CK_P;
+  wire processing_system7_0_DDR_CS_N;
+  wire [3:0]processing_system7_0_DDR_DM;
+  wire [31:0]processing_system7_0_DDR_DQ;
+  wire [3:0]processing_system7_0_DDR_DQS_N;
+  wire [3:0]processing_system7_0_DDR_DQS_P;
+  wire processing_system7_0_DDR_ODT;
+  wire processing_system7_0_DDR_RAS_N;
+  wire processing_system7_0_DDR_RESET_N;
+  wire processing_system7_0_DDR_WE_N;
+  wire processing_system7_0_FCLK_CLK0;
+  wire processing_system7_0_FIXED_IO_DDR_VRN;
+  wire processing_system7_0_FIXED_IO_DDR_VRP;
+  wire [53:0]processing_system7_0_FIXED_IO_MIO;
+  wire processing_system7_0_FIXED_IO_PS_CLK;
+  wire processing_system7_0_FIXED_IO_PS_PORB;
+  wire processing_system7_0_FIXED_IO_PS_SRSTB;
+
+  system_processing_system7_0_0 processing_system7_0
+       (.DDR_Addr(DDR_addr[14:0]),
+        .DDR_BankAddr(DDR_ba[2:0]),
+        .DDR_CAS_n(DDR_cas_n),
+        .DDR_CKE(DDR_cke),
+        .DDR_CS_n(DDR_cs_n),
+        .DDR_Clk(DDR_ck_p),
+        .DDR_Clk_n(DDR_ck_n),
+        .DDR_DM(DDR_dm[3:0]),
+        .DDR_DQ(DDR_dq[31:0]),
+        .DDR_DQS(DDR_dqs_p[3:0]),
+        .DDR_DQS_n(DDR_dqs_n[3:0]),
+        .DDR_DRSTB(DDR_reset_n),
+        .DDR_ODT(DDR_odt),
+        .DDR_RAS_n(DDR_ras_n),
+        .DDR_VRN(FIXED_IO_ddr_vrn),
+        .DDR_VRP(FIXED_IO_ddr_vrp),
+        .DDR_WEB(DDR_we_n),
+        .FCLK_CLK0(processing_system7_0_FCLK_CLK0),
+        .MIO(FIXED_IO_mio[53:0]),
+        .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
+        .M_AXI_GP0_ARREADY(1'b0),
+        .M_AXI_GP0_AWREADY(1'b0),
+        .M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_BRESP({1'b0,1'b0}),
+        .M_AXI_GP0_BVALID(1'b0),
+        .M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .M_AXI_GP0_RLAST(1'b0),
+        .M_AXI_GP0_RRESP({1'b0,1'b0}),
+        .M_AXI_GP0_RVALID(1'b0),
+        .M_AXI_GP0_WREADY(1'b0),
+        .PS_CLK(FIXED_IO_ps_clk),
+        .PS_PORB(FIXED_IO_ps_porb),
+        .PS_SRSTB(FIXED_IO_ps_srstb));
+endmodule
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bd b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bd
new file mode 100644
index 0000000..79a7be1
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bd
@@ -0,0 +1,753 @@
+
+
+
+  
+    xilinx.com
+    BlockDiagram
+    system
+    1.00.a
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+      
+        isTop
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+    
+    
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+        DDR
+        
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+            CAN_DEBUG
+            false
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+              
+            
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+          
+            TIMEPERIOD_PS
+            1250
+            
+              
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+              
+            
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+            MEMORY_TYPE
+            COMPONENTS
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+            DATA_MASK_ENABLED
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+              
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+            Single
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+          
+          
+            MEM_ADDR_MAP
+            ROW_COLUMN_BANK
+            
+              
+                
+              
+            
+          
+          
+            BURST_LENGTH
+            8
+            
+              
+                
+              
+            
+          
+          
+            AXI_ARBITRATION_SCHEME
+            TDM
+            
+              
+                
+              
+            
+          
+          
+            CAS_LATENCY
+            11
+            
+              
+                
+              
+            
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+            CAS_WRITE_LATENCY
+            11
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+              
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+              
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+          :vivado.xilinx.com:
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+
+  
+    xilinx.com
+    BlockDiagram
+    system_imp
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+          0
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+          4
+          4
+          4
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+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          0
+          0
+          0
+          DIRECT
+          3
+          0
+          0
+          None
+          None
+          LVCMOS 3.3V
+          LVCMOS 1.8V
+          1
+          0
+          DDR 3
+          32 Bit
+          8
+          Normal (0-85)
+          MT41K256M16 RE-125
+          1
+          1
+          1
+          0
+          0
+          1
+          MIO 1 .. 6
+          1
+          MIO 1 .. 6
+          0
+          x4
+          0
+          1
+          MIO 8
+          0xFCFFFFFF
+          1
+          MIO 16 .. 27
+          1
+          MIO 52 .. 53
+          1
+          Share reset pin
+          0
+          0
+          1
+          MIO 40 .. 45
+          1
+          MIO 47
+          0
+          0
+          0
+          0
+          1
+          MIO 48 .. 49
+          0
+          0
+          0
+          0
+          0
+          0
+          2
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          1
+          0
+          1
+          MIO
+          0
+          6:2:1
+          1000 Mbps
+          ARM PLL
+          DDR PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          IO PLL
+          External
+          External
+          External
+          CPU_1X
+          CPU_1X
+          CPU_1X
+          CPU_1X
+          CPU_1X
+          CPU_1X
+          CPU_1X
+          DDR PLL
+          IO PLL
+          Active Low
+          Active Low
+          Active Low
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 3.3V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          enabled
+          LVCMOS 1.8V
+          slow
+          NA
+          GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0
+          gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio
+          PRODUCTION
+          1
+          1
+          1
+          1
+          1
+          11
+          11
+          0
+          1
+          1
+          1
+          1
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+          1
+          1
+          1
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+          1
+          1
+          11
+          11
+          0
+          1
+          1
+          1
+          1
+          1
+          11
+          11
+          NA
+          NA
+          NA
+          NA
+          NA
+          NA
+          NA
+          clg400
+          0
+        
+      
+    
+    
+    
+      
+        processing_system7_0_FCLK_CLK0
+        
+        
+      
+    
+    
+      
+        
+      
+      
+        
+      
+    
+  
+
+  
+    xilinx.com
+    Addressing/processing_system7_0
+    processing_system7
+    5.5
+    
+      
+        M_AXI_GP0
+        
+          
+          0x40000000
+        
+        
+        
+      
+    
+    
+      
+        Data
+        4G
+        32
+        
+      
+    
+  
+
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bxml b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bxml
new file mode 100644
index 0000000..656ceb6
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system.bxml
@@ -0,0 +1,53 @@
+
+
+  
+    Composite Fileset
+    
+    
+    
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+        
+        
+        
+      
+      
+        
+        
+        
+      
+      
+        
+        
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+        
+      
+      
+        
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+        
+        
+      
+      
+        
+        
+        
+      
+    
+  
+
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system_ooc.xdc b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system_ooc.xdc
new file mode 100644
index 0000000..46d92ca
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/system_ooc.xdc
@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name processing_system7_0_FCLK_CLK0 -period 20 [get_pins processing_system7_0/FCLK_CLK0]
+
+################################################################################
\ No newline at end of file
diff --git a/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ui/bd_c954508f.ui b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ui/bd_c954508f.ui
new file mode 100644
index 0000000..15bf37a
--- /dev/null
+++ b/Miz_sys/Miz_sys.srcs/sources_1/bd/system/ui/bd_c954508f.ui
@@ -0,0 +1,16 @@
+{
+   ExpandedHierarchyInLayout: "",
+   guistr: "# # String gsaved with Nlview 6.6.11  2017-06-12 bk=1.3860 VDI=40 GEI=35 GUI=JA:1.6
+#  -string -flagsOSRD
+preplace port DDR -pg 1 -y 70 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -y 90 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 3 -y 110 -defaultsOSRD
+preplace netloc processing_system7_0_DDR 1 3 1 NJ
+preplace netloc processing_system7_0_FIXED_IO 1 3 1 NJ
+preplace netloc processing_system7_0_FCLK_CLK0 1 2 2 390 20 860
+levelinfo -pg 1 -50 120 370 660 880 -top -20 -bot 250
+",
+}
+{
+   da_ps7_cnt: "1",
+}
diff --git a/Miz_sys/Miz_sys.xpr b/Miz_sys/Miz_sys.xpr
new file mode 100644
index 0000000..9283d15
--- /dev/null
+++ b/Miz_sys/Miz_sys.xpr
@@ -0,0 +1,144 @@
+
+
+
+
+
+
+  
+  
+    
+  
+    
+      
+      
+        
+          
+          
+          
+        
+      
+      
+        
+          
+          
+          
+        
+      
+      
+      
+        
+    
+    
+      
+      
+        
+    
+    
+      
+      
+        
+    
+  
+  
+    
+      
+    
+      
+    
+      
+    
+      
+    
+      
+  
+  
+    
+      
+        
+        
+      
+      
+      
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+      
+      
+    
+  
+  
+
diff --git a/Miz_sys/Packages/.repos.xml b/Miz_sys/Packages/.repos.xml
new file mode 100644
index 0000000..55f8c8c
--- /dev/null
+++ b/Miz_sys/Packages/.repos.xml
@@ -0,0 +1,13 @@
+
+
+  
+    CMSIS Pack
+    Keil
+    http://www.keil.com/pack/index.idx
+  
+  
+    XCDL/CMSIS Pack
+    GNU ARM Eclipse
+    http://gnuarmeclipse.sourceforge.net/packages/content.xml
+  
+